1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 #include "opt_cpu.h"
43
44 #include <sys/param.h>
45 #include <sys/bus.h>
46 #include <sys/cpu.h>
47 #include <sys/eventhandler.h>
48 #include <sys/limits.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
51 #include <sys/sysctl.h>
52 #include <sys/power.h>
53
54 #include <vm/vm.h>
55 #include <vm/pmap.h>
56
57 #include <machine/asmacros.h>
58 #include <machine/clock.h>
59 #include <machine/cputypes.h>
60 #include <machine/frame.h>
61 #include <machine/intr_machdep.h>
62 #include <machine/md_var.h>
63 #include <machine/segments.h>
64 #include <machine/specialreg.h>
65
66 #include <amd64/vmm/intel/vmx_controls.h>
67 #include <x86/isa/icu.h>
68 #include <x86/vmware.h>
69
70 #ifdef XENHVM
71 #include <xen/xen-os.h>
72 #endif
73
74 #ifdef __i386__
75 #define IDENTBLUE_CYRIX486 0
76 #define IDENTBLUE_IBMCPU 1
77 #define IDENTBLUE_CYRIXM2 2
78
79 static void identifycyrix(void);
80 static void print_transmeta_info(void);
81 #endif
82 static u_int find_cpu_vendor_id(void);
83 static void print_AMD_info(void);
84 static void print_INTEL_info(void);
85 static void print_INTEL_TLB(u_int data);
86 static void print_hypervisor_info(void);
87 static void print_svm_info(void);
88 static void print_via_padlock_info(void);
89 static void print_vmx_info(void);
90
91 #ifdef __i386__
92 int cpu; /* Are we 386, 386sx, 486, etc? */
93 int cpu_class;
94 #endif
95 u_int cpu_feature; /* Feature flags */
96 u_int cpu_feature2; /* Feature flags */
97 u_int amd_feature; /* AMD feature flags */
98 u_int amd_feature2; /* AMD feature flags */
99 u_int amd_rascap; /* AMD RAS capabilities */
100 u_int amd_pminfo; /* AMD advanced power management info */
101 u_int amd_extended_feature_extensions;
102 u_int via_feature_rng; /* VIA RNG features */
103 u_int via_feature_xcrypt; /* VIA ACE features */
104 u_int cpu_high; /* Highest arg to CPUID */
105 u_int cpu_exthigh; /* Highest arg to extended CPUID */
106 u_int cpu_id; /* Stepping ID */
107 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
108 u_int cpu_procinfo2; /* Multicore info */
109 u_int cpu_procinfo3;
110 char cpu_vendor[20]; /* CPU Origin code */
111 u_int cpu_vendor_id; /* CPU vendor ID */
112 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
113 u_int cpu_clflush_line_size = 32;
114 u_int cpu_stdext_feature; /* %ebx */
115 u_int cpu_stdext_feature2; /* %ecx */
116 u_int cpu_stdext_feature3; /* %edx */
117 uint64_t cpu_ia32_arch_caps;
118 u_int cpu_max_ext_state_size;
119 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
120 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
121 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
122 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
123 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */
124 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */
125 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */
126 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */
127 char machine[] = MACHINE;
128
129 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
130 &via_feature_rng, 0,
131 "VIA RNG feature available in CPU");
132 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
133 &via_feature_xcrypt, 0,
134 "VIA xcrypt feature available in CPU");
135
136 #ifdef __amd64__
137 #ifdef SCTL_MASK32
138 extern int adaptive_machine_arch;
139 #endif
140
141 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)142 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
143 {
144 #ifdef SCTL_MASK32
145 static const char machine32[] = "i386";
146 #endif
147 int error;
148
149 #ifdef SCTL_MASK32
150 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
151 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
152 else
153 #endif
154 error = SYSCTL_OUT(req, machine, sizeof(machine));
155 return (error);
156
157 }
158 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
159 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
160 #else
161 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD,
162 machine, 0, "Machine class");
163 #endif
164
165 char cpu_model[128];
166 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD,
167 cpu_model, 0, "Machine model");
168
169 static int hw_clockrate;
170 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
171 &hw_clockrate, 0, "CPU instruction clock rate");
172
173 u_int hv_base;
174 u_int hv_high;
175 char hv_vendor[16];
176 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor,
177 0, "Hypervisor vendor");
178
179 static eventhandler_tag tsc_post_tag;
180
181 static char cpu_brand[48];
182
183 #ifdef __i386__
184 #define MAX_BRAND_INDEX 8
185
186 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
187 NULL, /* No brand */
188 "Intel Celeron",
189 "Intel Pentium III",
190 "Intel Pentium III Xeon",
191 NULL,
192 NULL,
193 NULL,
194 NULL,
195 "Intel Pentium 4"
196 };
197
198 static struct {
199 char *cpu_name;
200 int cpu_class;
201 } cpus[] = {
202 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
203 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
204 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
205 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
206 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
207 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
208 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
209 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
210 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
211 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
212 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
213 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
214 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
215 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
216 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
217 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
218 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
219 };
220 #endif
221
222 static struct {
223 char *vendor;
224 u_int vendor_id;
225 } cpu_vendors[] = {
226 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
227 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
228 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */
229 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
230 #ifdef __i386__
231 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
232 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
233 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
234 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
235 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
236 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
237 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
238 #if 0
239 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
240 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
241 #endif
242 #endif
243 };
244
245 void
printcpuinfo(void)246 printcpuinfo(void)
247 {
248 u_int regs[4], i;
249 char *brand;
250
251 printf("CPU: ");
252 #ifdef __i386__
253 cpu_class = cpus[cpu].cpu_class;
254 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
255 #else
256 strncpy(cpu_model, "Hammer", sizeof (cpu_model));
257 #endif
258
259 /* Check for extended CPUID information and a processor name. */
260 if (cpu_exthigh >= 0x80000004) {
261 brand = cpu_brand;
262 for (i = 0x80000002; i < 0x80000005; i++) {
263 do_cpuid(i, regs);
264 memcpy(brand, regs, sizeof(regs));
265 brand += sizeof(regs);
266 }
267 }
268
269 switch (cpu_vendor_id) {
270 case CPU_VENDOR_INTEL:
271 #ifdef __i386__
272 if ((cpu_id & 0xf00) > 0x300) {
273 u_int brand_index;
274
275 cpu_model[0] = '\0';
276
277 switch (cpu_id & 0x3000) {
278 case 0x1000:
279 strcpy(cpu_model, "Overdrive ");
280 break;
281 case 0x2000:
282 strcpy(cpu_model, "Dual ");
283 break;
284 }
285
286 switch (cpu_id & 0xf00) {
287 case 0x400:
288 strcat(cpu_model, "i486 ");
289 /* Check the particular flavor of 486 */
290 switch (cpu_id & 0xf0) {
291 case 0x00:
292 case 0x10:
293 strcat(cpu_model, "DX");
294 break;
295 case 0x20:
296 strcat(cpu_model, "SX");
297 break;
298 case 0x30:
299 strcat(cpu_model, "DX2");
300 break;
301 case 0x40:
302 strcat(cpu_model, "SL");
303 break;
304 case 0x50:
305 strcat(cpu_model, "SX2");
306 break;
307 case 0x70:
308 strcat(cpu_model,
309 "DX2 Write-Back Enhanced");
310 break;
311 case 0x80:
312 strcat(cpu_model, "DX4");
313 break;
314 }
315 break;
316 case 0x500:
317 /* Check the particular flavor of 586 */
318 strcat(cpu_model, "Pentium");
319 switch (cpu_id & 0xf0) {
320 case 0x00:
321 strcat(cpu_model, " A-step");
322 break;
323 case 0x10:
324 strcat(cpu_model, "/P5");
325 break;
326 case 0x20:
327 strcat(cpu_model, "/P54C");
328 break;
329 case 0x30:
330 strcat(cpu_model, "/P24T");
331 break;
332 case 0x40:
333 strcat(cpu_model, "/P55C");
334 break;
335 case 0x70:
336 strcat(cpu_model, "/P54C");
337 break;
338 case 0x80:
339 strcat(cpu_model, "/P55C (quarter-micron)");
340 break;
341 default:
342 /* nothing */
343 break;
344 }
345 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
346 /*
347 * XXX - If/when Intel fixes the bug, this
348 * should also check the version of the
349 * CPU, not just that it's a Pentium.
350 */
351 has_f00f_bug = 1;
352 #endif
353 break;
354 case 0x600:
355 /* Check the particular flavor of 686 */
356 switch (cpu_id & 0xf0) {
357 case 0x00:
358 strcat(cpu_model, "Pentium Pro A-step");
359 break;
360 case 0x10:
361 strcat(cpu_model, "Pentium Pro");
362 break;
363 case 0x30:
364 case 0x50:
365 case 0x60:
366 strcat(cpu_model,
367 "Pentium II/Pentium II Xeon/Celeron");
368 cpu = CPU_PII;
369 break;
370 case 0x70:
371 case 0x80:
372 case 0xa0:
373 case 0xb0:
374 strcat(cpu_model,
375 "Pentium III/Pentium III Xeon/Celeron");
376 cpu = CPU_PIII;
377 break;
378 default:
379 strcat(cpu_model, "Unknown 80686");
380 break;
381 }
382 break;
383 case 0xf00:
384 strcat(cpu_model, "Pentium 4");
385 cpu = CPU_P4;
386 break;
387 default:
388 strcat(cpu_model, "unknown");
389 break;
390 }
391
392 /*
393 * If we didn't get a brand name from the extended
394 * CPUID, try to look it up in the brand table.
395 */
396 if (cpu_high > 0 && *cpu_brand == '\0') {
397 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
398 if (brand_index <= MAX_BRAND_INDEX &&
399 cpu_brandtable[brand_index] != NULL)
400 strcpy(cpu_brand,
401 cpu_brandtable[brand_index]);
402 }
403 }
404 #else
405 /* Please make up your mind folks! */
406 strcat(cpu_model, "EM64T");
407 #endif
408 break;
409 case CPU_VENDOR_AMD:
410 /*
411 * Values taken from AMD Processor Recognition
412 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
413 * (also describes ``Features'' encodings.
414 */
415 strcpy(cpu_model, "AMD ");
416 #ifdef __i386__
417 switch (cpu_id & 0xFF0) {
418 case 0x410:
419 strcat(cpu_model, "Standard Am486DX");
420 break;
421 case 0x430:
422 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
423 break;
424 case 0x470:
425 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
426 break;
427 case 0x480:
428 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
429 break;
430 case 0x490:
431 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
432 break;
433 case 0x4E0:
434 strcat(cpu_model, "Am5x86 Write-Through");
435 break;
436 case 0x4F0:
437 strcat(cpu_model, "Am5x86 Write-Back");
438 break;
439 case 0x500:
440 strcat(cpu_model, "K5 model 0");
441 break;
442 case 0x510:
443 strcat(cpu_model, "K5 model 1");
444 break;
445 case 0x520:
446 strcat(cpu_model, "K5 PR166 (model 2)");
447 break;
448 case 0x530:
449 strcat(cpu_model, "K5 PR200 (model 3)");
450 break;
451 case 0x560:
452 strcat(cpu_model, "K6");
453 break;
454 case 0x570:
455 strcat(cpu_model, "K6 266 (model 1)");
456 break;
457 case 0x580:
458 strcat(cpu_model, "K6-2");
459 break;
460 case 0x590:
461 strcat(cpu_model, "K6-III");
462 break;
463 case 0x5a0:
464 strcat(cpu_model, "Geode LX");
465 break;
466 default:
467 strcat(cpu_model, "Unknown");
468 break;
469 }
470 #else
471 if ((cpu_id & 0xf00) == 0xf00)
472 strcat(cpu_model, "AMD64 Processor");
473 else
474 strcat(cpu_model, "Unknown");
475 #endif
476 break;
477 #ifdef __i386__
478 case CPU_VENDOR_CYRIX:
479 strcpy(cpu_model, "Cyrix ");
480 switch (cpu_id & 0xff0) {
481 case 0x440:
482 strcat(cpu_model, "MediaGX");
483 break;
484 case 0x520:
485 strcat(cpu_model, "6x86");
486 break;
487 case 0x540:
488 cpu_class = CPUCLASS_586;
489 strcat(cpu_model, "GXm");
490 break;
491 case 0x600:
492 strcat(cpu_model, "6x86MX");
493 break;
494 default:
495 /*
496 * Even though CPU supports the cpuid
497 * instruction, it can be disabled.
498 * Therefore, this routine supports all Cyrix
499 * CPUs.
500 */
501 switch (cyrix_did & 0xf0) {
502 case 0x00:
503 switch (cyrix_did & 0x0f) {
504 case 0x00:
505 strcat(cpu_model, "486SLC");
506 break;
507 case 0x01:
508 strcat(cpu_model, "486DLC");
509 break;
510 case 0x02:
511 strcat(cpu_model, "486SLC2");
512 break;
513 case 0x03:
514 strcat(cpu_model, "486DLC2");
515 break;
516 case 0x04:
517 strcat(cpu_model, "486SRx");
518 break;
519 case 0x05:
520 strcat(cpu_model, "486DRx");
521 break;
522 case 0x06:
523 strcat(cpu_model, "486SRx2");
524 break;
525 case 0x07:
526 strcat(cpu_model, "486DRx2");
527 break;
528 case 0x08:
529 strcat(cpu_model, "486SRu");
530 break;
531 case 0x09:
532 strcat(cpu_model, "486DRu");
533 break;
534 case 0x0a:
535 strcat(cpu_model, "486SRu2");
536 break;
537 case 0x0b:
538 strcat(cpu_model, "486DRu2");
539 break;
540 default:
541 strcat(cpu_model, "Unknown");
542 break;
543 }
544 break;
545 case 0x10:
546 switch (cyrix_did & 0x0f) {
547 case 0x00:
548 strcat(cpu_model, "486S");
549 break;
550 case 0x01:
551 strcat(cpu_model, "486S2");
552 break;
553 case 0x02:
554 strcat(cpu_model, "486Se");
555 break;
556 case 0x03:
557 strcat(cpu_model, "486S2e");
558 break;
559 case 0x0a:
560 strcat(cpu_model, "486DX");
561 break;
562 case 0x0b:
563 strcat(cpu_model, "486DX2");
564 break;
565 case 0x0f:
566 strcat(cpu_model, "486DX4");
567 break;
568 default:
569 strcat(cpu_model, "Unknown");
570 break;
571 }
572 break;
573 case 0x20:
574 if ((cyrix_did & 0x0f) < 8)
575 strcat(cpu_model, "6x86"); /* Where did you get it? */
576 else
577 strcat(cpu_model, "5x86");
578 break;
579 case 0x30:
580 strcat(cpu_model, "6x86");
581 break;
582 case 0x40:
583 if ((cyrix_did & 0xf000) == 0x3000) {
584 cpu_class = CPUCLASS_586;
585 strcat(cpu_model, "GXm");
586 } else
587 strcat(cpu_model, "MediaGX");
588 break;
589 case 0x50:
590 strcat(cpu_model, "6x86MX");
591 break;
592 case 0xf0:
593 switch (cyrix_did & 0x0f) {
594 case 0x0d:
595 strcat(cpu_model, "Overdrive CPU");
596 break;
597 case 0x0e:
598 strcpy(cpu_model, "Texas Instruments 486SXL");
599 break;
600 case 0x0f:
601 strcat(cpu_model, "486SLC/DLC");
602 break;
603 default:
604 strcat(cpu_model, "Unknown");
605 break;
606 }
607 break;
608 default:
609 strcat(cpu_model, "Unknown");
610 break;
611 }
612 break;
613 }
614 break;
615 case CPU_VENDOR_RISE:
616 strcpy(cpu_model, "Rise ");
617 switch (cpu_id & 0xff0) {
618 case 0x500: /* 6401 and 6441 (Kirin) */
619 case 0x520: /* 6510 (Lynx) */
620 strcat(cpu_model, "mP6");
621 break;
622 default:
623 strcat(cpu_model, "Unknown");
624 }
625 break;
626 #endif
627 case CPU_VENDOR_CENTAUR:
628 #ifdef __i386__
629 switch (cpu_id & 0xff0) {
630 case 0x540:
631 strcpy(cpu_model, "IDT WinChip C6");
632 break;
633 case 0x580:
634 strcpy(cpu_model, "IDT WinChip 2");
635 break;
636 case 0x590:
637 strcpy(cpu_model, "IDT WinChip 3");
638 break;
639 case 0x660:
640 strcpy(cpu_model, "VIA C3 Samuel");
641 break;
642 case 0x670:
643 if (cpu_id & 0x8)
644 strcpy(cpu_model, "VIA C3 Ezra");
645 else
646 strcpy(cpu_model, "VIA C3 Samuel 2");
647 break;
648 case 0x680:
649 strcpy(cpu_model, "VIA C3 Ezra-T");
650 break;
651 case 0x690:
652 strcpy(cpu_model, "VIA C3 Nehemiah");
653 break;
654 case 0x6a0:
655 case 0x6d0:
656 strcpy(cpu_model, "VIA C7 Esther");
657 break;
658 case 0x6f0:
659 strcpy(cpu_model, "VIA Nano");
660 break;
661 default:
662 strcpy(cpu_model, "VIA/IDT Unknown");
663 }
664 #else
665 strcpy(cpu_model, "VIA ");
666 if ((cpu_id & 0xff0) == 0x6f0)
667 strcat(cpu_model, "Nano Processor");
668 else
669 strcat(cpu_model, "Unknown");
670 #endif
671 break;
672 #ifdef __i386__
673 case CPU_VENDOR_IBM:
674 strcpy(cpu_model, "Blue Lightning CPU");
675 break;
676 case CPU_VENDOR_NSC:
677 switch (cpu_id & 0xff0) {
678 case 0x540:
679 strcpy(cpu_model, "Geode SC1100");
680 cpu = CPU_GEODE1100;
681 break;
682 default:
683 strcpy(cpu_model, "Geode/NSC unknown");
684 break;
685 }
686 break;
687 #endif
688 case CPU_VENDOR_HYGON:
689 strcpy(cpu_model, "Hygon ");
690 #ifdef __i386__
691 strcat(cpu_model, "Unknown");
692 #else
693 if ((cpu_id & 0xf00) == 0xf00)
694 strcat(cpu_model, "AMD64 Processor");
695 else
696 strcat(cpu_model, "Unknown");
697 #endif
698 break;
699
700 default:
701 strcat(cpu_model, "Unknown");
702 break;
703 }
704
705 /*
706 * Replace cpu_model with cpu_brand minus leading spaces if
707 * we have one.
708 */
709 brand = cpu_brand;
710 while (*brand == ' ')
711 ++brand;
712 if (*brand != '\0')
713 strcpy(cpu_model, brand);
714
715 printf("%s (", cpu_model);
716 if (tsc_freq != 0) {
717 hw_clockrate = (tsc_freq + 5000) / 1000000;
718 printf("%jd.%02d-MHz ",
719 (intmax_t)(tsc_freq + 4999) / 1000000,
720 (u_int)((tsc_freq + 4999) / 10000) % 100);
721 }
722 #ifdef __i386__
723 switch(cpu_class) {
724 case CPUCLASS_286:
725 printf("286");
726 break;
727 case CPUCLASS_386:
728 printf("386");
729 break;
730 #if defined(I486_CPU)
731 case CPUCLASS_486:
732 printf("486");
733 break;
734 #endif
735 #if defined(I586_CPU)
736 case CPUCLASS_586:
737 printf("586");
738 break;
739 #endif
740 #if defined(I686_CPU)
741 case CPUCLASS_686:
742 printf("686");
743 break;
744 #endif
745 default:
746 printf("Unknown"); /* will panic below... */
747 }
748 #else
749 printf("K8");
750 #endif
751 printf("-class CPU)\n");
752 if (*cpu_vendor)
753 printf(" Origin=\"%s\"", cpu_vendor);
754 if (cpu_id)
755 printf(" Id=0x%x", cpu_id);
756
757 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
758 cpu_vendor_id == CPU_VENDOR_AMD ||
759 cpu_vendor_id == CPU_VENDOR_HYGON ||
760 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
761 #ifdef __i386__
762 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
763 cpu_vendor_id == CPU_VENDOR_RISE ||
764 cpu_vendor_id == CPU_VENDOR_NSC ||
765 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
766 #endif
767 0) {
768 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
769 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
770 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
771 #ifdef __i386__
772 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
773 printf("\n DIR=0x%04x", cyrix_did);
774 #endif
775
776 /*
777 * AMD CPUID Specification
778 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
779 *
780 * Intel Processor Identification and CPUID Instruction
781 * http://www.intel.com/assets/pdf/appnote/241618.pdf
782 */
783 if (cpu_high > 0) {
784 /*
785 * Here we should probably set up flags indicating
786 * whether or not various features are available.
787 * The interesting ones are probably VME, PSE, PAE,
788 * and PGE. The code already assumes without bothering
789 * to check that all CPUs >= Pentium have a TSC and
790 * MSRs.
791 */
792 printf("\n Features=0x%b", cpu_feature,
793 "\020"
794 "\001FPU" /* Integral FPU */
795 "\002VME" /* Extended VM86 mode support */
796 "\003DE" /* Debugging Extensions (CR4.DE) */
797 "\004PSE" /* 4MByte page tables */
798 "\005TSC" /* Timestamp counter */
799 "\006MSR" /* Machine specific registers */
800 "\007PAE" /* Physical address extension */
801 "\010MCE" /* Machine Check support */
802 "\011CX8" /* CMPEXCH8 instruction */
803 "\012APIC" /* SMP local APIC */
804 "\013oldMTRR" /* Previous implementation of MTRR */
805 "\014SEP" /* Fast System Call */
806 "\015MTRR" /* Memory Type Range Registers */
807 "\016PGE" /* PG_G (global bit) support */
808 "\017MCA" /* Machine Check Architecture */
809 "\020CMOV" /* CMOV instruction */
810 "\021PAT" /* Page attributes table */
811 "\022PSE36" /* 36 bit address space support */
812 "\023PN" /* Processor Serial number */
813 "\024CLFLUSH" /* Has the CLFLUSH instruction */
814 "\025<b20>"
815 "\026DTS" /* Debug Trace Store */
816 "\027ACPI" /* ACPI support */
817 "\030MMX" /* MMX instructions */
818 "\031FXSR" /* FXSAVE/FXRSTOR */
819 "\032SSE" /* Streaming SIMD Extensions */
820 "\033SSE2" /* Streaming SIMD Extensions #2 */
821 "\034SS" /* Self snoop */
822 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
823 "\036TM" /* Thermal Monitor clock slowdown */
824 "\037IA64" /* CPU can execute IA64 instructions */
825 "\040PBE" /* Pending Break Enable */
826 );
827
828 if (cpu_feature2 != 0) {
829 printf("\n Features2=0x%b", cpu_feature2,
830 "\020"
831 "\001SSE3" /* SSE3 */
832 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
833 "\003DTES64" /* 64-bit Debug Trace */
834 "\004MON" /* MONITOR/MWAIT Instructions */
835 "\005DS_CPL" /* CPL Qualified Debug Store */
836 "\006VMX" /* Virtual Machine Extensions */
837 "\007SMX" /* Safer Mode Extensions */
838 "\010EST" /* Enhanced SpeedStep */
839 "\011TM2" /* Thermal Monitor 2 */
840 "\012SSSE3" /* SSSE3 */
841 "\013CNXT-ID" /* L1 context ID available */
842 "\014SDBG" /* IA32 silicon debug */
843 "\015FMA" /* Fused Multiply Add */
844 "\016CX16" /* CMPXCHG16B Instruction */
845 "\017xTPR" /* Send Task Priority Messages*/
846 "\020PDCM" /* Perf/Debug Capability MSR */
847 "\021<b16>"
848 "\022PCID" /* Process-context Identifiers*/
849 "\023DCA" /* Direct Cache Access */
850 "\024SSE4.1" /* SSE 4.1 */
851 "\025SSE4.2" /* SSE 4.2 */
852 "\026x2APIC" /* xAPIC Extensions */
853 "\027MOVBE" /* MOVBE Instruction */
854 "\030POPCNT" /* POPCNT Instruction */
855 "\031TSCDLT" /* TSC-Deadline Timer */
856 "\032AESNI" /* AES Crypto */
857 "\033XSAVE" /* XSAVE/XRSTOR States */
858 "\034OSXSAVE" /* OS-Enabled State Management*/
859 "\035AVX" /* Advanced Vector Extensions */
860 "\036F16C" /* Half-precision conversions */
861 "\037RDRAND" /* RDRAND Instruction */
862 "\040HV" /* Hypervisor */
863 );
864 }
865
866 if (amd_feature != 0) {
867 printf("\n AMD Features=0x%b", amd_feature,
868 "\020" /* in hex */
869 "\001<s0>" /* Same */
870 "\002<s1>" /* Same */
871 "\003<s2>" /* Same */
872 "\004<s3>" /* Same */
873 "\005<s4>" /* Same */
874 "\006<s5>" /* Same */
875 "\007<s6>" /* Same */
876 "\010<s7>" /* Same */
877 "\011<s8>" /* Same */
878 "\012<s9>" /* Same */
879 "\013<b10>" /* Undefined */
880 "\014SYSCALL" /* Have SYSCALL/SYSRET */
881 "\015<s12>" /* Same */
882 "\016<s13>" /* Same */
883 "\017<s14>" /* Same */
884 "\020<s15>" /* Same */
885 "\021<s16>" /* Same */
886 "\022<s17>" /* Same */
887 "\023<b18>" /* Reserved, unknown */
888 "\024MP" /* Multiprocessor Capable */
889 "\025NX" /* Has EFER.NXE, NX */
890 "\026<b21>" /* Undefined */
891 "\027MMX+" /* AMD MMX Extensions */
892 "\030<s23>" /* Same */
893 "\031<s24>" /* Same */
894 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
895 "\033Page1GB" /* 1-GB large page support */
896 "\034RDTSCP" /* RDTSCP */
897 "\035<b28>" /* Undefined */
898 "\036LM" /* 64 bit long mode */
899 "\0373DNow!+" /* AMD 3DNow! Extensions */
900 "\0403DNow!" /* AMD 3DNow! */
901 );
902 }
903
904 if (amd_feature2 != 0) {
905 printf("\n AMD Features2=0x%b", amd_feature2,
906 "\020"
907 "\001LAHF" /* LAHF/SAHF in long mode */
908 "\002CMP" /* CMP legacy */
909 "\003SVM" /* Secure Virtual Mode */
910 "\004ExtAPIC" /* Extended APIC register */
911 "\005CR8" /* CR8 in legacy mode */
912 "\006ABM" /* LZCNT instruction */
913 "\007SSE4A" /* SSE4A */
914 "\010MAS" /* Misaligned SSE mode */
915 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
916 "\012OSVW" /* OS visible workaround */
917 "\013IBS" /* Instruction based sampling */
918 "\014XOP" /* XOP extended instructions */
919 "\015SKINIT" /* SKINIT/STGI */
920 "\016WDT" /* Watchdog timer */
921 "\017<b14>"
922 "\020LWP" /* Lightweight Profiling */
923 "\021FMA4" /* 4-operand FMA instructions */
924 "\022TCE" /* Translation Cache Extension */
925 "\023<b18>"
926 "\024NodeId" /* NodeId MSR support */
927 "\025<b20>"
928 "\026TBM" /* Trailing Bit Manipulation */
929 "\027Topology" /* Topology Extensions */
930 "\030PCXC" /* Core perf count */
931 "\031PNXC" /* NB perf count */
932 "\032<b25>"
933 "\033DBE" /* Data Breakpoint extension */
934 "\034PTSC" /* Performance TSC */
935 "\035PL2I" /* L2I perf count */
936 "\036MWAITX" /* MONITORX/MWAITX instructions */
937 "\037ADMSKX" /* Address mask extension */
938 "\040<b31>"
939 );
940 }
941
942 if (cpu_stdext_feature != 0) {
943 printf("\n Structured Extended Features=0x%b",
944 cpu_stdext_feature,
945 "\020"
946 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
947 "\001FSGSBASE"
948 "\002TSCADJ"
949 "\003SGX"
950 /* Bit Manipulation Instructions */
951 "\004BMI1"
952 /* Hardware Lock Elision */
953 "\005HLE"
954 /* Advanced Vector Instructions 2 */
955 "\006AVX2"
956 /* FDP_EXCPTN_ONLY */
957 "\007FDPEXC"
958 /* Supervisor Mode Execution Prot. */
959 "\010SMEP"
960 /* Bit Manipulation Instructions */
961 "\011BMI2"
962 "\012ERMS"
963 /* Invalidate Processor Context ID */
964 "\013INVPCID"
965 /* Restricted Transactional Memory */
966 "\014RTM"
967 "\015PQM"
968 "\016NFPUSG"
969 /* Intel Memory Protection Extensions */
970 "\017MPX"
971 "\020PQE"
972 /* AVX512 Foundation */
973 "\021AVX512F"
974 "\022AVX512DQ"
975 /* Enhanced NRBG */
976 "\023RDSEED"
977 /* ADCX + ADOX */
978 "\024ADX"
979 /* Supervisor Mode Access Prevention */
980 "\025SMAP"
981 "\026AVX512IFMA"
982 /* Formerly PCOMMIT */
983 "\027<b22>"
984 "\030CLFLUSHOPT"
985 "\031CLWB"
986 "\032PROCTRACE"
987 "\033AVX512PF"
988 "\034AVX512ER"
989 "\035AVX512CD"
990 "\036SHA"
991 "\037AVX512BW"
992 "\040AVX512VL"
993 );
994 }
995
996 if (cpu_stdext_feature2 != 0) {
997 printf("\n Structured Extended Features2=0x%b",
998 cpu_stdext_feature2,
999 "\020"
1000 "\001PREFETCHWT1"
1001 "\002AVX512VBMI"
1002 "\003UMIP"
1003 "\004PKU"
1004 "\005OSPKE"
1005 "\006WAITPKG"
1006 "\007AVX512VBMI2"
1007 "\011GFNI"
1008 "\012VAES"
1009 "\013VPCLMULQDQ"
1010 "\014AVX512VNNI"
1011 "\015AVX512BITALG"
1012 "\016TME"
1013 "\017AVX512VPOPCNTDQ"
1014 "\021LA57"
1015 "\027RDPID"
1016 "\032CLDEMOTE"
1017 "\034MOVDIRI"
1018 "\035MOVDIR64B"
1019 "\036ENQCMD"
1020 "\037SGXLC"
1021 );
1022 }
1023
1024 if (cpu_stdext_feature3 != 0) {
1025 printf("\n Structured Extended Features3=0x%b",
1026 cpu_stdext_feature3,
1027 "\020"
1028 "\003AVX512_4VNNIW"
1029 "\004AVX512_4FMAPS"
1030 "\005FSRM"
1031 "\011AVX512VP2INTERSECT"
1032 "\012MCUOPT"
1033 "\013MD_CLEAR"
1034 "\016TSXFA"
1035 "\023PCONFIG"
1036 "\025IBT"
1037 "\033IBPB"
1038 "\034STIBP"
1039 "\035L1DFL"
1040 "\036ARCH_CAP"
1041 "\037CORE_CAP"
1042 "\040SSBD"
1043 );
1044 }
1045
1046 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1047 cpuid_count(0xd, 0x1, regs);
1048 if (regs[0] != 0) {
1049 printf("\n XSAVE Features=0x%b",
1050 regs[0],
1051 "\020"
1052 "\001XSAVEOPT"
1053 "\002XSAVEC"
1054 "\003XINUSE"
1055 "\004XSAVES");
1056 }
1057 }
1058
1059 if (cpu_ia32_arch_caps != 0) {
1060 printf("\n IA32_ARCH_CAPS=0x%b",
1061 (u_int)cpu_ia32_arch_caps,
1062 "\020"
1063 "\001RDCL_NO"
1064 "\002IBRS_ALL"
1065 "\003RSBA"
1066 "\004SKIP_L1DFL_VME"
1067 "\005SSB_NO"
1068 "\006MDS_NO"
1069 "\010TSX_CTRL"
1070 "\011TAA_NO"
1071 );
1072 }
1073
1074 if (amd_extended_feature_extensions != 0) {
1075 u_int amd_fe_masked;
1076
1077 amd_fe_masked = amd_extended_feature_extensions;
1078 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1079 amd_fe_masked &=
1080 ~(AMDFEID_IBRS_ALWAYSON |
1081 AMDFEID_PREFER_IBRS);
1082 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1083 amd_fe_masked &=
1084 ~AMDFEID_STIBP_ALWAYSON;
1085
1086 printf("\n "
1087 "AMD Extended Feature Extensions ID EBX="
1088 "0x%b", amd_fe_masked,
1089 "\020"
1090 "\001CLZERO"
1091 "\002IRPerf"
1092 "\003XSaveErPtr"
1093 "\004INVLPGB"
1094 "\005RDPRU"
1095 "\007BE"
1096 "\011MCOMMIT"
1097 "\012WBNOINVD"
1098 "\015IBPB"
1099 "\016INT_WBINVD"
1100 "\017IBRS"
1101 "\020STIBP"
1102 "\021IBRS_ALWAYSON"
1103 "\022STIBP_ALWAYSON"
1104 "\023PREFER_IBRS"
1105 "\024SAMEMODE_IBRS"
1106 "\025NOLMSLE"
1107 "\026INVLPGBNEST"
1108 "\030PPIN"
1109 "\031SSBD"
1110 "\032VIRT_SSBD"
1111 "\033SSB_NO"
1112 "\034CPPC"
1113 "\035PSFD"
1114 "\036BTC_NO"
1115 "\037IBPB_RET"
1116 );
1117 }
1118
1119 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1120 print_via_padlock_info();
1121
1122 if (cpu_feature2 & CPUID2_VMX)
1123 print_vmx_info();
1124
1125 if (amd_feature2 & AMDID2_SVM)
1126 print_svm_info();
1127
1128 if ((cpu_feature & CPUID_HTT) &&
1129 (cpu_vendor_id == CPU_VENDOR_AMD ||
1130 cpu_vendor_id == CPU_VENDOR_HYGON))
1131 cpu_feature &= ~CPUID_HTT;
1132
1133 /*
1134 * If this CPU supports P-state invariant TSC then
1135 * mention the capability.
1136 */
1137 if (tsc_is_invariant) {
1138 printf("\n TSC: P-state invariant");
1139 if (tsc_perf_stat)
1140 printf(", performance statistics");
1141 }
1142 }
1143 #ifdef __i386__
1144 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1145 printf(" DIR=0x%04x", cyrix_did);
1146 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
1147 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
1148 #ifndef CYRIX_CACHE_REALLY_WORKS
1149 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1150 printf("\n CPU cache: write-through mode");
1151 #endif
1152 #endif
1153 }
1154
1155 /* Avoid ugly blank lines: only print newline when we have to. */
1156 if (*cpu_vendor || cpu_id)
1157 printf("\n");
1158
1159 if (bootverbose) {
1160 if (cpu_vendor_id == CPU_VENDOR_AMD ||
1161 cpu_vendor_id == CPU_VENDOR_HYGON)
1162 print_AMD_info();
1163 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1164 print_INTEL_info();
1165 #ifdef __i386__
1166 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1167 print_transmeta_info();
1168 #endif
1169 }
1170
1171 print_hypervisor_info();
1172 }
1173
1174 #ifdef __i386__
1175 void
panicifcpuunsupported(void)1176 panicifcpuunsupported(void)
1177 {
1178
1179 #if !defined(lint)
1180 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1181 #error This kernel is not configured for one of the supported CPUs
1182 #endif
1183 #else /* lint */
1184 #endif /* lint */
1185 /*
1186 * Now that we have told the user what they have,
1187 * let them know if that machine type isn't configured.
1188 */
1189 switch (cpu_class) {
1190 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1191 case CPUCLASS_386:
1192 #if !defined(I486_CPU)
1193 case CPUCLASS_486:
1194 #endif
1195 #if !defined(I586_CPU)
1196 case CPUCLASS_586:
1197 #endif
1198 #if !defined(I686_CPU)
1199 case CPUCLASS_686:
1200 #endif
1201 panic("CPU class not configured");
1202 default:
1203 break;
1204 }
1205 }
1206
1207 static volatile u_int trap_by_rdmsr;
1208
1209 /*
1210 * Special exception 6 handler.
1211 * The rdmsr instruction generates invalid opcodes fault on 486-class
1212 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1213 * function identblue() when this handler is called. Stacked eip should
1214 * be advanced.
1215 */
1216 inthand_t bluetrap6;
1217 __asm
1218 (" \n\
1219 .text \n\
1220 .p2align 2,0x90 \n\
1221 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1222 " __XSTRING(CNAME(bluetrap6)) ": \n\
1223 ss \n\
1224 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1225 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1226 iret \n\
1227 ");
1228
1229 /*
1230 * Special exception 13 handler.
1231 * Accessing non-existent MSR generates general protection fault.
1232 */
1233 inthand_t bluetrap13;
1234 __asm
1235 (" \n\
1236 .text \n\
1237 .p2align 2,0x90 \n\
1238 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1239 " __XSTRING(CNAME(bluetrap13)) ": \n\
1240 ss \n\
1241 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1242 popl %eax /* discard error code */ \n\
1243 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1244 iret \n\
1245 ");
1246
1247 /*
1248 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1249 * support cpuid instruction. This function should be called after
1250 * loading interrupt descriptor table register.
1251 *
1252 * I don't like this method that handles fault, but I couldn't get
1253 * information for any other methods. Does blue giant know?
1254 */
1255 static int
identblue(void)1256 identblue(void)
1257 {
1258
1259 trap_by_rdmsr = 0;
1260
1261 /*
1262 * Cyrix 486-class CPU does not support rdmsr instruction.
1263 * The rdmsr instruction generates invalid opcode fault, and exception
1264 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1265 * bluetrap6() set the magic number to trap_by_rdmsr.
1266 */
1267 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1268 GSEL(GCODE_SEL, SEL_KPL));
1269
1270 /*
1271 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1272 * In this case, rdmsr generates general protection fault, and
1273 * exception will be trapped by bluetrap13().
1274 */
1275 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1276 GSEL(GCODE_SEL, SEL_KPL));
1277
1278 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1279
1280 if (trap_by_rdmsr == 0xa8c1d)
1281 return IDENTBLUE_CYRIX486;
1282 else if (trap_by_rdmsr == 0xa89c4)
1283 return IDENTBLUE_CYRIXM2;
1284 return IDENTBLUE_IBMCPU;
1285 }
1286
1287 /*
1288 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1289 *
1290 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1291 * +-------+-------+---------------+
1292 * | SID | RID | Device ID |
1293 * | (DIR 1) | (DIR 0) |
1294 * +-------+-------+---------------+
1295 */
1296 static void
identifycyrix(void)1297 identifycyrix(void)
1298 {
1299 register_t saveintr;
1300 int ccr2_test = 0, dir_test = 0;
1301 u_char ccr2, ccr3;
1302
1303 saveintr = intr_disable();
1304
1305 ccr2 = read_cyrix_reg(CCR2);
1306 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1307 read_cyrix_reg(CCR2);
1308 if (read_cyrix_reg(CCR2) != ccr2)
1309 ccr2_test = 1;
1310 write_cyrix_reg(CCR2, ccr2);
1311
1312 ccr3 = read_cyrix_reg(CCR3);
1313 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1314 read_cyrix_reg(CCR3);
1315 if (read_cyrix_reg(CCR3) != ccr3)
1316 dir_test = 1; /* CPU supports DIRs. */
1317 write_cyrix_reg(CCR3, ccr3);
1318
1319 if (dir_test) {
1320 /* Device ID registers are available. */
1321 cyrix_did = read_cyrix_reg(DIR1) << 8;
1322 cyrix_did += read_cyrix_reg(DIR0);
1323 } else if (ccr2_test)
1324 cyrix_did = 0x0010; /* 486S A-step */
1325 else
1326 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1327
1328 intr_restore(saveintr);
1329 }
1330 #endif
1331
1332 /* Update TSC freq with the value indicated by the caller. */
1333 static void
tsc_freq_changed(void * arg __unused,const struct cf_level * level,int status)1334 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1335 {
1336
1337 /* If there was an error during the transition, don't do anything. */
1338 if (status != 0)
1339 return;
1340
1341 /* Total setting for this level gives the new frequency in MHz. */
1342 hw_clockrate = level->total_set.freq;
1343 }
1344
1345 static void
hook_tsc_freq(void * arg __unused)1346 hook_tsc_freq(void *arg __unused)
1347 {
1348
1349 if (tsc_is_invariant)
1350 return;
1351
1352 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1353 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1354 }
1355
1356 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1357
1358 static struct {
1359 const char *vm_cpuid;
1360 int vm_guest;
1361 void (*init)(void);
1362 } vm_cpuids[] = {
1363 { "XenVMMXenVMM", VM_GUEST_XEN,
1364 #ifdef XENHVM
1365 &xen_early_init,
1366 #endif
1367 }, /* XEN */
1368 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */
1369 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */
1370 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */
1371 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */
1372 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */
1373 };
1374
1375 static void
identify_hypervisor_cpuid_base(void)1376 identify_hypervisor_cpuid_base(void)
1377 {
1378 void (*init_fn)(void) = NULL;
1379 u_int leaf, regs[4];
1380 int i;
1381
1382 /*
1383 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1384 * http://lkml.org/lkml/2008/10/1/246
1385 *
1386 * KB1009458: Mechanisms to determine if software is running in
1387 * a VMware virtual machine
1388 * http://kb.vmware.com/kb/1009458
1389 *
1390 * Search for a hypervisor that we recognize. If we cannot find
1391 * a specific hypervisor, return the first information about the
1392 * hypervisor that we found, as others may be able to use.
1393 */
1394 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1395 do_cpuid(leaf, regs);
1396
1397 /*
1398 * KVM from Linux kernels prior to commit
1399 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1400 * to 0 rather than a valid hv_high value. Check for
1401 * the KVM signature bytes and fixup %eax to the
1402 * highest supported leaf in that case.
1403 */
1404 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1405 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1406 regs[0] = leaf + 1;
1407
1408 if (regs[0] >= leaf) {
1409 enum VM_GUEST prev_vm_guest = vm_guest;
1410
1411 for (i = 0; i < nitems(vm_cpuids); i++)
1412 if (strncmp((const char *)®s[1],
1413 vm_cpuids[i].vm_cpuid, 12) == 0) {
1414 vm_guest = vm_cpuids[i].vm_guest;
1415 init_fn = vm_cpuids[i].init;
1416 break;
1417 }
1418
1419 /*
1420 * If this is the first entry or we found a
1421 * specific hypervisor, record the base, high value,
1422 * and vendor identifier.
1423 */
1424 if (vm_guest != prev_vm_guest || leaf == 0x40000000) {
1425 hv_base = leaf;
1426 hv_high = regs[0];
1427 ((u_int *)&hv_vendor)[0] = regs[1];
1428 ((u_int *)&hv_vendor)[1] = regs[2];
1429 ((u_int *)&hv_vendor)[2] = regs[3];
1430 hv_vendor[12] = '\0';
1431
1432 /*
1433 * If we found a specific hypervisor, then
1434 * we are finished.
1435 */
1436 if (vm_guest != VM_GUEST_VM &&
1437 /*
1438 * Xen and other hypervisors can expose the
1439 * HyperV signature in addition to the
1440 * native one in order to support Viridian
1441 * extensions for Windows guests.
1442 *
1443 * Do the full cpuid scan if HyperV is
1444 * detected, as the native hypervisor is
1445 * preferred.
1446 */
1447 vm_guest != VM_GUEST_HV)
1448 break;
1449 }
1450 }
1451 }
1452
1453 if (init_fn != NULL)
1454 init_fn();
1455 }
1456
1457 void
identify_hypervisor(void)1458 identify_hypervisor(void)
1459 {
1460 u_int regs[4];
1461 char *p;
1462
1463 TSENTER();
1464 /*
1465 * If CPUID2_HV is set, we are running in a hypervisor environment.
1466 */
1467 if (cpu_feature2 & CPUID2_HV) {
1468 vm_guest = VM_GUEST_VM;
1469 identify_hypervisor_cpuid_base();
1470
1471 /* If we have a definitive vendor, we can return now. */
1472 if (*hv_vendor != '\0') {
1473 TSEXIT();
1474 return;
1475 }
1476 }
1477
1478 /*
1479 * Examine SMBIOS strings for older hypervisors.
1480 */
1481 p = kern_getenv("smbios.system.serial");
1482 if (p != NULL) {
1483 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1484 vmware_hvcall(0, VMW_HVCMD_GETVERSION,
1485 VMW_HVCMD_DEFAULT_PARAM, regs);
1486 if (regs[1] == VMW_HVMAGIC) {
1487 vm_guest = VM_GUEST_VMWARE;
1488 freeenv(p);
1489 TSEXIT();
1490 return;
1491 }
1492 }
1493 freeenv(p);
1494 }
1495 TSEXIT();
1496 }
1497
1498 bool
fix_cpuid(void)1499 fix_cpuid(void)
1500 {
1501 uint64_t msr;
1502
1503 /*
1504 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1505 * get the largest standard CPUID function number again if it is set
1506 * from BIOS. It is necessary for probing correct CPU topology later
1507 * and for the correct operation of the AVX-aware userspace.
1508 */
1509 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1510 ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1511 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1512 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1513 CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1514 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1515 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1516 msr &= ~IA32_MISC_EN_LIMCPUID;
1517 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1518 return (true);
1519 }
1520 }
1521
1522 /*
1523 * Re-enable AMD Topology Extension that could be disabled by BIOS
1524 * on some notebook processors. Without the extension it's really
1525 * hard to determine the correct CPU cache topology.
1526 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1527 * Models 60h-6Fh Processors, Publication # 50742.
1528 */
1529 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1530 CPUID_TO_FAMILY(cpu_id) == 0x15) {
1531 msr = rdmsr(MSR_EXTFEATURES);
1532 if ((msr & ((uint64_t)1 << 54)) == 0) {
1533 msr |= (uint64_t)1 << 54;
1534 wrmsr(MSR_EXTFEATURES, msr);
1535 return (true);
1536 }
1537 }
1538 return (false);
1539 }
1540
1541 void
identify_cpu1(void)1542 identify_cpu1(void)
1543 {
1544 u_int regs[4];
1545
1546 do_cpuid(0, regs);
1547 cpu_high = regs[0];
1548 ((u_int *)&cpu_vendor)[0] = regs[1];
1549 ((u_int *)&cpu_vendor)[1] = regs[3];
1550 ((u_int *)&cpu_vendor)[2] = regs[2];
1551 cpu_vendor[12] = '\0';
1552
1553 do_cpuid(1, regs);
1554 cpu_id = regs[0];
1555 cpu_procinfo = regs[1];
1556 cpu_feature = regs[3];
1557 cpu_feature2 = regs[2];
1558 }
1559
1560 void
identify_cpu2(void)1561 identify_cpu2(void)
1562 {
1563 u_int regs[4], cpu_stdext_disable;
1564
1565 if (cpu_high >= 6) {
1566 cpuid_count(6, 0, regs);
1567 cpu_power_eax = regs[0];
1568 cpu_power_ebx = regs[1];
1569 cpu_power_ecx = regs[2];
1570 cpu_power_edx = regs[3];
1571 }
1572
1573 if (cpu_high >= 7) {
1574 cpuid_count(7, 0, regs);
1575 cpu_stdext_feature = regs[1];
1576
1577 /*
1578 * Some hypervisors failed to filter out unsupported
1579 * extended features. Allow to disable the
1580 * extensions, activation of which requires setting a
1581 * bit in CR4, and which VM monitors do not support.
1582 */
1583 cpu_stdext_disable = 0;
1584 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1585 cpu_stdext_feature &= ~cpu_stdext_disable;
1586
1587 cpu_stdext_feature2 = regs[2];
1588 cpu_stdext_feature3 = regs[3];
1589
1590 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1591 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1592 }
1593 }
1594
1595 void
identify_cpu_ext_features(void)1596 identify_cpu_ext_features(void)
1597 {
1598 u_int regs[4];
1599
1600 if (cpu_high >= 7) {
1601 cpuid_count(7, 0, regs);
1602 cpu_stdext_feature2 = regs[2];
1603 cpu_stdext_feature3 = regs[3];
1604 }
1605 }
1606
1607 void
identify_cpu_fixup_bsp(void)1608 identify_cpu_fixup_bsp(void)
1609 {
1610 u_int regs[4];
1611
1612 cpu_vendor_id = find_cpu_vendor_id();
1613
1614 if (fix_cpuid()) {
1615 do_cpuid(0, regs);
1616 cpu_high = regs[0];
1617 }
1618 }
1619
1620 /*
1621 * Final stage of CPU identification.
1622 */
1623 void
finishidentcpu(void)1624 finishidentcpu(void)
1625 {
1626 u_int regs[4];
1627 #ifdef __i386__
1628 u_char ccr3;
1629 #endif
1630
1631 identify_cpu_fixup_bsp();
1632
1633 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1634 do_cpuid(5, regs);
1635 cpu_mon_mwait_flags = regs[2];
1636 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1637 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1638 }
1639
1640 identify_cpu2();
1641
1642 #ifdef __i386__
1643 if (cpu_high > 0 &&
1644 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1645 cpu_vendor_id == CPU_VENDOR_AMD ||
1646 cpu_vendor_id == CPU_VENDOR_HYGON ||
1647 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1648 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1649 cpu_vendor_id == CPU_VENDOR_NSC)) {
1650 do_cpuid(0x80000000, regs);
1651 if (regs[0] >= 0x80000000)
1652 cpu_exthigh = regs[0];
1653 }
1654 #else
1655 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1656 cpu_vendor_id == CPU_VENDOR_AMD ||
1657 cpu_vendor_id == CPU_VENDOR_HYGON ||
1658 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1659 do_cpuid(0x80000000, regs);
1660 cpu_exthigh = regs[0];
1661 }
1662 #endif
1663 if (cpu_exthigh >= 0x80000001) {
1664 do_cpuid(0x80000001, regs);
1665 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1666 amd_feature2 = regs[2];
1667 }
1668 if (cpu_exthigh >= 0x80000007) {
1669 do_cpuid(0x80000007, regs);
1670 amd_rascap = regs[1];
1671 amd_pminfo = regs[3];
1672 }
1673 if (cpu_exthigh >= 0x80000008) {
1674 do_cpuid(0x80000008, regs);
1675 cpu_maxphyaddr = regs[0] & 0xff;
1676 amd_extended_feature_extensions = regs[1];
1677 cpu_procinfo2 = regs[2];
1678 cpu_procinfo3 = regs[3];
1679 } else {
1680 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1681 }
1682
1683 #ifdef __i386__
1684 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1685 if (cpu == CPU_486) {
1686 /*
1687 * These conditions are equivalent to:
1688 * - CPU does not support cpuid instruction.
1689 * - Cyrix/IBM CPU is detected.
1690 */
1691 if (identblue() == IDENTBLUE_IBMCPU) {
1692 strcpy(cpu_vendor, "IBM");
1693 cpu_vendor_id = CPU_VENDOR_IBM;
1694 cpu = CPU_BLUE;
1695 return;
1696 }
1697 }
1698 switch (cpu_id & 0xf00) {
1699 case 0x600:
1700 /*
1701 * Cyrix's datasheet does not describe DIRs.
1702 * Therefor, I assume it does not have them
1703 * and use the result of the cpuid instruction.
1704 * XXX they seem to have it for now at least. -Peter
1705 */
1706 identifycyrix();
1707 cpu = CPU_M2;
1708 break;
1709 default:
1710 identifycyrix();
1711 /*
1712 * This routine contains a trick.
1713 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1714 */
1715 switch (cyrix_did & 0x00f0) {
1716 case 0x00:
1717 case 0xf0:
1718 cpu = CPU_486DLC;
1719 break;
1720 case 0x10:
1721 cpu = CPU_CY486DX;
1722 break;
1723 case 0x20:
1724 if ((cyrix_did & 0x000f) < 8)
1725 cpu = CPU_M1;
1726 else
1727 cpu = CPU_M1SC;
1728 break;
1729 case 0x30:
1730 cpu = CPU_M1;
1731 break;
1732 case 0x40:
1733 /* MediaGX CPU */
1734 cpu = CPU_M1SC;
1735 break;
1736 default:
1737 /* M2 and later CPUs are treated as M2. */
1738 cpu = CPU_M2;
1739
1740 /*
1741 * enable cpuid instruction.
1742 */
1743 ccr3 = read_cyrix_reg(CCR3);
1744 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1745 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1746 write_cyrix_reg(CCR3, ccr3);
1747
1748 do_cpuid(0, regs);
1749 cpu_high = regs[0]; /* eax */
1750 do_cpuid(1, regs);
1751 cpu_id = regs[0]; /* eax */
1752 cpu_feature = regs[3]; /* edx */
1753 break;
1754 }
1755 }
1756 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1757 /*
1758 * There are BlueLightning CPUs that do not change
1759 * undefined flags by dividing 5 by 2. In this case,
1760 * the CPU identification routine in locore.s leaves
1761 * cpu_vendor null string and puts CPU_486 into the
1762 * cpu.
1763 */
1764 if (identblue() == IDENTBLUE_IBMCPU) {
1765 strcpy(cpu_vendor, "IBM");
1766 cpu_vendor_id = CPU_VENDOR_IBM;
1767 cpu = CPU_BLUE;
1768 return;
1769 }
1770 }
1771 #endif
1772 }
1773
1774 int
pti_get_default(void)1775 pti_get_default(void)
1776 {
1777
1778 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1779 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1780 return (0);
1781 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1782 return (0);
1783 return (1);
1784 }
1785
1786 static u_int
find_cpu_vendor_id(void)1787 find_cpu_vendor_id(void)
1788 {
1789 int i;
1790
1791 for (i = 0; i < nitems(cpu_vendors); i++)
1792 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1793 return (cpu_vendors[i].vendor_id);
1794 return (0);
1795 }
1796
1797 static void
print_AMD_assoc(int i)1798 print_AMD_assoc(int i)
1799 {
1800 if (i == 255)
1801 printf(", fully associative\n");
1802 else
1803 printf(", %d-way associative\n", i);
1804 }
1805
1806 static void
print_AMD_l2_assoc(int i)1807 print_AMD_l2_assoc(int i)
1808 {
1809 switch (i & 0x0f) {
1810 case 0: printf(", disabled/not present\n"); break;
1811 case 1: printf(", direct mapped\n"); break;
1812 case 2: printf(", 2-way associative\n"); break;
1813 case 4: printf(", 4-way associative\n"); break;
1814 case 6: printf(", 8-way associative\n"); break;
1815 case 8: printf(", 16-way associative\n"); break;
1816 case 15: printf(", fully associative\n"); break;
1817 default: printf(", reserved configuration\n"); break;
1818 }
1819 }
1820
1821 static void
print_AMD_info(void)1822 print_AMD_info(void)
1823 {
1824 #ifdef __i386__
1825 uint64_t amd_whcr;
1826 #endif
1827 u_int regs[4];
1828
1829 if (cpu_exthigh >= 0x80000005) {
1830 do_cpuid(0x80000005, regs);
1831 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1832 print_AMD_assoc(regs[0] >> 24);
1833
1834 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1835 print_AMD_assoc((regs[0] >> 8) & 0xff);
1836
1837 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1838 print_AMD_assoc(regs[1] >> 24);
1839
1840 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1841 print_AMD_assoc((regs[1] >> 8) & 0xff);
1842
1843 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1844 printf(", %d bytes/line", regs[2] & 0xff);
1845 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1846 print_AMD_assoc((regs[2] >> 16) & 0xff);
1847
1848 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1849 printf(", %d bytes/line", regs[3] & 0xff);
1850 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1851 print_AMD_assoc((regs[3] >> 16) & 0xff);
1852 }
1853
1854 if (cpu_exthigh >= 0x80000006) {
1855 do_cpuid(0x80000006, regs);
1856 if ((regs[0] >> 16) != 0) {
1857 printf("L2 2MB data TLB: %d entries",
1858 (regs[0] >> 16) & 0xfff);
1859 print_AMD_l2_assoc(regs[0] >> 28);
1860 printf("L2 2MB instruction TLB: %d entries",
1861 regs[0] & 0xfff);
1862 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1863 } else {
1864 printf("L2 2MB unified TLB: %d entries",
1865 regs[0] & 0xfff);
1866 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1867 }
1868 if ((regs[1] >> 16) != 0) {
1869 printf("L2 4KB data TLB: %d entries",
1870 (regs[1] >> 16) & 0xfff);
1871 print_AMD_l2_assoc(regs[1] >> 28);
1872
1873 printf("L2 4KB instruction TLB: %d entries",
1874 (regs[1] >> 16) & 0xfff);
1875 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1876 } else {
1877 printf("L2 4KB unified TLB: %d entries",
1878 (regs[1] >> 16) & 0xfff);
1879 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1880 }
1881 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1882 printf(", %d bytes/line", regs[2] & 0xff);
1883 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1884 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1885 }
1886
1887 #ifdef __i386__
1888 if (((cpu_id & 0xf00) == 0x500)
1889 && (((cpu_id & 0x0f0) > 0x80)
1890 || (((cpu_id & 0x0f0) == 0x80)
1891 && (cpu_id & 0x00f) > 0x07))) {
1892 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1893 amd_whcr = rdmsr(0xc0000082);
1894 if (!(amd_whcr & (0x3ff << 22))) {
1895 printf("Write Allocate Disable\n");
1896 } else {
1897 printf("Write Allocate Enable Limit: %dM bytes\n",
1898 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1899 printf("Write Allocate 15-16M bytes: %s\n",
1900 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1901 }
1902 } else if (((cpu_id & 0xf00) == 0x500)
1903 && ((cpu_id & 0x0f0) > 0x50)) {
1904 /* K6, K6-2(old core) */
1905 amd_whcr = rdmsr(0xc0000082);
1906 if (!(amd_whcr & (0x7f << 1))) {
1907 printf("Write Allocate Disable\n");
1908 } else {
1909 printf("Write Allocate Enable Limit: %dM bytes\n",
1910 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1911 printf("Write Allocate 15-16M bytes: %s\n",
1912 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1913 printf("Hardware Write Allocate Control: %s\n",
1914 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1915 }
1916 }
1917 #endif
1918 /*
1919 * Opteron Rev E shows a bug as in very rare occasions a read memory
1920 * barrier is not performed as expected if it is followed by a
1921 * non-atomic read-modify-write instruction.
1922 * As long as that bug pops up very rarely (intensive machine usage
1923 * on other operating systems generally generates one unexplainable
1924 * crash any 2 months) and as long as a model specific fix would be
1925 * impractical at this stage, print out a warning string if the broken
1926 * model and family are identified.
1927 */
1928 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1929 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1930 printf("WARNING: This architecture revision has known SMP "
1931 "hardware bugs which may cause random instability\n");
1932 }
1933
1934 static void
print_INTEL_info(void)1935 print_INTEL_info(void)
1936 {
1937 u_int regs[4];
1938 u_int rounds, regnum;
1939 u_int nwaycode, nway;
1940
1941 if (cpu_high >= 2) {
1942 rounds = 0;
1943 do {
1944 do_cpuid(0x2, regs);
1945 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1946 break; /* we have a buggy CPU */
1947
1948 for (regnum = 0; regnum <= 3; ++regnum) {
1949 if (regs[regnum] & (1<<31))
1950 continue;
1951 if (regnum != 0)
1952 print_INTEL_TLB(regs[regnum] & 0xff);
1953 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1954 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1955 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1956 }
1957 } while (--rounds > 0);
1958 }
1959
1960 if (cpu_exthigh >= 0x80000006) {
1961 do_cpuid(0x80000006, regs);
1962 nwaycode = (regs[2] >> 12) & 0x0f;
1963 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1964 nway = 1 << (nwaycode / 2);
1965 else
1966 nway = 0;
1967 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1968 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1969 }
1970 }
1971
1972 static void
print_INTEL_TLB(u_int data)1973 print_INTEL_TLB(u_int data)
1974 {
1975 switch (data) {
1976 case 0x0:
1977 case 0x40:
1978 default:
1979 break;
1980 case 0x1:
1981 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1982 break;
1983 case 0x2:
1984 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1985 break;
1986 case 0x3:
1987 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1988 break;
1989 case 0x4:
1990 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1991 break;
1992 case 0x6:
1993 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1994 break;
1995 case 0x8:
1996 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1997 break;
1998 case 0x9:
1999 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
2000 break;
2001 case 0xa:
2002 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
2003 break;
2004 case 0xb:
2005 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
2006 break;
2007 case 0xc:
2008 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
2009 break;
2010 case 0xd:
2011 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
2012 break;
2013 case 0xe:
2014 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
2015 break;
2016 case 0x1d:
2017 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2018 break;
2019 case 0x21:
2020 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2021 break;
2022 case 0x22:
2023 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2024 break;
2025 case 0x23:
2026 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2027 break;
2028 case 0x24:
2029 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2030 break;
2031 case 0x25:
2032 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2033 break;
2034 case 0x29:
2035 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2036 break;
2037 case 0x2c:
2038 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2039 break;
2040 case 0x30:
2041 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2042 break;
2043 case 0x39: /* De-listed in SDM rev. 54 */
2044 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2045 break;
2046 case 0x3b: /* De-listed in SDM rev. 54 */
2047 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2048 break;
2049 case 0x3c: /* De-listed in SDM rev. 54 */
2050 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2051 break;
2052 case 0x41:
2053 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2054 break;
2055 case 0x42:
2056 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2057 break;
2058 case 0x43:
2059 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2060 break;
2061 case 0x44:
2062 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2063 break;
2064 case 0x45:
2065 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2066 break;
2067 case 0x46:
2068 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2069 break;
2070 case 0x47:
2071 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2072 break;
2073 case 0x48:
2074 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2075 break;
2076 case 0x49:
2077 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2078 CPUID_TO_MODEL(cpu_id) == 0x6)
2079 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2080 else
2081 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2082 break;
2083 case 0x4a:
2084 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2085 break;
2086 case 0x4b:
2087 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2088 break;
2089 case 0x4c:
2090 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2091 break;
2092 case 0x4d:
2093 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2094 break;
2095 case 0x4e:
2096 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2097 break;
2098 case 0x4f:
2099 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2100 break;
2101 case 0x50:
2102 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2103 break;
2104 case 0x51:
2105 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2106 break;
2107 case 0x52:
2108 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2109 break;
2110 case 0x55:
2111 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2112 break;
2113 case 0x56:
2114 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2115 break;
2116 case 0x57:
2117 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2118 break;
2119 case 0x59:
2120 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2121 break;
2122 case 0x5a:
2123 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2124 break;
2125 case 0x5b:
2126 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2127 break;
2128 case 0x5c:
2129 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2130 break;
2131 case 0x5d:
2132 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2133 break;
2134 case 0x60:
2135 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2136 break;
2137 case 0x61:
2138 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2139 break;
2140 case 0x63:
2141 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2142 break;
2143 case 0x64:
2144 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2145 break;
2146 case 0x66:
2147 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2148 break;
2149 case 0x67:
2150 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2151 break;
2152 case 0x68:
2153 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2154 break;
2155 case 0x6a:
2156 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2157 break;
2158 case 0x6b:
2159 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2160 break;
2161 case 0x6c:
2162 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2163 break;
2164 case 0x6d:
2165 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2166 break;
2167 case 0x70:
2168 printf("Trace cache: 12K-uops, 8-way set associative\n");
2169 break;
2170 case 0x71:
2171 printf("Trace cache: 16K-uops, 8-way set associative\n");
2172 break;
2173 case 0x72:
2174 printf("Trace cache: 32K-uops, 8-way set associative\n");
2175 break;
2176 case 0x76:
2177 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2178 break;
2179 case 0x78:
2180 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2181 break;
2182 case 0x79:
2183 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2184 break;
2185 case 0x7a:
2186 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2187 break;
2188 case 0x7b:
2189 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2190 break;
2191 case 0x7c:
2192 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2193 break;
2194 case 0x7d:
2195 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2196 break;
2197 case 0x7f:
2198 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2199 break;
2200 case 0x80:
2201 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2202 break;
2203 case 0x82:
2204 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2205 break;
2206 case 0x83:
2207 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2208 break;
2209 case 0x84:
2210 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2211 break;
2212 case 0x85:
2213 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2214 break;
2215 case 0x86:
2216 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2217 break;
2218 case 0x87:
2219 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2220 break;
2221 case 0xa0:
2222 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2223 break;
2224 case 0xb0:
2225 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2226 break;
2227 case 0xb1:
2228 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2229 break;
2230 case 0xb2:
2231 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2232 break;
2233 case 0xb3:
2234 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2235 break;
2236 case 0xb4:
2237 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2238 break;
2239 case 0xb5:
2240 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2241 break;
2242 case 0xb6:
2243 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2244 break;
2245 case 0xba:
2246 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2247 break;
2248 case 0xc0:
2249 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2250 break;
2251 case 0xc1:
2252 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2253 break;
2254 case 0xc2:
2255 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2256 break;
2257 case 0xc3:
2258 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2259 break;
2260 case 0xc4:
2261 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2262 break;
2263 case 0xca:
2264 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2265 break;
2266 case 0xd0:
2267 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2268 break;
2269 case 0xd1:
2270 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2271 break;
2272 case 0xd2:
2273 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2274 break;
2275 case 0xd6:
2276 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2277 break;
2278 case 0xd7:
2279 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2280 break;
2281 case 0xd8:
2282 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2283 break;
2284 case 0xdc:
2285 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2286 break;
2287 case 0xdd:
2288 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2289 break;
2290 case 0xde:
2291 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2292 break;
2293 case 0xe2:
2294 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2295 break;
2296 case 0xe3:
2297 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2298 break;
2299 case 0xe4:
2300 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2301 break;
2302 case 0xea:
2303 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2304 break;
2305 case 0xeb:
2306 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2307 break;
2308 case 0xec:
2309 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2310 break;
2311 case 0xf0:
2312 printf("64-Byte prefetching\n");
2313 break;
2314 case 0xf1:
2315 printf("128-Byte prefetching\n");
2316 break;
2317 }
2318 }
2319
2320 static void
print_svm_info(void)2321 print_svm_info(void)
2322 {
2323 u_int features, regs[4];
2324 uint64_t msr;
2325 int comma;
2326
2327 printf("\n SVM: ");
2328 do_cpuid(0x8000000A, regs);
2329 features = regs[3];
2330
2331 msr = rdmsr(MSR_VM_CR);
2332 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2333 printf("(disabled in BIOS) ");
2334
2335 if (!bootverbose) {
2336 comma = 0;
2337 if (features & (1 << 0)) {
2338 printf("%sNP", comma ? "," : "");
2339 comma = 1;
2340 }
2341 if (features & (1 << 3)) {
2342 printf("%sNRIP", comma ? "," : "");
2343 comma = 1;
2344 }
2345 if (features & (1 << 5)) {
2346 printf("%sVClean", comma ? "," : "");
2347 comma = 1;
2348 }
2349 if (features & (1 << 6)) {
2350 printf("%sAFlush", comma ? "," : "");
2351 comma = 1;
2352 }
2353 if (features & (1 << 7)) {
2354 printf("%sDAssist", comma ? "," : "");
2355 comma = 1;
2356 }
2357 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2358 return;
2359 }
2360
2361 printf("Features=0x%b", features,
2362 "\020"
2363 "\001NP" /* Nested paging */
2364 "\002LbrVirt" /* LBR virtualization */
2365 "\003SVML" /* SVM lock */
2366 "\004NRIPS" /* NRIP save */
2367 "\005TscRateMsr" /* MSR based TSC rate control */
2368 "\006VmcbClean" /* VMCB clean bits */
2369 "\007FlushByAsid" /* Flush by ASID */
2370 "\010DecodeAssist" /* Decode assist */
2371 "\011<b8>"
2372 "\012<b9>"
2373 "\013PauseFilter" /* PAUSE intercept filter */
2374 "\014EncryptedMcodePatch"
2375 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2376 "\016AVIC" /* virtual interrupt controller */
2377 "\017<b14>"
2378 "\020V_VMSAVE_VMLOAD"
2379 "\021vGIF"
2380 "\022GMET" /* Guest Mode Execute Trap */
2381 "\023<b18>"
2382 "\024<b19>"
2383 "\025GuesSpecCtl" /* Guest Spec_ctl */
2384 "\026<b21>"
2385 "\027<b22>"
2386 "\030<b23>"
2387 "\031<b24>"
2388 "\032<b25>"
2389 "\033<b26>"
2390 "\034<b27>"
2391 "\035<b28>"
2392 "\036<b29>"
2393 "\037<b30>"
2394 "\040<b31>"
2395 );
2396 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2397 }
2398
2399 #ifdef __i386__
2400 static void
print_transmeta_info(void)2401 print_transmeta_info(void)
2402 {
2403 u_int regs[4], nreg = 0;
2404
2405 do_cpuid(0x80860000, regs);
2406 nreg = regs[0];
2407 if (nreg >= 0x80860001) {
2408 do_cpuid(0x80860001, regs);
2409 printf(" Processor revision %u.%u.%u.%u\n",
2410 (regs[1] >> 24) & 0xff,
2411 (regs[1] >> 16) & 0xff,
2412 (regs[1] >> 8) & 0xff,
2413 regs[1] & 0xff);
2414 }
2415 if (nreg >= 0x80860002) {
2416 do_cpuid(0x80860002, regs);
2417 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2418 (regs[1] >> 24) & 0xff,
2419 (regs[1] >> 16) & 0xff,
2420 (regs[1] >> 8) & 0xff,
2421 regs[1] & 0xff,
2422 regs[2]);
2423 }
2424 if (nreg >= 0x80860006) {
2425 char info[65];
2426 do_cpuid(0x80860003, (u_int*) &info[0]);
2427 do_cpuid(0x80860004, (u_int*) &info[16]);
2428 do_cpuid(0x80860005, (u_int*) &info[32]);
2429 do_cpuid(0x80860006, (u_int*) &info[48]);
2430 info[64] = 0;
2431 printf(" %s\n", info);
2432 }
2433 }
2434 #endif
2435
2436 static void
print_via_padlock_info(void)2437 print_via_padlock_info(void)
2438 {
2439 u_int regs[4];
2440
2441 do_cpuid(0xc0000001, regs);
2442 printf("\n VIA Padlock Features=0x%b", regs[3],
2443 "\020"
2444 "\003RNG" /* RNG */
2445 "\007AES" /* ACE */
2446 "\011AES-CTR" /* ACE2 */
2447 "\013SHA1,SHA256" /* PHE */
2448 "\015RSA" /* PMM */
2449 );
2450 }
2451
2452 static uint32_t
vmx_settable(uint64_t basic,int msr,int true_msr)2453 vmx_settable(uint64_t basic, int msr, int true_msr)
2454 {
2455 uint64_t val;
2456
2457 if (basic & (1ULL << 55))
2458 val = rdmsr(true_msr);
2459 else
2460 val = rdmsr(msr);
2461
2462 /* Just report the controls that can be set to 1. */
2463 return (val >> 32);
2464 }
2465
2466 static void
print_vmx_info(void)2467 print_vmx_info(void)
2468 {
2469 uint64_t basic, msr;
2470 uint32_t entry, exit, mask, pin, proc, proc2;
2471 int comma;
2472
2473 printf("\n VT-x: ");
2474 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2475 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2476 printf("(disabled in BIOS) ");
2477 basic = rdmsr(MSR_VMX_BASIC);
2478 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2479 MSR_VMX_TRUE_PINBASED_CTLS);
2480 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2481 MSR_VMX_TRUE_PROCBASED_CTLS);
2482 if (proc & PROCBASED_SECONDARY_CONTROLS)
2483 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2484 MSR_VMX_PROCBASED_CTLS2);
2485 else
2486 proc2 = 0;
2487 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2488 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2489
2490 if (!bootverbose) {
2491 comma = 0;
2492 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2493 entry & VM_ENTRY_LOAD_PAT) {
2494 printf("%sPAT", comma ? "," : "");
2495 comma = 1;
2496 }
2497 if (proc & PROCBASED_HLT_EXITING) {
2498 printf("%sHLT", comma ? "," : "");
2499 comma = 1;
2500 }
2501 if (proc & PROCBASED_MTF) {
2502 printf("%sMTF", comma ? "," : "");
2503 comma = 1;
2504 }
2505 if (proc & PROCBASED_PAUSE_EXITING) {
2506 printf("%sPAUSE", comma ? "," : "");
2507 comma = 1;
2508 }
2509 if (proc2 & PROCBASED2_ENABLE_EPT) {
2510 printf("%sEPT", comma ? "," : "");
2511 comma = 1;
2512 }
2513 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2514 printf("%sUG", comma ? "," : "");
2515 comma = 1;
2516 }
2517 if (proc2 & PROCBASED2_ENABLE_VPID) {
2518 printf("%sVPID", comma ? "," : "");
2519 comma = 1;
2520 }
2521 if (proc & PROCBASED_USE_TPR_SHADOW &&
2522 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2523 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2524 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2525 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2526 printf("%sVID", comma ? "," : "");
2527 comma = 1;
2528 if (pin & PINBASED_POSTED_INTERRUPT)
2529 printf(",PostIntr");
2530 }
2531 return;
2532 }
2533
2534 mask = basic >> 32;
2535 printf("Basic Features=0x%b", mask,
2536 "\020"
2537 "\02132PA" /* 32-bit physical addresses */
2538 "\022SMM" /* SMM dual-monitor */
2539 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2540 "\030TRUE" /* TRUE_CTLS MSRs */
2541 );
2542 printf("\n Pin-Based Controls=0x%b", pin,
2543 "\020"
2544 "\001ExtINT" /* External-interrupt exiting */
2545 "\004NMI" /* NMI exiting */
2546 "\006VNMI" /* Virtual NMIs */
2547 "\007PreTmr" /* Activate VMX-preemption timer */
2548 "\010PostIntr" /* Process posted interrupts */
2549 );
2550 printf("\n Primary Processor Controls=0x%b", proc,
2551 "\020"
2552 "\003INTWIN" /* Interrupt-window exiting */
2553 "\004TSCOff" /* Use TSC offsetting */
2554 "\010HLT" /* HLT exiting */
2555 "\012INVLPG" /* INVLPG exiting */
2556 "\013MWAIT" /* MWAIT exiting */
2557 "\014RDPMC" /* RDPMC exiting */
2558 "\015RDTSC" /* RDTSC exiting */
2559 "\020CR3-LD" /* CR3-load exiting */
2560 "\021CR3-ST" /* CR3-store exiting */
2561 "\024CR8-LD" /* CR8-load exiting */
2562 "\025CR8-ST" /* CR8-store exiting */
2563 "\026TPR" /* Use TPR shadow */
2564 "\027NMIWIN" /* NMI-window exiting */
2565 "\030MOV-DR" /* MOV-DR exiting */
2566 "\031IO" /* Unconditional I/O exiting */
2567 "\032IOmap" /* Use I/O bitmaps */
2568 "\034MTF" /* Monitor trap flag */
2569 "\035MSRmap" /* Use MSR bitmaps */
2570 "\036MONITOR" /* MONITOR exiting */
2571 "\037PAUSE" /* PAUSE exiting */
2572 );
2573 if (proc & PROCBASED_SECONDARY_CONTROLS)
2574 printf("\n Secondary Processor Controls=0x%b", proc2,
2575 "\020"
2576 "\001APIC" /* Virtualize APIC accesses */
2577 "\002EPT" /* Enable EPT */
2578 "\003DT" /* Descriptor-table exiting */
2579 "\004RDTSCP" /* Enable RDTSCP */
2580 "\005x2APIC" /* Virtualize x2APIC mode */
2581 "\006VPID" /* Enable VPID */
2582 "\007WBINVD" /* WBINVD exiting */
2583 "\010UG" /* Unrestricted guest */
2584 "\011APIC-reg" /* APIC-register virtualization */
2585 "\012VID" /* Virtual-interrupt delivery */
2586 "\013PAUSE-loop" /* PAUSE-loop exiting */
2587 "\014RDRAND" /* RDRAND exiting */
2588 "\015INVPCID" /* Enable INVPCID */
2589 "\016VMFUNC" /* Enable VM functions */
2590 "\017VMCS" /* VMCS shadowing */
2591 "\020EPT#VE" /* EPT-violation #VE */
2592 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2593 );
2594 printf("\n Exit Controls=0x%b", mask,
2595 "\020"
2596 "\003DR" /* Save debug controls */
2597 /* Ignore Host address-space size */
2598 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2599 "\020AckInt" /* Acknowledge interrupt on exit */
2600 "\023PAT-SV" /* Save MSR_PAT */
2601 "\024PAT-LD" /* Load MSR_PAT */
2602 "\025EFER-SV" /* Save MSR_EFER */
2603 "\026EFER-LD" /* Load MSR_EFER */
2604 "\027PTMR-SV" /* Save VMX-preemption timer value */
2605 );
2606 printf("\n Entry Controls=0x%b", mask,
2607 "\020"
2608 "\003DR" /* Save debug controls */
2609 /* Ignore IA-32e mode guest */
2610 /* Ignore Entry to SMM */
2611 /* Ignore Deactivate dual-monitor treatment */
2612 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2613 "\017PAT" /* Load MSR_PAT */
2614 "\020EFER" /* Load MSR_EFER */
2615 );
2616 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2617 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2618 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2619 mask = msr;
2620 printf("\n EPT Features=0x%b", mask,
2621 "\020"
2622 "\001XO" /* Execute-only translations */
2623 "\007PW4" /* Page-walk length of 4 */
2624 "\011UC" /* EPT paging-structure mem can be UC */
2625 "\017WB" /* EPT paging-structure mem can be WB */
2626 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2627 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2628 "\025INVEPT" /* INVEPT is supported */
2629 "\026AD" /* Accessed and dirty flags for EPT */
2630 "\032single" /* INVEPT single-context type */
2631 "\033all" /* INVEPT all-context type */
2632 );
2633 mask = msr >> 32;
2634 printf("\n VPID Features=0x%b", mask,
2635 "\020"
2636 "\001INVVPID" /* INVVPID is supported */
2637 "\011individual" /* INVVPID individual-address type */
2638 "\012single" /* INVVPID single-context type */
2639 "\013all" /* INVVPID all-context type */
2640 /* INVVPID single-context-retaining-globals type */
2641 "\014single-globals"
2642 );
2643 }
2644 }
2645
2646 static void
print_hypervisor_info(void)2647 print_hypervisor_info(void)
2648 {
2649
2650 if (*hv_vendor != '\0')
2651 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2652 }
2653
2654 /*
2655 * Returns the maximum physical address that can be used with the
2656 * current system.
2657 */
2658 vm_paddr_t
cpu_getmaxphyaddr(void)2659 cpu_getmaxphyaddr(void)
2660 {
2661
2662 #if defined(__i386__)
2663 if (!pae_mode)
2664 return (0xffffffff);
2665 #endif
2666 return ((1ULL << cpu_maxphyaddr) - 1);
2667 }
2668