1 /* $NetBSD: cs89x0.c,v 1.52 2022/09/18 17:21:18 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2004 Christopher Gilbert
5 * All rights reserved.
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the company nor the name of the author may be used to
13 * endorse or promote products derived from this software without specific
14 * prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * Copyright 1997
31 * Digital Equipment Corporation. All rights reserved.
32 *
33 * This software is furnished under license and may be used and
34 * copied only in accordance with the following terms and conditions.
35 * Subject to these conditions, you may download, copy, install,
36 * use, modify and distribute this software in source and/or binary
37 * form. No title or ownership is transferred hereby.
38 *
39 * 1) Any source code used, modified or distributed must reproduce
40 * and retain this copyright notice and list of conditions as
41 * they appear in the source file.
42 *
43 * 2) No right is granted to use any trade name, trademark, or logo of
44 * Digital Equipment Corporation. Neither the "Digital Equipment
45 * Corporation" name nor any trademark or logo of Digital Equipment
46 * Corporation may be used to endorse or promote products derived
47 * from this software without the prior written permission of
48 * Digital Equipment Corporation.
49 *
50 * 3) This software is provided "AS-IS" and any express or implied
51 * warranties, including but not limited to, any implied warranties
52 * of merchantability, fitness for a particular purpose, or
53 * non-infringement are disclaimed. In no event shall DIGITAL be
54 * liable for any damages whatsoever, and in particular, DIGITAL
55 * shall not be liable for special, indirect, consequential, or
56 * incidental damages or damages for lost profits, loss of
57 * revenue or loss of use, whether such damages arise in contract,
58 * negligence, tort, under statute, in equity, at law or otherwise,
59 * even if advised of the possibility of such damage.
60 */
61
62 /*
63 **++
64 ** FACILITY
65 **
66 ** Device Driver for the Crystal CS8900 ISA Ethernet Controller.
67 **
68 ** ABSTRACT
69 **
70 ** This module provides standard ethernet access for INET protocols
71 ** only.
72 **
73 ** AUTHORS
74 **
75 ** Peter Dettori SEA - Software Engineering.
76 **
77 ** CREATION DATE:
78 **
79 ** 13-Feb-1997.
80 **
81 ** MODIFICATION HISTORY (Digital):
82 **
83 ** Revision 1.27 1998/01/20 17:59:40 cgd
84 ** update for moved headers
85 **
86 ** Revision 1.26 1998/01/12 19:29:36 cgd
87 ** use arm32/isa versions of isadma code.
88 **
89 ** Revision 1.25 1997/12/12 01:35:27 cgd
90 ** convert to use new arp code (from Brini)
91 **
92 ** Revision 1.24 1997/12/10 22:31:56 cgd
93 ** trim some fat (get rid of ability to explicitly supply enet addr, since
94 ** it was never used and added a bunch of code which really doesn't belong in
95 ** an enet driver), and clean up slightly.
96 **
97 ** Revision 1.23 1997/10/06 16:42:12 cgd
98 ** copyright notices
99 **
100 ** Revision 1.22 1997/06/20 19:38:01 chaiken
101 ** fixes some smartcard problems
102 **
103 ** Revision 1.21 1997/06/10 02:56:20 grohn
104 ** Added call to ledNetActive
105 **
106 ** Revision 1.20 1997/06/05 00:47:06 dettori
107 ** Changed cs_process_rx_dma to reset and re-initialise the
108 ** ethernet chip when DMA gets out of sync, or mbufs
109 ** can't be allocated.
110 **
111 ** Revision 1.19 1997/06/03 03:09:58 dettori
112 ** Turn off sc_txbusy flag when a transmit underrun
113 ** occurs.
114 **
115 ** Revision 1.18 1997/06/02 00:04:35 dettori
116 ** redefined the transmit table to get around the nfs_timer bug while we are
117 ** looking into it further.
118 **
119 ** Also changed interrupts from EDGE to LEVEL.
120 **
121 ** Revision 1.17 1997/05/27 23:31:01 dettori
122 ** Pulled out changes to DMAMODE defines.
123 **
124 ** Revision 1.16 1997/05/23 04:25:16 cgd
125 ** reformat log so it fits in 80cols
126 **
127 ** Revision 1.15 1997/05/23 04:22:18 cgd
128 ** remove the existing copyright notice (which Peter Dettori indicated
129 ** was incorrect, copied from an existing NetBSD file only so that the
130 ** file would have a copyright notice on it, and which he'd intended to
131 ** replace). Replace it with a Digital copyright notice, cloned from
132 ** ess.c. It's not really correct either (it indicates that the source
133 ** is Digital confidential!), but is better than nothing and more
134 ** correct than what was there before.
135 **
136 ** Revision 1.14 1997/05/23 04:12:50 cgd
137 ** use an adaptive transmit start algorithm: start by telling the chip
138 ** to start transmitting after 381 bytes have been fed to it. if that
139 ** gets transmit underruns, ramp down to 1021 bytes then "whole
140 ** packet." If successful at a given level for a while, try the next
141 ** more aggressive level. This code doesn't ever try to start
142 ** transmitting after 5 bytes have been sent to the NIC, because
143 ** that underruns rather regularly. The back-off and ramp-up mechanism
144 ** could probably be tuned a little bit, but this works well enough to
145 ** support > 1MB/s transmit rates on a clear ethernet (which is about
146 ** 20-25% better than the driver had previously been getting).
147 **
148 ** Revision 1.13 1997/05/22 21:06:54 cgd
149 ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly
150 ** casting from uint8_t * to uint16_t * without worrying about alignment
151 ** issues. This would cause bogus data to be spit out for mbufs with
152 ** misaligned data. For instance, it caused the following bits to appear
153 ** on the wire:
154 ** ... etBND 1S2C .SHA(K) R ...
155 ** 11112222333344445555
156 ** which should have appeared as:
157 ** ... NetBSD 1.2C (SHARK) ...
158 ** 11112222333344445555
159 ** Note the apparent 'rotate' of the bytes in the word, which was due to
160 ** incorrect unaligned accesses. This data corruption was the cause of
161 ** incoming telnet/rlogin hangs.
162 **
163 ** Revision 1.12 1997/05/22 01:55:32 cgd
164 ** reformat log so it fits in 80cols
165 **
166 ** Revision 1.11 1997/05/22 01:50:27 cgd
167 ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case,
168 ** so packets aimed at other hosts don't get sent to ether_input().
169 ** * Add a static const char *rcsid initialized with an RCS Id tag, so that
170 ** you can easily tell (`strings`) what version of the driver is in your
171 ** kernel binary.
172 ** * get rid of ether_cmp(). It was inconsistently used, not necessarily
173 ** safe, and not really a performance win anyway. (It was only used when
174 ** setting up the multicast logical address filter, which is an
175 ** infrequent event. It could have been used in the IFF_PROMISCUOUS
176 ** address check above, but the benefit of it vs. memcmp would be
177 ** inconsequential, there.) Use memcmp() instead.
178 ** * restructure csStartOutput to avoid the following bugs in the case where
179 ** txWait was being set:
180 ** * it would accidentally drop the outgoing packet if told to wait
181 ** but the outgoing packet queue was empty.
182 ** * it would bpf_mtap() the outgoing packet multiple times (once for
183 ** each time it was told to wait), and would also recalculate
184 ** the length of the outgoing packet each time it was told to
185 ** wait.
186 ** While there, rename txWait to txLoop, since with the new structure of
187 ** the code, the latter name makes more sense.
188 **
189 ** Revision 1.10 1997/05/19 02:03:20 cgd
190 ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip()
191 ** is the only caller of cs_set_ladr_filt(), and always calls it, so this
192 ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC
193 ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave
194 ** as before.
195 **
196 ** Revision 1.9 1997/05/19 01:45:37 cgd
197 ** create a new function, cs_ether_input(), which does received-packet
198 ** BPF and ether_input processing. This code used to be in three places,
199 ** and centralizing it will make adding IFF_PROMISC support much easier.
200 ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to
201 ** do copies with bus_space_write_region_2(). It's more correct, and
202 ** potentially more efficient. That function needs to be gutted (to
203 ** deal properly with alignment issues, which it currently does wrong),
204 ** however, and the change doesn't gain much, so there's no point in
205 ** enabling it now.
206 **
207 ** Revision 1.8 1997/05/19 01:17:10 cgd
208 ** fix a comment re: the setting of the TxConfig register. Clean up
209 ** interface counter maintenance (make it use standard idiom).
210 **
211 **--
212 */
213
214 #include <sys/cdefs.h>
215 __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.52 2022/09/18 17:21:18 thorpej Exp $");
216
217 #include "opt_inet.h"
218
219 #include <sys/param.h>
220 #include <sys/systm.h>
221 #include <sys/mbuf.h>
222 #include <sys/syslog.h>
223 #include <sys/socket.h>
224 #include <sys/device.h>
225 #include <sys/malloc.h>
226 #include <sys/ioctl.h>
227 #include <sys/errno.h>
228 #include <sys/bus.h>
229 #include <sys/intr.h>
230 #include <sys/rndsource.h>
231
232 #include <net/if.h>
233 #include <net/if_ether.h>
234 #include <net/if_media.h>
235 #include <net/bpf.h>
236
237 #ifdef INET
238 #include <netinet/in.h>
239 #include <netinet/if_inarp.h>
240 #endif
241
242 #include <dev/ic/cs89x0reg.h>
243 #include <dev/ic/cs89x0var.h>
244
245 #ifdef SHARK
246 #include <shark/shark/sequoia.h>
247 #endif
248
249 /*
250 * MACRO DEFINITIONS
251 */
252 #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */
253
254 /*
255 * FUNCTION PROTOTYPES
256 */
257 static void cs_get_default_media(struct cs_softc *);
258 static int cs_get_params(struct cs_softc *);
259 static int cs_get_enaddr(struct cs_softc *);
260 static int cs_reset_chip(struct cs_softc *);
261 static void cs_reset(struct cs_softc *);
262 static int cs_ioctl(struct ifnet *, u_long, void *);
263 static void cs_initChip(struct cs_softc *);
264 static void cs_buffer_event(struct cs_softc *, uint16_t);
265 static void cs_transmit_event(struct cs_softc *, uint16_t);
266 static void cs_receive_event(struct cs_softc *, uint16_t);
267 static void cs_process_receive(struct cs_softc *);
268 static void cs_process_rx_early(struct cs_softc *);
269 static void cs_start_output(struct ifnet *);
270 static void cs_copy_tx_frame(struct cs_softc *, struct mbuf *);
271 static void cs_set_ladr_filt(struct cs_softc *, struct ethercom *);
272 static uint16_t cs_hash_index(char *);
273 static void cs_counter_event(struct cs_softc *, uint16_t);
274
275 static int cs_mediachange(struct ifnet *);
276 static void cs_mediastatus(struct ifnet *, struct ifmediareq *);
277
278 static bool cs_shutdown(device_t, int);
279 static int cs_enable(struct cs_softc *);
280 static void cs_disable(struct cs_softc *);
281 static void cs_stop(struct ifnet *, int);
282 static int cs_scan_eeprom(struct cs_softc *);
283 static int cs_read_pktpg_from_eeprom(struct cs_softc *, int, uint16_t *);
284
285
286 /*
287 * GLOBAL DECLARATIONS
288 */
289
290 /*
291 * Xmit-early table.
292 *
293 * To get better performance, we tell the chip to start packet
294 * transmission before the whole packet is copied to the chip.
295 * However, this can fail under load. When it fails, we back off
296 * to a safer setting for a little while.
297 *
298 * txcmd is the value of txcmd used to indicate when to start transmission.
299 * better is the next 'better' state in the table.
300 * better_count is the number of output packets before transition to the
301 * better state.
302 * worse is the next 'worse' state in the table.
303 *
304 * Transition to the next worse state happens automatically when a
305 * transmittion underrun occurs.
306 */
307 struct cs_xmit_early {
308 uint16_t txcmd;
309 int better;
310 int better_count;
311 int worse;
312 } cs_xmit_early_table[3] = {
313 { TX_CMD_START_381, 0, INT_MAX, 1, },
314 { TX_CMD_START_1021, 0, 50000, 2, },
315 { TX_CMD_START_ALL, 1, 5000, 2, },
316 };
317
318 int cs_default_media[] = {
319 IFM_ETHER | IFM_10_2,
320 IFM_ETHER | IFM_10_5,
321 IFM_ETHER | IFM_10_T,
322 IFM_ETHER | IFM_10_T | IFM_FDX,
323 };
324 int cs_default_nmedia = __arraycount(cs_default_media);
325
326 int
cs_attach(struct cs_softc * sc,uint8_t * enaddr,int * media,int nmedia,int defmedia)327 cs_attach(struct cs_softc *sc, uint8_t *enaddr, int *media,
328 int nmedia, int defmedia)
329 {
330 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
331 const char *chipname, *medname;
332 uint16_t reg;
333 int i;
334
335 /* Start out in IO mode */
336 sc->sc_memorymode = FALSE;
337
338 /* Make sure we're right */
339 for (i = 0; i < 10000; i++) {
340 reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM);
341 if (reg == EISA_NUM_CRYSTAL)
342 break;
343 }
344 if (i == 10000) {
345 aprint_error_dev(sc->sc_dev, "wrong id(0x%x)\n", reg);
346 return 1; /* XXX should panic? */
347 }
348
349 reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID);
350 sc->sc_prodid = reg & PROD_ID_MASK;
351 sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8;
352
353 switch (sc->sc_prodid) {
354 case PROD_ID_CS8900:
355 chipname = "CS8900";
356 break;
357 case PROD_ID_CS8920:
358 chipname = "CS8920";
359 break;
360 case PROD_ID_CS8920M:
361 chipname = "CS8920M";
362 break;
363 default:
364 panic("cs_attach: impossible");
365 }
366
367 /*
368 * The first thing to do is check that the mbuf cluster size is
369 * greater than the MTU for an ethernet frame. The code depends on
370 * this and to port this to a OS where this was not the case would
371 * not be straightforward.
372 *
373 * We need 1 byte spare because our packet read loop can overrun.
374 * and we may need pad bytes to align ip header.
375 */
376 if (MCLBYTES < ETHER_MAX_LEN + 1 + ALIGN(sizeof(struct ether_header))
377 - sizeof(struct ether_header)) {
378 printf("%s: MCLBYTES too small for Ethernet frame\n",
379 device_xname(sc->sc_dev));
380 return 1;
381 }
382
383 /* Start out not transmitting */
384 sc->sc_txbusy = FALSE;
385
386 /* Set up early transmit threshold */
387 sc->sc_xe_ent = 0;
388 sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count;
389
390 /* Initialize ifnet structure. */
391 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
392 ifp->if_softc = sc;
393 ifp->if_start = cs_start_output;
394 ifp->if_init = cs_init;
395 ifp->if_ioctl = cs_ioctl;
396 ifp->if_stop = cs_stop;
397 ifp->if_watchdog = NULL; /* No watchdog at this stage */
398 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
399 IFQ_SET_READY(&ifp->if_snd);
400
401 /* Initialize ifmedia structures. */
402 sc->sc_ethercom.ec_ifmedia = &sc->sc_media;
403 ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus);
404
405 if (media != NULL) {
406 for (i = 0; i < nmedia; i++)
407 ifmedia_add(&sc->sc_media, media[i], 0, NULL);
408 ifmedia_set(&sc->sc_media, defmedia);
409 } else {
410 for (i = 0; i < cs_default_nmedia; i++)
411 ifmedia_add(&sc->sc_media, cs_default_media[i],
412 0, NULL);
413 cs_get_default_media(sc);
414 }
415
416 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) {
417 if (cs_scan_eeprom(sc) == CS_ERROR) {
418 /*
419 * Failed to scan the eeprom, pretend there isn't an
420 * eeprom
421 */
422 aprint_error_dev(sc->sc_dev,
423 "unable to scan EEPROM\n");
424 sc->sc_cfgflags |= CFGFLG_NOT_EEPROM;
425 }
426 }
427
428 if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) {
429 /* Get parameters from the EEPROM */
430 if (cs_get_params(sc) == CS_ERROR) {
431 aprint_error_dev(sc->sc_dev,
432 "unable to get settings from EEPROM\n");
433 return 1;
434 }
435 }
436
437 if (enaddr != NULL)
438 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr));
439 else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) {
440 /* Get and store the Ethernet address */
441 if (cs_get_enaddr(sc) == CS_ERROR) {
442 aprint_error_dev(sc->sc_dev,
443 "unable to read Ethernet address\n");
444 return 1;
445 }
446 } else {
447 #if 1
448 int j;
449 uint v;
450
451 for (j = 0; j < 6; j += 2) {
452 v = CS_READ_PACKET_PAGE(sc, PKTPG_IND_ADDR + j);
453 sc->sc_enaddr[j + 0] = v;
454 sc->sc_enaddr[j + 1] = v >> 8;
455 }
456 #else
457 printf("%s: no Ethernet address!\n", device_xname(sc->sc_dev));
458 return 1;
459 #endif
460 }
461
462 switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) {
463 case IFM_10_2:
464 medname = "BNC";
465 break;
466 case IFM_10_5:
467 medname = "AUI";
468 break;
469 case IFM_10_T:
470 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX)
471 medname = "UTP <full-duplex>";
472 else
473 medname = "UTP";
474 break;
475 default:
476 panic("cs_attach: impossible");
477 }
478 printf("%s: %s rev. %c, address %s, media %s\n",
479 device_xname(sc->sc_dev),
480 chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr),
481 medname);
482
483 if (sc->sc_dma_attach)
484 (*sc->sc_dma_attach)(sc);
485
486 /* Attach the interface. */
487 if_attach(ifp);
488 if_deferred_start_init(ifp, NULL);
489 ether_ifattach(ifp, sc->sc_enaddr);
490
491 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
492 RND_TYPE_NET, RND_FLAG_DEFAULT);
493 sc->sc_cfgflags |= CFGFLG_ATTACHED;
494
495 if (pmf_device_register1(sc->sc_dev, NULL, NULL, cs_shutdown))
496 pmf_class_network_register(sc->sc_dev, ifp);
497 else
498 aprint_error_dev(sc->sc_dev,
499 "couldn't establish power handler\n");
500
501 /* Reset the chip */
502 if (cs_reset_chip(sc) == CS_ERROR) {
503 aprint_error_dev(sc->sc_dev, "reset failed\n");
504 cs_detach(sc);
505 return 1;
506 }
507
508 return 0;
509 }
510
511 int
cs_detach(struct cs_softc * sc)512 cs_detach(struct cs_softc *sc)
513 {
514 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
515
516 if (sc->sc_cfgflags & CFGFLG_ATTACHED) {
517 rnd_detach_source(&sc->rnd_source);
518 ether_ifdetach(ifp);
519 if_detach(ifp);
520 ifmedia_fini(&sc->sc_media);
521 sc->sc_cfgflags &= ~CFGFLG_ATTACHED;
522 }
523
524 #if 0
525 /* XXX not necessary */
526 if (sc->sc_cfgflags & CFGFLG_DMA_MODE) {
527 isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase,
528 sc->sc_dmasize);
529 isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr,
530 sc->sc_dmasize);
531 isa_dmamap_destroy(sc->sc_ic, sc->sc_drq);
532 sc->sc_cfgflags &= ~CFGFLG_DMA_MODE;
533 }
534 #endif
535
536 pmf_device_deregister(sc->sc_dev);
537
538 return 0;
539 }
540
541 bool
cs_shutdown(device_t self,int howto)542 cs_shutdown(device_t self, int howto)
543 {
544 struct cs_softc *sc;
545
546 sc = device_private(self);
547 cs_reset(sc);
548
549 return true;
550 }
551
552 void
cs_get_default_media(struct cs_softc * sc)553 cs_get_default_media(struct cs_softc *sc)
554 {
555 uint16_t adp_cfg, xmit_ctl;
556
557 if (cs_verify_eeprom(sc) == CS_ERROR) {
558 aprint_error_dev(sc->sc_dev,
559 "cs_get_default_media: EEPROM missing or bad\n");
560 goto fakeit;
561 }
562
563 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adp_cfg) == CS_ERROR) {
564 aprint_error_dev(sc->sc_dev,
565 "unable to read adapter config from EEPROM\n");
566 goto fakeit;
567 }
568
569 if (cs_read_eeprom(sc, EEPROM_XMIT_CTL, &xmit_ctl) == CS_ERROR) {
570 aprint_error_dev(sc->sc_dev,
571 "unable to read transmit control from EEPROM\n");
572 goto fakeit;
573 }
574
575 switch (adp_cfg & ADPTR_CFG_MEDIA) {
576 case ADPTR_CFG_AUI:
577 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_10_5);
578 break;
579 case ADPTR_CFG_10BASE2:
580 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_10_2);
581 break;
582 case ADPTR_CFG_10BASET:
583 default:
584 if (xmit_ctl & XMIT_CTL_FDX)
585 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_10_T
586 | IFM_FDX);
587 else
588 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_10_T);
589 break;
590 }
591 return;
592
593 fakeit:
594 aprint_error_dev(sc->sc_dev,
595 "WARNING: default media setting may be inaccurate\n");
596 /* XXX Arbitrary... */
597 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_10_T);
598 }
599
600 /*
601 * cs_scan_eeprom
602 *
603 * Attempt to take a complete copy of the eeprom into main memory.
604 * this will allow faster parsing of the eeprom data.
605 *
606 * Only tested against a 8920M's eeprom, but the data sheet for the
607 * 8920A indicates that is uses the same layout.
608 */
609 int
cs_scan_eeprom(struct cs_softc * sc)610 cs_scan_eeprom(struct cs_softc *sc)
611 {
612 uint16_t result;
613 int i;
614 int eeprom_size;
615 uint8_t checksum = 0;
616
617 if (cs_verify_eeprom(sc) == CS_ERROR) {
618 aprint_error_dev(sc->sc_dev,
619 "cs_scan_params: EEPROM missing or bad\n");
620 return CS_ERROR;
621 }
622
623 /*
624 * Read the 0th word from the eeprom, it will tell us the length
625 * and if the eeprom is valid
626 */
627 cs_read_eeprom(sc, 0, &result);
628
629 /* Check the eeprom signature */
630 if ((result & 0xE000) != 0xA000) {
631 /* Empty eeprom */
632 return CS_ERROR;
633 }
634
635 /*
636 * Take the eeprom size (note the read value doesn't include the header
637 * word)
638 */
639 eeprom_size = (result & 0xff) + 2;
640
641 sc->eeprom_data = malloc(eeprom_size, M_DEVBUF, M_WAITOK);
642 if (sc->eeprom_data == NULL) {
643 /* No memory, treat this as if there's no eeprom */
644 return CS_ERROR;
645 }
646
647 sc->eeprom_size = eeprom_size;
648
649 /* Read the eeprom into the buffer, also calculate the checksum */
650 for (i = 0; i < (eeprom_size >> 1); i++) {
651 cs_read_eeprom(sc, i, &(sc->eeprom_data[i]));
652 checksum += (sc->eeprom_data[i] & 0xff00) >> 8;
653 checksum += (sc->eeprom_data[i] & 0x00ff);
654 }
655
656 /*
657 * Validate checksum calculation, the sum of all the bytes should be 0,
658 * as the high byte of the last word is the 2's complement of the
659 * sum to that point.
660 */
661 if (checksum != 0) {
662 aprint_error_dev(sc->sc_dev, "eeprom checksum failure\n");
663 return CS_ERROR;
664 }
665
666 return CS_OK;
667 }
668
669 static int
cs_read_pktpg_from_eeprom(struct cs_softc * sc,int pktpg,uint16_t * pValue)670 cs_read_pktpg_from_eeprom(struct cs_softc *sc, int pktpg, uint16_t *pValue)
671 {
672 int x, maxword;
673
674 /* Check that we have eeprom data */
675 if ((sc->eeprom_data == NULL) || (sc->eeprom_size < 2))
676 return CS_ERROR;
677
678 /*
679 * We only want to read the data words, the last word contains the
680 * checksum
681 */
682 maxword = (sc->eeprom_size - 2) >> 1;
683
684 /* Start 1 word in, as the first word is the length and signature */
685 x = 1;
686
687 while ( x < (maxword)) {
688 uint16_t header;
689 int group_size;
690 int offset;
691 int offset_max;
692
693 /* Read in the group header word */
694 header = sc->eeprom_data[x];
695 x++; /* Skip group header */
696
697 /*
698 * Size of group in words is in the top 4 bits, note that it
699 * is one less than the number of words
700 */
701 group_size = header & 0xF000;
702
703 /*
704 * CS8900 Data sheet says this should be 0x01ff,
705 * but my cs8920 eeprom has higher offsets,
706 * perhaps the 8920 allows higher offsets, otherwise
707 * it's writing to places that it shouldn't
708 */
709 /* Work out the offsets this group covers */
710 offset = header & 0x0FFF;
711 offset_max = offset + (group_size << 1);
712
713 /* Check if the pkgpg we're after is in this group */
714 if ((offset <= pktpg) && (pktpg <= offset_max)) {
715 /* The pkgpg value we want is in here */
716 int eeprom_location;
717
718 eeprom_location = ((pktpg - offset) >> 1) ;
719
720 *pValue = sc->eeprom_data[x + eeprom_location];
721 return CS_OK;
722 } else {
723 /* Skip this group (+ 1 for first entry) */
724 x += group_size + 1;
725 }
726 }
727
728 /*
729 * If we've fallen out here then we don't have a value in the EEPROM
730 * for this pktpg so return an error
731 */
732 return CS_ERROR;
733 }
734
735 int
cs_get_params(struct cs_softc * sc)736 cs_get_params(struct cs_softc *sc)
737 {
738 uint16_t isaConfig;
739 uint16_t adapterConfig;
740
741 if (cs_verify_eeprom(sc) == CS_ERROR) {
742 aprint_error_dev(sc->sc_dev,
743 "cs_get_params: EEPROM missing or bad\n");
744 return CS_ERROR;
745 }
746
747 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) {
748 /* Get ISA configuration from the EEPROM */
749 if (cs_read_pktpg_from_eeprom(sc, PKTPG_BUS_CTL, &isaConfig)
750 == CS_ERROR) {
751 /*
752 * Eeprom doesn't have this value, use data sheet
753 * default
754 */
755 isaConfig = 0x0017;
756 }
757
758 /* Get adapter configuration from the EEPROM */
759 if (cs_read_pktpg_from_eeprom(sc, PKTPG_SELF_CTL,
760 &adapterConfig) == CS_ERROR) {
761 /*
762 * Eeprom doesn't have this value, use data sheet
763 * default
764 */
765 adapterConfig = 0x0015;
766 }
767
768 /* Copy the USE_SA flag */
769 if (isaConfig & BUS_CTL_USE_SA)
770 sc->sc_cfgflags |= CFGFLG_USE_SA;
771
772 /* Copy the IO Channel Ready flag */
773 if (isaConfig & BUS_CTL_IOCHRDY)
774 sc->sc_cfgflags |= CFGFLG_IOCHRDY;
775
776 /* Copy the DC/DC Polarity flag */
777 if (adapterConfig & SELF_CTL_HCB1)
778 sc->sc_cfgflags |= CFGFLG_DCDC_POL;
779 } else {
780 /* Get ISA configuration from the EEPROM */
781 if (cs_read_eeprom(sc, EEPROM_ISA_CFG, &isaConfig) == CS_ERROR)
782 goto eeprom_bad;
783
784 /* Get adapter configuration from the EEPROM */
785 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adapterConfig)
786 == CS_ERROR)
787 goto eeprom_bad;
788
789 /* Copy the USE_SA flag */
790 if (isaConfig & ISA_CFG_USE_SA)
791 sc->sc_cfgflags |= CFGFLG_USE_SA;
792
793 /* Copy the IO Channel Ready flag */
794 if (isaConfig & ISA_CFG_IOCHRDY)
795 sc->sc_cfgflags |= CFGFLG_IOCHRDY;
796
797 /* Copy the DC/DC Polarity flag */
798 if (adapterConfig & ADPTR_CFG_DCDC_POL)
799 sc->sc_cfgflags |= CFGFLG_DCDC_POL;
800 }
801
802 return CS_OK;
803 eeprom_bad:
804 aprint_error_dev(sc->sc_dev,
805 "cs_get_params: unable to read from EEPROM\n");
806 return CS_ERROR;
807 }
808
809 int
cs_get_enaddr(struct cs_softc * sc)810 cs_get_enaddr(struct cs_softc *sc)
811 {
812 uint16_t myea[ETHER_ADDR_LEN / sizeof(uint16_t)];
813 int i;
814
815 if (cs_verify_eeprom(sc) == CS_ERROR) {
816 aprint_error_dev(sc->sc_dev,
817 "cs_get_enaddr: EEPROM missing or bad\n");
818 return CS_ERROR;
819 }
820
821 /* Get Ethernet address from the EEPROM */
822 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) {
823 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR, &myea[0])
824 == CS_ERROR)
825 goto eeprom_bad;
826 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 2, &myea[1])
827 == CS_ERROR)
828 goto eeprom_bad;
829 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 4, &myea[2])
830 == CS_ERROR)
831 goto eeprom_bad;
832 } else {
833 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_H, &myea[0]) == CS_ERROR)
834 goto eeprom_bad;
835 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_M, &myea[1]) == CS_ERROR)
836 goto eeprom_bad;
837 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_L, &myea[2]) == CS_ERROR)
838 goto eeprom_bad;
839 }
840
841 for (i = 0; i < __arraycount(myea); i++) {
842 sc->sc_enaddr[i * 2 + 0] = myea[i];
843 sc->sc_enaddr[i * 2 + 1] = myea[i] >> 8;
844 }
845
846 return CS_OK;
847
848 eeprom_bad:
849 aprint_error_dev(sc->sc_dev,
850 "cs_get_enaddr: unable to read from EEPROM\n");
851 return CS_ERROR;
852 }
853
854 int
cs_reset_chip(struct cs_softc * sc)855 cs_reset_chip(struct cs_softc *sc)
856 {
857 int intState;
858 int x;
859
860 /* Disable interrupts at the CPU so reset command is atomic */
861 intState = splnet();
862
863 /*
864 * We are now resetting the chip
865 *
866 * A spurious interrupt is generated by the chip when it is reset. This
867 * variable informs the interrupt handler to ignore this interrupt.
868 */
869 sc->sc_resetting = TRUE;
870
871 /* Issue a reset command to the chip */
872 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET);
873
874 /* Re-enable interrupts at the CPU */
875 splx(intState);
876
877 /* The chip is always in IO mode after a reset */
878 sc->sc_memorymode = FALSE;
879
880 /* If transmission was in progress, it is not now */
881 sc->sc_txbusy = FALSE;
882
883 /*
884 * There was a delay(125); here, but it seems uneccesary 125 usec is
885 * 1/8000 of a second, not 1/8 of a second. the data sheet advises
886 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below
887 * should be sufficient.
888 */
889
890 /* Transition SBHE to switch chip from 8-bit to 16-bit */
891 IO_READ_1(sc, PORT_PKTPG_PTR + 0);
892 IO_READ_1(sc, PORT_PKTPG_PTR + 1);
893 IO_READ_1(sc, PORT_PKTPG_PTR + 0);
894 IO_READ_1(sc, PORT_PKTPG_PTR + 1);
895
896 /* Wait until the EEPROM is not busy */
897 for (x = 0; x < MAXLOOP; x++) {
898 if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY))
899 break;
900 }
901
902 if (x == MAXLOOP)
903 return CS_ERROR;
904
905 /* Wait until initialization is done */
906 for (x = 0; x < MAXLOOP; x++) {
907 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE)
908 break;
909 }
910
911 if (x == MAXLOOP)
912 return CS_ERROR;
913
914 /* Reset is no longer in progress */
915 sc->sc_resetting = FALSE;
916
917 return CS_OK;
918 }
919
920 int
cs_verify_eeprom(struct cs_softc * sc)921 cs_verify_eeprom(struct cs_softc *sc)
922 {
923 uint16_t self_status;
924
925 /* Verify that the EEPROM is present and OK */
926 self_status = CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST);
927 if (((self_status & SELF_ST_EEP_PRES) &&
928 (self_status & SELF_ST_EEP_OK)) == 0)
929 return CS_ERROR;
930
931 return CS_OK;
932 }
933
934 int
cs_read_eeprom(struct cs_softc * sc,int offset,uint16_t * pValue)935 cs_read_eeprom(struct cs_softc *sc, int offset, uint16_t *pValue)
936 {
937 int x;
938
939 /* Ensure that the EEPROM is not busy */
940 for (x = 0; x < MAXLOOP; x++) {
941 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) &
942 SELF_ST_SI_BUSY))
943 break;
944 }
945
946 if (x == MAXLOOP)
947 return CS_ERROR;
948
949 /* Issue the command to read the offset within the EEPROM */
950 CS_WRITE_PACKET_PAGE_IO(sc, PKTPG_EEPROM_CMD,
951 offset | EEPROM_CMD_READ);
952
953 /* Wait until the command is completed */
954 for (x = 0; x < MAXLOOP; x++) {
955 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) &
956 SELF_ST_SI_BUSY))
957 break;
958 }
959
960 if (x == MAXLOOP)
961 return CS_ERROR;
962
963 /* Get the EEPROM data from the EEPROM Data register */
964 *pValue = CS_READ_PACKET_PAGE_IO(sc, PKTPG_EEPROM_DATA);
965
966 return CS_OK;
967 }
968
969 void
cs_initChip(struct cs_softc * sc)970 cs_initChip(struct cs_softc *sc)
971 {
972 uint16_t busCtl;
973 uint16_t selfCtl;
974 uint16_t v;
975 uint16_t isaId;
976 int i;
977 int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media);
978
979 /* Disable reception and transmission of frames */
980 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL,
981 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) &
982 ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON);
983
984 /* Disable interrupt at the chip */
985 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
986 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL);
987
988 /* If IOCHRDY is enabled then clear the bit in the busCtl register */
989 busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL);
990 if (sc->sc_cfgflags & CFGFLG_IOCHRDY) {
991 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
992 busCtl & ~BUS_CTL_IOCHRDY);
993 } else {
994 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
995 busCtl | BUS_CTL_IOCHRDY);
996 }
997
998 /* Set the Line Control register to match the media type */
999 if (media == IFM_10_T)
1000 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET);
1001 else
1002 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY);
1003
1004 /*
1005 * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to
1006 * enable the DC/DC converter
1007 */
1008 selfCtl = SELF_CTL_HC1E;
1009
1010 /* If the media type is 10Base2 */
1011 if (media == IFM_10_2) {
1012 /* Enable the DC/DC converter if it has a low enable. */
1013 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0)
1014 /*
1015 * Set the HCB1 bit, which causes the HC1 pin to go
1016 * low.
1017 */
1018 selfCtl |= SELF_CTL_HCB1;
1019 } else { /* Media type is 10BaseT or AUI */
1020 /* Disable the DC/DC converter if it has a high enable. */
1021 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) {
1022 /*
1023 * Set the HCB1 bit, which causes the HC1 pin to go
1024 * low.
1025 */
1026 selfCtl |= SELF_CTL_HCB1;
1027 }
1028 }
1029 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl);
1030
1031 /* Enable normal link pulse */
1032 if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M)
1033 CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE);
1034
1035 /* Enable full-duplex, if appropriate */
1036 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX)
1037 CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX);
1038
1039 /* RX_CTL set in cs_set_ladr_filt(), below */
1040
1041 /* Enable all transmission interrupts */
1042 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE);
1043
1044 /* Accept all receive interrupts */
1045 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE);
1046
1047 /*
1048 * Configure Operational Modes
1049 *
1050 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this
1051 * is a better way to do it because the card has a counter which can be
1052 * read to update the RX_MISS counter. This saves many interrupts.
1053 *
1054 * I have turned on the tx and rx overflow interrupts to counter using
1055 * the receive miss interrupt. This is a better estimate of errors
1056 * and requires lower system overhead.
1057 */
1058 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE |
1059 BUF_CFG_RX_DMA_IE);
1060
1061 if (sc->sc_dma_chipinit)
1062 (*sc->sc_dma_chipinit)(sc);
1063
1064 /* If memory mode is enabled */
1065 if (sc->sc_cfgflags & CFGFLG_MEM_MODE) {
1066 /* If external logic is present for address decoding */
1067 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) {
1068 /*
1069 * Program the external logic to decode address bits
1070 * SA20-SA23
1071 */
1072 CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD,
1073 ((sc->sc_pktpgaddr & 0xffffff) >> 20) |
1074 EEPROM_CMD_ELSEL);
1075 }
1076
1077 /*
1078 * Write the packet page base physical address to the memory
1079 * base register.
1080 */
1081 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0,
1082 sc->sc_pktpgaddr & 0xFFFF);
1083 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2,
1084 sc->sc_pktpgaddr >> 16);
1085 busCtl = BUS_CTL_MEM_MODE;
1086
1087 /* Tell the chip to read the addresses off the SA pins */
1088 if (sc->sc_cfgflags & CFGFLG_USE_SA) {
1089 busCtl |= BUS_CTL_USE_SA;
1090 }
1091 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
1092 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl);
1093
1094 /* We are in memory mode now! */
1095 sc->sc_memorymode = TRUE;
1096
1097 /*
1098 * Wait here (10ms) for the chip to swap over. this is the
1099 * maximum time that this could take.
1100 */
1101 delay(10000);
1102
1103 /* Verify that we can read from the chip */
1104 isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM);
1105
1106 /*
1107 * As a last minute sanity check before actually using mapped
1108 * memory we verify that we can read the isa number from the
1109 * chip in memory mode.
1110 */
1111 if (isaId != EISA_NUM_CRYSTAL) {
1112 aprint_error_dev(sc->sc_dev,
1113 "failed to enable memory mode\n");
1114 sc->sc_memorymode = FALSE;
1115 } else {
1116 /*
1117 * We are in memory mode so if we aren't using DMA,
1118 * then program the chip to interrupt early.
1119 */
1120 if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) {
1121 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG,
1122 BUF_CFG_RX_DEST_IE |
1123 BUF_CFG_RX_MISS_OVER_IE |
1124 BUF_CFG_TX_COL_OVER_IE);
1125 }
1126 }
1127
1128 }
1129
1130 /* Put Ethernet address into the Individual Address register */
1131 for (i = 0; i < 6; i += 2) {
1132 v = sc->sc_enaddr[i + 0] | (sc->sc_enaddr[i + 1]) << 8;
1133 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + i, v);
1134 }
1135
1136 if (sc->sc_irq != -1) {
1137 /* Set the interrupt level in the chip */
1138 if (sc->sc_prodid == PROD_ID_CS8900) {
1139 if (sc->sc_irq == 5)
1140 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3);
1141 else
1142 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM,
1143 (sc->sc_irq) - 10);
1144 } else { /* CS8920 */
1145 CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM,
1146 sc->sc_irq);
1147 }
1148 }
1149
1150 /* Write the multicast mask to the address filter register */
1151 cs_set_ladr_filt(sc, &sc->sc_ethercom);
1152
1153 /* Enable reception and transmission of frames */
1154 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL,
1155 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) |
1156 LINE_CTL_RX_ON | LINE_CTL_TX_ON);
1157
1158 /* Enable interrupt at the chip */
1159 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
1160 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL);
1161 }
1162
1163 int
cs_init(struct ifnet * ifp)1164 cs_init(struct ifnet *ifp)
1165 {
1166 int intState;
1167 int error = CS_OK;
1168 struct cs_softc *sc = ifp->if_softc;
1169
1170 if (cs_enable(sc))
1171 goto out;
1172
1173 cs_stop(ifp, 0);
1174
1175 intState = splnet();
1176
1177 #if 0
1178 /* Mark the interface as down */
1179 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING);
1180 #endif
1181
1182 #ifdef CS_DEBUG
1183 /* Enable debugging */
1184 sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG;
1185 #endif
1186
1187 /* Reset the chip */
1188 if ((error = cs_reset_chip(sc)) == CS_OK) {
1189 /* Initialize the chip */
1190 cs_initChip(sc);
1191
1192 /* Mark the interface as running */
1193 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING;
1194 sc->sc_ethercom.ec_if.if_timer = 0;
1195
1196 /* Assume we have carrier until we are told otherwise. */
1197 sc->sc_carrier = 1;
1198 } else
1199 aprint_error_dev(sc->sc_dev, "unable to reset chip\n");
1200
1201 splx(intState);
1202 out:
1203 if (error == CS_OK)
1204 return 0;
1205 return EIO;
1206 }
1207
1208 void
cs_set_ladr_filt(struct cs_softc * sc,struct ethercom * ec)1209 cs_set_ladr_filt(struct cs_softc *sc, struct ethercom *ec)
1210 {
1211 struct ifnet *ifp = &ec->ec_if;
1212 struct ether_multi *enm;
1213 struct ether_multistep step;
1214 uint16_t af[4];
1215 uint16_t port, mask, index;
1216
1217 /*
1218 * Set up multicast address filter by passing all multicast addresses
1219 * through a crc generator, and then using the high order 6 bits as an
1220 * index into the 64 bit logical address filter. The high order bit
1221 * selects the word, while the rest of the bits select the bit within
1222 * the word.
1223 */
1224 if (ifp->if_flags & IFF_PROMISC) {
1225 /* Accept all valid frames. */
1226 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL,
1227 RX_CTL_PROMISC_A | RX_CTL_RX_OK_A |
1228 RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A);
1229 ifp->if_flags |= IFF_ALLMULTI;
1230 return;
1231 }
1232
1233 /*
1234 * Accept frames if a. crc valid, b. individual address match c.
1235 * broadcast address,and d. multicast addresses matched in the hash
1236 * filter
1237 */
1238 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL,
1239 RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A);
1240
1241
1242 /*
1243 * Start off with all multicast flag clear, set it if we need to
1244 * later, otherwise we will leave it.
1245 */
1246 ifp->if_flags &= ~IFF_ALLMULTI;
1247 af[0] = af[1] = af[2] = af[3] = 0x0000;
1248
1249 /*
1250 * Loop through all the multicast addresses unless we get a range of
1251 * addresses, in which case we will just accept all packets.
1252 * Justification for this is given in the next comment.
1253 */
1254 ETHER_LOCK(ec);
1255 ETHER_FIRST_MULTI(step, ec, enm);
1256 while (enm != NULL) {
1257 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1258 sizeof enm->enm_addrlo)) {
1259 /*
1260 * We must listen to a range of multicast addresses.
1261 * For now, just accept all multicasts, rather than
1262 * trying to set only those filter bits needed to match
1263 * the range. (At this time, the only use of address
1264 * ranges is for IP multicast routing, for which the
1265 * range is big enough to require all bits set.)
1266 */
1267 ifp->if_flags |= IFF_ALLMULTI;
1268 af[0] = af[1] = af[2] = af[3] = 0xffff;
1269 break;
1270 } else {
1271 /*
1272 * We have got an individual address so just set that
1273 * bit.
1274 */
1275 index = cs_hash_index(enm->enm_addrlo);
1276
1277 /* Set the bit the Logical address filter. */
1278 port = (uint16_t) (index >> 4);
1279 mask = (uint16_t) (1 << (index & 0xf));
1280 af[port] |= mask;
1281
1282 ETHER_NEXT_MULTI(step, enm);
1283 }
1284 }
1285 ETHER_UNLOCK(ec);
1286
1287 /* Now program the chip with the addresses */
1288 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]);
1289 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]);
1290 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]);
1291 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]);
1292 return;
1293 }
1294
1295 uint16_t
cs_hash_index(char * addr)1296 cs_hash_index(char *addr)
1297 {
1298 uint32_t crc;
1299 uint16_t hash_code;
1300
1301 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
1302
1303 hash_code = crc >> 26;
1304 return hash_code;
1305 }
1306
1307 void
cs_reset(struct cs_softc * sc)1308 cs_reset(struct cs_softc *sc)
1309 {
1310
1311 /* Mark the interface as down */
1312 sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING;
1313
1314 /* Reset the chip */
1315 cs_reset_chip(sc);
1316 }
1317
1318 int
cs_ioctl(struct ifnet * ifp,u_long cmd,void * data)1319 cs_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1320 {
1321 struct cs_softc *sc = ifp->if_softc;
1322 int state;
1323 int result;
1324
1325 state = splnet();
1326
1327 result = 0; /* Only set if something goes wrong */
1328
1329 switch (cmd) {
1330 default:
1331 result = ether_ioctl(ifp, cmd, data);
1332 if (result == ENETRESET) {
1333 if (ifp->if_flags & IFF_RUNNING) {
1334 /*
1335 * Multicast list has changed. Set the
1336 * hardware filter accordingly.
1337 */
1338 cs_set_ladr_filt(sc, &sc->sc_ethercom);
1339 }
1340 result = 0;
1341 }
1342 break;
1343 }
1344
1345 splx(state);
1346
1347 return result;
1348 }
1349
1350 int
cs_mediachange(struct ifnet * ifp)1351 cs_mediachange(struct ifnet *ifp)
1352 {
1353
1354 /*
1355 * Current media is already set up. Just reset the interface
1356 * to let the new value take hold.
1357 */
1358 cs_init(ifp);
1359 return 0;
1360 }
1361
1362 void
cs_mediastatus(struct ifnet * ifp,struct ifmediareq * ifmr)1363 cs_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
1364 {
1365 struct cs_softc *sc = ifp->if_softc;
1366
1367 /* The currently selected media is always the active media. */
1368 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media;
1369
1370 if (ifp->if_flags & IFF_UP) {
1371 /* Interface up, status is valid. */
1372 ifmr->ifm_status = IFM_AVALID |
1373 (sc->sc_carrier ? IFM_ACTIVE : 0);
1374 }
1375 else ifmr->ifm_status = 0;
1376 }
1377
1378 int
cs_intr(void * arg)1379 cs_intr(void *arg)
1380 {
1381 struct cs_softc *sc = arg;
1382 uint16_t Event;
1383 uint16_t rndEvent;
1384
1385 /*printf("cs_intr %p\n", sc);*/
1386 /* Ignore any interrupts that happen while the chip is being reset */
1387 if (sc->sc_resetting) {
1388 printf("%s: cs_intr: reset in progress\n",
1389 device_xname(sc->sc_dev));
1390 return 1;
1391 }
1392
1393 /* Read an event from the Interrupt Status Queue */
1394 if (sc->sc_memorymode)
1395 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ);
1396 else
1397 Event = CS_READ_PORT(sc, PORT_ISQ);
1398
1399 if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff)
1400 return 0; /* Not ours */
1401
1402 rndEvent = Event;
1403
1404 /* Process all the events in the Interrupt Status Queue */
1405 while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) {
1406 /* Dispatch to an event handler based on the register number */
1407 switch (Event & REG_NUM_MASK) {
1408 case REG_NUM_RX_EVENT:
1409 cs_receive_event(sc, Event);
1410 break;
1411 case REG_NUM_TX_EVENT:
1412 cs_transmit_event(sc, Event);
1413 break;
1414 case REG_NUM_BUF_EVENT:
1415 cs_buffer_event(sc, Event);
1416 break;
1417 case REG_NUM_TX_COL:
1418 case REG_NUM_RX_MISS:
1419 cs_counter_event(sc, Event);
1420 break;
1421 default:
1422 printf("%s: unknown interrupt event 0x%x\n",
1423 device_xname(sc->sc_dev), Event);
1424 break;
1425 }
1426
1427 /* Read another event from the Interrupt Status Queue */
1428 if (sc->sc_memorymode)
1429 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ);
1430 else
1431 Event = CS_READ_PORT(sc, PORT_ISQ);
1432 }
1433
1434 /* have handled the interrupt */
1435 rnd_add_uint32(&sc->rnd_source, rndEvent);
1436 return 1;
1437 }
1438
1439 void
cs_counter_event(struct cs_softc * sc,uint16_t cntEvent)1440 cs_counter_event(struct cs_softc *sc, uint16_t cntEvent)
1441 {
1442 struct ifnet *ifp;
1443 uint16_t errorCount;
1444
1445 ifp = &sc->sc_ethercom.ec_if;
1446
1447 switch (cntEvent & REG_NUM_MASK) {
1448 case REG_NUM_TX_COL:
1449 /* The count should be read before an overflow occurs. */
1450 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL);
1451 /*
1452 * The tramsit event routine always checks the number of
1453 * collisions for any packet so we don't increment any
1454 * counters here, as they should already have been
1455 * considered.
1456 */
1457 break;
1458 case REG_NUM_RX_MISS:
1459 /* The count should be read before an overflow occurs. */
1460 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS);
1461 /*
1462 * Increment the input error count, the first 6bits are the
1463 * register id.
1464 */
1465 if_statadd(ifp, if_ierrors, (errorCount & 0xffC0) >> 6);
1466 break;
1467 default:
1468 /* Do nothing */
1469 break;
1470 }
1471 }
1472
1473 void
cs_buffer_event(struct cs_softc * sc,uint16_t bufEvent)1474 cs_buffer_event(struct cs_softc *sc, uint16_t bufEvent)
1475 {
1476
1477 /*
1478 * Multiple events can be in the buffer event register at one time so
1479 * a standard switch statement will not suffice, here every event
1480 * must be checked.
1481 */
1482
1483 /*
1484 * If 128 bits have been rxed by the time we get here, the dest event
1485 * will be cleared and 128 event will be set.
1486 */
1487 if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0)
1488 cs_process_rx_early(sc);
1489
1490 if (bufEvent & BUF_EVENT_RX_DMA) {
1491 /* Process the receive data */
1492 if (sc->sc_dma_process_rx)
1493 (*sc->sc_dma_process_rx)(sc);
1494 else
1495 /* Should panic? */
1496 aprint_error_dev(sc->sc_dev, "unexpected DMA event\n");
1497 }
1498
1499 if (bufEvent & BUF_EVENT_TX_UNDR) {
1500 #if 0
1501 /*
1502 * This can happen occasionally, and it's not worth worrying
1503 * about.
1504 */
1505 printf("%s: transmit underrun (%d -> %d)\n",
1506 device_xname(sc->sc_dev), sc->sc_xe_ent,
1507 cs_xmit_early_table[sc->sc_xe_ent].worse);
1508 #endif
1509 sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse;
1510 sc->sc_xe_togo =
1511 cs_xmit_early_table[sc->sc_xe_ent].better_count;
1512
1513 /* had an underrun, transmit is finished */
1514 sc->sc_txbusy = FALSE;
1515 }
1516
1517 if (bufEvent & BUF_EVENT_SW_INT)
1518 printf("%s: software initiated interrupt\n",
1519 device_xname(sc->sc_dev));
1520 }
1521
1522 void
cs_transmit_event(struct cs_softc * sc,uint16_t txEvent)1523 cs_transmit_event(struct cs_softc *sc, uint16_t txEvent)
1524 {
1525 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1526
1527 /* If there were any errors transmitting this frame */
1528 if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR |
1529 TX_EVENT_OUT_WIN | TX_EVENT_JABBER | TX_EVENT_16_COLL)) {
1530 /* Increment the output error count */
1531 if_statinc(ifp, if_oerrors);
1532
1533 /* Note carrier loss. */
1534 if (txEvent & TX_EVENT_LOSS_CRS)
1535 sc->sc_carrier = 0;
1536
1537 /* If debugging is enabled then log error messages */
1538 if (ifp->if_flags & IFF_DEBUG) {
1539 if (txEvent & TX_EVENT_LOSS_CRS)
1540 aprint_error_dev(sc->sc_dev, "lost carrier\n");
1541
1542 if (txEvent & TX_EVENT_SQE_ERR)
1543 aprint_error_dev(sc->sc_dev, "SQE error\n");
1544
1545 if (txEvent & TX_EVENT_OUT_WIN)
1546 aprint_error_dev(sc->sc_dev,
1547 "out-of-window collision\n");
1548
1549 if (txEvent & TX_EVENT_JABBER)
1550 aprint_error_dev(sc->sc_dev, "jabber\n");
1551
1552 if (txEvent & TX_EVENT_16_COLL)
1553 aprint_error_dev(sc->sc_dev,
1554 "16 collisions\n");
1555 }
1556 } else {
1557 /* Transmission successful, carrier is up. */
1558 sc->sc_carrier = 1;
1559 #ifdef SHARK
1560 ledNetActive();
1561 #endif
1562 }
1563
1564 /* Add the number of collisions for this frame */
1565 net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
1566 if (txEvent & TX_EVENT_16_COLL)
1567 if_statadd_ref(nsr, if_collisions, 16);
1568 else
1569 if_statadd_ref(nsr, if_collisions,
1570 ((txEvent & TX_EVENT_COLL_MASK) >> 11));
1571
1572 if_statinc_ref(nsr, if_opackets);
1573 IF_STAT_PUTREF(ifp);
1574
1575 /* Transmission is no longer in progress */
1576 sc->sc_txbusy = FALSE;
1577
1578 /* If there is more to transmit, start the next transmission */
1579 if_schedule_deferred_start(ifp);
1580 }
1581
1582 void
cs_print_rx_errors(struct cs_softc * sc,uint16_t rxEvent)1583 cs_print_rx_errors(struct cs_softc *sc, uint16_t rxEvent)
1584 {
1585
1586 if (rxEvent & RX_EVENT_RUNT)
1587 aprint_error_dev(sc->sc_dev, "runt\n");
1588
1589 if (rxEvent & RX_EVENT_X_DATA)
1590 aprint_error_dev(sc->sc_dev, "extra data\n");
1591
1592 if (rxEvent & RX_EVENT_CRC_ERR) {
1593 if (rxEvent & RX_EVENT_DRIBBLE)
1594 aprint_error_dev(sc->sc_dev, "alignment error\n");
1595 else
1596 aprint_error_dev(sc->sc_dev, "CRC error\n");
1597 } else {
1598 if (rxEvent & RX_EVENT_DRIBBLE)
1599 aprint_error_dev(sc->sc_dev, "dribble bits\n");
1600 }
1601 }
1602
1603 void
cs_receive_event(struct cs_softc * sc,uint16_t rxEvent)1604 cs_receive_event(struct cs_softc *sc, uint16_t rxEvent)
1605 {
1606 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1607
1608 /* If the frame was not received OK */
1609 if (!(rxEvent & RX_EVENT_RX_OK)) {
1610 /* Increment the input error count */
1611 if_statinc(ifp, if_ierrors);
1612
1613 /* If debugging is enabled then log error messages. */
1614 if (ifp->if_flags & IFF_DEBUG) {
1615 if (rxEvent != REG_NUM_RX_EVENT) {
1616 cs_print_rx_errors(sc, rxEvent);
1617
1618 /*
1619 * Must read the length of all received
1620 * frames
1621 */
1622 CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH);
1623
1624 /* Skip the received frame */
1625 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1626 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) |
1627 RX_CFG_SKIP);
1628 } else
1629 aprint_error_dev(sc->sc_dev, "implied skip\n");
1630 }
1631 } else {
1632 /*
1633 * Process the received frame and pass it up to the upper
1634 * layers.
1635 */
1636 cs_process_receive(sc);
1637 }
1638 }
1639
1640 void
cs_ether_input(struct cs_softc * sc,struct mbuf * m)1641 cs_ether_input(struct cs_softc *sc, struct mbuf *m)
1642 {
1643 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1644
1645 /* Pass the packet up. */
1646 if_percpuq_enqueue(ifp->if_percpuq, m);
1647 }
1648
1649 void
cs_process_receive(struct cs_softc * sc)1650 cs_process_receive(struct cs_softc *sc)
1651 {
1652 struct ifnet *ifp;
1653 struct mbuf *m;
1654 int totlen;
1655 uint16_t *pBuff, *pBuffLimit;
1656 int pad;
1657 unsigned int frameOffset = 0; /* XXX: gcc */
1658
1659 #ifdef SHARK
1660 ledNetActive();
1661 #endif
1662
1663 ifp = &sc->sc_ethercom.ec_if;
1664
1665 /* Received a packet; carrier is up. */
1666 sc->sc_carrier = 1;
1667
1668 if (sc->sc_memorymode) {
1669 /* Initialize the frame offset */
1670 frameOffset = PKTPG_RX_LENGTH;
1671
1672 /* Get the length of the received frame */
1673 totlen = CS_READ_PACKET_PAGE(sc, frameOffset);
1674 frameOffset += 2;
1675 } else {
1676 /* Drop status */
1677 CS_READ_PORT(sc, PORT_RXTX_DATA);
1678
1679 /* Get the length of the received frame */
1680 totlen = CS_READ_PORT(sc, PORT_RXTX_DATA);
1681 }
1682
1683 if (totlen > ETHER_MAX_LEN) {
1684 aprint_error_dev(sc->sc_dev, "invalid packet length %d\n",
1685 totlen);
1686
1687 /* Skip the received frame */
1688 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1689 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
1690 return;
1691 }
1692
1693 MGETHDR(m, M_DONTWAIT, MT_DATA);
1694 if (m == 0) {
1695 aprint_error_dev(sc->sc_dev,
1696 "cs_process_receive: unable to allocate mbuf\n");
1697 if_statinc(ifp, if_ierrors);
1698 /*
1699 * Couldn't allocate an mbuf so things are not good, may as
1700 * well drop the packet I think.
1701 *
1702 * have already read the length so we should be right to skip
1703 * the packet.
1704 */
1705 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1706 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
1707 return;
1708 }
1709 m_set_rcvif(m, ifp);
1710 m->m_pkthdr.len = totlen;
1711
1712 /* Number of bytes to align ip header on word boundary for ipintr */
1713 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
1714
1715 /*
1716 * Alloc mbuf cluster if we need.
1717 * We need 1 byte spare because following packet read loop can overrun.
1718 */
1719 if (totlen + pad + 1 > MHLEN) {
1720 MCLGET(m, M_DONTWAIT);
1721 if ((m->m_flags & M_EXT) == 0) {
1722 /* Couldn't allocate an mbuf cluster */
1723 aprint_error_dev(sc->sc_dev,
1724 "cs_process_receive: "
1725 "unable to allocate a cluster\n");
1726 m_freem(m);
1727
1728 /* Skip the received frame */
1729 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1730 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG)
1731 | RX_CFG_SKIP);
1732 return;
1733 }
1734 }
1735
1736 /* Align ip header on word boundary for ipintr */
1737 m->m_data += pad;
1738
1739 m->m_len = totlen;
1740 pBuff = mtod(m, uint16_t *);
1741
1742 /* Now read the data from the chip */
1743 if (sc->sc_memorymode) {
1744 /* Don't want to go over */
1745 pBuffLimit = pBuff + (totlen + 1) / 2;
1746
1747 while (pBuff < pBuffLimit) {
1748 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset);
1749 frameOffset += 2;
1750 }
1751 } else
1752 IO_READ_MULTI_2(sc, PORT_RXTX_DATA, pBuff, (totlen + 1)>>1);
1753
1754 cs_ether_input(sc, m);
1755 }
1756
1757 void
cs_process_rx_early(struct cs_softc * sc)1758 cs_process_rx_early(struct cs_softc *sc)
1759 {
1760 struct ifnet *ifp;
1761 struct mbuf *m;
1762 uint16_t frameCount, oldFrameCount;
1763 uint16_t rxEvent;
1764 uint16_t *pBuff;
1765 int pad;
1766 unsigned int frameOffset;
1767
1768
1769 ifp = &sc->sc_ethercom.ec_if;
1770
1771 /* Initialize the frame offset */
1772 frameOffset = PKTPG_RX_FRAME;
1773 frameCount = 0;
1774
1775 MGETHDR(m, M_DONTWAIT, MT_DATA);
1776 if (m == 0) {
1777 aprint_error_dev(sc->sc_dev,
1778 "cs_process_rx_early: unable to allocate mbuf\n");
1779 if_statinc(ifp, if_ierrors);
1780 /*
1781 * Couldn't allocate an mbuf so things are not good, may as
1782 * well drop the packet I think.
1783 *
1784 * have already read the length so we should be right to skip
1785 * the packet.
1786 */
1787 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1788 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
1789 return;
1790 }
1791 m_set_rcvif(m, ifp);
1792 /*
1793 * Save processing by always using a mbuf cluster, guaranteed to fit
1794 * packet
1795 */
1796 MCLGET(m, M_DONTWAIT);
1797 if ((m->m_flags & M_EXT) == 0) {
1798 /* Couldn't allocate an mbuf cluster */
1799 aprint_error_dev(sc->sc_dev,
1800 "cs_process_rx_early: unable to allocate a cluster\n");
1801 m_freem(m);
1802 /* Skip the frame */
1803 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1804 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
1805 return;
1806 }
1807
1808 /* Align ip header on word boundary for ipintr */
1809 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
1810 m->m_data += pad;
1811
1812 /* Set up the buffer pointer to point to the data area */
1813 pBuff = mtod(m, uint16_t *);
1814
1815 /*
1816 * Now read the frame byte counter until we have finished reading the
1817 * frame
1818 */
1819 oldFrameCount = 0;
1820 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT);
1821 while ((frameCount != 0) && (frameCount < MCLBYTES)) {
1822 for (; oldFrameCount < frameCount; oldFrameCount += 2) {
1823 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset);
1824 frameOffset += 2;
1825 }
1826
1827 /* Read the new count from the chip */
1828 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT);
1829 }
1830
1831 /* Update the mbuf counts */
1832 m->m_len = oldFrameCount;
1833 m->m_pkthdr.len = oldFrameCount;
1834
1835 /* Now check the Rx Event register */
1836 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT);
1837
1838 if ((rxEvent & RX_EVENT_RX_OK) != 0) {
1839 /*
1840 * Do an implied skip, it seems to be more reliable than a
1841 * forced skip.
1842 */
1843 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS);
1844 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH);
1845
1846 /*
1847 * Now read the RX_EVENT register to perform an implied skip.
1848 */
1849 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT);
1850
1851 cs_ether_input(sc, m);
1852 } else {
1853 m_freem(m);
1854 if_statinc(ifp, if_ierrors);
1855 }
1856 }
1857
1858 void
cs_start_output(struct ifnet * ifp)1859 cs_start_output(struct ifnet *ifp)
1860 {
1861 struct cs_softc *sc;
1862 struct mbuf *pMbuf;
1863 struct mbuf *pMbufChain;
1864 uint16_t BusStatus;
1865 uint16_t Length;
1866 int txLoop = 0;
1867 int dropout = 0;
1868
1869 sc = ifp->if_softc;
1870
1871 /* Check that the interface is up and running */
1872 if ((ifp->if_flags & IFF_RUNNING) == 0)
1873 return;
1874
1875 /* Don't interrupt a transmission in progress */
1876 if (sc->sc_txbusy)
1877 return;
1878
1879 /* This loop will only run through once if transmission is successful */
1880 /*
1881 * While there are packets to transmit and a transmit is not in
1882 * progress
1883 */
1884 while (sc->sc_txbusy == 0 && dropout == 0) {
1885 IFQ_DEQUEUE(&ifp->if_snd, pMbufChain);
1886 if (pMbufChain == NULL)
1887 break;
1888
1889 /*
1890 * If BPF is listening on this interface, let it see the packet
1891 * before we commit it to the wire.
1892 */
1893 bpf_mtap(ifp, pMbufChain, BPF_D_OUT);
1894
1895 /* Find the total length of the data to transmit */
1896 Length = 0;
1897 for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next)
1898 Length += pMbuf->m_len;
1899
1900 do {
1901 /*
1902 * Request that the transmit be started after all
1903 * data has been copied
1904 *
1905 * In IO mode must write to the IO port not the packet
1906 * page address
1907 *
1908 * If this is changed to start transmission after a
1909 * small amount of data has been copied you tend to
1910 * get packet missed errors i think because the ISA
1911 * bus is too slow. Or possibly the copy routine is
1912 * not streamlined enough.
1913 */
1914 if (sc->sc_memorymode) {
1915 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD,
1916 cs_xmit_early_table[sc->sc_xe_ent].txcmd);
1917 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length);
1918 } else {
1919 CS_WRITE_PORT(sc, PORT_TX_CMD,
1920 cs_xmit_early_table[sc->sc_xe_ent].txcmd);
1921 CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length);
1922 }
1923
1924 /* Adjust early-transmit machinery. */
1925 if (--sc->sc_xe_togo == 0) {
1926 sc->sc_xe_ent =
1927 cs_xmit_early_table[sc->sc_xe_ent].better;
1928 sc->sc_xe_togo =
1929 cs_xmit_early_table[sc->sc_xe_ent].better_count;
1930 }
1931 /*
1932 * Read the BusStatus register which indicates
1933 * success of the request
1934 */
1935 BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST);
1936
1937 /*
1938 * If there was an error in the transmit bid free the
1939 * mbuf and go on. This is presuming that mbuf is
1940 * corrupt.
1941 */
1942 if (BusStatus & BUS_ST_TX_BID_ERR) {
1943 aprint_error_dev(sc->sc_dev,
1944 "transmit bid error (too big)");
1945
1946 /* Discard the bad mbuf chain */
1947 m_freem(pMbufChain);
1948 if_statinc(&sc->sc_ethercom.ec_if, if_oerrors);
1949
1950 /* Loop up to transmit the next chain */
1951 txLoop = 0;
1952 } else {
1953 if (BusStatus & BUS_ST_RDY4TXNOW) {
1954 /*
1955 * The chip is ready for transmission
1956 * now
1957 */
1958 /*
1959 * Copy the frame to the chip to
1960 * start transmission
1961 */
1962 cs_copy_tx_frame(sc, pMbufChain);
1963
1964 /* Free the mbuf chain */
1965 m_freem(pMbufChain);
1966
1967 /* Transmission is now in progress */
1968 sc->sc_txbusy = TRUE;
1969 txLoop = 0;
1970 } else {
1971 /*
1972 * If we get here we want to try
1973 * again with the same mbuf, until
1974 * the chip lets us transmit.
1975 */
1976 txLoop++;
1977 if (txLoop > CS_OUTPUT_LOOP_MAX) {
1978 /* Free the mbuf chain */
1979 m_freem(pMbufChain);
1980 /*
1981 * Transmission is not in
1982 * progress
1983 */
1984 sc->sc_txbusy = FALSE;
1985 /*
1986 * Increment the output error
1987 * count
1988 */
1989 if_statinc(ifp, if_oerrors);
1990 /*
1991 * exit the routine and drop
1992 * the packet.
1993 */
1994 txLoop = 0;
1995 dropout = 1;
1996 }
1997 }
1998 }
1999 } while (txLoop);
2000 }
2001 }
2002
2003 void
cs_copy_tx_frame(struct cs_softc * sc,struct mbuf * m0)2004 cs_copy_tx_frame(struct cs_softc *sc, struct mbuf *m0)
2005 {
2006 struct mbuf *m;
2007 int len, leftover, frameoff;
2008 uint16_t dbuf;
2009 uint8_t *p;
2010 #ifdef DIAGNOSTIC
2011 uint8_t *lim;
2012 #endif
2013
2014 /* Initialize frame pointer and data port address */
2015 frameoff = PKTPG_TX_FRAME;
2016
2017 /* Start out with no leftover data */
2018 leftover = 0;
2019 dbuf = 0;
2020
2021 /* Process the chain of mbufs */
2022 for (m = m0; m != NULL; m = m->m_next) {
2023 /* Process all of the data in a single mbuf. */
2024 p = mtod(m, uint8_t *);
2025 len = m->m_len;
2026 #ifdef DIAGNOSTIC
2027 lim = p + len;
2028 #endif
2029
2030 while (len > 0) {
2031 if (leftover) {
2032 /*
2033 * Data left over (from mbuf or realignment).
2034 * Buffer the next byte, and write it and
2035 * the leftover data out.
2036 */
2037 dbuf |= *p++ << 8;
2038 len--;
2039 if (sc->sc_memorymode) {
2040 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf);
2041 frameoff += 2;
2042 }
2043 else {
2044 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf);
2045 }
2046 leftover = 0;
2047 } else if ((long) p & 1) {
2048 /* Misaligned data. Buffer the next byte. */
2049 dbuf = *p++;
2050 len--;
2051 leftover = 1;
2052 } else {
2053 /*
2054 * Aligned data. This is the case we like.
2055 *
2056 * Write-region out as much as we can, then
2057 * buffer the remaining byte (if any).
2058 */
2059 leftover = len & 1;
2060 len &= ~1;
2061 if (sc->sc_memorymode) {
2062 MEM_WRITE_REGION_2(sc, frameoff,
2063 (uint16_t *) p, len >> 1);
2064 frameoff += len;
2065 } else
2066 IO_WRITE_MULTI_2(sc, PORT_RXTX_DATA,
2067 (uint16_t *)p, len >> 1);
2068 p += len;
2069
2070 if (leftover)
2071 dbuf = *p++;
2072 len = 0;
2073 }
2074 }
2075 if (len < 0)
2076 panic("cs_copy_tx_frame: negative len");
2077 #ifdef DIAGNOSTIC
2078 if (p != lim)
2079 panic("cs_copy_tx_frame: p != lim");
2080 #endif
2081 }
2082 if (leftover) {
2083 if (sc->sc_memorymode)
2084 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf);
2085 else
2086 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf);
2087 }
2088 }
2089
2090 static int
cs_enable(struct cs_softc * sc)2091 cs_enable(struct cs_softc *sc)
2092 {
2093
2094 if (CS_IS_ENABLED(sc) == 0) {
2095 if (sc->sc_enable != NULL) {
2096 int error;
2097
2098 error = (*sc->sc_enable)(sc);
2099 if (error)
2100 return error;
2101 }
2102 sc->sc_cfgflags |= CFGFLG_ENABLED;
2103 }
2104
2105 return 0;
2106 }
2107
2108 static void
cs_disable(struct cs_softc * sc)2109 cs_disable(struct cs_softc *sc)
2110 {
2111
2112 if (CS_IS_ENABLED(sc)) {
2113 if (sc->sc_disable != NULL)
2114 (*sc->sc_disable)(sc);
2115
2116 sc->sc_cfgflags &= ~CFGFLG_ENABLED;
2117 }
2118 }
2119
2120 static void
cs_stop(struct ifnet * ifp,int disable)2121 cs_stop(struct ifnet *ifp, int disable)
2122 {
2123 struct cs_softc *sc = ifp->if_softc;
2124
2125 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0);
2126 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0);
2127 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0);
2128 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0);
2129
2130 if (disable)
2131 cs_disable(sc);
2132
2133 ifp->if_flags &= ~IFF_RUNNING;
2134 }
2135
2136 int
cs_activate(device_t self,enum devact act)2137 cs_activate(device_t self, enum devact act)
2138 {
2139 struct cs_softc *sc = device_private(self);
2140
2141 switch (act) {
2142 case DVACT_DEACTIVATE:
2143 if_deactivate(&sc->sc_ethercom.ec_if);
2144 return 0;
2145 default:
2146 return EOPNOTSUPP;
2147 }
2148 }
2149