1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)zsvar.h 8.1 (Berkeley) 06/11/93 17 * 18 * from: $Header: zsvar.h,v 1.7 92/11/26 01:28:04 torek Exp $ (LBL) 19 */ 20 21 /* 22 * Software state, per zs channel. 23 * 24 * The zs chip has insufficient buffering, so we provide a software 25 * buffer using a two-level interrupt scheme. The hardware (high priority) 26 * interrupt simply grabs the `cause' of the interrupt and stuffs it into 27 * a ring buffer. It then schedules a software interrupt; the latter 28 * empties the ring as fast as it can, hoping to avoid overflow. 29 * 30 * Interrupts can happen because of: 31 * - received data; 32 * - transmit pseudo-DMA done; and 33 * - status change. 34 * These are all stored together in the (single) ring. The size of the 35 * ring is a power of two, to make % operations fast. Since we need two 36 * bits to distinguish the interrupt type, and up to 16 for the received 37 * data plus RR1 status, we use 32 bits per ring entry. 38 * 39 * When the value is a character + RR1 status, the character is in the 40 * upper 8 bits of the RR1 status. 41 */ 42 #define ZLRB_RING_SIZE 256 /* ZS line ring buffer size */ 43 #define ZLRB_RING_MASK 255 /* mask for same */ 44 45 /* 0 is reserved (means "no interrupt") */ 46 #define ZRING_RINT 1 /* receive data interrupt */ 47 #define ZRING_XINT 2 /* transmit done interrupt */ 48 #define ZRING_SINT 3 /* status change interrupt */ 49 50 #define ZRING_TYPE(x) ((x) & 3) 51 #define ZRING_VALUE(x) ((x) >> 8) 52 #define ZRING_MAKE(t, v) ((t) | (v) << 8) 53 54 struct zs_chanstate { 55 struct zs_chanstate *cs_next; /* linked list for zshard() */ 56 volatile struct zschan *cs_zc; /* points to hardware regs */ 57 int cs_unit; /* unit number */ 58 struct tty *cs_ttyp; /* ### */ 59 60 /* 61 * We must keep a copy of the write registers as they are 62 * mostly write-only and we sometimes need to set and clear 63 * individual bits (e.g., in WR3). Not all of these are 64 * needed but 16 bytes is cheap and this makes the addressing 65 * simpler. Unfortunately, we can only write to some registers 66 * when the chip is not actually transmitting, so whenever 67 * we are expecting a `transmit done' interrupt the preg array 68 * is allowed to `get ahead' of the current values. In a 69 * few places we must change the current value of a register, 70 * rather than (or in addition to) the pending value; for these 71 * cs_creg[] contains the current value. 72 */ 73 u_char cs_creg[16]; /* current values */ 74 u_char cs_preg[16]; /* pending values */ 75 u_char cs_heldchange; /* change pending (creg != preg) */ 76 u_char cs_rr0; /* last rr0 processed */ 77 78 /* pure software data, per channel */ 79 char cs_softcar; /* software carrier */ 80 char cs_conk; /* is console keyboard, decode L1-A */ 81 char cs_brkabort; /* abort (as if via L1-A) on BREAK */ 82 char cs_kgdb; /* enter debugger on frame char */ 83 char cs_consio; /* port does /dev/console I/O */ 84 char cs_xxx; /* (spare) */ 85 int cs_speed; /* default baud rate (from ROM) */ 86 87 /* 88 * The transmit byte count and address are used for pseudo-DMA 89 * output in the hardware interrupt code. PDMA can be suspended 90 * to get pending changes done; heldtbc is used for this. It can 91 * also be stopped for ^S; this sets TS_TTSTOP in tp->t_state. 92 */ 93 int cs_tbc; /* transmit byte count */ 94 caddr_t cs_tba; /* transmit buffer address */ 95 int cs_heldtbc; /* held tbc while xmission stopped */ 96 97 /* 98 * Printing an overrun error message often takes long enough to 99 * cause another overrun, so we only print one per second. 100 */ 101 long cs_rotime; /* time of last ring overrun */ 102 long cs_fotime; /* time of last fifo overrun */ 103 104 /* 105 * The ring buffer. 106 */ 107 u_int cs_rbget; /* ring buffer `get' index */ 108 volatile u_int cs_rbput; /* ring buffer `put' index */ 109 int cs_rbuf[ZLRB_RING_SIZE];/* type, value pairs */ 110 }; 111 112 /* 113 * Macros to read and write individual registers (except 0) in a channel. 114 * 115 * On the SparcStation the 1.6 microsecond recovery time is 116 * handled in hardware. 117 */ 118 #define ZS_READ(c, r) ((c)->zc_csr = (r), (c)->zc_csr) 119 #define ZS_WRITE(c, r, v) ((c)->zc_csr = (r), (c)->zc_csr = (v)) 120