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36 /******************************************************************************
37 @File fsl_qman.h
38
39 @Description QM header
40 *//***************************************************************************/
41 #ifndef __FSL_QMAN_H
42 #define __FSL_QMAN_H
43
44 #include "std_ext.h"
45 #include "string_ext.h"
46 #include "qm_ext.h"
47
48
49 /*************************************************/
50 /* QMan s/w corenet portal, low-level i/face */
51 /*************************************************/
52 typedef enum {
53 e_QmPortalPCI = 0, /* PI index, cache-inhibited */
54 e_QmPortalPCE, /* PI index, cache-enabled */
55 e_QmPortalPVB /* valid-bit */
56 } e_QmPortalProduceMode;
57
58 typedef enum {
59 e_QmPortalEqcrCCI = 0, /* CI index, cache-inhibited */
60 e_QmPortalEqcrCCE /* CI index, cache-enabled */
61 } e_QmPortalEqcrConsumeMode;
62
63 typedef enum {
64 e_QmPortalDqrrCCI = 0, /* CI index, cache-inhibited */
65 e_QmPortalDqrrCCE, /* CI index, cache-enabled */
66 e_QmPortalDqrrDCA /* Discrete Consumption Acknowledgment */
67 } e_QmPortalDqrrConsumeMode;
68
69 typedef enum {
70 e_QmPortalMrCCI = 0, /* CI index, cache-inhibited */
71 e_QmPortalMrCCE /* CI index, cache-enabled */
72 } e_QmPortalMrConsumeMode;
73
74 typedef enum {
75 e_QmPortalDequeuePushMode = 0, /* SDQCR + VDQCR */
76 e_QmPortalDequeuePullMode /* PDQCR */
77 } e_QmPortalDequeueMode;
78
79 /* Portal constants */
80 #define QM_EQCR_SIZE 8
81 #define QM_DQRR_SIZE 16
82 #define QM_MR_SIZE 8
83
84 /* Hardware constants */
85
86 enum qm_isr_reg {
87 qm_isr_status = 0,
88 qm_isr_enable = 1,
89 qm_isr_disable = 2,
90 qm_isr_inhibit = 3
91 };
92 enum qm_dc_portal {
93 qm_dc_portal_fman0 = 0,
94 qm_dc_portal_fman1 = 1,
95 qm_dc_portal_caam = 2,
96 qm_dc_portal_pme = 3
97 };
98
99 /* Represents s/w corenet portal mapped data structures */
100 struct qm_eqcr_entry; /* EQCR (EnQueue Command Ring) entries */
101 struct qm_dqrr_entry; /* DQRR (DeQueue Response Ring) entries */
102 struct qm_mr_entry; /* MR (Message Ring) entries */
103 struct qm_mc_command; /* MC (Management Command) command */
104 struct qm_mc_result; /* MC result */
105
106 /* This type represents a s/w corenet portal space, and is used for creating the
107 * portal objects within it (EQCR, DQRR, etc) */
108 struct qm_portal;
109
110 /* When iterating the available portals, this is the exposed config structure */
111 struct qm_portal_config {
112 /* If the caller enables DQRR stashing (and thus wishes to operate the
113 * portal from only one cpu), this is the logical CPU that the portal
114 * will stash to. Whether stashing is enabled or not, this setting is
115 * also used for any "core-affine" portals, ie. default portals
116 * associated to the corresponding cpu. -1 implies that there is no core
117 * affinity configured. */
118 int cpu;
119 /* portal interrupt line */
120 uintptr_t irq;
121 /* The portal's dedicated channel id, use this value for initializing
122 * frame queues to target this portal when scheduled. */
123 e_QmFQChannel channel;
124 /* A mask of which pool channels this portal has dequeue access to
125 * (using QM_SDQCR_CHANNELS_POOL(n) for the bitmask) */
126 uint32_t pools;
127 /* which portal sub-interfaces are already bound (ie. "in use") */
128 uint8_t bound;
129 };
130 /* qm_portal_config::bound uses these bit masks */
131 #define QM_BIND_EQCR 0x01
132 #define QM_BIND_DQRR 0x02
133 #define QM_BIND_MR 0x04
134 #define QM_BIND_MC 0x08
135 #define QM_BIND_ISR 0x10
136
137 /* This struct represents a pool channel */
138 struct qm_pool_channel {
139 /* The QM_SDQCR_CHANNELS_POOL(n) bit that corresponds to this channel */
140 uint32_t pool;
141 /* The channel id, used for initialising frame queues to target this
142 * channel. */
143 e_QmFQChannel channel;
144 /* Bitmask of portal (logical-, not cell-)indices that have dequeue
145 * access to this channel;
146 * 0x001 -> qm_portal_get(0)
147 * 0x002 -> qm_portal_get(1)
148 * 0x004 -> qm_portal_get(2)
149 * ...
150 * 0x200 -> qm_portal_get(9)
151 */
152 uint32_t portals;
153 };
154
155 /* ------------------------------ */
156 /* --- Portal enumeration API --- */
157
158 /* Obtain the number of portals available */
159 uint8_t qm_portal_num(void);
160
161 /* Obtain a portal handle and configuration information about it */
162 struct qm_portal *qm_portal_get(uint8_t idx);
163
164
165 /* ------------------------------------ */
166 /* --- Pool channel enumeration API --- */
167
168 /* Obtain a mask of the available pool channels, expressed using
169 * QM_SDQCR_CHANNELS_POOL(n). */
170 uint32_t qm_pools(void);
171
172 /* Retrieve a pool channel configuration, given a QM_SDQCR_CHANNEL_POOL(n)
173 * bit-mask (the least significant bit of 'mask' is used if more than one bit is
174 * set). */
175 const struct qm_pool_channel *qm_pool_channel(uint32_t mask);
176
177 /* Flags to qm_fq_free_flags() */
178 #define QM_FQ_FREE_WAIT 0x00000001 /* wait if RCR is full */
179 #define QM_FQ_FREE_WAIT_INT 0x00000002 /* if wait, interruptible? */
180 #define QM_FQ_FREE_WAIT_SYNC 0x00000004 /* if wait, until consumed? */
181
182
183 #define QM_SDQCR_SOURCE_CHANNELS 0x0
184 #define QM_SDQCR_SOURCE_SPECIFICWQ 0x40000000
185 #define QM_SDQCR_COUNT_EXACT1 0x0
186 #define QM_SDQCR_COUNT_UPTO3 0x20000000
187 #define QM_SDQCR_DEDICATED_PRECEDENCE 0x10000000
188 #define QM_SDQCR_TYPE_MASK 0x03000000
189 #define QM_SDQCR_TYPE_NULL 0x0
190 #define QM_SDQCR_TYPE_PRIO_QOS 0x01000000
191 #define QM_SDQCR_TYPE_ACTIVE_QOS 0x02000000
192 #define QM_SDQCR_TYPE_ACTIVE 0x03000000
193 #define QM_SDQCR_TYPE_SET(v) (((v) & 0x03) << (31-7))
194 #define QM_SDQCR_TOKEN_MASK 0x00ff0000
195 #define QM_SDQCR_TOKEN_SET(v) (((v) & 0xff) << 16)
196 #define QM_SDQCR_TOKEN_GET(v) (((v) >> 16) & 0xff)
197 #define QM_SDQCR_CHANNELS_DEDICATED 0x00008000
198 #define QM_SDQCR_CHANNELS_POOL_MASK 0x00007fff
199 #define QM_SDQCR_CHANNELS_POOL(n) (0x00008000 >> (n))
200 #define QM_SDQCR_SPECIFICWQ_MASK 0x000000f7
201 #define QM_SDQCR_SPECIFICWQ_DEDICATED 0x00000000
202 #define QM_SDQCR_SPECIFICWQ_POOL(n) ((n) << 4)
203 #define QM_SDQCR_SPECIFICWQ_WQ(n) (n)
204
205 /* For qm_dqrr_vdqcr_set(); Choose one PRECEDENCE. EXACT is optional. Use
206 * NUMFRAMES(n) (6-bit) or NUMFRAMES_TILLEMPTY to fill in the frame-count. Use
207 * FQID(n) to fill in the frame queue ID. */
208 #define QM_VDQCR_PRECEDENCE_VDQCR 0x0
209 #define QM_VDQCR_PRECEDENCE_SDQCR 0x80000000
210 #define QM_VDQCR_EXACT 0x40000000
211 #define QM_VDQCR_NUMFRAMES_MASK 0x3f000000
212 #define QM_VDQCR_NUMFRAMES_SET(n) (((n) & 0x3f) << 24)
213 #define QM_VDQCR_NUMFRAMES_GET(n) (((n) >> 24) & 0x3f)
214 #define QM_VDQCR_NUMFRAMES_TILLEMPTY QM_VDQCR_NUMFRAMES_SET(0)
215 #define QM_VDQCR_FQID_MASK 0x00ffffff
216 #define QM_VDQCR_FQID(n) ((n) & QM_VDQCR_FQID_MASK)
217
218 /* For qm_dqrr_pdqcr_set(); Choose one MODE. Choose one COUNT.
219 * If MODE==SCHEDULED
220 * Choose SCHEDULED_CHANNELS or SCHEDULED_SPECIFICWQ. Choose one dequeue TYPE.
221 * If CHANNELS,
222 * Choose CHANNELS_DEDICATED and/or CHANNELS_POOL() channels.
223 * You can choose DEDICATED_PRECEDENCE if the portal channel should have
224 * priority.
225 * If SPECIFICWQ,
226 * Either select the work-queue ID with SPECIFICWQ_WQ(), or select the
227 * channel (SPECIFICWQ_DEDICATED or SPECIFICWQ_POOL()) and specify the
228 * work-queue priority (0-7) with SPECIFICWQ_WQ() - either way, you get the
229 * same value.
230 * If MODE==UNSCHEDULED
231 * Choose FQID().
232 */
233 #define QM_PDQCR_MODE_SCHEDULED 0x0
234 #define QM_PDQCR_MODE_UNSCHEDULED 0x80000000
235 #define QM_PDQCR_SCHEDULED_CHANNELS 0x0
236 #define QM_PDQCR_SCHEDULED_SPECIFICWQ 0x40000000
237 #define QM_PDQCR_COUNT_EXACT1 0x0
238 #define QM_PDQCR_COUNT_UPTO3 0x20000000
239 #define QM_PDQCR_DEDICATED_PRECEDENCE 0x10000000
240 #define QM_PDQCR_TYPE_MASK 0x03000000
241 #define QM_PDQCR_TYPE_NULL 0x0
242 #define QM_PDQCR_TYPE_PRIO_QOS 0x01000000
243 #define QM_PDQCR_TYPE_ACTIVE_QOS 0x02000000
244 #define QM_PDQCR_TYPE_ACTIVE 0x03000000
245 #define QM_PDQCR_CHANNELS_DEDICATED 0x00008000
246 #define QM_PDQCR_CHANNELS_POOL(n) (0x00008000 >> (n))
247 #define QM_PDQCR_SPECIFICWQ_MASK 0x000000f7
248 #define QM_PDQCR_SPECIFICWQ_DEDICATED 0x00000000
249 #define QM_PDQCR_SPECIFICWQ_POOL(n) ((n) << 4)
250 #define QM_PDQCR_SPECIFICWQ_WQ(n) (n)
251 #define QM_PDQCR_FQID(n) ((n) & 0xffffff)
252
253 /* ------------------------------------- */
254 /* --- Portal interrupt register API --- */
255
256 /* Quick explanation of the Qman interrupt model. Each bit has a source
257 * condition, that source is asserted iff the condition is true. Eg. Each
258 * DQAVAIL source bit tracks whether the corresponding channel's work queues
259 * contain any truly scheduled frame queues. That source exists "asserted" if
260 * and while there are truly-scheduled FQs available, it is deasserted as/when
261 * there are no longer any truly-scheduled FQs available. The same is true for
262 * the various other interrupt source conditions (QM_PIRQ_***). The following
263 * steps indicate what those source bits affect;
264 * 1. if the corresponding bit is set in the disable register, the source
265 * bit is masked off, we never see any effect from it.
266 * 2. otherwise, the corresponding bit is set in the status register. Once
267 * asserted in the status register, it must be write-1-to-clear'd - the
268 * status register bit will stay set even if the source condition
269 * deasserts.
270 * 3. if a bit is set in the status register but *not* set in the enable
271 * register, it will not cause the interrupt to assert. Other bits may
272 * still cause the interrupt to assert of course, and a read of the
273 * status register can still reveal un-enabled bits - this is why the
274 * enable and disable registers aren't strictly speaking "opposites".
275 * "Un-enabled" means it won't, on its own, trigger an interrupt.
276 * "Disabled" means it won't even show up in the status register.
277 * 4. if a bit is set in the status register *and* the enable register, the
278 * interrupt line will assert if and only if the inhibit register is
279 * zero. The inhibit register is the only interrupt-related register that
280 * does not share the bit definitions - it is a boolean on/off register.
281 */
282
283 /* Create/destroy */
284
285 /* Used by all portal interrupt registers except 'inhibit' */
286 #define QM_PIRQ_CSCI 0x00100000 /* Congestion State Change */
287 #define QM_PIRQ_EQCI 0x00080000 /* Enqueue Command Committed */
288 #define QM_PIRQ_EQRI 0x00040000 /* EQCR Ring (below threshold) */
289 #define QM_PIRQ_DQRI 0x00020000 /* DQRR Ring (non-empty) */
290 #define QM_PIRQ_MRI 0x00010000 /* MR Ring (non-empty) */
291 /* The DQAVAIL interrupt fields break down into these bits; */
292 #define QM_PIRQ_DQAVAIL 0x0000ffff /* Channels with frame availability */
293 #define QM_DQAVAIL_PORTAL 0x8000 /* Portal channel */
294 #define QM_DQAVAIL_POOL(n) (0x8000 >> (n)) /* Pool channel, n==[1..15] */
295
296 /* These are qm_<reg>_<verb>(). So for example, qm_disable_write() means "write
297 * the disable register" rather than "disable the ability to write". */
298 #define qm_isr_status_read(qm) __qm_isr_read(qm, qm_isr_status)
299 #define qm_isr_status_clear(qm, m) __qm_isr_write(qm, qm_isr_status, m)
300 #define qm_isr_enable_read(qm) __qm_isr_read(qm, qm_isr_enable)
301 #define qm_isr_enable_write(qm, v) __qm_isr_write(qm, qm_isr_enable, v)
302 #define qm_isr_disable_read(qm) __qm_isr_read(qm, qm_isr_disable)
303 #define qm_isr_disable_write(qm, v) __qm_isr_write(qm, qm_isr_disable, v)
304 #define qm_isr_inhibit(qm) __qm_isr_write(qm, qm_isr_inhibit, 1)
305 #define qm_isr_uninhibit(qm) __qm_isr_write(qm, qm_isr_inhibit, 0)
306
307 /* ------------------------------------------------------- */
308 /* --- Qman data structures (and associated constants) --- */
309
310 /* See David Lapp's "Frame formats" document, "dpateam", Jan 07, 2008 */
311 #define QM_FD_FORMAT_SG 0x4
312 #define QM_FD_FORMAT_LONG 0x2
313 #define QM_FD_FORMAT_COMPOUND 0x1
314 enum qm_fd_format {
315 /* 'contig' implies a contiguous buffer, whereas 'sg' implies a
316 * scatter-gather table. 'big' implies a 29-bit length with no offset
317 * field, otherwise length is 20-bit and offset is 9-bit. 'compound'
318 * implies a s/g-like table, where each entry itself represents a frame
319 * (contiguous or scatter-gather) and the 29-bit "length" is
320 * interpreted purely for congestion calculations, ie. a "congestion
321 * weight". */
322 qm_fd_contig = 0,
323 qm_fd_contig_big = QM_FD_FORMAT_LONG,
324 qm_fd_sg = QM_FD_FORMAT_SG,
325 qm_fd_sg_big = QM_FD_FORMAT_SG | QM_FD_FORMAT_LONG,
326 qm_fd_compound = QM_FD_FORMAT_COMPOUND
327 };
328
329 #if defined(__MWERKS__) && !defined(__GNUC__)
330 #pragma pack(push,1)
331 #endif /* defined(__MWERKS__) && ... */
332 #define MEM_MAP_START
333
334 _Packed struct qm_fqd_stashing {
335 /* See QM_STASHING_EXCL_<...> */
336 volatile uint8_t exclusive;
337 volatile uint8_t reserved1:2;
338 /* Numbers of cachelines */
339 volatile uint8_t annotation_cl:2;
340 volatile uint8_t data_cl:2;
341 volatile uint8_t context_cl:2;
342 } _PackedType;
343
344 typedef _Packed union {
345 /* Treat it as 64-bit opaque */
346 _Packed struct {
347 volatile uint32_t hi;
348 volatile uint32_t lo;
349 } _PackedType;
350 /* Treat it as s/w portal stashing config */
351 /* See 1.5.6.7.1: "FQD Context_A field used for [...] */
352 _Packed struct {
353 struct qm_fqd_stashing stashing;
354 volatile uint8_t reserved1;
355 /* 40-bit address of FQ context to
356 * stash, must be cacheline-aligned */
357 volatile uint8_t context_hi;
358 volatile uint32_t context_lo;
359 } _PackedType;
360 } _PackedType u_QmFqdContextA;
361
362 /* See 1.5.1.1: "Frame Descriptor (FD)" */
363 _Packed struct qm_fd {
364 volatile uint8_t dd:2; /* dynamic debug */
365 volatile uint8_t liodn_offset:6; /* aka. "Partition ID" in rev1.0 */
366 volatile uint8_t bpid; /* Buffer Pool ID */
367 volatile uint8_t eliodn_offset:4;
368 volatile uint8_t reserved:4;
369 volatile uint8_t addr_hi; /* high 8-bits of 40-bit address */
370 volatile uint32_t addr_lo; /* low 32-bits of 40-bit address */
371 /* The 'format' field indicates the interpretation of the remaining 29
372 * bits of the 32-bit word. For packing reasons, it is duplicated in the
373 * other union elements. */
374 _Packed union {
375 /* If 'format' is _contig or _sg, 20b length and 9b offset */
376 _Packed struct {
377 volatile enum qm_fd_format format:3;
378 volatile uint16_t offset:9;
379 volatile uint32_t length20:20;
380 } _PackedType;
381 /* If 'format' is _contig_big or _sg_big, 29b length */
382 _Packed struct {
383 volatile enum qm_fd_format _format1:3;
384 volatile uint32_t length29:29;
385 } _PackedType;
386 /* If 'format' is _compound, 29b "congestion weight" */
387 _Packed struct {
388 volatile enum qm_fd_format _format2:3;
389 volatile uint32_t cong_weight:29;
390 } _PackedType;
391 /* For easier/faster copying of this part of the fd (eg. from a
392 * DQRR entry to an EQCR entry) copy 'opaque' */
393 volatile uint32_t opaque;
394 } _PackedType;
395 _Packed union {
396 volatile uint32_t cmd;
397 volatile uint32_t status;
398 }_PackedType;
399 } _PackedType;
400
401 #define QM_FD_DD_NULL 0x00
402 #define QM_FD_PID_MASK 0x3f
403
404 /* See 1.5.8.1: "Enqueue Command" */
405 _Packed struct qm_eqcr_entry {
406 volatile uint8_t __dont_write_directly__verb;
407 volatile uint8_t dca;
408 volatile uint16_t seqnum;
409 volatile uint32_t orp; /* 24-bit */
410 volatile uint32_t fqid; /* 24-bit */
411 volatile uint32_t tag;
412 volatile struct qm_fd fd;
413 volatile uint8_t reserved3[32];
414 } _PackedType;
415
416 #define QM_EQCR_VERB_VBIT 0x80
417 #define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */
418 #define QM_EQCR_VERB_CMD_ENQUEUE 0x01
419 #define QM_EQCR_VERB_COLOUR_MASK 0x18 /* 4 possible values; */
420 #define QM_EQCR_VERB_COLOUR_GREEN 0x00
421 #define QM_EQCR_VERB_COLOUR_YELLOW 0x08
422 #define QM_EQCR_VERB_COLOUR_RED 0x10
423 #define QM_EQCR_VERB_COLOUR_OVERRIDE 0x18
424 #define QM_EQCR_VERB_INTERRUPT 0x04 /* on command consumption */
425 #define QM_EQCR_VERB_ORP 0x02 /* enable order restoration */
426 #define QM_EQCR_DCA_ENABLE 0x80
427 #define QM_EQCR_DCA_PARK 0x40
428 #define QM_EQCR_DCA_IDXMASK 0x0f /* "DQRR::idx" goes here */
429 #define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */
430 #define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */
431 #define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */
432 #define QM_EQCR_FQID_NULL 0 /* eg. for an ORP seqnum hole */
433
434 /* See 1.5.8.2: "Frame Dequeue Response" */
435 _Packed struct qm_dqrr_entry {
436 volatile uint8_t verb;
437 volatile uint8_t stat;
438 volatile uint16_t seqnum; /* 15-bit */
439 volatile uint8_t tok;
440 volatile uint8_t reserved2[3];
441 volatile uint32_t fqid; /* 24-bit */
442 volatile uint32_t contextB;
443 volatile struct qm_fd fd;
444 volatile uint8_t reserved4[32];
445 } _PackedType;
446
447 #define QM_DQRR_VERB_VBIT 0x80
448 #define QM_DQRR_VERB_MASK 0x7f /* where the verb contains; */
449 #define QM_DQRR_VERB_FRAME_DEQUEUE 0x60 /* "this format" */
450 #define QM_DQRR_STAT_FQ_EMPTY 0x80 /* FQ empty */
451 #define QM_DQRR_STAT_FQ_HELDACTIVE 0x40 /* FQ held active */
452 #define QM_DQRR_STAT_FQ_FORCEELIGIBLE 0x20 /* FQ was force-eligible'd */
453 #define QM_DQRR_STAT_FD_VALID 0x10 /* has a non-NULL FD */
454 #define QM_DQRR_STAT_UNSCHEDULED 0x02 /* Unscheduled dequeue */
455 #define QM_DQRR_STAT_DQCR_EXPIRED 0x01 /* VDQCR or PDQCR expired*/
456
457 #define VDQCR_DONE (QM_DQRR_STAT_UNSCHEDULED | QM_DQRR_STAT_DQCR_EXPIRED)
458
459
460 /* See 1.5.8.3: "ERN Message Response" */
461 /* See 1.5.8.4: "FQ State Change Notification" */
462 _Packed struct qm_mr_entry {
463 volatile uint8_t verb;
464 _Packed union {
465 _Packed struct {
466 volatile uint8_t dca;
467 volatile uint16_t seqnum;
468 volatile uint8_t rc; /* Rejection Code */
469 volatile uint32_t orp:24;
470 volatile uint32_t fqid; /* 24-bit */
471 volatile uint32_t tag;
472 volatile struct qm_fd fd;
473 } _PackedType ern;
474 _Packed struct {
475 volatile uint8_t colour:2; /* See QM_MR_DCERN_COLOUR_* */
476 volatile uint8_t reserved1:3;
477 volatile enum qm_dc_portal portal:3;
478 volatile uint16_t reserved2;
479 volatile uint8_t rc; /* Rejection Code */
480 volatile uint32_t reserved3:24;
481 volatile uint32_t fqid; /* 24-bit */
482 volatile uint32_t tag;
483 volatile struct qm_fd fd;
484 } _PackedType dcern;
485 _Packed struct {
486 volatile uint8_t fqs; /* Frame Queue Status */
487 volatile uint8_t reserved1[6];
488 volatile uint32_t fqid; /* 24-bit */
489 volatile uint32_t contextB;
490 volatile uint8_t reserved2[16];
491 } _PackedType fq; /* FQRN/FQRNI/FQRL/FQPN */
492 } _PackedType;
493 volatile uint8_t reserved2[32];
494 } _PackedType;
495
496 #define QM_MR_VERB_VBIT 0x80
497 /* The "ern" VERB bits match QM_EQCR_VERB_*** so aren't reproduced here. ERNs
498 * originating from direct-connect portals ("dcern") use 0x20 as a verb which
499 * would be invalid as a s/w enqueue verb. A s/w ERN can be distinguished from
500 * the other MR types by noting if the 0x20 bit is unset. */
501 #define QM_MR_VERB_TYPE_MASK 0x23
502 #define QM_MR_VERB_DC_ERN 0x20
503 #define QM_MR_VERB_FQRN 0x21
504 #define QM_MR_VERB_FQRNI 0x22
505 #define QM_MR_VERB_FQRL 0x23
506 #define QM_MR_VERB_FQPN 0x24
507 #define QM_MR_RC_MASK 0xf0 /* contains one of; */
508 #define QM_MR_RC_CGR_TAILDROP 0x00
509 #define QM_MR_RC_WRED 0x10
510 #define QM_MR_RC_ERROR 0x20
511 #define QM_MR_RC_ORPWINDOW_EARLY 0x30
512 #define QM_MR_RC_ORPWINDOW_LATE 0x40
513 #define QM_MR_RC_FQ_TAILDROP 0x50
514 #define QM_MR_RC_ORP_RETIRED 0x60
515 #define QM_MR_RC_ORP_DISABLE 0x70
516 #define QM_MR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */
517 #define QM_MR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */
518 #define QM_MR_DCERN_COLOUR_GREEN 0x00
519 #define QM_MR_DCERN_COLOUR_YELLOW 0x01
520 #define QM_MR_DCERN_COLOUR_RED 0x02
521 #define QM_MR_DCERN_COLOUR_OVERRIDE 0x03
522
523 /* This identical structure of FQD fields is present in the "Init FQ" command
524 * and the "Query FQ" result. It's suctioned out here into its own struct. It's
525 * also used as the qman_query_fq() result structure in the high-level API. */
526
527 /* TODO What about OAC for intra-class? */
528 #define QM_FQD_TD_THRESH_OAC_EN 0x4000
529
530 _Packed struct qm_fqd {
531 _Packed union {
532 volatile uint8_t orpc;
533 _Packed struct {
534 volatile uint8_t reserved1:2;
535 volatile uint8_t orprws:3;
536 volatile uint8_t oa:1;
537 volatile uint8_t olws:2;
538 } _PackedType;
539 } _PackedType;
540 volatile uint8_t cgid;
541 volatile uint16_t fq_ctrl; /* See QM_FQCTRL_<...> */
542 _Packed union {
543 volatile uint16_t dest_wq;
544 _Packed struct {
545 volatile uint16_t channel:13; /* enum qm_channel */
546 volatile uint16_t wq:3;
547 } _PackedType dest;
548 } _PackedType;
549 volatile uint16_t reserved2:1;
550 volatile uint16_t ics_cred:15;
551 _Packed union {
552 volatile uint16_t td_thresh;
553 _Packed struct {
554 volatile uint16_t reserved1:3;
555 volatile uint16_t mant:8;
556 volatile uint16_t exp:5;
557 } _PackedType td;
558 } _PackedType;
559 volatile uint32_t context_b;
560 volatile u_QmFqdContextA context_a;
561 } _PackedType;
562
563 /* See 1.5.2.2: "Frame Queue Descriptor (FQD)" */
564 /* Frame Queue Descriptor (FQD) field 'fq_ctrl' uses these constants */
565 #define QM_FQCTRL_MASK 0x07ff /* 'fq_ctrl' flags; */
566 #define QM_FQCTRL_CGE 0x0400 /* Congestion Group Enable */
567 #define QM_FQCTRL_TDE 0x0200 /* Tail-Drop Enable */
568 #define QM_FQCTRL_ORP 0x0100 /* ORP Enable */
569 #define QM_FQCTRL_CTXASTASHING 0x0080 /* Context-A stashing */
570 #define QM_FQCTRL_CPCSTASH 0x0040 /* CPC Stash Enable */
571 #define QM_FQCTRL_FORCESFDR 0x0008 /* High-priority SFDRs */
572 #define QM_FQCTRL_AVOIDBLOCK 0x0004 /* Don't block active */
573 #define QM_FQCTRL_HOLDACTIVE 0x0002 /* Hold active in portal */
574 #define QM_FQCTRL_LOCKINCACHE 0x0001 /* Aggressively cache FQD */
575
576 /* See 1.5.6.7.1: "FQD Context_A field used for [...] */
577 /* Frame Queue Descriptor (FQD) field 'CONTEXT_A' uses these constants */
578 #define QM_STASHING_EXCL_ANNOTATION 0x04
579 #define QM_STASHING_EXCL_DATA 0x02
580 #define QM_STASHING_EXCL_CONTEXT 0x01
581
582 /* See 1.5.8.4: "FQ State Change Notification" */
583 /* This struct represents the 32-bit "WR_PARM_[GYR]" parameters in CGR fields
584 * and associated commands/responses. The WRED parameters are calculated from
585 * these fields as follows;
586 * MaxTH = MA * (2 ^ Mn)
587 * Slope = SA / (2 ^ Sn)
588 * MaxP = 4 * (Pn + 1)
589 */
590 _Packed struct qm_cgr_wr_parm {
591 _Packed union {
592 volatile uint32_t word;
593 _Packed struct {
594 volatile uint32_t MA:8;
595 volatile uint32_t Mn:5;
596 volatile uint32_t SA:7; /* must be between 64-127 */
597 volatile uint32_t Sn:6;
598 volatile uint32_t Pn:6;
599 } _PackedType;
600 } _PackedType;
601 } _PackedType;
602
603 /* This struct represents the 13-bit "CS_THRES" CGR field. In the corresponding
604 * management commands, this is padded to a 16-bit structure field, so that's
605 * how we represent it here. The congestion state threshold is calculated from
606 * these fields as follows;
607 * CS threshold = TA * (2 ^ Tn)
608 */
609 _Packed struct qm_cgr_cs_thres {
610 volatile uint16_t reserved:3;
611 volatile uint16_t TA:8;
612 volatile uint16_t Tn:5;
613 } _PackedType;
614
615 /* This identical structure of CGR fields is present in the "Init/Modify CGR"
616 * commands and the "Query CGR" result. It's suctioned out here into its own
617 * struct. */
618 _Packed struct __qm_mc_cgr {
619 volatile struct qm_cgr_wr_parm wr_parm_g;
620 volatile struct qm_cgr_wr_parm wr_parm_y;
621 volatile struct qm_cgr_wr_parm wr_parm_r;
622 volatile uint8_t wr_en_g; /* boolean, use QM_CGR_EN */
623 volatile uint8_t wr_en_y; /* boolean, use QM_CGR_EN */
624 volatile uint8_t wr_en_r; /* boolean, use QM_CGR_EN */
625 volatile uint8_t cscn_en; /* boolean, use QM_CGR_EN */
626 volatile uint32_t cscn_targ; /* use QM_CGR_TARG_* */
627 volatile uint8_t cstd_en; /* boolean, use QM_CGR_EN */
628 volatile uint8_t cs; /* boolean, only used in query response */
629 volatile struct qm_cgr_cs_thres cs_thres;
630 volatile uint8_t frame_mode; /* boolean, use QM_CGR_EN */
631 } _PackedType;
632
633 #define QM_CGR_EN 0x01 /* For wr_en_*, cscn_en, cstd_en, frame_mode */
634
635 /* See 1.5.8.5.1: "Initialize FQ" */
636 /* See 1.5.8.5.2: "Query FQ" */
637 /* See 1.5.8.5.3: "Query FQ Non-Programmable Fields" */
638 /* See 1.5.8.5.4: "Alter FQ State Commands " */
639 /* See 1.5.8.6.1: "Initialize/Modify CGR" */
640 /* See 1.5.8.6.2: "Query CGR" */
641 /* See 1.5.8.6.3: "Query Congestion Group State" */
642 _Packed struct qm_mc_command {
643 volatile uint8_t __dont_write_directly__verb;
644 _Packed union {
645 _Packed struct qm_mcc_initfq {
646 volatile uint8_t reserved1;
647 volatile uint16_t we_mask; /* Write Enable Mask */
648 volatile uint32_t fqid; /* 24-bit */
649 volatile uint16_t count; /* Initialises 'count+1' FQDs */
650 volatile struct qm_fqd fqd; /* the FQD fields go here */
651 volatile uint8_t reserved3[32];
652 } _PackedType initfq;
653 _Packed struct qm_mcc_queryfq {
654 volatile uint8_t reserved1[3];
655 volatile uint32_t fqid; /* 24-bit */
656 volatile uint8_t reserved2[56];
657 } _PackedType queryfq;
658 _Packed struct qm_mcc_queryfq_np {
659 volatile uint8_t reserved1[3];
660 volatile uint32_t fqid; /* 24-bit */
661 volatile uint8_t reserved2[56];
662 } _PackedType queryfq_np;
663 _Packed struct qm_mcc_alterfq {
664 volatile uint8_t reserved1[3];
665 volatile uint32_t fqid; /* 24-bit */
666 volatile uint8_t reserved2[12];
667 volatile uint32_t context_b;
668 volatile uint8_t reserved3[40];
669 } _PackedType alterfq;
670 _Packed struct qm_mcc_initcgr {
671 volatile uint8_t reserved1;
672 volatile uint16_t we_mask; /* Write Enable Mask */
673 volatile struct __qm_mc_cgr cgr; /* CGR fields */
674 volatile uint8_t reserved2[2];
675 volatile uint8_t cgid;
676 volatile uint8_t reserved4[32];
677 } _PackedType initcgr;
678 _Packed struct qm_mcc_querycgr {
679 volatile uint8_t reserved1[30];
680 volatile uint8_t cgid;
681 volatile uint8_t reserved2[32];
682 } _PackedType querycgr;
683 _Packed struct qm_mcc_querycongestion {
684 volatile uint8_t reserved[63];
685 } _PackedType querycongestion;
686 _Packed struct qm_mcc_querywq {
687 volatile uint8_t reserved;
688 /* select channel if verb != QUERYWQ_DEDICATED */
689 _Packed union {
690 volatile uint16_t channel_wq; /* ignores wq (3 lsbits) */
691 _Packed struct {
692 volatile uint16_t id:13; /* enum qm_channel */
693 volatile uint16_t reserved1:3;
694 } _PackedType channel;
695 } _PackedType;
696 volatile uint8_t reserved2[60];
697 } _PackedType querywq;
698 } _PackedType;
699 } _PackedType;
700
701 #define QM_MCC_VERB_VBIT 0x80
702 #define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */
703 #define QM_MCC_VERB_INITFQ_PARKED 0x40
704 #define QM_MCC_VERB_INITFQ_SCHED 0x41
705 #define QM_MCC_VERB_QUERYFQ 0x44
706 #define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */
707 #define QM_MCC_VERB_QUERYWQ 0x46
708 #define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47
709 #define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */
710 #define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */
711 #define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */
712 #define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */
713 #define QM_MCC_VERB_ALTER_RETIRE_CTXB 0x4c /* Retire FQ with contextB*/
714 #define QM_MCC_VERB_INITCGR 0x50
715 #define QM_MCC_VERB_MODIFYCGR 0x51
716 #define QM_MCC_VERB_QUERYCGR 0x58
717 #define QM_MCC_VERB_QUERYCONGESTION 0x59
718 /* INITFQ-specific flags */
719 #define QM_INITFQ_WE_MASK 0x01ff /* 'Write Enable' flags; */
720 #define QM_INITFQ_WE_OAC 0x0100
721 #define QM_INITFQ_WE_ORPC 0x0080
722 #define QM_INITFQ_WE_CGID 0x0040
723 #define QM_INITFQ_WE_FQCTRL 0x0020
724 #define QM_INITFQ_WE_DESTWQ 0x0010
725 #define QM_INITFQ_WE_ICSCRED 0x0008
726 #define QM_INITFQ_WE_TDTHRESH 0x0004
727 #define QM_INITFQ_WE_CONTEXTB 0x0002
728 #define QM_INITFQ_WE_CONTEXTA 0x0001
729 /* INITCGR/MODIFYCGR-specific flags */
730 #define QM_CGR_WE_MASK 0x07ff /* 'Write Enable Mask'; */
731 #define QM_CGR_WE_WR_PARM_G 0x0400
732 #define QM_CGR_WE_WR_PARM_Y 0x0200
733 #define QM_CGR_WE_WR_PARM_R 0x0100
734 #define QM_CGR_WE_WR_EN_G 0x0080
735 #define QM_CGR_WE_WR_EN_Y 0x0040
736 #define QM_CGR_WE_WR_EN_R 0x0020
737 #define QM_CGR_WE_CSCN_EN 0x0010
738 #define QM_CGR_WE_CSCN_TARG 0x0008
739 #define QM_CGR_WE_CSTD_EN 0x0004
740 #define QM_CGR_WE_CS_THRES 0x0002
741 #define QM_CGR_WE_MODE 0x0001
742
743 /* See 1.5.8.5.1: "Initialize FQ" */
744 /* See 1.5.8.5.2: "Query FQ" */
745 /* See 1.5.8.5.3: "Query FQ Non-Programmable Fields" */
746 /* See 1.5.8.5.4: "Alter FQ State Commands " */
747 /* See 1.5.8.6.1: "Initialize/Modify CGR" */
748 /* See 1.5.8.6.2: "Query CGR" */
749 /* See 1.5.8.6.3: "Query Congestion Group State" */
750 _Packed struct qm_mc_result {
751 volatile uint8_t verb;
752 volatile uint8_t result;
753 _Packed union {
754 _Packed struct qm_mcr_initfq {
755 volatile uint8_t reserved1[62];
756 } _PackedType initfq;
757 _Packed struct qm_mcr_queryfq {
758 volatile uint8_t reserved1[8];
759 volatile struct qm_fqd fqd; /* the FQD fields are here */
760 volatile uint16_t oac;
761 volatile uint8_t reserved2[30];
762 } _PackedType queryfq;
763 _Packed struct qm_mcr_queryfq_np {
764 volatile uint8_t reserved1;
765 volatile uint8_t state; /* QM_MCR_NP_STATE_*** */
766 volatile uint8_t reserved2;
767 volatile uint32_t fqd_link:24;
768 volatile uint16_t odp_seq;
769 volatile uint16_t orp_nesn;
770 volatile uint16_t orp_ea_hseq;
771 volatile uint16_t orp_ea_tseq;
772 volatile uint8_t reserved3;
773 volatile uint32_t orp_ea_hptr:24;
774 volatile uint8_t reserved4;
775 volatile uint32_t orp_ea_tptr:24;
776 volatile uint8_t reserved5;
777 volatile uint32_t pfdr_hptr:24;
778 volatile uint8_t reserved6;
779 volatile uint32_t pfdr_tptr:24;
780 volatile uint8_t reserved7[5];
781 volatile uint8_t reserved8:7;
782 volatile uint8_t is:1;
783 volatile uint16_t ics_surp;
784 volatile uint32_t byte_cnt;
785 volatile uint8_t reserved9;
786 volatile uint32_t frm_cnt:24;
787 volatile uint32_t reserved10;
788 volatile uint16_t ra1_sfdr; /* QM_MCR_NP_RA1_*** */
789 volatile uint16_t ra2_sfdr; /* QM_MCR_NP_RA2_*** */
790 volatile uint16_t reserved11;
791 volatile uint16_t od1_sfdr; /* QM_MCR_NP_OD1_*** */
792 volatile uint16_t od2_sfdr; /* QM_MCR_NP_OD2_*** */
793 volatile uint16_t od3_sfdr; /* QM_MCR_NP_OD3_*** */
794 } _PackedType queryfq_np;
795 _Packed struct qm_mcr_alterfq {
796 volatile uint8_t fqs; /* Frame Queue Status */
797 volatile uint8_t reserved1[61];
798 } _PackedType alterfq;
799 _Packed struct qm_mcr_initcgr {
800 volatile uint8_t reserved1[62];
801 } _PackedType initcgr;
802 _Packed struct qm_mcr_querycgr {
803 volatile uint16_t reserved1;
804 volatile struct __qm_mc_cgr cgr; /* CGR fields */
805 volatile uint8_t reserved2[3];
806 volatile uint32_t reserved3:24;
807 volatile uint32_t i_bcnt_hi:8;/* high 8-bits of 40-bit "Instant" */
808 volatile uint32_t i_bcnt_lo; /* low 32-bits of 40-bit */
809 volatile uint32_t reserved4:24;
810 volatile uint32_t a_bcnt_hi:8;/* high 8-bits of 40-bit "Average" */
811 volatile uint32_t a_bcnt_lo; /* low 32-bits of 40-bit */
812 volatile uint32_t lgt; /* Last Group Tick */
813 volatile uint8_t reserved5[12];
814 } _PackedType querycgr;
815 _Packed struct qm_mcr_querycongestion {
816 volatile uint8_t reserved[30];
817 /* Access this struct using QM_MCR_QUERYCONGESTION() */
818 _Packed struct __qm_mcr_querycongestion {
819 volatile uint32_t __state[8];
820 } _PackedType state;
821 } _PackedType querycongestion;
822 _Packed struct qm_mcr_querywq {
823 _Packed union {
824 volatile uint16_t channel_wq; /* ignores wq (3 lsbits) */
825 _Packed struct {
826 volatile uint16_t id:13; /* enum qm_channel */
827 volatile uint16_t reserved:3;
828 } _PackedType channel;
829 } _PackedType;
830 volatile uint8_t reserved[28];
831 volatile uint32_t wq_len[8];
832 } _PackedType querywq;
833 } _PackedType;
834 } _PackedType;
835
836 #define QM_MCR_VERB_RRID 0x80
837 #define QM_MCR_VERB_MASK QM_MCC_VERB_MASK
838 #define QM_MCR_VERB_INITFQ_PARKED QM_MCC_VERB_INITFQ_PARKED
839 #define QM_MCR_VERB_INITFQ_SCHED QM_MCC_VERB_INITFQ_SCHED
840 #define QM_MCR_VERB_QUERYFQ QM_MCC_VERB_QUERYFQ
841 #define QM_MCR_VERB_QUERYFQ_NP QM_MCC_VERB_QUERYFQ_NP
842 #define QM_MCR_VERB_QUERYWQ QM_MCC_VERB_QUERYWQ
843 #define QM_MCR_VERB_QUERYWQ_DEDICATED QM_MCC_VERB_QUERYWQ_DEDICATED
844 #define QM_MCR_VERB_ALTER_SCHED QM_MCC_VERB_ALTER_SCHED
845 #define QM_MCR_VERB_ALTER_FE QM_MCC_VERB_ALTER_FE
846 #define QM_MCR_VERB_ALTER_RETIRE QM_MCC_VERB_ALTER_RETIRE
847 #define QM_MCR_VERB_ALTER_RETIRE_CTXB QM_MCC_VERB_ALTER_RETIRE_CTXB
848 #define QM_MCR_VERB_ALTER_OOS QM_MCC_VERB_ALTER_OOS
849 #define QM_MCR_RESULT_NULL 0x00
850 #define QM_MCR_RESULT_OK 0xf0
851 #define QM_MCR_RESULT_ERR_FQID 0xf1
852 #define QM_MCR_RESULT_ERR_FQSTATE 0xf2
853 #define QM_MCR_RESULT_ERR_NOTEMPTY 0xf3 /* OOS fails if FQ is !empty */
854 #define QM_MCR_RESULT_ERR_BADCHANNEL 0xf4
855 #define QM_MCR_RESULT_PENDING 0xf8
856 #define QM_MCR_RESULT_ERR_BADCOMMAND 0xff
857 #define QM_MCR_NP_STATE_FE 0x10
858 #define QM_MCR_NP_STATE_R 0x08
859 #define QM_MCR_NP_STATE_MASK 0x07 /* Reads FQD::STATE; */
860 #define QM_MCR_NP_STATE_OOS 0x00
861 #define QM_MCR_NP_STATE_RETIRED 0x01
862 #define QM_MCR_NP_STATE_TEN_SCHED 0x02
863 #define QM_MCR_NP_STATE_TRU_SCHED 0x03
864 #define QM_MCR_NP_STATE_PARKED 0x04
865 #define QM_MCR_NP_STATE_ACTIVE 0x05
866 #define QM_MCR_NP_PTR_MASK 0x07ff /* for RA[12] & OD[123] */
867 #define QM_MCR_NP_RA1_NRA(v) (((v) >> 14) & 0x3) /* FQD::NRA */
868 #define QM_MCR_NP_RA2_IT(v) (((v) >> 14) & 0x1) /* FQD::IT */
869 #define QM_MCR_NP_OD1_NOD(v) (((v) >> 14) & 0x3) /* FQD::NOD */
870 #define QM_MCR_NP_OD3_NPC(v) (((v) >> 14) & 0x3) /* FQD::NPC */
871 #define QM_MCR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */
872 #define QM_MCR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */
873
874 #define MEM_MAP_END
875 #if defined(__MWERKS__) && !defined(__GNUC__)
876 #pragma pack(pop)
877 #endif /* defined(__MWERKS__) && ... */
878
879
880 /* This extracts the state for congestion group 'n' from a query response.
881 * Eg.
882 * uint8_t cgr = [...];
883 * struct qm_mc_result *res = [...];
884 * printf("congestion group %d congestion state: %d\n", cgr,
885 * QM_MCR_QUERYCONGESTION(&res->querycongestion.state, cgr));
886 */
887 #define __CGR_WORD(num) (num >> 5)
888 #define __CGR_SHIFT(num) (num & 0x1f)
QM_MCR_QUERYCONGESTION(struct __qm_mcr_querycongestion * p,uint8_t cgr)889 static __inline__ int QM_MCR_QUERYCONGESTION(struct __qm_mcr_querycongestion *p,
890 uint8_t cgr)
891 {
892 return (int)(p->__state[__CGR_WORD(cgr)] & (0x80000000 >> __CGR_SHIFT(cgr)));
893 }
894
895
896 /*********************/
897 /* Utility interface */
898 /*********************/
899
900 /* Represents an allocator over a range of FQIDs. NB, accesses are not locked,
901 * spinlock them yourself if needed. */
902 struct qman_fqid_pool;
903
904 /* Create/destroy a FQID pool, num must be a multiple of 32. NB, _destroy()
905 * always succeeds, but returns non-zero if there were "leaked" FQID
906 * allocations. */
907 struct qman_fqid_pool *qman_fqid_pool_create(uint32_t fqid_start, uint32_t num);
908 int qman_fqid_pool_destroy(struct qman_fqid_pool *pool);
909 /* Alloc/free a FQID from the range. _alloc() returns zero for success. */
910 int qman_fqid_pool_alloc(struct qman_fqid_pool *pool, uint32_t *fqid);
911 void qman_fqid_pool_free(struct qman_fqid_pool *pool, uint32_t fqid);
912 uint32_t qman_fqid_pool_used(struct qman_fqid_pool *pool);
913
914 /*******************************************************************/
915 /* Managed (aka "shared" or "mux/demux") portal, high-level i/face */
916 /*******************************************************************/
917
918 /* Congestion Groups */
919 /* ----------------- */
920 /* This wrapper represents a bit-array for the state of the 256 Qman congestion
921 * groups. Is also used as a *mask* for congestion groups, eg. so we ignore
922 * those that don't concern us. We harness the structure and accessor details
923 * already used in the management command to query congestion groups. */
924 struct qman_cgrs {
925 struct __qm_mcr_querycongestion q;
926 };
QMAN_CGRS_INIT(struct qman_cgrs * c)927 static __inline__ void QMAN_CGRS_INIT(struct qman_cgrs *c)
928 {
929 memset(c, 0, sizeof(*c));
930 }
QMAN_CGRS_GET(struct qman_cgrs * c,int num)931 static __inline__ int QMAN_CGRS_GET(struct qman_cgrs *c, int num)
932 {
933 return QM_MCR_QUERYCONGESTION(&c->q, (uint8_t)num);
934 }
QMAN_CGRS_SET(struct qman_cgrs * c,int num)935 static __inline__ void QMAN_CGRS_SET(struct qman_cgrs *c, int num)
936 {
937 c->q.__state[__CGR_WORD(num)] |= (0x80000000 >> __CGR_SHIFT(num));
938 }
QMAN_CGRS_UNSET(struct qman_cgrs * c,int num)939 static __inline__ void QMAN_CGRS_UNSET(struct qman_cgrs *c, int num)
940 {
941 c->q.__state[__CGR_WORD(num)] &= ~(0x80000000 >> __CGR_SHIFT(num));
942 }
943
944 /* Portal and Frame Queues */
945 /* ----------------------- */
946
947 /* This object type represents Qman frame queue descriptors (FQD), and is
948 * stored within a cacheline passed to qman_new_fq(). */
949 struct qman_fq;
950
951 /* This enum, and the callback type that returns it, are used when handling
952 * dequeued frames via DQRR. Note that for "null" callbacks registered with the
953 * portal object (for handling dequeues that do not demux because contextB is
954 * NULL), the return value *MUST* be qman_cb_dqrr_consume. */
955 enum qman_cb_dqrr_result {
956 /* DQRR entry can be consumed */
957 qman_cb_dqrr_consume,
958 /* DQRR entry cannot be consumed now, pause until next poll request */
959 qman_cb_dqrr_pause,
960 /* Like _consume, but requests parking - FQ must be held-active */
961 qman_cb_dqrr_park,
962 /* Does not consume, for DCA mode only. This allows out-of-order
963 * consumes by explicit calls to qman_dca() and/or the use of implicit
964 * DCA via EQCR entries. */
965 qman_cb_dqrr_defer
966 };
967
968 /*typedef enum qman_cb_dqrr_result (*qman_cb_dqrr)(t_Handle h_Arg,
969 t_Handle h_QmPortal,
970 struct qman_fq *fq,
971 const struct qm_dqrr_entry *dqrr);*/
972 typedef t_QmReceivedFrameCallback * qman_cb_dqrr;
973 typedef t_QmReceivedFrameCallback * qman_cb_fqs;
974 typedef t_QmRejectedFrameCallback * qman_cb_ern;
975 /* This callback type is used when handling ERNs, FQRNs and FQRLs via MR. They
976 * are always consumed after the callback returns. */
977 typedef void (*qman_cb_mr)(t_Handle h_Arg,
978 t_Handle h_QmPortal,
979 struct qman_fq *fq,
980 const struct qm_mr_entry *msg);
981
982 struct qman_fq_cb {
983 qman_cb_dqrr dqrr; /* for dequeued frames */
984 qman_cb_ern ern; /* for s/w ERNs */
985 qman_cb_mr dc_ern; /* for diverted h/w ERNs */
986 qman_cb_mr fqs; /* frame-queue state changes*/
987 };
988
989 enum qman_fq_state {
990 qman_fq_state_oos,
991 qman_fq_state_waiting_parked,
992 qman_fq_state_parked,
993 qman_fq_state_sched,
994 qman_fq_state_retired
995 };
996
997 /* Flags to qman_create_portal() */
998 #define QMAN_PORTAL_FLAG_IRQ 0x00000001 /* use interrupt handler */
999 #define QMAN_PORTAL_FLAG_IRQ_FAST 0x00000002 /* ... for fast-path too! */
1000 #define QMAN_PORTAL_FLAG_IRQ_SLOW 0x00000003 /* ... for slow-path too! */
1001 #define QMAN_PORTAL_FLAG_DCA 0x00000004 /* use DCA */
1002 #define QMAN_PORTAL_FLAG_LOCKED 0x00000008 /* multi-core locking */
1003 #define QMAN_PORTAL_FLAG_NOTAFFINE 0x00000010 /* not cpu-default portal */
1004 #define QMAN_PORTAL_FLAG_RSTASH 0x00000020 /* enable DQRR entry stashing */
1005 #define QMAN_PORTAL_FLAG_DSTASH 0x00000040 /* enable data stashing */
1006 #define QMAN_PORTAL_FLAG_RECOVER 0x00000080 /* recovery mode */
1007 #define QMAN_PORTAL_FLAG_WAIT 0x00000100 /* for recovery; can wait */
1008 #define QMAN_PORTAL_FLAG_WAIT_INT 0x00000200 /* for wait; interruptible */
1009 #define QMAN_PORTAL_FLAG_CACHE 0x00000400 /* use cachable area for EQCR/DQRR */
1010
1011 /* Flags to qman_create_fq() */
1012 #define QMAN_FQ_FLAG_NO_ENQUEUE 0x00000001 /* can't enqueue */
1013 #define QMAN_FQ_FLAG_NO_MODIFY 0x00000002 /* can only enqueue */
1014 #define QMAN_FQ_FLAG_TO_DCPORTAL 0x00000004 /* consumed by CAAM/PME/Fman */
1015 #define QMAN_FQ_FLAG_LOCKED 0x00000008 /* multi-core locking */
1016 #define QMAN_FQ_FLAG_RECOVER 0x00000010 /* recovery mode */
1017 #define QMAN_FQ_FLAG_DYNAMIC_FQID 0x00000020 /* (de)allocate fqid */
1018
1019 /* Flags to qman_destroy_fq() */
1020 #define QMAN_FQ_DESTROY_PARKED 0x00000001 /* FQ can be parked or OOS */
1021
1022 /* Flags from qman_fq_state() */
1023 #define QMAN_FQ_STATE_CHANGING 0x80000000 /* 'state' is changing */
1024 #define QMAN_FQ_STATE_NE 0x40000000 /* retired FQ isn't empty */
1025 #define QMAN_FQ_STATE_ORL 0x20000000 /* retired FQ has ORL */
1026 #define QMAN_FQ_STATE_BLOCKOOS 0xe0000000 /* if any are set, no OOS */
1027 #define QMAN_FQ_STATE_CGR_EN 0x10000000 /* CGR enabled */
1028 #define QMAN_FQ_STATE_VDQCR 0x08000000 /* being volatile dequeued */
1029
1030 /* Flags to qman_init_fq() */
1031 #define QMAN_INITFQ_FLAG_SCHED 0x00000001 /* schedule rather than park */
1032 #define QMAN_INITFQ_FLAG_NULL 0x00000002 /* zero 'contextB', no demux */
1033 #define QMAN_INITFQ_FLAG_LOCAL 0x00000004 /* set dest portal */
1034
1035 /* Flags to qman_volatile_dequeue() */
1036 #define QMAN_VOLATILE_FLAG_WAIT_INT 0x00000001 /* if we wait, interruptible? */
1037 #define QMAN_VOLATILE_FLAG_WAIT 0x00000002 /* wait if VDQCR is in use */
1038 #define QMAN_VOLATILE_FLAG_FINISH 0x00000004 /* wait till VDQCR completes */
1039
1040 /* Flags to qman_enqueue(). NB, the strange numbering is to align with
1041 * hardware, bit-wise. */
1042 #define QMAN_ENQUEUE_FLAG_WAIT 0x00010000 /* wait if EQCR is full */
1043 #define QMAN_ENQUEUE_FLAG_WAIT_INT 0x00020000 /* if wait, interruptible? */
1044 #define QMAN_ENQUEUE_FLAG_WAIT_SYNC 0x00040000 /* if wait, until consumed? */
1045 #define QMAN_ENQUEUE_FLAG_WATCH_CGR 0x00080000 /* watch congestion state */
1046 #define QMAN_ENQUEUE_FLAG_INTERRUPT 0x00000004 /* on command consumption */
1047 #define QMAN_ENQUEUE_FLAG_DCA 0x00008000 /* perform enqueue-DCA */
1048 #define QMAN_ENQUEUE_FLAG_DCA_PARK 0x00004000 /* If DCA, requests park */
1049 #define QMAN_ENQUEUE_FLAG_DCA_PTR(p) /* If DCA, p is DQRR entry */ \
1050 (((uint32_t)(p) << 2) & 0x00000f00)
1051 #define QMAN_ENQUEUE_FLAG_C_GREEN 0x00000000 /* choose one C_*** flag */
1052 #define QMAN_ENQUEUE_FLAG_C_YELLOW 0x00000008
1053 #define QMAN_ENQUEUE_FLAG_C_RED 0x00000010
1054 #define QMAN_ENQUEUE_FLAG_C_OVERRIDE 0x00000018
1055 /* For the ORP-specific qman_enqueue_orp() variant, this flag indicates "Not
1056 * Last In Sequence", ie. a non-terminating fragment. */
1057 #define QMAN_ENQUEUE_FLAG_NLIS 0x01000000
1058 /* - this flag performs no enqueue but fills in an ORP sequence number that
1059 * would otherwise block it (eg. if a frame has been dropped). */
1060 #define QMAN_ENQUEUE_FLAG_HOLE 0x02000000
1061 /* - this flag performs no enqueue but advances NESN to the given sequence
1062 * number. */
1063 #define QMAN_ENQUEUE_FLAG_NESN 0x04000000
1064
1065 /* FQ management */
1066 /* ------------- */
1067 /**
1068 * qman_free_fq - Deallocates a FQ
1069 * @fq: the frame queue object to release
1070 * @flags: bit-mask of QMAN_FQ_FREE_*** options
1071 *
1072 * The memory for this frame queue object ('mem' provided in qman_new_fq()) is
1073 * not deallocated but the caller regains ownership, to do with as desired. The
1074 * FQ must be in the 'out-of-service' state unless the QMAN_FQ_FREE_PARKED flag
1075 * is specified, in which case it may also be in the 'parked' state.
1076 */
1077 void qman_free_fq(struct qman_fq *fq, uint32_t flags);
1078
1079 /**
1080 * qman_fq_fqid - Queries the frame queue ID of a FQ object
1081 * @fq: the frame queue object to query
1082 */
1083 uint32_t qman_fq_fqid(struct qman_fq *fq);
1084
1085 /**
1086 * qman_fq_state - Queries the state of a FQ object
1087 * @fq: the frame queue object to query
1088 * @state: pointer to state enum to return the FQ scheduling state
1089 * @flags: pointer to state flags to receive QMAN_FQ_STATE_*** bitmask
1090 *
1091 * Queries the state of the FQ object, without performing any h/w commands.
1092 * This captures the state, as seen by the driver, at the time the function
1093 * executes.
1094 */
1095 void qman_fq_state(struct qman_fq *fq, enum qman_fq_state *state, uint32_t *flags);
1096
1097 #endif /* __FSL_QMAN_H */
1098