xref: /original-bsd/sys/vax/if/if_cssreg.h (revision 983d6bab)
1 /*
2  * Copyright (c) 1982, 1986 Regents of the University of California.
3  * All rights reserved.
4  *
5  * %sccs.include.redist.c%
6  *
7  *	@(#)if_cssreg.h	7.3 (Berkeley) 06/28/90
8  */
9 
10 /*
11  * DEC/CSS IMP11-A ARPAnet interface
12  */
13 
14 struct cssdma {
15 	short	wc;		/* word count */
16 	u_short	ba;		/* bus address (low 16 bits) */
17 	short	csr;		/* status register */
18 	short	db;		/* data buffer*/
19 };
20 
21 struct cssdevice {
22 	struct	cssdma	css_output;	/* transmit DR11-B */
23 	struct	cssdma	css_hole;	/* unclever gap */
24 	struct	cssdma	css_input;	/* receive DR11-B */
25 };
26 
27 #define css_icsr        css_input.csr
28 #define css_iba         css_input.ba
29 #define css_iwc         css_input.wc
30 #define css_ocsr        css_output.csr
31 #define css_oba         css_output.ba
32 #define css_owc         css_output.wc
33 
34 /*
35  * Bits Common to both input and out CSR's
36  */
37 #define CSS_ERR         0x8000          /* error present */
38 #define CSS_NXM         0x4000          /* non-existant memory */
39 #define	CSS_ATTN	0x2000		/* attention */
40 #define	CSS_MAINT	0x1000		/* maintenance mode */
41 #define	CSS_CYCLE	0x0100		/* force bus cycle */
42 #define CSS_RDY         0x0080          /* ready */
43 #define CSS_IE          0x0040          /* interrupt enable */
44 #define	CSS_XA		0x0030		/* extended address bits */
45 #define	CSS_CLR		0x0020		/* clear status (reset) */
46 #define CSS_GO          0x0001          /* start operation */
47 
48 /*
49  * Input Control Status Register
50  */
51 #define IN_EOM          0x0800          /* end-of-message recieved */
52 #define IN_IMPNR	0x0400          /* IMP not ready */
53 #define IN_RLE          0x0200          /* ready line error */
54 #define IN_WEN          0x0008          /* write enable */
55 #define IN_HRDY         0x0004          /* host ready */
56 
57 #define CSS_INBITS \
58 "\20\20ERR\17NXM\16ATTN\15MAINT\14EOM\13IMPNR\12RLE\11CYCLE\10RDY\7IE\6XBA17\5XBA16\4WE\3HRDY\2CLR\1GO"
59 
60 
61 /*
62  * Output Control Status Register
63  */
64 #define OUT_TXEC	0x0008          /* tx error clear */
65 #define OUT_ENLB	0x0004          /* enable last bit */
66 
67 #define CSS_OUTBITS \
68 "\20\20ERR\17NXM\16ATTN\15MAINT\11CYCLE\10RDY\7IE\6XBA17\5XBA16\4TXEC\3ENLB\2CLR\1GO"
69