1 /* Definitions of target machine for Mitsubishi D30V.
2 Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
4
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "rtl.h"
25 #include "tree.h"
26 #include "regs.h"
27 #include "hard-reg-set.h"
28 #include "real.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "output.h"
32 #include "insn-attr.h"
33 #include "flags.h"
34 #include "recog.h"
35 #include "expr.h"
36 #include "obstack.h"
37 #include "tm_p.h"
38 #include "except.h"
39 #include "function.h"
40 #include "toplev.h"
41 #include "integrate.h"
42 #include "ggc.h"
43 #include "target.h"
44 #include "target-def.h"
45 #include "langhooks.h"
46
47 static void d30v_print_operand_memory_reference PARAMS ((FILE *, rtx));
48 static void d30v_build_long_insn PARAMS ((HOST_WIDE_INT, HOST_WIDE_INT,
49 rtx, rtx));
50 static struct machine_function * d30v_init_machine_status PARAMS ((void));
51 static void d30v_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
52 static void d30v_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
53 static int d30v_adjust_cost PARAMS ((rtx, rtx, rtx, int));
54 static int d30v_issue_rate PARAMS ((void));
55
56 /* Define the information needed to generate branch and scc insns. This is
57 stored from the compare operation. */
58
59 struct rtx_def *d30v_compare_op0;
60 struct rtx_def *d30v_compare_op1;
61
62 /* Cached value of d30v_stack_info */
63 static d30v_stack_t *d30v_stack_cache = (d30v_stack_t *)0;
64
65 /* Values of the -mbranch-cost=n string. */
66 int d30v_branch_cost = D30V_DEFAULT_BRANCH_COST;
67 const char *d30v_branch_cost_string = (const char *)0;
68
69 /* Values of the -mcond-exec=n string. */
70 int d30v_cond_exec = D30V_DEFAULT_MAX_CONDITIONAL_EXECUTE;
71 const char *d30v_cond_exec_string = (const char *)0;
72
73 /* Whether or not a hard register can accept a register */
74 unsigned char hard_regno_mode_ok[ (int)MAX_MACHINE_MODE ][FIRST_PSEUDO_REGISTER];
75
76 /* Whether to try and avoid moves between two different modes */
77 unsigned char modes_tieable_p[ (NUM_MACHINE_MODES) * (NUM_MACHINE_MODES) ];
78
79 /* Map register number to smallest register class. */
80 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
81
82 /* Map class letter into register class */
83 enum reg_class reg_class_from_letter[256];
84
85 /* Initialize the GCC target structure. */
86 #undef TARGET_ASM_ALIGNED_HI_OP
87 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
88 #undef TARGET_ASM_ALIGNED_SI_OP
89 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
90
91 #undef TARGET_ASM_FUNCTION_PROLOGUE
92 #define TARGET_ASM_FUNCTION_PROLOGUE d30v_output_function_prologue
93 #undef TARGET_ASM_FUNCTION_EPILOGUE
94 #define TARGET_ASM_FUNCTION_EPILOGUE d30v_output_function_epilogue
95 #undef TARGET_SCHED_ADJUST_COST
96 #define TARGET_SCHED_ADJUST_COST d30v_adjust_cost
97 #undef TARGET_SCHED_ISSUE_RATE
98 #define TARGET_SCHED_ISSUE_RATE d30v_issue_rate
99
100 struct gcc_target targetm = TARGET_INITIALIZER;
101
102 /* Sometimes certain combinations of command options do not make
103 sense on a particular target machine. You can define a macro
104 `OVERRIDE_OPTIONS' to take account of this. This macro, if
105 defined, is executed once just after all the command options have
106 been parsed.
107
108 Don't use this macro to turn on various extra optimizations for
109 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
110
111 void
override_options()112 override_options ()
113 {
114 int regno, i, ok_p;
115 enum machine_mode mode1, mode2;
116
117 /* Set up the branch cost information */
118 if (d30v_branch_cost_string)
119 d30v_branch_cost = atoi (d30v_branch_cost_string);
120
121 /* Set up max # instructions to use with conditional execution */
122 if (d30v_cond_exec_string)
123 d30v_cond_exec = atoi (d30v_cond_exec_string);
124
125 /* Setup hard_regno_mode_ok/modes_tieable_p */
126 for (mode1 = VOIDmode;
127 (int)mode1 < NUM_MACHINE_MODES;
128 mode1 = (enum machine_mode)((int)mode1 + 1))
129 {
130 int size = GET_MODE_SIZE (mode1);
131 int large_p = size > UNITS_PER_WORD;
132 int int_p = GET_MODE_CLASS (mode1) == MODE_INT;
133
134 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
135 {
136 if (mode1 == VOIDmode)
137 ok_p = FALSE;
138
139 else if (GPR_P (regno))
140 {
141 if (!large_p)
142 ok_p = TRUE;
143 else
144 ok_p = (((regno - GPR_FIRST) & 1) == 0);
145 }
146
147 else if (FLAG_P (regno))
148 ok_p = (mode1 == CCmode);
149
150 else if (CR_P (regno))
151 ok_p = int_p && !large_p;
152
153 else if (ACCUM_P (regno))
154 ok_p = (mode1 == DImode);
155
156 else if (SPECIAL_REG_P (regno))
157 ok_p = (mode1 == SImode);
158
159 else
160 ok_p = FALSE;
161
162 hard_regno_mode_ok[ (int)mode1 ][ regno ] = ok_p;
163 }
164
165 /* A C expression that is nonzero if it is desirable to choose
166 register allocation so as to avoid move instructions between a
167 value of mode MODE1 and a value of mode MODE2.
168
169 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
170 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
171 MODE2)' must be zero. */
172 for (mode2 = VOIDmode;
173 (int)mode2 <= NUM_MACHINE_MODES;
174 mode2 = (enum machine_mode)((int)mode2 + 1))
175 {
176 if (mode1 == mode2)
177 ok_p = TRUE;
178
179 #if 0
180 else if (GET_MODE_CLASS (mode1) == MODE_INT
181 && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD
182 && GET_MODE_CLASS (mode2) == MODE_INT
183 && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
184 ok_p = TRUE;
185 #endif
186
187 else
188 ok_p = FALSE;
189
190 modes_tieable_p[ ((int)mode1 * (NUM_MACHINE_MODES)) + (int)mode2 ] = ok_p;
191 }
192 }
193
194 #if 0
195 for (mode1 = VOIDmode;
196 (int)mode1 < NUM_MACHINE_MODES;
197 mode1 = (enum machine_mode)((int)mode1 + 1))
198 {
199 for (mode2 = VOIDmode;
200 (int)mode2 <= NUM_MACHINE_MODES;
201 mode2 = (enum machine_mode)((int)mode2 + 1))
202 {
203 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
204 if (ok_p
205 && (hard_regno_mode_ok[(int)mode1][regno]
206 != hard_regno_mode_ok[(int)mode2][regno]))
207 error ("bad modes_tieable_p for register %s, mode1 %s, mode2 %s",
208 reg_names[regno], GET_MODE_NAME (mode1),
209 GET_MODE_NAME (mode2));
210 }
211 }
212 #endif
213
214 /* A C expression whose value is a register class containing hard
215 register REGNO. In general there is more than one such class;
216 choose a class which is "minimal", meaning that no smaller class
217 also contains the register. */
218 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
219 {
220 enum reg_class class;
221
222 if (GPR_P (regno))
223 class = (IN_RANGE_P (regno, GPR_FIRST+2, GPR_FIRST+62)
224 && ((regno - GPR_FIRST) & 1) == 0) ? EVEN_REGS : GPR_REGS;
225
226 else if (regno == FLAG_F0)
227 class = F0_REGS;
228
229 else if (regno == FLAG_F1)
230 class = F1_REGS;
231
232 else if (FLAG_P (regno))
233 class = OTHER_FLAG_REGS;
234
235 else if (ACCUM_P (regno))
236 class = ACCUM_REGS;
237
238 else if (regno == CR_RPT_C)
239 class = REPEAT_REGS;
240
241 else if (CR_P (regno))
242 class = CR_REGS;
243
244 else if (SPECIAL_REG_P (regno))
245 class = GPR_REGS;
246
247 else
248 class = NO_REGS;
249
250 regno_reg_class[regno] = class;
251
252 #if 0
253 {
254 static const char *const names[] = REG_CLASS_NAMES;
255 fprintf (stderr, "Register %s class is %s, can hold modes", reg_names[regno], names[class]);
256 for (mode1 = VOIDmode;
257 (int)mode1 < NUM_MACHINE_MODES;
258 mode1 = (enum machine_mode)((int)mode1 + 1))
259 {
260 if (hard_regno_mode_ok[ (int)mode1 ][ regno ])
261 fprintf (stderr, " %s", GET_MODE_NAME (mode1));
262 }
263 fprintf (stderr, "\n");
264 }
265 #endif
266 }
267
268 /* A C expression which defines the machine-dependent operand
269 constraint letters for register classes. If CHAR is such a
270 letter, the value should be the register class corresponding to
271 it. Otherwise, the value should be `NO_REGS'. The register
272 letter `r', corresponding to class `GENERAL_REGS', will not be
273 passed to this macro; you do not need to handle it.
274
275 The following letters are unavailable, due to being used as
276 constraints:
277 '0'..'9'
278 '<', '>'
279 'E', 'F', 'G', 'H'
280 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
281 'Q', 'R', 'S', 'T', 'U'
282 'V', 'X'
283 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
284
285 for (i = 0; i < 256; i++)
286 reg_class_from_letter[i] = NO_REGS;
287
288 reg_class_from_letter['a'] = ACCUM_REGS;
289 reg_class_from_letter['b'] = BR_FLAG_REGS;
290 reg_class_from_letter['c'] = CR_REGS;
291 reg_class_from_letter['d'] = GPR_REGS;
292 reg_class_from_letter['e'] = EVEN_REGS;
293 reg_class_from_letter['f'] = FLAG_REGS;
294 reg_class_from_letter['l'] = REPEAT_REGS;
295 reg_class_from_letter['x'] = F0_REGS;
296 reg_class_from_letter['y'] = F1_REGS;
297 reg_class_from_letter['z'] = OTHER_FLAG_REGS;
298 }
299
300
301 /* Return true if a memory operand is a short memory operand. */
302
303 int
short_memory_operand(op,mode)304 short_memory_operand (op, mode)
305 register rtx op;
306 enum machine_mode mode;
307 {
308 if (GET_CODE (op) != MEM)
309 return FALSE;
310
311 if (GET_MODE (op) != mode && mode != VOIDmode)
312 return FALSE;
313
314 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
315 == 1);
316 }
317
318 /* Return true if a memory operand is a long operand. */
319
320 int
long_memory_operand(op,mode)321 long_memory_operand (op, mode)
322 rtx op;
323 enum machine_mode mode;
324 {
325 if (GET_CODE (op) != MEM)
326 return FALSE;
327
328 if (GET_MODE (op) != mode && mode != VOIDmode)
329 return FALSE;
330
331 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
332 == 2);
333 }
334
335 /* Return true if a memory operand is valid for the D30V. */
336
337 int
d30v_memory_operand(op,mode)338 d30v_memory_operand (op, mode)
339 rtx op;
340 enum machine_mode mode;
341 {
342 if (GET_CODE (op) != MEM)
343 return FALSE;
344
345 if (GET_MODE (op) != mode && mode != VOIDmode)
346 return FALSE;
347
348 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
349 != 0);
350 }
351
352 /* Return true if a memory operand uses a single register for the
353 address. */
354
355 int
single_reg_memory_operand(op,mode)356 single_reg_memory_operand (op, mode)
357 rtx op;
358 enum machine_mode mode;
359 {
360 rtx addr;
361
362 if (GET_CODE (op) != MEM)
363 return FALSE;
364
365 if (GET_MODE (op) != mode && mode != VOIDmode)
366 return FALSE;
367
368 addr = XEXP (op, 0);
369 if (! d30v_legitimate_address_p (mode, addr, reload_completed))
370 return FALSE;
371
372 if (GET_CODE (addr) == SUBREG)
373 addr = SUBREG_REG (addr);
374
375 return (GET_CODE (addr) == REG);
376 }
377
378 /* Return true if a memory operand uses a constant address. */
379
380 int
const_addr_memory_operand(op,mode)381 const_addr_memory_operand (op, mode)
382 rtx op;
383 enum machine_mode mode;
384 {
385 if (GET_CODE (op) != MEM)
386 return FALSE;
387
388 if (GET_MODE (op) != mode && mode != VOIDmode)
389 return FALSE;
390
391 if (! d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed))
392 return FALSE;
393
394 switch (GET_CODE (XEXP (op, 0)))
395 {
396 default:
397 break;
398
399 case SYMBOL_REF:
400 case LABEL_REF:
401 case CONST_INT:
402 case CONST:
403 return TRUE;
404 }
405
406 return FALSE;
407 }
408
409 /* Return true if operand is a memory reference suitable for a call. */
410
411 int
call_operand(op,mode)412 call_operand (op, mode)
413 rtx op;
414 enum machine_mode mode;
415 {
416 if (GET_CODE (op) != MEM)
417 return FALSE;
418
419 if (GET_MODE (op) != mode && mode != VOIDmode)
420 return FALSE;
421
422 if (! d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed))
423 return FALSE;
424
425 switch (GET_CODE (XEXP (op, 0)))
426 {
427 default:
428 break;
429
430 case SUBREG:
431 op = SUBREG_REG (op);
432 if (GET_CODE (op) != REG)
433 return FALSE;
434
435 /* fall through */
436
437 case REG:
438 return (GPR_OR_PSEUDO_P (REGNO (XEXP (op, 0))));
439
440 case SYMBOL_REF:
441 case LABEL_REF:
442 case CONST_INT:
443 case CONST:
444 return TRUE;
445 }
446
447 return FALSE;
448 }
449
450 /* Return true if operand is a GPR register. */
451
452 int
gpr_operand(op,mode)453 gpr_operand (op, mode)
454 rtx op;
455 enum machine_mode mode;
456 {
457 if (GET_MODE (op) != mode && mode != VOIDmode)
458 return FALSE;
459
460 if (GET_CODE (op) == SUBREG)
461 {
462 if (GET_CODE (SUBREG_REG (op)) != REG)
463 return register_operand (op, mode);
464
465 op = SUBREG_REG (op);
466 }
467
468 if (GET_CODE (op) != REG)
469 return FALSE;
470
471 return GPR_OR_PSEUDO_P (REGNO (op));
472 }
473
474 /* Return true if operand is an accumulator register. */
475
476 int
accum_operand(op,mode)477 accum_operand (op, mode)
478 rtx op;
479 enum machine_mode mode;
480 {
481 if (GET_MODE (op) != mode && mode != VOIDmode)
482 return FALSE;
483
484 if (GET_CODE (op) == SUBREG)
485 {
486 if (GET_CODE (SUBREG_REG (op)) != REG)
487 return register_operand (op, mode);
488
489 op = SUBREG_REG (op);
490 }
491
492 if (GET_CODE (op) != REG)
493 return FALSE;
494
495 return ACCUM_OR_PSEUDO_P (REGNO (op));
496 }
497
498 /* Return true if operand is a GPR or an accumulator register. */
499
500 int
gpr_or_accum_operand(op,mode)501 gpr_or_accum_operand (op, mode)
502 rtx op;
503 enum machine_mode mode;
504 {
505 if (GET_MODE (op) != mode && mode != VOIDmode)
506 return FALSE;
507
508 if (GET_CODE (op) == SUBREG)
509 {
510 if (GET_CODE (SUBREG_REG (op)) != REG)
511 return register_operand (op, mode);
512
513 op = SUBREG_REG (op);
514 }
515
516 if (GET_CODE (op) != REG)
517 return FALSE;
518
519 if (ACCUM_P (REGNO (op)))
520 return TRUE;
521
522 return GPR_OR_PSEUDO_P (REGNO (op));
523 }
524
525 /* Return true if operand is a CR register. */
526
527 int
cr_operand(op,mode)528 cr_operand (op, mode)
529 rtx op;
530 enum machine_mode mode;
531 {
532 if (GET_MODE (op) != mode && mode != VOIDmode)
533 return FALSE;
534
535 if (GET_CODE (op) == SUBREG)
536 {
537 if (GET_CODE (SUBREG_REG (op)) != REG)
538 return register_operand (op, mode);
539
540 op = SUBREG_REG (op);
541 }
542
543 if (GET_CODE (op) != REG)
544 return FALSE;
545
546 return CR_OR_PSEUDO_P (REGNO (op));
547 }
548
549 /* Return true if operand is the repeat count register. */
550
551 int
repeat_operand(op,mode)552 repeat_operand (op, mode)
553 rtx op;
554 enum machine_mode mode;
555 {
556 if (GET_MODE (op) != mode && mode != VOIDmode)
557 return FALSE;
558
559 if (GET_CODE (op) == SUBREG)
560 {
561 if (GET_CODE (SUBREG_REG (op)) != REG)
562 return register_operand (op, mode);
563
564 op = SUBREG_REG (op);
565 }
566
567 if (GET_CODE (op) != REG)
568 return FALSE;
569
570 return (REGNO (op) == CR_RPT_C || REGNO (op) >= FIRST_PSEUDO_REGISTER);
571 }
572
573 /* Return true if operand is a FLAG register. */
574
575 int
flag_operand(op,mode)576 flag_operand (op, mode)
577 rtx op;
578 enum machine_mode mode;
579 {
580 if (GET_MODE (op) != mode && mode != VOIDmode)
581 return FALSE;
582
583 if (GET_CODE (op) == SUBREG)
584 {
585 if (GET_CODE (SUBREG_REG (op)) != REG)
586 return register_operand (op, mode);
587
588 op = SUBREG_REG (op);
589 }
590
591 if (GET_CODE (op) != REG)
592 return FALSE;
593
594 return FLAG_OR_PSEUDO_P (REGNO (op));
595 }
596
597 /* Return true if operand is either F0 or F1. */
598
599 int
br_flag_operand(op,mode)600 br_flag_operand (op, mode)
601 rtx op;
602 enum machine_mode mode;
603 {
604 if (GET_MODE (op) != mode && mode != VOIDmode)
605 return FALSE;
606
607 if (GET_CODE (op) == SUBREG)
608 {
609 if (GET_CODE (SUBREG_REG (op)) != REG)
610 return register_operand (op, mode);
611
612 op = SUBREG_REG (op);
613 }
614
615 if (GET_CODE (op) != REG)
616 return FALSE;
617
618 return BR_FLAG_OR_PSEUDO_P (REGNO (op));
619 }
620
621 /* Return true if operand is either F0/F1 or the constants 0/1. */
622
623 int
br_flag_or_constant_operand(op,mode)624 br_flag_or_constant_operand (op, mode)
625 rtx op;
626 enum machine_mode mode;
627 {
628 if (GET_MODE (op) != mode && mode != VOIDmode)
629 return FALSE;
630
631 if (GET_CODE (op) == SUBREG)
632 {
633 if (GET_CODE (SUBREG_REG (op)) != REG)
634 return register_operand (op, mode);
635
636 op = SUBREG_REG (op);
637 }
638
639 if (GET_CODE (op) == CONST_INT)
640 return (INTVAL (op) == 0 || INTVAL (op) == 1);
641
642 if (GET_CODE (op) != REG)
643 return FALSE;
644
645 return BR_FLAG_OR_PSEUDO_P (REGNO (op));
646 }
647
648 /* Return true if operand is either F0 or F1, or a GPR register. */
649
650 int
gpr_or_br_flag_operand(op,mode)651 gpr_or_br_flag_operand (op, mode)
652 rtx op;
653 enum machine_mode mode;
654 {
655 if (GET_MODE (op) != mode && mode != VOIDmode)
656 return FALSE;
657
658 if (GET_CODE (op) == SUBREG)
659 {
660 if (GET_CODE (SUBREG_REG (op)) != REG)
661 return register_operand (op, mode);
662
663 op = SUBREG_REG (op);
664 }
665
666 if (GET_CODE (op) != REG)
667 return FALSE;
668
669 return GPR_OR_PSEUDO_P (REGNO (op)) || BR_FLAG_P (REGNO (op));
670 }
671
672 /* Return true if operand is the F0 register. */
673
674 int
f0_operand(op,mode)675 f0_operand (op, mode)
676 rtx op;
677 enum machine_mode mode;
678 {
679 if (GET_MODE (op) != mode && mode != VOIDmode)
680 return FALSE;
681
682 if (GET_CODE (op) == SUBREG)
683 {
684 if (GET_CODE (SUBREG_REG (op)) != REG)
685 return register_operand (op, mode);
686
687 op = SUBREG_REG (op);
688 }
689
690 if (GET_CODE (op) != REG)
691 return FALSE;
692
693 return (REGNO (op) == FLAG_F0 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
694 }
695
696 /* Return true if operand is the F1 register. */
697
698 int
f1_operand(op,mode)699 f1_operand (op, mode)
700 rtx op;
701 enum machine_mode mode;
702 {
703 if (GET_MODE (op) != mode && mode != VOIDmode)
704 return FALSE;
705
706 if (GET_CODE (op) == SUBREG)
707 {
708 if (GET_CODE (SUBREG_REG (op)) != REG)
709 return register_operand (op, mode);
710
711 op = SUBREG_REG (op);
712 }
713
714 if (GET_CODE (op) != REG)
715 return FALSE;
716
717 return (REGNO (op) == FLAG_F1 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
718 }
719
720 /* Return true if operand is the F1 register. */
721
722 int
carry_operand(op,mode)723 carry_operand (op, mode)
724 rtx op;
725 enum machine_mode mode;
726 {
727 if (GET_MODE (op) != mode && mode != VOIDmode)
728 return FALSE;
729
730 if (GET_CODE (op) == SUBREG)
731 {
732 if (GET_CODE (SUBREG_REG (op)) != REG)
733 return register_operand (op, mode);
734
735 op = SUBREG_REG (op);
736 }
737
738 if (GET_CODE (op) != REG)
739 return FALSE;
740
741 return (REGNO (op) == FLAG_CARRY || REGNO (op) >= FIRST_PSEUDO_REGISTER);
742 }
743
744 /* Return true if operand is a register of any flavor or a 0 of the
745 appropriate type. */
746
747 int
reg_or_0_operand(op,mode)748 reg_or_0_operand (op, mode)
749 rtx op;
750 enum machine_mode mode;
751 {
752 switch (GET_CODE (op))
753 {
754 default:
755 break;
756
757 case REG:
758 case SUBREG:
759 if (GET_MODE (op) != mode && mode != VOIDmode)
760 return FALSE;
761
762 return register_operand (op, mode);
763
764 case CONST_INT:
765 return INTVAL (op) == 0;
766
767 case CONST_DOUBLE:
768 return CONST_DOUBLE_HIGH (op) == 0 && CONST_DOUBLE_LOW (op) == 0;
769 }
770
771 return FALSE;
772 }
773
774 /* Return true if operand is a GPR register or a signed 6 bit immediate. */
775
776 int
gpr_or_signed6_operand(op,mode)777 gpr_or_signed6_operand (op, mode)
778 rtx op;
779 enum machine_mode mode;
780 {
781 if (GET_CODE (op) == SUBREG)
782 {
783 if (GET_CODE (SUBREG_REG (op)) != REG)
784 return register_operand (op, mode);
785
786 op = SUBREG_REG (op);
787 }
788
789 if (GET_CODE (op) == CONST_INT)
790 return IN_RANGE_P (INTVAL (op), -32, 31);
791
792 if (GET_CODE (op) != REG)
793 return FALSE;
794
795 if (GET_MODE (op) != mode && mode != VOIDmode)
796 return FALSE;
797
798 return GPR_OR_PSEUDO_P (REGNO (op));
799 }
800
801 /* Return true if operand is a GPR register or an unsigned 5 bit immediate. */
802
803 int
gpr_or_unsigned5_operand(op,mode)804 gpr_or_unsigned5_operand (op, mode)
805 rtx op;
806 enum machine_mode mode;
807 {
808 if (GET_CODE (op) == SUBREG)
809 {
810 if (GET_CODE (SUBREG_REG (op)) != REG)
811 return register_operand (op, mode);
812
813 op = SUBREG_REG (op);
814 }
815
816 if (GET_CODE (op) == CONST_INT)
817 return IN_RANGE_P (INTVAL (op), 0, 31);
818
819 if (GET_CODE (op) != REG)
820 return FALSE;
821
822 if (GET_MODE (op) != mode && mode != VOIDmode)
823 return FALSE;
824
825 return GPR_OR_PSEUDO_P (REGNO (op));
826 }
827
828 /* Return true if operand is a GPR register or an unsigned 6 bit immediate. */
829
830 int
gpr_or_unsigned6_operand(op,mode)831 gpr_or_unsigned6_operand (op, mode)
832 rtx op;
833 enum machine_mode mode;
834 {
835 if (GET_CODE (op) == SUBREG)
836 {
837 if (GET_CODE (SUBREG_REG (op)) != REG)
838 return register_operand (op, mode);
839
840 op = SUBREG_REG (op);
841 }
842
843 if (GET_CODE (op) == CONST_INT)
844 return IN_RANGE_P (INTVAL (op), 0, 63);
845
846 if (GET_CODE (op) != REG)
847 return FALSE;
848
849 if (GET_MODE (op) != mode && mode != VOIDmode)
850 return FALSE;
851
852 return GPR_OR_PSEUDO_P (REGNO (op));
853 }
854
855 /* Return true if operand is a GPR register or a constant of some form. */
856
857 int
gpr_or_constant_operand(op,mode)858 gpr_or_constant_operand (op, mode)
859 rtx op;
860 enum machine_mode mode;
861 {
862 switch (GET_CODE (op))
863 {
864 default:
865 break;
866
867 case CONST_INT:
868 case SYMBOL_REF:
869 case LABEL_REF:
870 case CONST:
871 return TRUE;
872
873 case SUBREG:
874 if (GET_CODE (SUBREG_REG (op)) != REG)
875 return register_operand (op, mode);
876
877 op = SUBREG_REG (op);
878 /* fall through */
879
880 case REG:
881 if (GET_MODE (op) != mode && mode != VOIDmode)
882 return FALSE;
883
884 return GPR_OR_PSEUDO_P (REGNO (op));
885 }
886
887 return FALSE;
888 }
889
890 /* Return true if operand is a GPR register or a constant of some form,
891 including a CONST_DOUBLE, which gpr_or_constant_operand doesn't recognize. */
892
893 int
gpr_or_dbl_const_operand(op,mode)894 gpr_or_dbl_const_operand (op, mode)
895 rtx op;
896 enum machine_mode mode;
897 {
898 switch (GET_CODE (op))
899 {
900 default:
901 break;
902
903 case CONST_INT:
904 case CONST_DOUBLE:
905 case SYMBOL_REF:
906 case LABEL_REF:
907 case CONST:
908 return TRUE;
909
910 case SUBREG:
911 if (GET_CODE (SUBREG_REG (op)) != REG)
912 return register_operand (op, mode);
913
914 op = SUBREG_REG (op);
915 /* fall through */
916
917 case REG:
918 if (GET_MODE (op) != mode && mode != VOIDmode)
919 return FALSE;
920
921 return GPR_OR_PSEUDO_P (REGNO (op));
922 }
923
924 return FALSE;
925 }
926
927 /* Return true if operand is a gpr register or a valid memory operation. */
928
929 int
gpr_or_memory_operand(op,mode)930 gpr_or_memory_operand (op, mode)
931 rtx op;
932 enum machine_mode mode;
933 {
934 switch (GET_CODE (op))
935 {
936 default:
937 break;
938
939 case SUBREG:
940 if (GET_CODE (SUBREG_REG (op)) != REG)
941 return register_operand (op, mode);
942
943 op = SUBREG_REG (op);
944 /* fall through */
945
946 case REG:
947 if (GET_MODE (op) != mode && mode != VOIDmode)
948 return FALSE;
949
950 return GPR_OR_PSEUDO_P (REGNO (op));
951
952 case MEM:
953 return d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed);
954 }
955
956 return FALSE;
957 }
958
959 /* Return true if operand is something that can be an input for a move
960 operation. */
961
962 int
move_input_operand(op,mode)963 move_input_operand (op, mode)
964 rtx op;
965 enum machine_mode mode;
966 {
967 rtx subreg;
968 enum rtx_code code;
969
970 switch (GET_CODE (op))
971 {
972 default:
973 break;
974
975 case CONST_INT:
976 case CONST_DOUBLE:
977 case SYMBOL_REF:
978 case LABEL_REF:
979 case CONST:
980 return TRUE;
981
982 case SUBREG:
983 if (GET_MODE (op) != mode && mode != VOIDmode)
984 return FALSE;
985
986 subreg = SUBREG_REG (op);
987 code = GET_CODE (subreg);
988 if (code == MEM)
989 return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0),
990 reload_completed);
991
992 return (code == REG);
993
994 case REG:
995 if (GET_MODE (op) != mode && mode != VOIDmode)
996 return FALSE;
997
998 return TRUE;
999
1000 case MEM:
1001 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1002 return TRUE;
1003 return d30v_legitimate_address_p (mode, XEXP (op, 0),
1004 reload_completed);
1005 }
1006
1007 return FALSE;
1008 }
1009
1010 /* Return true if operand is something that can be an output for a move
1011 operation. */
1012
1013 int
move_output_operand(op,mode)1014 move_output_operand (op, mode)
1015 rtx op;
1016 enum machine_mode mode;
1017 {
1018 rtx subreg;
1019 enum rtx_code code;
1020
1021 switch (GET_CODE (op))
1022 {
1023 default:
1024 break;
1025
1026 case SUBREG:
1027 if (GET_MODE (op) != mode && mode != VOIDmode)
1028 return FALSE;
1029
1030 subreg = SUBREG_REG (op);
1031 code = GET_CODE (subreg);
1032 if (code == MEM)
1033 return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0),
1034 reload_completed);
1035
1036 return (code == REG);
1037
1038 case REG:
1039 if (GET_MODE (op) != mode && mode != VOIDmode)
1040 return FALSE;
1041
1042 return TRUE;
1043
1044 case MEM:
1045 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1046 return TRUE;
1047 return d30v_legitimate_address_p (mode, XEXP (op, 0),
1048 reload_completed);
1049 }
1050
1051 return FALSE;
1052 }
1053
1054 /* Return true if operand is a signed 6 bit immediate. */
1055
1056 int
signed6_operand(op,mode)1057 signed6_operand (op, mode)
1058 rtx op;
1059 enum machine_mode mode ATTRIBUTE_UNUSED;
1060 {
1061 if (GET_CODE (op) == CONST_INT)
1062 return IN_RANGE_P (INTVAL (op), -32, 31);
1063
1064 return FALSE;
1065 }
1066
1067 /* Return true if operand is an unsigned 5 bit immediate. */
1068
1069 int
unsigned5_operand(op,mode)1070 unsigned5_operand (op, mode)
1071 rtx op;
1072 enum machine_mode mode ATTRIBUTE_UNUSED;
1073 {
1074 if (GET_CODE (op) == CONST_INT)
1075 return IN_RANGE_P (INTVAL (op), 0, 31);
1076
1077 return FALSE;
1078 }
1079
1080 /* Return true if operand is an unsigned 6 bit immediate. */
1081
1082 int
unsigned6_operand(op,mode)1083 unsigned6_operand (op, mode)
1084 rtx op;
1085 enum machine_mode mode ATTRIBUTE_UNUSED;
1086 {
1087 if (GET_CODE (op) == CONST_INT)
1088 return IN_RANGE_P (INTVAL (op), 0, 63);
1089
1090 return FALSE;
1091 }
1092
1093 /* Return true if operand is a constant with a single bit set. */
1094
1095 int
bitset_operand(op,mode)1096 bitset_operand (op, mode)
1097 rtx op;
1098 enum machine_mode mode ATTRIBUTE_UNUSED;
1099 {
1100 if (GET_CODE (op) == CONST_INT)
1101 return IN_RANGE_P (exact_log2 (INTVAL (op)), 0, 31);
1102
1103 return FALSE;
1104 }
1105
1106 /* Return true if the operator is a ==/!= test against f0 or f1 that can be
1107 used in conditional execution. */
1108
1109 int
condexec_test_operator(op,mode)1110 condexec_test_operator (op, mode)
1111 rtx op;
1112 enum machine_mode mode;
1113 {
1114 rtx x0, x1;
1115
1116 if (GET_MODE (op) != mode && mode != VOIDmode)
1117 return FALSE;
1118
1119 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1120 return FALSE;
1121
1122 x0 = XEXP (op, 0);
1123 if (GET_CODE (x0) != REG || !BR_FLAG_OR_PSEUDO_P (REGNO (x0)))
1124 return FALSE;
1125
1126 x1 = XEXP (op, 1);
1127 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1128 return FALSE;
1129
1130 return TRUE;
1131 }
1132
1133 /* Return true if the operator is a ==/!= test against f0, f1, or a general
1134 register that can be used in a branch instruction. */
1135
1136 int
condexec_branch_operator(op,mode)1137 condexec_branch_operator (op, mode)
1138 rtx op;
1139 enum machine_mode mode;
1140 {
1141 rtx x0, x1;
1142
1143 if (GET_MODE (op) != mode && mode != VOIDmode)
1144 return FALSE;
1145
1146 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1147 return FALSE;
1148
1149 x0 = XEXP (op, 0);
1150 if (GET_CODE (x0) == REG)
1151 {
1152 int regno = REGNO (x0);
1153 if (!GPR_OR_PSEUDO_P (regno) && !BR_FLAG_P (regno))
1154 return FALSE;
1155 }
1156 /* Allow the optimizer to generate things like:
1157 (if_then_else (ne (const_int 1) (const_int 0))) */
1158 else if (GET_CODE (x0) != CONST_INT)
1159 return FALSE;
1160
1161 x1 = XEXP (op, 1);
1162 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1163 return FALSE;
1164
1165 return TRUE;
1166 }
1167
1168 /* Return true if the unary operator can be executed with conditional
1169 execution. */
1170
1171 int
condexec_unary_operator(op,mode)1172 condexec_unary_operator (op, mode)
1173 rtx op;
1174 enum machine_mode mode ATTRIBUTE_UNUSED;
1175 {
1176 rtx op0;
1177
1178 /* Only do this after register allocation, so that we can look at the register # */
1179 if (!reload_completed)
1180 return FALSE;
1181
1182 if (GET_RTX_CLASS (GET_CODE (op)) != '1')
1183 return FALSE;
1184
1185 op0 = XEXP (op, 0);
1186 if (GET_CODE (op0) == SUBREG)
1187 op0 = SUBREG_REG (op0);
1188
1189 switch (GET_CODE (op))
1190 {
1191 default:
1192 break;
1193
1194 case ABS:
1195 case NOT:
1196 if (GET_MODE (op) == SImode && GET_CODE (op0) == REG && GPR_P (REGNO (op0)))
1197 return TRUE;
1198
1199 break;
1200 }
1201
1202 return FALSE;
1203 }
1204
1205 /* Return true if the add or subtraction can be executed with conditional
1206 execution. */
1207
1208 int
condexec_addsub_operator(op,mode)1209 condexec_addsub_operator (op, mode)
1210 rtx op;
1211 enum machine_mode mode ATTRIBUTE_UNUSED;
1212 {
1213 rtx op0, op1;
1214
1215 /* Only do this after register allocation, so that we can look at the register # */
1216 if (!reload_completed)
1217 return FALSE;
1218
1219 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1220 return FALSE;
1221
1222 op0 = XEXP (op, 0);
1223 op1 = XEXP (op, 1);
1224
1225 if (GET_CODE (op0) == SUBREG)
1226 op0 = SUBREG_REG (op0);
1227
1228 if (GET_CODE (op1) == SUBREG)
1229 op1 = SUBREG_REG (op1);
1230
1231 if (GET_CODE (op0) != REG)
1232 return FALSE;
1233
1234 switch (GET_CODE (op))
1235 {
1236 default:
1237 break;
1238
1239 case PLUS:
1240 case MINUS:
1241 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1242 && gpr_or_constant_operand (op1, SImode));
1243 }
1244
1245 return FALSE;
1246 }
1247
1248 /* Return true if the binary operator can be executed with conditional
1249 execution. We don't include add/sub here, since they have extra
1250 clobbers for the flags registers. */
1251
1252 int
condexec_binary_operator(op,mode)1253 condexec_binary_operator (op, mode)
1254 rtx op;
1255 enum machine_mode mode ATTRIBUTE_UNUSED;
1256 {
1257 rtx op0, op1;
1258
1259 /* Only do this after register allocation, so that we can look at the register # */
1260 if (!reload_completed)
1261 return FALSE;
1262
1263 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1264 return FALSE;
1265
1266 op0 = XEXP (op, 0);
1267 op1 = XEXP (op, 1);
1268
1269 if (GET_CODE (op0) == SUBREG)
1270 op0 = SUBREG_REG (op0);
1271
1272 if (GET_CODE (op1) == SUBREG)
1273 op1 = SUBREG_REG (op1);
1274
1275 if (GET_CODE (op0) != REG)
1276 return FALSE;
1277
1278 /* MULT is not included here, because it is an IU only instruction. */
1279 switch (GET_CODE (op))
1280 {
1281 default:
1282 break;
1283
1284 case AND:
1285 case IOR:
1286 case XOR:
1287 case ASHIFTRT:
1288 case LSHIFTRT:
1289 case ROTATERT:
1290 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1291 && gpr_or_constant_operand (op1, SImode));
1292
1293 case ASHIFT:
1294 case ROTATE:
1295 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1296 && GET_CODE (op1) == CONST_INT);
1297 }
1298
1299 return FALSE;
1300 }
1301
1302 /* Return true if the shift/rotate left operator can be executed with
1303 conditional execution. */
1304
1305 int
condexec_shiftl_operator(op,mode)1306 condexec_shiftl_operator (op, mode)
1307 rtx op;
1308 enum machine_mode mode ATTRIBUTE_UNUSED;
1309 {
1310 rtx op0, op1;
1311
1312 /* Only do this after register allocation, so that we can look at the register # */
1313 if (!reload_completed)
1314 return FALSE;
1315
1316 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1317 return FALSE;
1318
1319 op0 = XEXP (op, 0);
1320 op1 = XEXP (op, 1);
1321
1322 if (GET_CODE (op0) == SUBREG)
1323 op0 = SUBREG_REG (op0);
1324
1325 if (GET_CODE (op1) == SUBREG)
1326 op1 = SUBREG_REG (op1);
1327
1328 if (GET_CODE (op0) != REG)
1329 return FALSE;
1330
1331 switch (GET_CODE (op))
1332 {
1333 default:
1334 break;
1335
1336 case ASHIFT:
1337 case ROTATE:
1338 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1339 && GET_CODE (op1) == NEG
1340 && GET_CODE (XEXP (op1, 0)) == REG
1341 && GPR_P (REGNO (XEXP (op1, 0))));
1342 }
1343
1344 return FALSE;
1345 }
1346
1347 /* Return true if the {sign,zero} extend operator from memory can be
1348 conditionally executed. */
1349
1350 int
condexec_extend_operator(op,mode)1351 condexec_extend_operator (op, mode)
1352 rtx op;
1353 enum machine_mode mode ATTRIBUTE_UNUSED;
1354 {
1355 /* Only do this after register allocation, so that we can look at the register # */
1356 if (!reload_completed)
1357 return FALSE;
1358
1359 if (GET_RTX_CLASS (GET_CODE (op)) != '1')
1360 return FALSE;
1361
1362 switch (GET_CODE (op))
1363 {
1364 default:
1365 break;
1366
1367 case SIGN_EXTEND:
1368 case ZERO_EXTEND:
1369 if ((GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == QImode)
1370 || (GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == HImode)
1371 || (GET_MODE (op) == HImode && GET_MODE (XEXP (op, 0)) == QImode))
1372 return TRUE;
1373
1374 break;
1375 }
1376
1377 return FALSE;
1378 }
1379
1380 /* Return true for comparisons against 0 that can be turned into a
1381 bratnz/bratzr instruction. */
1382
1383 int
branch_zero_operator(op,mode)1384 branch_zero_operator (op, mode)
1385 rtx op;
1386 enum machine_mode mode;
1387 {
1388 rtx x0, x1;
1389
1390 if (GET_MODE (op) != mode && mode != VOIDmode)
1391 return FALSE;
1392
1393 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1394 return FALSE;
1395
1396 x0 = XEXP (op, 0);
1397 if (GET_CODE (x0) != REG || !GPR_OR_PSEUDO_P (REGNO (x0)))
1398 return FALSE;
1399
1400 x1 = XEXP (op, 1);
1401 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1402 return FALSE;
1403
1404 return TRUE;
1405 }
1406
1407 /* Return true if an operand is simple, suitable for use as the destination of
1408 a conditional move */
1409
1410 int
cond_move_dest_operand(op,mode)1411 cond_move_dest_operand (op, mode)
1412 register rtx op;
1413 enum machine_mode mode ATTRIBUTE_UNUSED;
1414 {
1415 rtx addr;
1416
1417 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1418 return FALSE;
1419
1420 switch (GET_CODE (op))
1421 {
1422 default:
1423 break;
1424
1425 case REG:
1426 case SUBREG:
1427 return gpr_operand (op, mode);
1428
1429 /* Don't allow post dec/inc, since we might not get the side effects correct. */
1430 case MEM:
1431 addr = XEXP (op, 0);
1432 return (GET_CODE (addr) != POST_DEC
1433 && GET_CODE (addr) != POST_INC
1434 && d30v_legitimate_address_p (mode, addr, reload_completed));
1435 }
1436
1437 return FALSE;
1438 }
1439
1440 /* Return true if an operand is simple, suitable for use in a conditional move */
1441
1442 int
cond_move_operand(op,mode)1443 cond_move_operand (op, mode)
1444 register rtx op;
1445 enum machine_mode mode ATTRIBUTE_UNUSED;
1446 {
1447 rtx addr;
1448
1449 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1450 return FALSE;
1451
1452 switch (GET_CODE (op))
1453 {
1454 default:
1455 break;
1456
1457 case REG:
1458 case SUBREG:
1459 return gpr_operand (op, mode);
1460
1461 case CONST_DOUBLE:
1462 return GET_MODE (op) == SFmode;
1463
1464 case CONST_INT:
1465 case SYMBOL_REF:
1466 case LABEL_REF:
1467 case CONST:
1468 return TRUE;
1469
1470 /* Don't allow post dec/inc, since we might not get the side effects correct. */
1471 case MEM:
1472 addr = XEXP (op, 0);
1473 return (GET_CODE (addr) != POST_DEC
1474 && GET_CODE (addr) != POST_INC
1475 && d30v_legitimate_address_p (mode, addr, reload_completed));
1476 }
1477
1478 return FALSE;
1479 }
1480
1481 /* Return true if an operand is simple, suitable for use in conditional execution.
1482 Unlike cond_move, we can allow auto inc/dec. */
1483
1484 int
cond_exec_operand(op,mode)1485 cond_exec_operand (op, mode)
1486 register rtx op;
1487 enum machine_mode mode;
1488 {
1489 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1490 return FALSE;
1491
1492 switch (GET_CODE (op))
1493 {
1494 default:
1495 break;
1496
1497 case REG:
1498 case SUBREG:
1499 return gpr_operand (op, mode);
1500
1501 case CONST_DOUBLE:
1502 return GET_MODE (op) == SFmode;
1503
1504 case CONST_INT:
1505 case SYMBOL_REF:
1506 case LABEL_REF:
1507 case CONST:
1508 return TRUE;
1509
1510 case MEM:
1511 return memory_operand (op, mode);
1512 }
1513
1514 return FALSE;
1515 }
1516
1517 /* Return true if operand is a SI mode signed relational test. */
1518
1519 int
srelational_si_operator(op,mode)1520 srelational_si_operator (op, mode)
1521 register rtx op;
1522 enum machine_mode mode;
1523 {
1524 rtx x0, x1;
1525
1526 if (GET_MODE (op) != mode && mode != VOIDmode)
1527 return FALSE;
1528
1529 switch (GET_CODE (op))
1530 {
1531 default:
1532 return FALSE;
1533
1534 case EQ:
1535 case NE:
1536 case LT:
1537 case LE:
1538 case GT:
1539 case GE:
1540 break;
1541 }
1542
1543 x0 = XEXP (op, 0);
1544 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1545 return FALSE;
1546
1547 if (GET_MODE (x0) != SImode)
1548 return FALSE;
1549
1550 x1 = XEXP (op, 1);
1551 switch (GET_CODE (x1))
1552 {
1553 default:
1554 return FALSE;
1555
1556 case REG:
1557 case SUBREG:
1558 case CONST_INT:
1559 case LABEL_REF:
1560 case SYMBOL_REF:
1561 case CONST:
1562 break;
1563 }
1564
1565 return TRUE;
1566 }
1567
1568 /* Return true if operand is a SI mode unsigned relational test. */
1569
1570 int
urelational_si_operator(op,mode)1571 urelational_si_operator (op, mode)
1572 register rtx op;
1573 enum machine_mode mode;
1574 {
1575 rtx x0, x1;
1576
1577 if (GET_MODE (op) != mode && mode != VOIDmode)
1578 return FALSE;
1579
1580 switch (GET_CODE (op))
1581 {
1582 default:
1583 return FALSE;
1584
1585 case LTU:
1586 case LEU:
1587 case GTU:
1588 case GEU:
1589 break;
1590 }
1591
1592 x0 = XEXP (op, 0);
1593 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1594 return FALSE;
1595
1596 if (GET_MODE (x0) != SImode)
1597 return FALSE;
1598
1599 x1 = XEXP (op, 1);
1600 switch (GET_CODE (x1))
1601 {
1602 default:
1603 return FALSE;
1604
1605 case REG:
1606 case SUBREG:
1607 case CONST_INT:
1608 case LABEL_REF:
1609 case SYMBOL_REF:
1610 case CONST:
1611 break;
1612 }
1613
1614 return TRUE;
1615 }
1616
1617 /* Return true if operand is a DI mode relational test. */
1618
1619 int
relational_di_operator(op,mode)1620 relational_di_operator (op, mode)
1621 register rtx op;
1622 enum machine_mode mode;
1623 {
1624 rtx x0, x1;
1625
1626 if (GET_MODE (op) != mode && mode != VOIDmode)
1627 return FALSE;
1628
1629 if (GET_RTX_CLASS (GET_CODE (op)) != '<')
1630 return FALSE;
1631
1632 x0 = XEXP (op, 0);
1633 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1634 return FALSE;
1635
1636 if (GET_MODE (x0) != DImode)
1637 return FALSE;
1638
1639 x1 = XEXP (op, 1);
1640 if (GET_CODE (x1) != REG && GET_CODE (x1) != SUBREG
1641 && GET_CODE (x1) != CONST_INT && GET_CODE (x1) != CONST_DOUBLE)
1642 return FALSE;
1643
1644 return TRUE;
1645 }
1646
1647
1648 /* Calculate the stack information for the current function.
1649
1650 D30V stack frames look like:
1651
1652 high | .... |
1653 +-------------------------------+
1654 | Argument word #19 |
1655 +-------------------------------+
1656 | Argument word #18 |
1657 +-------------------------------+
1658 | Argument word #17 |
1659 +-------------------------------+
1660 | Argument word #16 |
1661 Prev sp +-------------------------------+
1662 | |
1663 | Save for arguments 1..16 if |
1664 | the func. uses stdarg/varargs |
1665 | |
1666 +-------------------------------+
1667 | |
1668 | Save area for GPR registers |
1669 | |
1670 +-------------------------------+
1671 | |
1672 | Save area for accumulators |
1673 | |
1674 +-------------------------------+
1675 | |
1676 | Local variables |
1677 | |
1678 +-------------------------------+
1679 | |
1680 | alloca space if used |
1681 | |
1682 +-------------------------------+
1683 | |
1684 | Space for outgoing arguments |
1685 | |
1686 low SP----> +-------------------------------+
1687 */
1688
1689 d30v_stack_t *
d30v_stack_info()1690 d30v_stack_info ()
1691 {
1692 static d30v_stack_t info, zero_info;
1693 d30v_stack_t *info_ptr = &info;
1694 tree fndecl = current_function_decl;
1695 tree fntype = TREE_TYPE (fndecl);
1696 int varargs_p = 0;
1697 tree cur_arg;
1698 tree next_arg;
1699 int saved_gprs;
1700 int saved_accs;
1701 int memrefs_2words;
1702 int memrefs_1word;
1703 unsigned char save_gpr_p[GPR_LAST];
1704 int i;
1705
1706 /* If we've already calculated the values and reload is complete, just return now */
1707 if (d30v_stack_cache)
1708 return d30v_stack_cache;
1709
1710 /* Zero all fields */
1711 info = zero_info;
1712
1713 if (current_function_profile)
1714 regs_ever_live[GPR_LINK] = 1;
1715
1716 /* Determine if this is a stdarg function */
1717 if (TYPE_ARG_TYPES (fntype) != 0
1718 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
1719 varargs_p = 1;
1720 else
1721 {
1722 /* Find the last argument, and see if it is __builtin_va_alist. */
1723 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1724 {
1725 next_arg = TREE_CHAIN (cur_arg);
1726 if (next_arg == (tree)0)
1727 {
1728 if (DECL_NAME (cur_arg)
1729 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1730 varargs_p = 1;
1731
1732 break;
1733 }
1734 }
1735 }
1736
1737 /* Calculate which registers need to be saved & save area size */
1738 saved_accs = 0;
1739 memrefs_2words = 0;
1740 memrefs_1word = 0;
1741 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
1742 {
1743 if (regs_ever_live[i] && !call_used_regs[i])
1744 {
1745 info_ptr->save_p[i] = 2;
1746 saved_accs++;
1747 memrefs_2words++;
1748 }
1749 }
1750
1751 saved_gprs = 0;
1752 for (i = GPR_FIRST; i <= GPR_LAST; i++)
1753 {
1754 if (regs_ever_live[i] && (!call_used_regs[i] || i == GPR_LINK))
1755 {
1756 save_gpr_p[i] = 1;
1757 saved_gprs++;
1758 }
1759 else
1760 save_gpr_p[i] = 0;
1761 }
1762
1763 /* Determine which register pairs can be saved together with ld2w/st2w */
1764 for (i = GPR_FIRST; i <= GPR_LAST; i++)
1765 {
1766 if (((i - GPR_FIRST) & 1) == 0 && save_gpr_p[i] && save_gpr_p[i+1])
1767 {
1768 memrefs_2words++;
1769 info_ptr->save_p[i++] = 2;
1770 }
1771 else if (save_gpr_p[i])
1772 {
1773 memrefs_1word++;
1774 info_ptr->save_p[i] = 1;
1775 }
1776 }
1777
1778 /* Determine various sizes */
1779 info_ptr->varargs_p = varargs_p;
1780 info_ptr->varargs_size = ((varargs_p)
1781 ? (GPR_ARG_LAST + 1 - GPR_ARG_FIRST) * UNITS_PER_WORD
1782 : 0);
1783
1784 info_ptr->accum_size = 2 * UNITS_PER_WORD * saved_accs;
1785 info_ptr->gpr_size = D30V_ALIGN (UNITS_PER_WORD * saved_gprs,
1786 2 * UNITS_PER_WORD);
1787 info_ptr->vars_size = D30V_ALIGN (get_frame_size (), 2 * UNITS_PER_WORD);
1788 info_ptr->parm_size = D30V_ALIGN (current_function_outgoing_args_size,
1789 2 * UNITS_PER_WORD);
1790
1791 info_ptr->total_size = D30V_ALIGN ((info_ptr->gpr_size
1792 + info_ptr->accum_size
1793 + info_ptr->vars_size
1794 + info_ptr->parm_size
1795 + info_ptr->varargs_size
1796 + current_function_pretend_args_size),
1797 (STACK_BOUNDARY / BITS_PER_UNIT));
1798
1799 info_ptr->save_offset = (info_ptr->total_size
1800 - (current_function_pretend_args_size
1801 + info_ptr->varargs_size
1802 + info_ptr->gpr_size
1803 + info_ptr->accum_size));
1804
1805 /* The link register is the last GPR saved, but there might be some padding
1806 bytes after it, so account for that. */
1807 info_ptr->link_offset = (info_ptr->total_size
1808 - (current_function_pretend_args_size
1809 + info_ptr->varargs_size
1810 + (info_ptr->gpr_size
1811 - UNITS_PER_WORD * saved_gprs)
1812 + UNITS_PER_WORD));
1813
1814 info_ptr->memrefs_varargs = info_ptr->varargs_size / (2 * UNITS_PER_WORD);
1815 info_ptr->memrefs_2words = memrefs_2words;
1816 info_ptr->memrefs_1word = memrefs_1word;
1817
1818 if (reload_completed)
1819 d30v_stack_cache = info_ptr;
1820
1821 return info_ptr;
1822 }
1823
1824
1825 /* Internal function to print all of the information about the stack */
1826
1827 void
debug_stack_info(info)1828 debug_stack_info (info)
1829 d30v_stack_t *info;
1830 {
1831 int i;
1832
1833 if (!info)
1834 info = d30v_stack_info ();
1835
1836 fprintf (stderr, "\nStack information for function %s:\n",
1837 ((current_function_decl && DECL_NAME (current_function_decl))
1838 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1839 : "<unknown>"));
1840
1841 fprintf (stderr, "\tsave_offset = %d\n", info->save_offset);
1842 fprintf (stderr, "\tmemrefs_varargs = %d\n", info->memrefs_varargs);
1843 fprintf (stderr, "\tmemrefs_2words = %d\n", info->memrefs_2words);
1844 fprintf (stderr, "\tmemrefs_1word = %d\n", info->memrefs_1word);
1845 fprintf (stderr, "\tvarargs_p = %d\n", info->varargs_p);
1846 fprintf (stderr, "\tvarargs_size = %d\n", info->varargs_size);
1847 fprintf (stderr, "\tvars_size = %d\n", info->vars_size);
1848 fprintf (stderr, "\tparm_size = %d\n", info->parm_size);
1849 fprintf (stderr, "\tgpr_size = %d\n", info->gpr_size);
1850 fprintf (stderr, "\taccum_size = %d\n", info->accum_size);
1851 fprintf (stderr, "\ttotal_size = %d\n", info->total_size);
1852 fprintf (stderr, "\tsaved registers =");
1853
1854 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1855 {
1856 if (info->save_p[i] == 2)
1857 {
1858 fprintf (stderr, " %s-%s", reg_names[i], reg_names[i+1]);
1859 i++;
1860 }
1861 else if (info->save_p[i])
1862 fprintf (stderr, " %s", reg_names[i]);
1863 }
1864
1865 putc ('\n', stderr);
1866 fflush (stderr);
1867 }
1868
1869
1870 /* Return nonzero if this function is known to have a null or 1 instruction epilogue. */
1871
1872 int
direct_return()1873 direct_return ()
1874 {
1875 if (reload_completed)
1876 {
1877 d30v_stack_t *info = d30v_stack_info ();
1878
1879 /* If no epilogue code is needed, can use just a simple jump */
1880 if (info->total_size == 0)
1881 return 1;
1882
1883 #if 0
1884 /* If just a small amount of local stack was allocated and no registers
1885 saved, skip forward branch */
1886 if (info->total_size == info->vars_size
1887 && IN_RANGE_P (info->total_size, 1, 31))
1888 return 1;
1889 #endif
1890 }
1891
1892 return 0;
1893 }
1894
1895
1896 /* A C statement (sans semicolon) for initializing the variable CUM for the
1897 state at the beginning of the argument list. The variable has type
1898 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
1899 of the function which will receive the args, or 0 if the args are to a
1900 compiler support library function. The value of INDIRECT is nonzero when
1901 processing an indirect call, for example a call through a function pointer.
1902 The value of INDIRECT is zero for a call to an explicitly named function, a
1903 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
1904 arguments for the function being compiled.
1905
1906 When processing a call to a compiler support library function, LIBNAME
1907 identifies which one. It is a `symbol_ref' rtx which contains the name of
1908 the function, as a string. LIBNAME is 0 when an ordinary C function call is
1909 being processed. Thus, each time this macro is called, either LIBNAME or
1910 FNTYPE is nonzero, but never both of them at once. */
1911
1912 void
d30v_init_cumulative_args(cum,fntype,libname,indirect,incoming)1913 d30v_init_cumulative_args (cum, fntype, libname, indirect, incoming)
1914 CUMULATIVE_ARGS *cum;
1915 tree fntype;
1916 rtx libname;
1917 int indirect;
1918 int incoming;
1919 {
1920 *cum = GPR_ARG_FIRST;
1921
1922 if (TARGET_DEBUG_ARG)
1923 {
1924 fprintf (stderr, "\ninit_cumulative_args:");
1925 if (indirect)
1926 fputs (" indirect", stderr);
1927
1928 if (incoming)
1929 fputs (" incoming", stderr);
1930
1931 if (fntype)
1932 {
1933 tree ret_type = TREE_TYPE (fntype);
1934 fprintf (stderr, " return=%s,",
1935 tree_code_name[ (int)TREE_CODE (ret_type) ]);
1936 }
1937
1938 if (libname && GET_CODE (libname) == SYMBOL_REF)
1939 fprintf (stderr, " libname=%s", XSTR (libname, 0));
1940
1941 putc ('\n', stderr);
1942 }
1943 }
1944
1945
1946 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1947 argument with the specified mode and type. If it is not defined,
1948 `PARM_BOUNDARY' is used for all arguments. */
1949
1950 int
d30v_function_arg_boundary(mode,type)1951 d30v_function_arg_boundary (mode, type)
1952 enum machine_mode mode;
1953 tree type;
1954 {
1955 int size = ((mode == BLKmode && type)
1956 ? int_size_in_bytes (type)
1957 : (int) GET_MODE_SIZE (mode));
1958
1959 return (size > UNITS_PER_WORD) ? 2*UNITS_PER_WORD : UNITS_PER_WORD;
1960 }
1961
1962
1963 /* A C expression that controls whether a function argument is passed in a
1964 register, and which register.
1965
1966 The arguments are CUM, which summarizes all the previous arguments; MODE,
1967 the machine mode of the argument; TYPE, the data type of the argument as a
1968 tree node or 0 if that is not known (which happens for C support library
1969 functions); and NAMED, which is 1 for an ordinary argument and 0 for
1970 nameless arguments that correspond to `...' in the called function's
1971 prototype.
1972
1973 The value of the expression should either be a `reg' RTX for the hard
1974 register in which to pass the argument, or zero to pass the argument on the
1975 stack.
1976
1977 For machines like the VAX and 68000, where normally all arguments are
1978 pushed, zero suffices as a definition.
1979
1980 The usual way to make the ANSI library `stdarg.h' work on a machine where
1981 some arguments are usually passed in registers, is to cause nameless
1982 arguments to be passed on the stack instead. This is done by making
1983 `FUNCTION_ARG' return 0 whenever NAMED is 0.
1984
1985 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
1986 this macro to determine if this argument is of a type that must be passed in
1987 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
1988 returns nonzero for such an argument, the compiler will abort. If
1989 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
1990 stack and then loaded into a register. */
1991
1992 rtx
d30v_function_arg(cum,mode,type,named,incoming)1993 d30v_function_arg (cum, mode, type, named, incoming)
1994 CUMULATIVE_ARGS *cum;
1995 enum machine_mode mode;
1996 tree type;
1997 int named;
1998 int incoming ATTRIBUTE_UNUSED;
1999 {
2000 int size = ((mode == BLKmode && type)
2001 ? int_size_in_bytes (type)
2002 : (int) GET_MODE_SIZE (mode));
2003 int adjust = (size > UNITS_PER_WORD && (*cum & 1) != 0);
2004 rtx ret;
2005
2006 /* Return a marker for use in the call instruction. */
2007 if (mode == VOIDmode)
2008 ret = const0_rtx;
2009
2010 else if (*cum + adjust <= GPR_ARG_LAST)
2011 ret = gen_rtx (REG, mode, *cum + adjust);
2012
2013 else
2014 ret = NULL_RTX;
2015
2016 if (TARGET_DEBUG_ARG)
2017 fprintf (stderr,
2018 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d, arg = %s\n",
2019 *cum, GET_MODE_NAME (mode), named, size, adjust,
2020 (ret) ? ((ret == const0_rtx) ? "<0>" : reg_names[ REGNO (ret) ]) : "memory");
2021
2022 return ret;
2023 }
2024
2025
2026 /* A C expression for the number of words, at the beginning of an argument,
2027 must be put in registers. The value must be zero for arguments that are
2028 passed entirely in registers or that are entirely pushed on the stack.
2029
2030 On some machines, certain arguments must be passed partially in registers
2031 and partially in memory. On these machines, typically the first N words of
2032 arguments are passed in registers, and the rest on the stack. If a
2033 multi-word argument (a `double' or a structure) crosses that boundary, its
2034 first few words must be passed in registers and the rest must be pushed.
2035 This macro tells the compiler when this occurs, and how many of the words
2036 should go in registers.
2037
2038 `FUNCTION_ARG' for these arguments should return the first register to be
2039 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
2040 the called function. */
2041
2042 int
d30v_function_arg_partial_nregs(cum,mode,type,named)2043 d30v_function_arg_partial_nregs (cum, mode, type, named)
2044 CUMULATIVE_ARGS *cum;
2045 enum machine_mode mode;
2046 tree type;
2047 int named ATTRIBUTE_UNUSED;
2048 {
2049 int bytes = ((mode == BLKmode)
2050 ? int_size_in_bytes (type)
2051 : (int) GET_MODE_SIZE (mode));
2052 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2053 int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0);
2054 int arg_num = *cum + adjust;
2055 int ret;
2056
2057 ret = ((arg_num <= GPR_ARG_LAST && arg_num + words > GPR_ARG_LAST+1)
2058 ? GPR_ARG_LAST - arg_num + 1
2059 : 0);
2060
2061 if (TARGET_DEBUG_ARG && ret)
2062 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
2063
2064 return ret;
2065 }
2066
2067
2068 /* A C expression that indicates when an argument must be passed by reference.
2069 If nonzero for an argument, a copy of that argument is made in memory and a
2070 pointer to the argument is passed instead of the argument itself. The
2071 pointer is passed in whatever way is appropriate for passing a pointer to
2072 that type.
2073
2074 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
2075 definition of this macro might be
2076 #define FUNCTION_ARG_PASS_BY_REFERENCE\
2077 (CUM, MODE, TYPE, NAMED) \
2078 MUST_PASS_IN_STACK (MODE, TYPE) */
2079
2080 int
d30v_function_arg_pass_by_reference(cum,mode,type,named)2081 d30v_function_arg_pass_by_reference (cum, mode, type, named)
2082 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
2083 enum machine_mode mode;
2084 tree type;
2085 int named ATTRIBUTE_UNUSED;
2086 {
2087 int ret = MUST_PASS_IN_STACK (mode, type);
2088
2089 if (TARGET_DEBUG_ARG && ret)
2090 fprintf (stderr, "function_arg_pass_by_reference: %d\n", ret);
2091
2092 return ret;
2093 }
2094
2095
2096 /* A C statement (sans semicolon) to update the summarizer variable CUM to
2097 advance past an argument in the argument list. The values MODE, TYPE and
2098 NAMED describe that argument. Once this is done, the variable CUM is
2099 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
2100
2101 This macro need not do anything if the argument in question was passed on
2102 the stack. The compiler knows how to track the amount of stack space used
2103 for arguments without any special help. */
2104
2105 void
d30v_function_arg_advance(cum,mode,type,named)2106 d30v_function_arg_advance (cum, mode, type, named)
2107 CUMULATIVE_ARGS *cum;
2108 enum machine_mode mode;
2109 tree type;
2110 int named;
2111 {
2112 int bytes = ((mode == BLKmode)
2113 ? int_size_in_bytes (type)
2114 : (int) GET_MODE_SIZE (mode));
2115 int words = D30V_ALIGN (bytes, UNITS_PER_WORD) / UNITS_PER_WORD;
2116 int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0);
2117
2118 *cum += words + adjust;
2119
2120 if (TARGET_DEBUG_ARG)
2121 fprintf (stderr,
2122 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d\n",
2123 *cum, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD, adjust);
2124 }
2125
2126
2127 /* If defined, is a C expression that produces the machine-specific code for a
2128 call to `__builtin_saveregs'. This code will be moved to the very beginning
2129 of the function, before any parameter access are made. The return value of
2130 this function should be an RTX that contains the value to use as the return
2131 of `__builtin_saveregs'.
2132
2133 If this macro is not defined, the compiler will output an ordinary call to
2134 the library function `__builtin_saveregs'. */
2135
2136 rtx
d30v_expand_builtin_saveregs()2137 d30v_expand_builtin_saveregs ()
2138 {
2139 int offset = UNITS_PER_WORD * (GPR_ARG_LAST + 1 - GPR_ARG_FIRST);
2140
2141 if (TARGET_DEBUG_ARG)
2142 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2143 offset);
2144
2145 return gen_rtx (PLUS, Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2146 }
2147
2148
2149 /* This macro offers an alternative to using `__builtin_saveregs' and defining
2150 the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
2151 arguments into the stack so that all the arguments appear to have been
2152 passed consecutively on the stack. Once this is done, you can use the
2153 standard implementation of varargs that works for machines that pass all
2154 their arguments on the stack.
2155
2156 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
2157 the values that obtain after processing of the named arguments. The
2158 arguments MODE and TYPE describe the last named argument--its machine mode
2159 and its data type as a tree node.
2160
2161 The macro implementation should do two things: first, push onto the stack
2162 all the argument registers *not* used for the named arguments, and second,
2163 store the size of the data thus pushed into the `int'-valued variable whose
2164 name is supplied as the argument PRETEND_ARGS_SIZE. The value that you
2165 store here will serve as additional offset for setting up the stack frame.
2166
2167 Because you must generate code to push the anonymous arguments at compile
2168 time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
2169 useful on machines that have just a single category of argument register and
2170 use it uniformly for all data types.
2171
2172 If the argument SECOND_TIME is nonzero, it means that the arguments of the
2173 function are being analyzed for the second time. This happens for an inline
2174 function, which is not actually compiled until the end of the source file.
2175 The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
2176 this case. */
2177
2178 void
d30v_setup_incoming_varargs(cum,mode,type,pretend_size,second_time)2179 d30v_setup_incoming_varargs (cum, mode, type, pretend_size, second_time)
2180 CUMULATIVE_ARGS *cum;
2181 enum machine_mode mode;
2182 tree type ATTRIBUTE_UNUSED;
2183 int *pretend_size ATTRIBUTE_UNUSED;
2184 int second_time;
2185 {
2186 if (TARGET_DEBUG_ARG)
2187 fprintf (stderr,
2188 "setup_vararg: words = %2d, mode = %4s, second_time = %d\n",
2189 *cum, GET_MODE_NAME (mode), second_time);
2190 }
2191
2192
2193 /* Create the va_list data type. */
2194
2195 tree
d30v_build_va_list()2196 d30v_build_va_list ()
2197 {
2198 tree f_arg_ptr, f_arg_num, record, type_decl;
2199 tree int_type_node;
2200
2201 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2202 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
2203 int_type_node = make_signed_type (INT_TYPE_SIZE);
2204
2205 f_arg_ptr = build_decl (FIELD_DECL, get_identifier ("__va_arg_ptr"),
2206 ptr_type_node);
2207 f_arg_num = build_decl (FIELD_DECL, get_identifier ("__va_arg_num"),
2208 int_type_node);
2209
2210 DECL_FIELD_CONTEXT (f_arg_ptr) = record;
2211 DECL_FIELD_CONTEXT (f_arg_num) = record;
2212
2213 TREE_CHAIN (record) = type_decl;
2214 TYPE_NAME (record) = type_decl;
2215 TYPE_FIELDS (record) = f_arg_ptr;
2216 TREE_CHAIN (f_arg_ptr) = f_arg_num;
2217
2218 layout_type (record);
2219
2220 /* The correct type is an array type of one element. */
2221 return build_array_type (record, build_index_type (size_zero_node));
2222 }
2223
2224
2225 /* Expand __builtin_va_start to do the va_start macro. */
2226
2227 void
d30v_expand_builtin_va_start(valist,nextarg)2228 d30v_expand_builtin_va_start (valist, nextarg)
2229 tree valist;
2230 rtx nextarg ATTRIBUTE_UNUSED;
2231 {
2232 HOST_WIDE_INT words;
2233 tree f_arg_ptr, f_arg_num;
2234 tree arg_ptr, arg_num, saveregs, t;
2235
2236 f_arg_ptr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2237 f_arg_num = TREE_CHAIN (f_arg_ptr);
2238
2239 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2240 arg_ptr = build (COMPONENT_REF, TREE_TYPE (f_arg_ptr), valist, f_arg_ptr);
2241 arg_num = build (COMPONENT_REF, TREE_TYPE (f_arg_num), valist, f_arg_num);
2242
2243 words = current_function_args_info; /* __builtin_args_info (0) */
2244
2245 /* (AP)->__va_arg_ptr = (int *) __builtin_saveregs (); */
2246 saveregs = make_tree (TREE_TYPE (arg_ptr), d30v_expand_builtin_saveregs ());
2247 t = build (MODIFY_EXPR, TREE_TYPE (arg_ptr), arg_ptr, saveregs);
2248 TREE_SIDE_EFFECTS (t) = 1;
2249 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2250
2251 /* (AP)->__va_arg_num = __builtin_args_info (0) - 2; */
2252 t = build (PLUS_EXPR, TREE_TYPE (arg_num), build_int_2 (words, 0),
2253 build_int_2 (-GPR_ARG_FIRST, 0));
2254 t = build (MODIFY_EXPR, TREE_TYPE (arg_num), arg_num, t);
2255 TREE_SIDE_EFFECTS (t) = 1;
2256 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2257 }
2258
2259
2260 /* Expand __builtin_va_arg to do the va_arg macro. */
2261
2262 rtx
d30v_expand_builtin_va_arg(valist,type)2263 d30v_expand_builtin_va_arg(valist, type)
2264 tree valist;
2265 tree type;
2266 {
2267 tree f_arg_ptr, f_arg_num;
2268 tree arg_ptr, arg_num, t, ptr;
2269 int num, size;
2270 rtx lab_false, ptr_rtx, r;
2271
2272 f_arg_ptr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2273 f_arg_num = TREE_CHAIN (f_arg_ptr);
2274
2275 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2276 arg_ptr = build (COMPONENT_REF, TREE_TYPE (f_arg_ptr), valist, f_arg_ptr);
2277 arg_num = build (COMPONENT_REF, TREE_TYPE (f_arg_num), valist, f_arg_num);
2278
2279 size = int_size_in_bytes (type);
2280
2281 lab_false = gen_label_rtx ();
2282 ptr_rtx = gen_reg_rtx (Pmode);
2283
2284 /* if (sizeof (TYPE) > 4 && ((AP)->__va_arg_num & 1) != 0)
2285 (AP)->__va_arg_num++; */
2286
2287 if (size > UNITS_PER_WORD)
2288 {
2289 t = build (BIT_AND_EXPR, TREE_TYPE (arg_num), arg_num,
2290 build_int_2 (1, 0));
2291
2292 emit_cmp_and_jump_insns (expand_expr (t, NULL_RTX, QImode, EXPAND_NORMAL),
2293 GEN_INT (0), EQ, const1_rtx, QImode, 1,
2294 lab_false);
2295
2296 t = build (POSTINCREMENT_EXPR, TREE_TYPE (arg_num), arg_num,
2297 build_int_2 (1, 0));
2298 TREE_SIDE_EFFECTS (t) = 1;
2299 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2300
2301 emit_label (lab_false);
2302 }
2303
2304
2305 /* __ptr = (TYPE *)(((char *)(void *)((AP)->__va_arg_ptr
2306 + (AP)->__va_arg_num))); */
2307
2308 t = build (MULT_EXPR, TREE_TYPE (arg_num), arg_num, build_int_2 (4, 0));
2309 t = build (PLUS_EXPR, ptr_type_node, arg_ptr, t);
2310
2311 /* if (sizeof (TYPE) < 4)
2312 __ptr = (void *)__ptr + 4 - sizeof (TYPE); */
2313
2314 if (size < UNITS_PER_WORD)
2315 t = build (PLUS_EXPR, ptr_type_node, t,
2316 build_int_2 (UNITS_PER_WORD - size, 0));
2317
2318 TREE_SIDE_EFFECTS (t) = 1;
2319
2320 ptr = build1 (NOP_EXPR, build_pointer_type (type), t);
2321 t = build (MODIFY_EXPR, type, ptr, t);
2322
2323 r = expand_expr (t, ptr_rtx, Pmode, EXPAND_NORMAL);
2324 if (r != ptr_rtx)
2325 emit_move_insn (ptr_rtx, r);
2326
2327
2328 /* (AP)->__va_arg_num += (sizeof (TYPE) + 3) / 4; */
2329 num = (size + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
2330 t = build (POSTINCREMENT_EXPR, TREE_TYPE (arg_num), arg_num,
2331 build_int_2 (num, 0));
2332 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2333
2334 return ptr_rtx;
2335 }
2336
2337 /* Generate the assembly code for function entry. FILE is a stdio
2338 stream to output the code to. SIZE is an int: how many units of
2339 temporary storage to allocate.
2340
2341 Refer to the array `regs_ever_live' to determine which registers to
2342 save; `regs_ever_live[I]' is nonzero if register number I is ever
2343 used in the function. This function is responsible for knowing
2344 which registers should not be saved even if used. */
2345
2346 static void
d30v_output_function_prologue(stream,size)2347 d30v_output_function_prologue (stream, size)
2348 FILE *stream ATTRIBUTE_UNUSED;
2349 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2350 {
2351 /* For the d30v, move all of the prologue processing into separate
2352 insns. */
2353 }
2354
2355
2356 /* Called after register allocation to add any instructions needed for
2357 the prologue. Using a prologue insn is favored compared to putting
2358 all of the instructions in output_function_prologue (), since it
2359 allows the scheduler to intermix instructions with the saves of the
2360 caller saved registers. In some cases, it might be necessary to
2361 emit a barrier instruction as the last insn to prevent such
2362 scheduling. */
2363
2364 void
d30v_expand_prologue()2365 d30v_expand_prologue ()
2366 {
2367 rtx sp = stack_pointer_rtx;
2368 d30v_stack_t *info = d30v_stack_info ();
2369 int i;
2370 rtx mem_di = NULL_RTX;
2371 rtx mem_si = NULL_RTX;
2372 int num_memrefs = (info->memrefs_2words
2373 + info->memrefs_1word
2374 + info->memrefs_varargs);
2375
2376 if (TARGET_DEBUG_STACK)
2377 debug_stack_info (info);
2378
2379 /* Grow the stack. */
2380 if (info->total_size)
2381 emit_insn (gen_addsi3 (sp, sp, GEN_INT (- info->total_size)));
2382
2383 /* If there is more than one save, use post-increment addressing which will
2384 result in smaller code, than would the normal references. If there is
2385 only one save, just do the store as normal. */
2386
2387 if (num_memrefs > 1)
2388 {
2389 rtx save_tmp = gen_rtx (REG, Pmode, GPR_STACK_TMP);
2390 rtx post_inc = gen_rtx (POST_INC, Pmode, save_tmp);
2391 mem_di = gen_rtx (MEM, DImode, post_inc);
2392 mem_si = gen_rtx (MEM, SImode, post_inc);
2393 emit_insn (gen_addsi3 (save_tmp, sp, GEN_INT (info->save_offset)));
2394 }
2395 else if (num_memrefs == 1)
2396 {
2397 rtx addr = plus_constant (sp, info->save_offset);
2398 mem_di = gen_rtx (MEM, DImode, addr);
2399 mem_si = gen_rtx (MEM, SImode, addr);
2400 }
2401
2402 /* Save the accumulators. */
2403 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
2404 if (info->save_p[i])
2405 {
2406 rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST);
2407 emit_insn (gen_movdi (acc_tmp, gen_rtx (REG, DImode, i)));
2408 emit_insn (gen_movdi (mem_di, acc_tmp));
2409 }
2410
2411 /* Save the GPR registers that are adjacent to each other with st2w. */
2412 for (i = GPR_FIRST; i <= GPR_LAST; i += 2)
2413 if (info->save_p[i] == 2)
2414 emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i)));
2415
2416 /* Save the GPR registers that need to be saved with a single word store. */
2417 for (i = GPR_FIRST; i <= GPR_LAST; i++)
2418 if (info->save_p[i] == 1)
2419 emit_insn (gen_movsi (mem_si, gen_rtx (REG, SImode, i)));
2420
2421 /* Save the argument registers if this function accepts variable args. */
2422 if (info->varargs_p)
2423 {
2424 /* Realign r22 if an odd # of GPRs were saved. */
2425 if ((info->memrefs_1word & 1) != 0)
2426 {
2427 rtx save_tmp = XEXP (XEXP (mem_si, 0), 0);
2428 emit_insn (gen_addsi3 (save_tmp, save_tmp, GEN_INT (UNITS_PER_WORD)));
2429 }
2430
2431 for (i = GPR_ARG_FIRST; i <= GPR_ARG_LAST; i += 2)
2432 emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i)));
2433 }
2434
2435 /* Update the frame pointer. */
2436 if (frame_pointer_needed)
2437 emit_move_insn (frame_pointer_rtx, sp);
2438
2439 /* Hack for now, to prevent scheduler from being too cleaver */
2440 emit_insn (gen_blockage ());
2441 }
2442
2443
2444 /* This function generates the assembly code for function exit.
2445 Args are as for output_function_prologue ().
2446
2447 The function epilogue should not depend on the current stack
2448 pointer! It should use the frame pointer only. This is mandatory
2449 because of alloca; we also take advantage of it to omit stack
2450 adjustments before returning. */
2451
2452 static void
d30v_output_function_epilogue(stream,size)2453 d30v_output_function_epilogue (stream, size)
2454 FILE *stream ATTRIBUTE_UNUSED;
2455 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2456 {
2457 /* For the d30v, move all processing to be as insns, but do any
2458 cleanup here, since it is done after handling all of the insns. */
2459 d30v_stack_cache = (d30v_stack_t *)0; /* reset stack cache */
2460 }
2461
2462
2463
2464 /* Called after register allocation to add any instructions needed for
2465 the epilogue. Using an epilogue insn is favored compared to putting
2466 all of the instructions in output_function_prologue(), since it
2467 allows the scheduler to intermix instructions with the saves of the
2468 caller saved registers. In some cases, it might be necessary to
2469 emit a barrier instruction as the last insn to prevent such
2470 scheduling. */
2471
2472 void
d30v_expand_epilogue()2473 d30v_expand_epilogue ()
2474 {
2475 rtx sp = stack_pointer_rtx;
2476 d30v_stack_t *info = d30v_stack_info ();
2477 int i;
2478 rtx mem_di = NULL_RTX;
2479 rtx mem_si = NULL_RTX;
2480 rtx post_inc;
2481 int extra_stack;
2482
2483 /* Hack for now, to prevent scheduler from being too cleaver */
2484 emit_insn (gen_blockage ());
2485
2486 /* Restore sp from fp. */
2487 if (frame_pointer_needed)
2488 emit_move_insn (sp, frame_pointer_rtx);
2489
2490 /* For the epilogue, use post-increment addressing all of the time. First
2491 adjust the sp, to eliminate all of the stack, except for the save area. */
2492
2493 if (info->save_offset)
2494 emit_insn (gen_addsi3 (sp, sp, GEN_INT (info->save_offset)));
2495
2496 post_inc = gen_rtx (POST_INC, Pmode, sp);
2497 mem_di = gen_rtx (MEM, DImode, post_inc);
2498 mem_si = gen_rtx (MEM, SImode, post_inc);
2499
2500 /* Restore the accumulators. */
2501 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
2502 if (info->save_p[i])
2503 {
2504 rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST);
2505 emit_insn (gen_movdi (acc_tmp, mem_di));
2506 emit_insn (gen_movdi (gen_rtx (REG, DImode, i), acc_tmp));
2507 }
2508
2509 /* Restore the GPR registers that are adjacent to each other with ld2w. */
2510 for (i = GPR_FIRST; i <= GPR_LAST; i += 2)
2511 if (info->save_p[i] == 2)
2512 emit_insn (gen_movdi (gen_rtx (REG, DImode, i), mem_di));
2513
2514 /* Save the GPR registers that need to be saved with a single word store. */
2515 extra_stack = 0;
2516 for (i = GPR_FIRST; i <= GPR_LAST; i++)
2517 if (info->save_p[i] == 1)
2518 {
2519 if (cfun->machine->eh_epilogue_sp_ofs && i == GPR_LINK)
2520 extra_stack = 4;
2521 else
2522 {
2523 if (extra_stack)
2524 {
2525 emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack)));
2526 extra_stack = 0;
2527 }
2528 emit_insn (gen_movsi (gen_rtx (REG, SImode, i), mem_si));
2529 }
2530 }
2531
2532 /* Release any remaining stack that was allocated for saving the
2533 varargs registers or because an odd # of registers were stored. */
2534 if ((info->memrefs_1word & 1) != 0)
2535 extra_stack += UNITS_PER_WORD;
2536 extra_stack += current_function_pretend_args_size + info->varargs_size;
2537
2538 if (extra_stack)
2539 {
2540 if (cfun->machine->eh_epilogue_sp_ofs)
2541 emit_insn (gen_addsi3 (cfun->machine->eh_epilogue_sp_ofs,
2542 cfun->machine->eh_epilogue_sp_ofs,
2543 GEN_INT (extra_stack)));
2544 else
2545 emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack)));
2546 }
2547 if (cfun->machine->eh_epilogue_sp_ofs)
2548 emit_insn (gen_addsi3 (sp, sp, cfun->machine->eh_epilogue_sp_ofs));
2549
2550 /* Now emit the return instruction. */
2551 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
2552 }
2553
2554
2555 /* A C statement or compound statement to output to FILE some assembler code to
2556 call the profiling subroutine `mcount'. Before calling, the assembler code
2557 must load the address of a counter variable into a register where `mcount'
2558 expects to find the address. The name of this variable is `LP' followed by
2559 the number LABELNO, so you would generate the name using `LP%d' in a
2560 `fprintf'.
2561
2562 The details of how the address should be passed to `mcount' are determined
2563 by your operating system environment, not by GNU CC. To figure them out,
2564 compile a small program for profiling using the system's installed C
2565 compiler and look at the assembler code that results. */
2566
2567 void
d30v_function_profiler(stream,labelno)2568 d30v_function_profiler (stream, labelno)
2569 FILE *stream;
2570 int labelno ATTRIBUTE_UNUSED;
2571 {
2572 fprintf (stream, "# profile\n");
2573 }
2574
2575
2576 /* Split a 64 bit item into an upper and a lower part. We specifically do not
2577 want to call gen_highpart/gen_lowpart on CONST_DOUBLEs since it will give us
2578 the wrong part for floating point in cross compilers, and split_double does
2579 not handle registers. Also abort if the register is not a general purpose
2580 register. */
2581
2582 void
d30v_split_double(value,p_high,p_low)2583 d30v_split_double (value, p_high, p_low)
2584 rtx value;
2585 rtx *p_high;
2586 rtx *p_low;
2587 {
2588 int offset = 0;
2589 int regno;
2590
2591 if (!reload_completed)
2592 abort ();
2593
2594 switch (GET_CODE (value))
2595 {
2596 case SUBREG:
2597 if (GET_CODE (SUBREG_REG (value)) != REG)
2598 abort ();
2599 offset = subreg_regno_offset (REGNO (SUBREG_REG (value)),
2600 GET_MODE (SUBREG_REG (value)),
2601 SUBREG_BYTE (value),
2602 GET_MODE (value));
2603 value = SUBREG_REG (value);
2604
2605 /* fall through */
2606
2607 case REG:
2608 regno = REGNO (value) + offset;
2609 if (!GPR_P (regno))
2610 abort ();
2611
2612 *p_high = gen_rtx (REG, SImode, regno);
2613 *p_low = gen_rtx (REG, SImode, regno+1);
2614 break;
2615
2616 case CONST_INT:
2617 case CONST_DOUBLE:
2618 split_double (value, p_high, p_low);
2619 break;
2620
2621 default:
2622 abort ();
2623 }
2624 }
2625
2626
2627 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2628 for an instruction operand that is a memory reference whose address is X. X
2629 is an RTL expression. */
2630
2631 void
d30v_print_operand_address(stream,x)2632 d30v_print_operand_address (stream, x)
2633 FILE *stream;
2634 rtx x;
2635 {
2636 if (GET_CODE (x) == MEM)
2637 x = XEXP (x, 0);
2638
2639 switch (GET_CODE (x))
2640 {
2641 default:
2642 break;
2643
2644 case REG:
2645 fputs (reg_names[ REGNO (x) ], stream);
2646 return;
2647
2648 case CONST_INT:
2649 fprintf (stream, "%ld", (long) INTVAL (x));
2650 return;
2651
2652 /* We wrap simple symbol refs inside a parenthesis, so that a name
2653 like `r2' is not taken for a register name. */
2654 case SYMBOL_REF:
2655 fputs ("(", stream);
2656 assemble_name (stream, XSTR (x, 0));
2657 fputs (")", stream);
2658 return;
2659
2660 case LABEL_REF:
2661 case CONST:
2662 output_addr_const (stream, x);
2663 return;
2664 }
2665
2666 fatal_insn ("bad insn to d30v_print_operand_address:", x);
2667 }
2668
2669
2670 /* Print a memory reference suitable for the ld/st instructions. */
2671
2672 static void
d30v_print_operand_memory_reference(stream,x)2673 d30v_print_operand_memory_reference (stream, x)
2674 FILE *stream;
2675 rtx x;
2676 {
2677 rtx x0 = NULL_RTX;
2678 rtx x1 = NULL_RTX;
2679
2680 switch (GET_CODE (x))
2681 {
2682 default:
2683 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2684 break;
2685
2686 case SUBREG:
2687 case REG:
2688 case POST_DEC:
2689 case POST_INC:
2690 x0 = x;
2691 break;
2692
2693 case CONST_INT:
2694 case SYMBOL_REF:
2695 case LABEL_REF:
2696 case CONST:
2697 x1 = x;
2698 break;
2699
2700 case PLUS:
2701 x0 = XEXP (x, 0);
2702 x1 = XEXP (x, 1);
2703 if (GET_CODE (x0) == CONST_INT || GET_CODE (x0) == SYMBOL_REF
2704 || GET_CODE (x0) == CONST || GET_CODE (x0) == LABEL_REF)
2705 {
2706 x0 = XEXP (x, 1);
2707 x1 = XEXP (x, 0);
2708 }
2709 break;
2710 }
2711
2712 fputs ("@(", stream);
2713 if (!x0)
2714 fputs (reg_names[GPR_R0], stream);
2715
2716 else
2717 {
2718 const char *suffix = "";
2719 int offset0 = 0;
2720
2721 if (GET_CODE (x0) == SUBREG)
2722 {
2723 offset0 = subreg_regno_offset (REGNO (SUBREG_REG (x0)),
2724 GET_MODE (SUBREG_REG (x0)),
2725 SUBREG_BYTE (x0),
2726 GET_MODE (x0));
2727 x0 = SUBREG_REG (x0);
2728 }
2729
2730 if (GET_CODE (x0) == POST_INC)
2731 {
2732 x0 = XEXP (x0, 0);
2733 suffix = "+";
2734 }
2735 else if (GET_CODE (x0) == POST_DEC)
2736 {
2737 x0 = XEXP (x0, 0);
2738 suffix = "-";
2739 }
2740
2741 if (GET_CODE (x0) == REG && GPR_P (REGNO (x0)))
2742 fprintf (stream, "%s%s", reg_names[REGNO (x0) + offset0], suffix);
2743 else
2744 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2745 }
2746
2747 fputs (",", stream);
2748
2749 if (!x1)
2750 fputs (reg_names[GPR_R0], stream);
2751
2752 else
2753 {
2754 int offset1 = 0;
2755
2756 switch (GET_CODE (x1))
2757 {
2758 case SUBREG:
2759 offset1 = subreg_regno_offset (REGNO (SUBREG_REG (x1)),
2760 GET_MODE (SUBREG_REG (x1)),
2761 SUBREG_BYTE (x1),
2762 GET_MODE (x1));
2763 x1 = SUBREG_REG (x1);
2764 if (GET_CODE (x1) != REG)
2765 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2766
2767 /* fall through */
2768 case REG:
2769 fputs (reg_names[REGNO (x1) + offset1], stream);
2770 break;
2771
2772 case CONST_INT:
2773 fprintf (stream, "%ld", (long) INTVAL (x1));
2774 break;
2775
2776 case SYMBOL_REF:
2777 case LABEL_REF:
2778 case CONST:
2779 d30v_print_operand_address (stream, x1);
2780 break;
2781
2782 default:
2783 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2784 }
2785 }
2786
2787 fputs (")", stream);
2788 }
2789
2790
2791 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2792 for an instruction operand X. X is an RTL expression.
2793
2794 LETTER is a value that can be used to specify one of several ways of
2795 printing the operand. It is used when identical operands must be printed
2796 differently depending on the context. LETTER comes from the `%'
2797 specification that was used to request printing of the operand. If the
2798 specification was just `%DIGIT' then LETTER is 0; if the specification was
2799 `%LTR DIGIT' then LETTER is the ASCII code for LTR.
2800
2801 If X is a register, this macro should print the register's name. The names
2802 can be found in an array `reg_names' whose type is `char *[]'. `reg_names'
2803 is initialized from `REGISTER_NAMES'.
2804
2805 When the machine description has a specification `%PUNCT' (a `%' followed by
2806 a punctuation character), this macro is called with a null pointer for X and
2807 the punctuation character for LETTER.
2808
2809 Standard operand flags that are handled elsewhere:
2810 `=' Output a number unique to each instruction in the compilation.
2811 `a' Substitute an operand as if it were a memory reference.
2812 `c' Omit the syntax that indicates an immediate operand.
2813 `l' Substitute a LABEL_REF into a jump instruction.
2814 `n' Like %cDIGIT, except negate the value before printing.
2815
2816 The d30v specific operand flags are:
2817 `.' Print r0.
2818 `f' Print a SF constant as an int.
2819 `s' Subtract 32 and negate.
2820 `A' Print accumulator number without an `a' in front of it.
2821 `B' Print bit offset for BSET, etc. instructions.
2822 `E' Print u if this is zero extend, nothing if this is sign extend.
2823 `F' Emit /{f,t,x}{f,t,x} for executing a false condition.
2824 `L' Print the lower half of a 64 bit item.
2825 `M' Print a memory reference for ld/st instructions.
2826 `R' Return appropriate cmp instruction for relational test.
2827 `S' Subtract 32.
2828 `T' Emit /{f,t,x}{f,t,x} for executing a true condition.
2829 `U' Print the upper half of a 64 bit item. */
2830
2831 void
d30v_print_operand(stream,x,letter)2832 d30v_print_operand (stream, x, letter)
2833 FILE *stream;
2834 rtx x;
2835 int letter;
2836 {
2837 enum rtx_code code = (x) ? GET_CODE (x) : NIL;
2838 rtx split_values[2];
2839 REAL_VALUE_TYPE rv;
2840 long num;
2841 int log;
2842
2843 switch (letter)
2844 {
2845 case '.': /* Output r0 */
2846 fputs (reg_names[GPR_R0], stream);
2847 break;
2848
2849 case 'f': /* Print a SF floating constant as an int */
2850 if (GET_CODE (x) != CONST_DOUBLE)
2851 fatal_insn ("bad insn to d30v_print_operand, 'f' modifier:", x);
2852
2853 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2854 REAL_VALUE_TO_TARGET_SINGLE (rv, num);
2855 fprintf (stream, "%ld", num);
2856 break;
2857
2858 case 'A': /* Print accumulator number without an `a' in front of it. */
2859 if (GET_CODE (x) != REG || !ACCUM_P (REGNO (x)))
2860 fatal_insn ("bad insn to d30v_print_operand, 'A' modifier:", x);
2861
2862 putc ('0' + REGNO (x) - ACCUM_FIRST, stream);
2863 break;
2864
2865 case 'M': /* Print a memory reference for ld/st */
2866 if (GET_CODE (x) != MEM)
2867 fatal_insn ("bad insn to d30v_print_operand, 'M' modifier:", x);
2868
2869 d30v_print_operand_memory_reference (stream, XEXP (x, 0));
2870 break;
2871
2872 case 'L': /* print lower part of 64 bit item. */
2873 case 'U': /* print upper part of 64 bit item. */
2874 d30v_split_double (x, &split_values[0], &split_values[1]);
2875 d30v_print_operand (stream, split_values[ letter == 'L' ], '\0');
2876 break;
2877
2878 case ':': /* Output the condition for the current insn. */
2879 x = current_insn_predicate;
2880 if (x == NULL_RTX)
2881 break;
2882 letter = 'T';
2883 /* FALLTHRU */
2884
2885 case 'F': /* Print an appropriate suffix for a false comparision. */
2886 case 'T': /* Print an appropriate suffix for a true comparision. */
2887 /* Note that the sense of appropriate suffix is for conditional execution
2888 and opposite of what branches want. Branches just use the inverse
2889 operation. */
2890 if ((GET_CODE (x) == NE || GET_CODE (x) == EQ)
2891 && GET_MODE (x) == CCmode
2892 && GET_CODE (XEXP (x, 0)) == REG
2893 && (GPR_P (REGNO (XEXP (x, 0))) || BR_FLAG_P (REGNO (XEXP (x, 0))))
2894 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
2895 {
2896 int true_false = (letter == 'T');
2897
2898 if (GET_CODE (x) == EQ)
2899 true_false = !true_false;
2900
2901 if (REGNO (XEXP (x, 0)) == FLAG_F0)
2902 fprintf (stream, "/%cx", (true_false) ? 'f' : 't');
2903
2904 else if (REGNO (XEXP (x, 0)) == FLAG_F1)
2905 fprintf (stream, "/x%c", (true_false) ? 'f' : 't');
2906
2907 else
2908 fputs ((true_false) ? "tnz" : "tzr", stream);
2909 }
2910
2911 else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F0)
2912 fprintf (stream, "/%cx", (letter == 'T') ? 't' : 'f');
2913
2914 else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F1)
2915 fprintf (stream, "/x%c", (letter == 'T') ? 't' : 'f');
2916
2917 else if (GET_CODE (x) == REG && GPR_P (REGNO (x)))
2918 fputs ((letter == 'T') ? "tnz" : "tzr", stream);
2919
2920 else
2921 fatal_insn ("bad insn to print_operand, 'F' or 'T' modifier:", x);
2922 break;
2923
2924 case 'B': /* emit offset single bit to change */
2925 if (GET_CODE (x) == CONST_INT && (log = exact_log2 (INTVAL (x))) >= 0)
2926 fprintf (stream, "%d", 31 - log);
2927
2928 else if (GET_CODE (x) == CONST_INT && (log = exact_log2 (~ INTVAL (x))) >= 0)
2929 fprintf (stream, "%d", 31 - log);
2930
2931 else
2932 fatal_insn ("bad insn to print_operand, 'B' modifier:", x);
2933 break;
2934
2935 case 'E': /* Print u if this is zero extend, nothing if sign extend. */
2936 if (GET_CODE (x) == ZERO_EXTEND)
2937 putc ('u', stream);
2938 else if (GET_CODE (x) != SIGN_EXTEND)
2939 fatal_insn ("bad insn to print_operand, 'E' modifier:", x);
2940 break;
2941
2942 case 'R': /* Return appropriate cmp instruction for relational test. */
2943 switch (GET_CODE (x))
2944 {
2945 case EQ: fputs ("cmpeq", stream); break;
2946 case NE: fputs ("cmpne", stream); break;
2947 case LT: fputs ("cmplt", stream); break;
2948 case LE: fputs ("cmple", stream); break;
2949 case GT: fputs ("cmpgt", stream); break;
2950 case GE: fputs ("cmpge", stream); break;
2951 case LTU: fputs ("cmpult", stream); break;
2952 case LEU: fputs ("cmpule", stream); break;
2953 case GTU: fputs ("cmpugt", stream); break;
2954 case GEU: fputs ("cmpuge", stream); break;
2955
2956 default:
2957 fatal_insn ("bad insn to print_operand, 'R' modifier:", x);
2958 }
2959 break;
2960
2961 case 's': /* Subtract 32 and negate (for 64 bit shifts). */
2962 if (GET_CODE (x) == CONST_INT)
2963 fprintf (stream, "%d", (int) (32 - INTVAL (x)));
2964
2965 else
2966 fatal_insn ("bad insn to print_operand, 's' modifier:", x);
2967 break;
2968
2969 case 'S': /* Subtract 32. */
2970 if (GET_CODE (x) == CONST_INT)
2971 fprintf (stream, "%d", (int)(INTVAL (x) - 32));
2972
2973 else
2974 fatal_insn ("bad insn to print_operand, 's' modifier:", x);
2975 break;
2976
2977
2978 case 'z': /* If arg is 0 or 0.0, print r0, otherwise print as normal */
2979 if ((GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2980 || (GET_CODE (x) == CONST_DOUBLE && CONST_DOUBLE_LOW (x) == 0
2981 && CONST_DOUBLE_HIGH (x) == 0))
2982 {
2983 fputs (reg_names[GPR_FIRST], stream);
2984 return;
2985 }
2986
2987 /* fall through */
2988
2989 case '\0':
2990 if (code == REG)
2991 fputs (reg_names[ REGNO (x) ], stream);
2992
2993 else if (code == CONST_INT)
2994 fprintf (stream, "%d", (int)INTVAL (x));
2995
2996 else if (code == MEM)
2997 d30v_print_operand_address (stream, XEXP (x, 0));
2998
2999 else if (CONSTANT_ADDRESS_P (x))
3000 d30v_print_operand_address (stream, x);
3001
3002 else
3003 fatal_insn ("bad insn in d30v_print_operand, 0 case", x);
3004
3005 return;
3006
3007 default:
3008 {
3009 char buf[80];
3010
3011 sprintf (buf, "invalid asm template character '%%%c'", letter);
3012 fatal_insn (buf, x);
3013 }
3014 }
3015 }
3016
3017
3018 /* A C expression for the size in bytes of the trampoline, as an integer. */
3019
3020 int
d30v_trampoline_size()3021 d30v_trampoline_size ()
3022 {
3023 return 16;
3024 }
3025
3026
3027 /* Create a long instruction for building up a trampoline. */
3028
3029 static void
d30v_build_long_insn(high_bits,low_bits,imm,mem)3030 d30v_build_long_insn (high_bits, low_bits, imm, mem)
3031 HOST_WIDE_INT high_bits;
3032 HOST_WIDE_INT low_bits;
3033 rtx imm;
3034 rtx mem;
3035 {
3036 rtx reg = gen_reg_rtx (DImode);
3037 rtx high_word = gen_highpart (SImode, reg);
3038 rtx low_word = gen_lowpart (SImode, reg);
3039 rtx tmp1 = gen_reg_rtx (SImode);
3040 rtx tmp2 = gen_reg_rtx (SImode);
3041 rtx tmp3 = gen_reg_rtx (SImode);
3042 rtx tmp4 = gen_reg_rtx (SImode);
3043 rtx tmp5 = gen_reg_rtx (SImode);
3044 rtx tmp6 = gen_reg_rtx (SImode);
3045
3046 imm = force_reg (SImode, imm);
3047
3048 /* Stuff top 6 bits of immediate value into high word */
3049 emit_insn (gen_lshrsi3 (tmp1, imm, GEN_INT (26)));
3050 emit_insn (gen_andsi3 (tmp2, tmp1, GEN_INT (0x3F)));
3051 emit_insn (gen_iorsi3 (high_word, tmp2, GEN_INT (high_bits)));
3052
3053 /* Now get the next 8 bits for building the low word */
3054 emit_insn (gen_andsi3 (tmp3, imm, GEN_INT (0x03FC0000)));
3055 emit_insn (gen_ashlsi3 (tmp4, tmp3, GEN_INT (2)));
3056
3057 /* And the bottom 18 bits */
3058 emit_insn (gen_andsi3 (tmp5, imm, GEN_INT (0x0003FFFF)));
3059 emit_insn (gen_iorsi3 (tmp6, tmp4, tmp5));
3060 emit_insn (gen_iorsi3 (low_word, tmp6, GEN_INT (low_bits)));
3061
3062 /* Store the instruction */
3063 emit_insn (gen_movdi (mem, reg));
3064 }
3065
3066
3067 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
3068 RTX for the address of the trampoline; FNADDR is an RTX for the address of
3069 the nested function; STATIC_CHAIN is an RTX for the static chain value that
3070 should be passed to the function when it is called. */
3071
3072 void
d30v_initialize_trampoline(addr,fnaddr,static_chain)3073 d30v_initialize_trampoline (addr, fnaddr, static_chain)
3074 rtx addr;
3075 rtx fnaddr;
3076 rtx static_chain;
3077 {
3078 /* The instruction space can only be accessed by ld2w/st2w.
3079 Generate on the fly:
3080 or r18,r0,<static-chain>
3081 jmp <fnaddr> */
3082 d30v_build_long_insn (0x83A80000 | ((STATIC_CHAIN_REGNUM - GPR_FIRST) << 12),
3083 0x80000000, static_chain,
3084 gen_rtx (MEM, DImode, addr));
3085
3086 d30v_build_long_insn (0x80180000, 0x80000000, fnaddr,
3087 gen_rtx (MEM, DImode, plus_constant (addr, 8)));
3088 }
3089
3090
3091 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3092 RTX) is a legitimate memory address on the target machine for a memory
3093 operand of mode MODE. */
3094
3095 #define XREGNO_OK_FOR_BASE_P(REGNO, STRICT_P) \
3096 ((STRICT_P) \
3097 ? REGNO_OK_FOR_BASE_P (REGNO) \
3098 : GPR_OR_PSEUDO_P (REGNO))
3099
3100 int
d30v_legitimate_address_p(mode,x,strict_p)3101 d30v_legitimate_address_p (mode, x, strict_p)
3102 enum machine_mode mode;
3103 rtx x;
3104 int strict_p;
3105 {
3106 rtx x0, x1;
3107 int ret = 0;
3108
3109 switch (GET_CODE (x))
3110 {
3111 default:
3112 break;
3113
3114 case SUBREG:
3115 x = SUBREG_REG (x);
3116 if (GET_CODE (x) != REG)
3117 break;
3118
3119 /* fall through */
3120
3121 case REG:
3122 ret = XREGNO_OK_FOR_BASE_P (REGNO (x), strict_p);
3123 break;
3124
3125 case PLUS:
3126 x0 = XEXP (x, 0);
3127 x1 = XEXP (x, 1);
3128
3129 if (GET_CODE (x0) == SUBREG)
3130 x0 = SUBREG_REG (x0);
3131
3132 if (GET_CODE (x0) == POST_INC || GET_CODE (x0) == POST_DEC)
3133 x0 = XEXP (x0, 0);
3134
3135 if (GET_CODE (x0) != REG || !XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
3136 break;
3137
3138 switch (GET_CODE (x1))
3139 {
3140 default:
3141 break;
3142
3143 case SUBREG:
3144 x1 = SUBREG_REG (x1);
3145 if (GET_CODE (x1) != REG)
3146 break;
3147
3148 /* fall through */
3149
3150 case REG:
3151 ret = XREGNO_OK_FOR_BASE_P (REGNO (x1), strict_p);
3152 break;
3153
3154 case CONST_INT:
3155 ret = (IN_RANGE_P (INTVAL (x1), -32, 31)) ? 1 : 2;
3156 break;
3157
3158 case SYMBOL_REF:
3159 case LABEL_REF:
3160 case CONST:
3161 ret = 2;
3162 break;
3163 }
3164 break;
3165
3166 case CONST_INT:
3167 ret = (IN_RANGE_P (INTVAL (x), -32, 31)) ? 1 : 2;
3168 break;
3169
3170 case SYMBOL_REF:
3171 case LABEL_REF:
3172 case CONST:
3173 ret = 2;
3174 break;
3175
3176 case POST_INC:
3177 case POST_DEC:
3178 x0 = XEXP (x, 0);
3179 if (GET_CODE (x0) == REG && XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
3180 ret = 1;
3181 break;
3182 }
3183
3184 if (TARGET_DEBUG_ADDR)
3185 {
3186 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict\n",
3187 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ");
3188 debug_rtx (x);
3189 }
3190
3191 return ret;
3192 }
3193
3194
3195 /* A C compound statement that attempts to replace X with a valid memory
3196 address for an operand of mode MODE. WIN will be a C statement label
3197 elsewhere in the code; the macro definition may use
3198
3199 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3200
3201 to avoid further processing if the address has become legitimate.
3202
3203 X will always be the result of a call to `break_out_memory_refs', and OLDX
3204 will be the operand that was given to that function to produce X.
3205
3206 The code generated by this macro should not alter the substructure of X. If
3207 it transforms X into a more legitimate form, it should assign X (which will
3208 always be a C variable) a new value.
3209
3210 It is not necessary for this macro to come up with a legitimate address.
3211 The compiler has standard ways of doing so in all cases. In fact, it is
3212 safe for this macro to do nothing. But often a machine-dependent strategy
3213 can generate better code. */
3214
3215 rtx
d30v_legitimize_address(x,oldx,mode,strict_p)3216 d30v_legitimize_address (x, oldx, mode, strict_p)
3217 rtx x;
3218 rtx oldx ATTRIBUTE_UNUSED;
3219 enum machine_mode mode ATTRIBUTE_UNUSED;
3220 int strict_p ATTRIBUTE_UNUSED;
3221 {
3222 rtx ret = NULL_RTX;
3223
3224 if (TARGET_DEBUG_ADDR)
3225 {
3226 if (ret)
3227 {
3228 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, transformed:\n");
3229 debug_rtx (x);
3230 fprintf (stderr, "\ninto:\n");
3231 debug_rtx (ret);
3232 }
3233 else
3234 {
3235 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, did nothing with:\n");
3236 debug_rtx (x);
3237 }
3238 }
3239
3240 return ret;
3241 }
3242
3243
3244 /* A C statement or compound statement with a conditional `goto LABEL;'
3245 executed if memory address X (an RTX) can have different meanings depending
3246 on the machine mode of the memory reference it is used for or if the address
3247 is valid for some modes but not others.
3248
3249 Autoincrement and autodecrement addresses typically have mode-dependent
3250 effects because the amount of the increment or decrement is the size of the
3251 operand being addressed. Some machines have other mode-dependent addresses.
3252 Many RISC machines have no mode-dependent addresses.
3253
3254 You may assume that ADDR is a valid address for the machine. */
3255
3256 int
d30v_mode_dependent_address_p(addr)3257 d30v_mode_dependent_address_p (addr)
3258 rtx addr;
3259 {
3260 switch (GET_CODE (addr))
3261 {
3262 default:
3263 break;
3264
3265 case POST_INC:
3266 case POST_DEC:
3267 return TRUE;
3268 }
3269
3270 return FALSE;
3271 }
3272
3273
3274 /* Generate the appropriate comparison code for a test. */
3275
3276 rtx
d30v_emit_comparison(test_int,result,arg1,arg2)3277 d30v_emit_comparison (test_int, result, arg1, arg2)
3278 int test_int;
3279 rtx result;
3280 rtx arg1;
3281 rtx arg2;
3282 {
3283 enum rtx_code test = (enum rtx_code) test_int;
3284 enum machine_mode mode = GET_MODE (arg1);
3285 rtx rtx_test = gen_rtx (SET, VOIDmode, result, gen_rtx (test, CCmode, arg1, arg2));
3286
3287 if (mode == SImode
3288 || (mode == DImode && (test == EQ || test == NE))
3289 || (mode == DImode && (test == LT || test == GE)
3290 && GET_CODE (arg2) == CONST_INT && INTVAL (arg2) == 0))
3291 return rtx_test;
3292
3293 else if (mode == DImode)
3294 return gen_rtx (PARALLEL, VOIDmode,
3295 gen_rtvec (2,
3296 rtx_test,
3297 gen_rtx (CLOBBER, VOIDmode,
3298 gen_reg_rtx (CCmode))));
3299
3300 else
3301 fatal_insn ("d30v_emit_comparison", rtx_test);
3302 }
3303
3304
3305 /* Return appropriate code to move 2 words. Since DImode registers must start
3306 on even register numbers, there is no possibility of overlap. */
3307
3308 const char *
d30v_move_2words(operands,insn)3309 d30v_move_2words (operands, insn)
3310 rtx operands[];
3311 rtx insn;
3312 {
3313 if (GET_CODE (operands[0]) == REG && GPR_P (REGNO (operands[0])))
3314 {
3315 if (GET_CODE (operands[1]) == REG && GPR_P (REGNO (operands[1])))
3316 return "or %U0,%.,%U1\n\tor %L0,%.,%L1";
3317
3318 else if (GET_CODE (operands[1]) == REG && ACCUM_P (REGNO (operands[1])))
3319 return "mvfacc %L0,%1,%.\n\tmvfacc %U0,%1,32";
3320
3321 else if (GET_CODE (operands[1]) == MEM)
3322 return "ld2w %0,%M1";
3323
3324 else if (GET_CODE (operands[1]) == CONST_INT
3325 || GET_CODE (operands[1]) == CONST_DOUBLE)
3326 return "or %U0,%.,%U1\n\tor %L0,%.,%L1";
3327 }
3328
3329 else if (GET_CODE (operands[0]) == REG && ACCUM_P (REGNO (operands[0])))
3330 {
3331 if (GET_CODE (operands[1]) == REG
3332 && GPR_P (REGNO (operands[1])))
3333 return "mvtacc %0,%U1,%L1";
3334
3335 if (GET_CODE (operands[1]) == CONST_INT
3336 && INTVAL (operands[1]) == 0)
3337 return "mvtacc %0,%.,%.";
3338 }
3339
3340 else if (GET_CODE (operands[0]) == MEM
3341 && GET_CODE (operands[1]) == REG
3342 && GPR_P (REGNO (operands[1])))
3343 return "st2w %1,%M0";
3344
3345 fatal_insn ("bad call to d30v_move_2words", insn);
3346 }
3347
3348
3349 /* Emit the code to do a conditional move instruction. Return FALSE
3350 if the conditional move could not be executed. */
3351
3352 int
d30v_emit_cond_move(dest,test,true_value,false_value)3353 d30v_emit_cond_move (dest, test, true_value, false_value)
3354 rtx dest;
3355 rtx test;
3356 rtx true_value;
3357 rtx false_value;
3358 {
3359 rtx br_reg;
3360 enum machine_mode mode = GET_MODE (dest);
3361 int two_mem_moves_p = FALSE;
3362
3363 if (GET_CODE (dest) == MEM)
3364 {
3365 if (!reg_or_0_operand (true_value, mode))
3366 return FALSE;
3367
3368 if (rtx_equal_p (dest, false_value))
3369 two_mem_moves_p = TRUE;
3370
3371 else if (!reg_or_0_operand (false_value, mode))
3372 return FALSE;
3373 }
3374
3375 /* We used to try to optimize setting 0/1 by using mvfsys, but that turns out
3376 to be slower than just doing the conditional execution. */
3377
3378 br_reg = gen_reg_rtx (CCmode);
3379 emit_insn (d30v_emit_comparison (GET_CODE (test), br_reg,
3380 d30v_compare_op0, d30v_compare_op1));
3381
3382 if (!two_mem_moves_p)
3383 emit_insn (gen_rtx_SET (VOIDmode,
3384 dest,
3385 gen_rtx_IF_THEN_ELSE (mode,
3386 gen_rtx_NE (CCmode, br_reg,
3387 const0_rtx),
3388 true_value,
3389 false_value)));
3390 else
3391 {
3392 /* Emit conditional stores as two separate stores. This avoids a problem
3393 where you have a conditional store, and one of the arms of the
3394 conditional store is spilled to memory. */
3395 emit_insn (gen_rtx_SET (VOIDmode,
3396 dest,
3397 gen_rtx_IF_THEN_ELSE (mode,
3398 gen_rtx_NE (CCmode, br_reg,
3399 const0_rtx),
3400 true_value,
3401 dest)));
3402
3403 emit_insn (gen_rtx_SET (VOIDmode,
3404 dest,
3405 gen_rtx_IF_THEN_ELSE (mode,
3406 gen_rtx_EQ (CCmode, br_reg,
3407 const0_rtx),
3408 false_value,
3409 dest)));
3410
3411 }
3412
3413 return TRUE;
3414 }
3415
3416
3417 /* In rare cases, correct code generation requires extra machine dependent
3418 processing between the second jump optimization pass and delayed branch
3419 scheduling. On those machines, define this macro as a C statement to act on
3420 the code starting at INSN. */
3421
3422 void
d30v_machine_dependent_reorg(insn)3423 d30v_machine_dependent_reorg (insn)
3424 rtx insn ATTRIBUTE_UNUSED;
3425 {
3426 }
3427
3428
3429 /* A C statement (sans semicolon) to update the integer variable COST based on
3430 the relationship between INSN that is dependent on DEP_INSN through the
3431 dependence LINK. The default is to make no adjustment to COST. This can be
3432 used for example to specify to the scheduler that an output- or
3433 anti-dependence does not incur the same cost as a data-dependence. */
3434
3435 /* For the d30v, try to insure that the source operands for a load/store are
3436 set 2 cycles before the memory reference. */
3437
3438 static int
d30v_adjust_cost(insn,link,dep_insn,cost)3439 d30v_adjust_cost (insn, link, dep_insn, cost)
3440 rtx insn;
3441 rtx link ATTRIBUTE_UNUSED;
3442 rtx dep_insn;
3443 int cost;
3444 {
3445 rtx set_dep = single_set (dep_insn);
3446 rtx set_insn = single_set (insn);
3447
3448 if (set_dep != NULL_RTX && set_insn != NULL_RTX
3449 && GET_CODE (SET_DEST (set_dep)) == REG)
3450 {
3451 rtx reg = SET_DEST (set_dep);
3452 rtx mem;
3453
3454 if ((GET_CODE (mem = SET_SRC (set_insn)) == MEM
3455 && reg_mentioned_p (reg, XEXP (mem, 0)))
3456 || (GET_CODE (mem = SET_DEST (set_insn)) == MEM
3457 && reg_mentioned_p (reg, XEXP (mem, 0))))
3458 {
3459 return cost + 2;
3460 }
3461 }
3462
3463 return cost;
3464 }
3465
3466 /* Function which returns the number of insns that can be
3467 scheduled in the same machine cycle. This must be constant
3468 over an entire compilation. The default is 1. */
3469 static int
d30v_issue_rate()3470 d30v_issue_rate ()
3471 {
3472 return 2;
3473 }
3474
3475
3476 /* Routine to allocate, mark and free a per-function,
3477 machine specific structure. */
3478
3479 static struct machine_function *
d30v_init_machine_status()3480 d30v_init_machine_status ()
3481 {
3482 return ggc_alloc_cleared (sizeof (machine_function));
3483 }
3484
3485 /* Do anything needed before RTL is emitted for each function. */
3486
3487 void
d30v_init_expanders()3488 d30v_init_expanders ()
3489 {
3490 /* Arrange to save and restore machine status around nested functions. */
3491 init_machine_status = d30v_init_machine_status;
3492 }
3493
3494 /* Find the current function's return address.
3495
3496 ??? It would be better to arrange things such that if we would ordinarily
3497 have been a leaf function and we didn't spill the hard reg that we
3498 wouldn't have to save the register in the prolog. But it's not clear
3499 how to get the right information at the right time. */
3500
3501 rtx
d30v_return_addr()3502 d30v_return_addr ()
3503 {
3504 return get_hard_reg_initial_val (Pmode, GPR_LINK);
3505 }
3506