1 /* $OpenBSD: dbdma.h,v 1.5 2021/03/11 11:16:58 jsg Exp $ */ 2 /* $NetBSD: dbdma.h,v 1.2 1998/08/21 16:13:28 tsubai Exp $ */ 3 4 /* 5 * Copyright 1991-1998 by Open Software Foundation, Inc. 6 * All Rights Reserved 7 * 8 * Permission to use, copy, modify, and distribute this software and 9 * its documentation for any purpose and without fee is hereby granted, 10 * provided that the above copyright notice appears in all copies and 11 * that both the copyright notice and this permission notice appear in 12 * supporting documentation. 13 * 14 * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 16 * FOR A PARTICULAR PURPOSE. 17 * 18 * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR 19 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 20 * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, 21 * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 22 * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 23 * 24 */ 25 26 #include <machine/bus.h> 27 #include <machine/pio.h> 28 29 #ifndef _POWERMAC_DBDMA_H_ 30 #define _POWERMAC_DBDMA_H_ 31 32 #define DBDMA_CMD_OUT_MORE 0 33 #define DBDMA_CMD_OUT_LAST 1 34 #define DBDMA_CMD_IN_MORE 2 35 #define DBDMA_CMD_IN_LAST 3 36 #define DBDMA_CMD_STORE_QUAD 4 37 #define DBDMA_CMD_LOAD_QUAD 5 38 #define DBDMA_CMD_NOP 6 39 #define DBDMA_CMD_STOP 7 40 41 /* Keys */ 42 43 #define DBDMA_KEY_STREAM0 0 44 #define DBDMA_KEY_STREAM1 1 45 #define DBDMA_KEY_STREAM2 2 46 #define DBDMA_KEY_STREAM3 3 47 48 /* value 4 is reserved */ 49 #define DBDMA_KEY_REGS 5 50 #define DBDMA_KEY_SYSTEM 6 51 #define DBDMA_KEY_DEVICE 7 52 53 #define DBDMA_INT_NEVER 0 54 #define DBDMA_INT_IF_TRUE 1 55 #define DBDMA_INT_IF_FALSE 2 56 #define DBDMA_INT_ALWAYS 3 57 58 #define DBDMA_BRANCH_NEVER 0 59 #define DBDMA_BRANCH_IF_TRUE 1 60 #define DBDMA_BRANCH_IF_FALSE 2 61 #define DBDMA_BRANCH_ALWAYS 3 62 63 #define DBDMA_WAIT_NEVER 0 64 #define DBDMA_WAIT_IF_TRUE 1 65 #define DBDMA_WAIT_IF_FALSE 2 66 #define DBDMA_WAIT_ALWAYS 3 67 68 69 /* Channels */ 70 71 #define DBDMA_SCSI0 0x0 72 #define DBDMA_CURIO_SCSI DBDMA_SCSI0 73 #define DBDMA_FLOPPY 0x1 74 #define DBDMA_ETHERNET_TX 0x2 75 #define DBDMA_ETHERNET_RV 0x3 76 #define DBDMA_SCC_XMIT_A 0x4 77 #define DBDMA_SCC_RECV_A 0x5 78 #define DBDMA_SCC_XMIT_B 0x6 79 #define DBDMA_SCC_RECV_B 0x7 80 #define DBDMA_AUDIO_OUT 0x8 81 #define DBDMA_AUDIO_IN 0x9 82 #define DBDMA_SCSI1 0xA 83 84 /* Control register values (in little endian) */ 85 86 #define DBDMA_STATUS_MASK 0x000000ff /* Status Mask */ 87 #define DBDMA_CNTRL_BRANCH 0x00000100 88 /* 0x200 reserved */ 89 #define DBDMA_CNTRL_ACTIVE 0x00000400 90 #define DBDMA_CNTRL_DEAD 0x00000800 91 #define DBDMA_CNTRL_WAKE 0x00001000 92 #define DBDMA_CNTRL_FLUSH 0x00002000 93 #define DBDMA_CNTRL_PAUSE 0x00004000 94 #define DBDMA_CNTRL_RUN 0x00008000 95 96 #define DBDMA_SET_CNTRL(x) ( ((x) | (x) << 16) ) 97 #define DBDMA_CLEAR_CNTRL(x) ( (x) << 16) 98 99 #define DBDMA_COUNT_MAX 0x8000 100 101 #define DBDMA_REGMAP(channel) \ 102 (dbdma_regmap_t *)((v_u_char *) POWERMAC_IO(PCI_DMA_BASE_PHYS) \ 103 + (channel << 8)) 104 105 /* This struct is layout in little endian format */ 106 107 struct dbdma_command { 108 u_int16_t d_count; 109 u_int16_t d_command; 110 u_int32_t d_address; 111 u_int32_t d_cmddep; 112 u_int16_t d_resid; 113 u_int16_t d_status; 114 }; 115 116 typedef struct dbdma_command dbdma_command_t; 117 118 #define DBDMA_BUILD_CMD(d, cmd, key, interrupt, wait, branch) { \ 119 dbdma_st16(&(d)->d_command, \ 120 ((cmd) << 12) | ((key) << 8) | \ 121 ((interrupt) << 4) | \ 122 ((branch) << 2) | (wait)); \ 123 } 124 125 #define DBDMA_BUILD(d, cmd, key, count, address, interrupt, wait, branch) { \ 126 dbdma_st16(&(d)->d_count, count); \ 127 dbdma_st32(&(d)->d_address, address); \ 128 (d)->d_resid = 0; \ 129 (d)->d_status = 0; \ 130 (d)->d_cmddep = 0; \ 131 dbdma_st16(&(d)->d_command, \ 132 ((cmd) << 12) | ((key) << 8) | \ 133 ((interrupt) << 4) | \ 134 ((branch) << 2) | (wait)); \ 135 } 136 137 #if 0 138 static __inline__ void 139 dbdma_st32(a, x) 140 volatile u_int32_t *a; 141 u_int32_t x; 142 { 143 __asm__ volatile 144 ("stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory"); 145 __asm__ volatile ("eieio"); 146 } 147 148 static __inline__ void 149 dbdma_st16(a, x) 150 volatile u_int16_t *a; 151 u_int16_t x; 152 { 153 __asm__ volatile 154 ("sthbrx %0,0,%1" : : "r" (x), "r" (a) : "memory"); 155 __asm__ volatile ("eieio"); 156 } 157 158 static __inline__ u_int32_t 159 dbdma_ld32(a) 160 volatile u_int32_t *a; 161 { 162 u_int32_t swap; 163 164 __asm__ volatile ("eieio"); 165 __asm__ volatile 166 ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a)); 167 168 return swap; 169 } 170 171 static __inline__ u_int16_t 172 dbdma_ld16(a) 173 volatile u_int16_t *a; 174 { 175 u_int16_t swap; 176 177 __asm__ volatile ("eieio"); 178 __asm__ volatile 179 ("lhbrx %0,0,%1" : "=r" (swap) : "r" (a)); 180 181 return swap; 182 } 183 184 #define DBDMA_LD4_ENDIAN(a) dbdma_ld32(a) 185 #define DBDMA_ST4_ENDIAN(a, x) dbdma_st32(a, x) 186 #else 187 #define DBDMA_LD4_ENDIAN(a) in32rb(a) 188 #define DBDMA_ST4_ENDIAN(a, x) out32rb(a, x) 189 #define dbdma_st16(a,x) out16rb((a),(x)) 190 #define dbdma_ld16(a) in16rb(a) 191 #define dbdma_st32(a,x) out32rb((a),(x)) 192 #define dbdma_ld32(a) in32rb(a) 193 #endif 194 195 196 /* 197 * DBDMA Channel layout 198 * 199 * NOTE - This structure is in little-endian format. 200 */ 201 202 struct dbdma_regmap { 203 u_int32_t d_control; /* Control Register */ 204 u_int32_t d_status; /* DBDMA Status Register */ 205 u_int32_t d_cmdptrhi; /* MSB of command pointer (not used yet) */ 206 u_int32_t d_cmdptrlo; /* LSB of command pointer */ 207 u_int32_t d_intselect; /* Interrupt Select */ 208 u_int32_t d_branch; /* Branch selection */ 209 u_int32_t d_wait; /* Wait selection */ 210 u_int32_t d_transmode; /* Transfer modes */ 211 u_int32_t d_dataptrhi; /* MSB of Data Pointer */ 212 u_int32_t d_dataptrlo; /* LSB of Data Pointer */ 213 u_int32_t d_reserved; /* Reserved for the moment */ 214 u_int32_t d_branchptrhi; /* MSB of Branch Pointer */ 215 u_int32_t d_branchptrlo; /* LSB of Branch Pointer */ 216 /* The remaining fields are undefined and unimplemented */ 217 }; 218 219 typedef volatile struct dbdma_regmap dbdma_regmap_t; 220 221 /* DBDMA routines */ 222 typedef 223 struct dbdma_desc { 224 bus_dma_tag_t d_dmat; 225 bus_dmamap_t d_map; 226 dbdma_command_t *d_addr; 227 #define d_paddr d_segs->ds_addr 228 bus_dma_segment_t d_segs[1]; 229 int d_nsegs; 230 size_t d_size; 231 } *dbdma_t; 232 233 dbdma_t dbdma_alloc(bus_dma_tag_t, int); /* Allocate command structures */ 234 void dbdma_free(dbdma_t); /* Dispose command structures */ 235 void dbdma_start(dbdma_regmap_t *channel, dbdma_t dt); 236 void dbdma_stop(dbdma_regmap_t *channel); 237 void dbdma_flush(dbdma_regmap_t *channel); 238 void dbdma_reset(dbdma_regmap_t *channel); 239 void dbdma_continue(dbdma_regmap_t *channel); 240 void dbdma_pause(dbdma_regmap_t *channel); 241 242 243 #endif /* !defined(_POWERMAC_DBDMA_H_) */ 244