1 /* $OpenBSD: if_bwfm_pci.h,v 1.9 2022/11/08 18:28:10 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2010-2016 Broadcom Corporation 4 * Copyright (c) 2017 Patrick Wildt <patrick@blueri.se> 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* Registers */ 20 #define BWFM_PCI_BAR0_WINDOW 0x80 21 #define BWFM_PCI_BAR0_REG_SIZE 0x1000 22 23 #define BWFM_PCI_ARMCR4REG_BANKIDX 0x40 24 #define BWFM_PCI_ARMCR4REG_BANKPDA 0x4C 25 26 #define BWFM_PCI_REG_SBMBX 0x98 27 28 #define BWFM_PCI_PCIE2REG_INTMASK 0x24 29 #define BWFM_PCI_PCIE2REG_MAILBOXINT 0x48 30 #define BWFM_PCI_PCIE2REG_MAILBOXMASK 0x4C 31 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_FN0_0 0x0100 32 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_FN0_1 0x0200 33 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 0x10000 34 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 0x20000 35 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 0x40000 36 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 0x80000 37 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 0x100000 38 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 0x200000 39 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 0x400000 40 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1 0x800000 41 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H_DB \ 42 (BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 | \ 43 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 | \ 44 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 | \ 45 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 | \ 46 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 | \ 47 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 | \ 48 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 | \ 49 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1) 50 #define BWFM_PCI_PCIE2REG_CONFIGADDR 0x120 51 #define BWFM_PCI_PCIE2REG_CONFIGDATA 0x124 52 #define BWFM_PCI_PCIE2REG_H2D_MAILBOX_0 0x140 53 #define BWFM_PCI_PCIE2REG_H2D_MAILBOX_1 0x144 54 55 #define BWFM_PCI_64_PCIE2REG_INTMASK 0xC14 56 #define BWFM_PCI_64_PCIE2REG_MAILBOXINT 0xC30 57 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK 0xC34 58 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 1 59 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 2 60 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 4 61 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 8 62 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 0x10 63 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 0x20 64 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 0x40 65 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1 0x80 66 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H4_DB0 0x100 67 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H4_DB1 0x200 68 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H5_DB0 0x400 69 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H5_DB1 0x800 70 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H6_DB0 0x1000 71 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H6_DB1 0x2000 72 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H7_DB0 0x4000 73 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H7_DB1 0x8000 74 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H_DB \ 75 (BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 | \ 76 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 | \ 77 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 | \ 78 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 | \ 79 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 | \ 80 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 | \ 81 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 | \ 82 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1 | \ 83 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H4_DB0 | \ 84 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H4_DB1 | \ 85 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H5_DB0 | \ 86 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H5_DB1 | \ 87 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H6_DB0 | \ 88 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H6_DB1 | \ 89 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H7_DB0 | \ 90 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H7_DB1) 91 #define BWFM_PCI_64_PCIE2REG_H2D_MAILBOX_0 0xA20 92 #define BWFM_PCI_64_PCIE2REG_H2D_MAILBOX_1 0xA24 93 94 #define BWFM_PCI_CFGREG_STATUS_CMD 0x004 95 #define BWFM_PCI_CFGREG_PM_CSR 0x04C 96 #define BWFM_PCI_CFGREG_MSI_CAP 0x058 97 #define BWFM_PCI_CFGREG_MSI_ADDR_L 0x05C 98 #define BWFM_PCI_CFGREG_MSI_ADDR_H 0x060 99 #define BWFM_PCI_CFGREG_MSI_DATA 0x064 100 #define BWFM_PCI_CFGREG_LINK_STATUS_CTRL 0x0BC 101 #define BWFM_PCI_CFGREG_LINK_STATUS_CTRL_ASPM_ENAB 0x3 102 #define BWFM_PCI_CFGREG_LINK_STATUS_CTRL2 0x0DC 103 #define BWFM_PCI_CFGREG_RBAR_CTRL 0x228 104 #define BWFM_PCI_CFGREG_PML1_SUB_CTRL1 0x248 105 #define BWFM_PCI_CFGREG_REG_BAR2_CONFIG 0x4E0 106 #define BWFM_PCI_CFGREG_REG_BAR3_CONFIG 0x4F4 107 108 #define BWFM_RAMSIZE 0x6c 109 #define BWFM_RAMSIZE_MAGIC 0x534d4152 /* SMAR */ 110 111 #define BWFM_SHARED_INFO 0x000 112 #define BWFM_SHARED_INFO_MIN_VERSION 5 113 #define BWFM_SHARED_INFO_MAX_VERSION 7 114 #define BWFM_SHARED_INFO_VERSION_MASK 0x00FF 115 #define BWFM_SHARED_INFO_DMA_INDEX 0x10000 116 #define BWFM_SHARED_INFO_DMA_2B_IDX 0x100000 117 #define BWFM_SHARED_INFO_USE_MAILBOX 0x2000000 118 #define BWFM_SHARED_INFO_TIMESTAMP_DB0 0x8000000 119 #define BWFM_SHARED_INFO_HOSTRDY_DB1 0x10000000 120 #define BWFM_SHARED_INFO_NO_OOB_DW 0x20000000 121 #define BWFM_SHARED_INFO_INBAND_DS 0x40000000 122 #define BWFM_SHARED_INFO_SHARED_DAR 0x80000000 123 #define BWFM_SHARED_CONSOLE_ADDR 0x14 124 #define BWFM_SHARED_MAX_RXBUFPOST 0x22 125 #define BWFM_SHARED_MAX_RXBUFPOST_DEFAULT 255 126 #define BWFM_SHARED_RX_DATAOFFSET 0x24 127 #define BWFM_SHARED_HTOD_MB_DATA_ADDR 0x28 128 #define BWFM_PCI_H2D_HOST_D3_INFORM 0x00000001 129 #define BWFM_PCI_H2D_HOST_DS_ACK 0x00000002 130 #define BWFM_PCI_H2D_HOST_D0_INFORM_IN_USE 0x00000008 131 #define BWFM_PCI_H2D_HOST_D0_INFORM 0x00000010 132 #define BWFM_SHARED_DTOH_MB_DATA_ADDR 0x2c 133 #define BWFM_PCI_D2H_DEV_D3_ACK 0x00000001 134 #define BWFM_PCI_D2H_DEV_DS_ENTER_REQ 0x00000002 135 #define BWFM_PCI_D2H_DEV_DS_EXIT_NOTE 0x00000004 136 #define BWFM_PCI_D2H_DEV_FWHALT 0x10000000 137 #define BWFM_SHARED_RING_INFO_ADDR 0x30 138 #define BWFM_SHARED_DMA_SCRATCH_LEN 0x34 139 #define BWFM_SHARED_DMA_SCRATCH_ADDR_LOW 0x38 140 #define BWFM_SHARED_DMA_SCRATCH_ADDR_HIGH 0x3c 141 #define BWFM_SHARED_DMA_RINGUPD_LEN 0x40 142 #define BWFM_SHARED_DMA_RINGUPD_ADDR_LOW 0x44 143 #define BWFM_SHARED_DMA_RINGUPD_ADDR_HIGH 0x48 144 #define BWFM_SHARED_HOST_CAP 0x54 145 #define BWFM_SHARED_HOST_CAP_H2D_ENABLE_HOSTRDY 0x00000400 146 #define BWFM_SHARED_HOST_CAP_DS_NO_OOB_DW 0x00001000 147 #define BWFM_SHARED_HOST_CAP_H2D_DAR 0x00010000 148 #define BWFM_SHARED_HOST_CAP2 0x70 149 150 #define BWFM_RING_MAX_ITEM 0x04 151 #define BWFM_RING_LEN_ITEMS 0x06 152 #define BWFM_RING_MEM_BASE_ADDR_LOW 0x08 153 #define BWFM_RING_MEM_BASE_ADDR_HIGH 0x0c 154 #define BWFM_RING_MEM_SZ 16 155 156 #define BWFM_CONSOLE_BUFADDR 0x08 157 #define BWFM_CONSOLE_BUFSIZE 0x0c 158 #define BWFM_CONSOLE_WRITEIDX 0x10 159 160 #define BWFM_RANDOM_SEED_MAGIC 0xfeedc0de 161 #define BWFM_RANDOM_SEED_LENGTH 0x100 162 163 struct bwfm_pci_random_seed_footer { 164 uint32_t length; 165 uint32_t magic; 166 }; 167 168 struct bwfm_pci_ringinfo { 169 uint32_t ringmem; 170 uint32_t h2d_w_idx_ptr; 171 uint32_t h2d_r_idx_ptr; 172 uint32_t d2h_w_idx_ptr; 173 uint32_t d2h_r_idx_ptr; 174 uint32_t h2d_w_idx_hostaddr_low; 175 uint32_t h2d_w_idx_hostaddr_high; 176 uint32_t h2d_r_idx_hostaddr_low; 177 uint32_t h2d_r_idx_hostaddr_high; 178 uint32_t d2h_w_idx_hostaddr_low; 179 uint32_t d2h_w_idx_hostaddr_high; 180 uint32_t d2h_r_idx_hostaddr_low; 181 uint32_t d2h_r_idx_hostaddr_high; 182 uint16_t max_flowrings; 183 uint16_t max_submissionrings; 184 uint16_t max_completionrings; 185 }; 186 187 /* Msgbuf defines */ 188 #define MSGBUF_IOCTL_RESP_TIMEOUT 2000 /* msecs */ 189 #define MSGBUF_IOCTL_REQ_PKTID 0xFFFE 190 #define MSGBUF_MAX_PKT_SIZE 2048 191 #define MSGBUF_MAX_CTL_PKT_SIZE 8192 192 193 #define MSGBUF_TYPE_GEN_STATUS 0x1 194 #define MSGBUF_TYPE_RING_STATUS 0x2 195 #define MSGBUF_TYPE_FLOW_RING_CREATE 0x3 196 #define MSGBUF_TYPE_FLOW_RING_CREATE_CMPLT 0x4 197 #define MSGBUF_TYPE_FLOW_RING_DELETE 0x5 198 #define MSGBUF_TYPE_FLOW_RING_DELETE_CMPLT 0x6 199 #define MSGBUF_TYPE_FLOW_RING_FLUSH 0x7 200 #define MSGBUF_TYPE_FLOW_RING_FLUSH_CMPLT 0x8 201 #define MSGBUF_TYPE_IOCTLPTR_REQ 0x9 202 #define MSGBUF_TYPE_IOCTLPTR_REQ_ACK 0xA 203 #define MSGBUF_TYPE_IOCTLRESP_BUF_POST 0xB 204 #define MSGBUF_TYPE_IOCTL_CMPLT 0xC 205 #define MSGBUF_TYPE_EVENT_BUF_POST 0xD 206 #define MSGBUF_TYPE_WL_EVENT 0xE 207 #define MSGBUF_TYPE_TX_POST 0xF 208 #define MSGBUF_TYPE_TX_STATUS 0x10 209 #define MSGBUF_TYPE_RXBUF_POST 0x11 210 #define MSGBUF_TYPE_RX_CMPLT 0x12 211 #define MSGBUF_TYPE_LPBK_DMAXFER 0x13 212 #define MSGBUF_TYPE_LPBK_DMAXFER_CMPLT 0x14 213 #define MSGBUF_TYPE_H2D_MAILBOX_DATA 0x23 214 #define MSGBUF_TYPE_D2H_MAILBOX_DATA 0x24 215 216 struct msgbuf_common_hdr { 217 uint8_t msgtype; 218 uint8_t ifidx; 219 uint8_t flags; 220 uint8_t rsvd0; 221 uint32_t request_id; 222 }; 223 224 struct msgbuf_buf_addr { 225 uint32_t low_addr; 226 uint32_t high_addr; 227 }; 228 229 struct msgbuf_ioctl_req_hdr { 230 struct msgbuf_common_hdr msg; 231 uint32_t cmd; 232 uint16_t trans_id; 233 uint16_t input_buf_len; 234 uint16_t output_buf_len; 235 uint16_t rsvd0[3]; 236 struct msgbuf_buf_addr req_buf_addr; 237 uint32_t rsvd1[2]; 238 }; 239 240 struct msgbuf_tx_msghdr { 241 struct msgbuf_common_hdr msg; 242 uint8_t txhdr[ETHER_HDR_LEN]; 243 uint8_t flags; 244 #define BWFM_MSGBUF_PKT_FLAGS_FRAME_802_3 (1 << 0) 245 #define BWFM_MSGBUF_PKT_FLAGS_PRIO_SHIFT 5 246 uint8_t seg_cnt; 247 struct msgbuf_buf_addr metadata_buf_addr; 248 struct msgbuf_buf_addr data_buf_addr; 249 uint16_t metadata_buf_len; 250 uint16_t data_len; 251 uint32_t rsvd0; 252 }; 253 254 struct msgbuf_rx_bufpost { 255 struct msgbuf_common_hdr msg; 256 uint16_t metadata_buf_len; 257 uint16_t data_buf_len; 258 uint32_t rsvd0; 259 struct msgbuf_buf_addr metadata_buf_addr; 260 struct msgbuf_buf_addr data_buf_addr; 261 }; 262 263 struct msgbuf_rx_ioctl_resp_or_event { 264 struct msgbuf_common_hdr msg; 265 uint16_t host_buf_len; 266 uint16_t rsvd0[3]; 267 struct msgbuf_buf_addr host_buf_addr; 268 uint32_t rsvd1[4]; 269 }; 270 271 struct msgbuf_completion_hdr { 272 uint16_t status; 273 uint16_t flow_ring_id; 274 }; 275 276 struct msgbuf_rx_event { 277 struct msgbuf_common_hdr msg; 278 struct msgbuf_completion_hdr compl_hdr; 279 uint16_t event_data_len; 280 uint16_t seqnum; 281 uint16_t rsvd0[4]; 282 }; 283 284 struct msgbuf_ioctl_resp_hdr { 285 struct msgbuf_common_hdr msg; 286 struct msgbuf_completion_hdr compl_hdr; 287 uint16_t resp_len; 288 uint16_t trans_id; 289 uint32_t cmd; 290 uint32_t rsvd0; 291 }; 292 293 struct msgbuf_tx_status { 294 struct msgbuf_common_hdr msg; 295 struct msgbuf_completion_hdr compl_hdr; 296 uint16_t metadata_len; 297 uint16_t tx_status; 298 }; 299 300 struct msgbuf_rx_complete { 301 struct msgbuf_common_hdr msg; 302 struct msgbuf_completion_hdr compl_hdr; 303 uint16_t metadata_len; 304 uint16_t data_len; 305 uint16_t data_offset; 306 uint16_t flags; 307 uint32_t rx_status_0; 308 uint32_t rx_status_1; 309 uint32_t rsvd0; 310 }; 311 312 struct msgbuf_tx_flowring_create_req { 313 struct msgbuf_common_hdr msg; 314 uint8_t da[ETHER_ADDR_LEN]; 315 uint8_t sa[ETHER_ADDR_LEN]; 316 uint8_t tid; 317 uint8_t if_flags; 318 uint16_t flow_ring_id; 319 uint8_t tc; 320 uint8_t priority; 321 uint16_t int_vector; 322 uint16_t max_items; 323 uint16_t len_item; 324 struct msgbuf_buf_addr flow_ring_addr; 325 }; 326 327 struct msgbuf_tx_flowring_delete_req { 328 struct msgbuf_common_hdr msg; 329 uint16_t flow_ring_id; 330 uint16_t reason; 331 uint32_t rsvd0[7]; 332 }; 333 334 struct msgbuf_flowring_create_resp { 335 struct msgbuf_common_hdr msg; 336 struct msgbuf_completion_hdr compl_hdr; 337 uint32_t rsvd0[3]; 338 }; 339 340 struct msgbuf_flowring_delete_resp { 341 struct msgbuf_common_hdr msg; 342 struct msgbuf_completion_hdr compl_hdr; 343 uint32_t rsvd0[3]; 344 }; 345 346 struct msgbuf_flowring_flush_resp { 347 struct msgbuf_common_hdr msg; 348 struct msgbuf_completion_hdr compl_hdr; 349 uint32_t rsvd0[3]; 350 }; 351 352 struct msgbuf_h2d_mailbox_data { 353 struct msgbuf_common_hdr msg; 354 uint32_t data; 355 uint32_t rsvd0[7]; 356 }; 357 358 struct msgbuf_d2h_mailbox_data { 359 struct msgbuf_common_hdr msg; 360 struct msgbuf_completion_hdr compl_hdr; 361 uint32_t data; 362 uint32_t rsvd0[2]; 363 }; 364