1 /* $NetBSD: dbri.c,v 1.45 2021/02/06 13:02:28 isaki Exp $ */
2
3 /*
4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
5 * Copyright (c) 1998, 1999 Brent Baccala (baccala@freesoft.org)
6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill@netbsd.org>
7 * Copyright (c) 2005 Michael Lorenz <macallan@netbsd.org>
8 * All rights reserved.
9 *
10 * This driver is losely based on a Linux driver written by Rudolf Koenig and
11 * Brent Baccala who kindly gave their permission to use their code in a
12 * BSD-licensed driver.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.45 2021/02/06 13:02:28 isaki Exp $");
38
39 #include "audio.h"
40 #if NAUDIO > 0
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/errno.h>
45 #include <sys/device.h>
46 #include <sys/proc.h>
47 #include <sys/kernel.h>
48 #include <sys/bus.h>
49 #include <sys/intr.h>
50 #include <sys/kmem.h>
51
52 #include <dev/sbus/sbusvar.h>
53 #include <sparc/sparc/auxreg.h>
54 #include <machine/autoconf.h>
55
56 #include <sys/audioio.h>
57 #include <dev/audio/audio_if.h>
58
59 #include <dev/ic/cs4215reg.h>
60 #include <dev/ic/cs4215var.h>
61 #include <dev/sbus/dbrireg.h>
62 #include <dev/sbus/dbrivar.h>
63
64 #include "opt_sbus_dbri.h"
65
66 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI"
67
68 #ifdef DBRI_DEBUG
69 # define DPRINTF aprint_normal
70 #else
71 # define DPRINTF while (0) printf
72 #endif
73
74 static const char *dbri_supported[] = {
75 "e",
76 "s3",
77 ""
78 };
79
80 enum ms {
81 CHImaster,
82 CHIslave
83 };
84
85 enum io {
86 PIPEinput,
87 PIPEoutput
88 };
89
90 /*
91 * Function prototypes
92 */
93
94 /* softc stuff */
95 static void dbri_attach_sbus(device_t, device_t, void *);
96 static int dbri_match_sbus(device_t, cfdata_t, void *);
97
98 static int dbri_config_interrupts(device_t);
99
100 /* interrupt handler */
101 static int dbri_intr(void *);
102 static void dbri_softint(void *);
103
104 /* supporting subroutines */
105 static int dbri_init(struct dbri_softc *);
106 static int dbri_reset(struct dbri_softc *);
107 static volatile uint32_t *dbri_command_lock(struct dbri_softc *);
108 static void dbri_command_send(struct dbri_softc *, volatile uint32_t *);
109 static void dbri_process_interrupt_buffer(struct dbri_softc *);
110 static void dbri_process_interrupt(struct dbri_softc *, int32_t);
111
112 /* mmcodec subroutines */
113 static int mmcodec_init(struct dbri_softc *);
114 static void mmcodec_init_data(struct dbri_softc *);
115 static void mmcodec_pipe_init(struct dbri_softc *);
116 static void mmcodec_default(struct dbri_softc *);
117 static void mmcodec_setgain(struct dbri_softc *, int);
118 static int mmcodec_setcontrol(struct dbri_softc *);
119
120 /* chi subroutines */
121 static void chi_reset(struct dbri_softc *, enum ms, int);
122
123 /* pipe subroutines */
124 static void pipe_setup(struct dbri_softc *, int, int);
125 static void pipe_reset(struct dbri_softc *, int);
126 static void pipe_receive_fixed(struct dbri_softc *, int,
127 volatile uint32_t *);
128 static void pipe_transmit_fixed(struct dbri_softc *, int, uint32_t);
129
130 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int);
131 static int pipe_active(struct dbri_softc *, int);
132
133 /* audio(9) stuff */
134 static int dbri_query_format(void *, audio_format_query_t *);
135 static int dbri_set_format(void *, int,
136 const audio_params_t *, const audio_params_t *,
137 audio_filter_reg_t *, audio_filter_reg_t *);
138 static int dbri_round_blocksize(void *, int, int, const audio_params_t *);
139 static int dbri_halt_output(void *);
140 static int dbri_halt_input(void *);
141 static int dbri_getdev(void *, struct audio_device *);
142 static int dbri_set_port(void *, mixer_ctrl_t *);
143 static int dbri_get_port(void *, mixer_ctrl_t *);
144 static int dbri_query_devinfo(void *, mixer_devinfo_t *);
145 static int dbri_get_props(void *);
146 static int dbri_open(void *, int);
147 static void dbri_close(void *);
148
149 static void setup_ring_xmit(struct dbri_softc *, int, int, int, int,
150 void (*)(void *), void *);
151 static void setup_ring_recv(struct dbri_softc *, int, int, int, int,
152 void (*)(void *), void *);
153
154 static int dbri_trigger_output(void *, void *, void *, int,
155 void (*)(void *), void *, const struct audio_params *);
156 static int dbri_trigger_input(void *, void *, void *, int,
157 void (*)(void *), void *, const struct audio_params *);
158 static void dbri_get_locks(void *, kmutex_t **, kmutex_t **);
159
160 static void *dbri_malloc(void *, int, size_t);
161 static void dbri_free(void *, void *, size_t);
162 static void dbri_set_power(struct dbri_softc *, int);
163 static void dbri_bring_up(struct dbri_softc *);
164 static bool dbri_suspend(device_t, const pmf_qual_t *);
165 static bool dbri_resume(device_t, const pmf_qual_t *);
166 static int dbri_commit(void *);
167
168 /* stupid support routines */
169 static uint32_t reverse_bytes(uint32_t, int);
170
171 struct audio_device dbri_device = {
172 "CS4215",
173 "",
174 "dbri"
175 };
176
177 struct audio_hw_if dbri_hw_if = {
178 .open = dbri_open,
179 .close = dbri_close,
180 .query_format = dbri_query_format,
181 .set_format = dbri_set_format,
182 .round_blocksize = dbri_round_blocksize,
183 .halt_output = dbri_halt_output,
184 .halt_input = dbri_halt_input,
185 .getdev = dbri_getdev,
186 .set_port = dbri_set_port,
187 .get_port = dbri_get_port,
188 .query_devinfo = dbri_query_devinfo,
189 .allocm = dbri_malloc,
190 .freem = dbri_free,
191 .get_props = dbri_get_props,
192 .trigger_output = dbri_trigger_output,
193 .trigger_input = dbri_trigger_input,
194 .get_locks = dbri_get_locks,
195 .commit_settings = dbri_commit,
196 };
197
198 CFATTACH_DECL_NEW(dbri, sizeof(struct dbri_softc),
199 dbri_match_sbus, dbri_attach_sbus, NULL, NULL);
200
201 /* The HW actually supports more encodings/frequencies, but it's enough. */
202 static const struct audio_format dbri_formats[] = {
203 {
204 .mode = AUMODE_PLAY | AUMODE_RECORD,
205 .encoding = AUDIO_ENCODING_SLINEAR_BE,
206 .validbits = 16,
207 .precision = 16,
208 .channels = 2,
209 .channel_mask = AUFMT_STEREO,
210 .frequency_type = 8,
211 .frequency =
212 { 8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000 },
213 },
214 };
215 #define DBRI_NFORMATS __arraycount(dbri_formats)
216
217 enum {
218 DBRI_OUTPUT_CLASS,
219 DBRI_VOL_OUTPUT,
220 DBRI_ENABLE_MONO,
221 DBRI_ENABLE_HEADPHONE,
222 DBRI_ENABLE_LINE,
223 DBRI_MONITOR_CLASS,
224 DBRI_VOL_MONITOR,
225 DBRI_INPUT_CLASS,
226 DBRI_INPUT_GAIN,
227 DBRI_INPUT_SELECT,
228 DBRI_RECORD_CLASS,
229 DBRI_ENUM_LAST
230 };
231
232 /*
233 * Autoconfig routines
234 */
235 static int
dbri_match_sbus(device_t parent,cfdata_t match,void * aux)236 dbri_match_sbus(device_t parent, cfdata_t match, void *aux)
237 {
238 struct sbus_attach_args *sa = aux;
239 char *ver;
240 int i;
241
242 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9))
243 return (0);
244
245 ver = &sa->sa_name[9];
246
247 for (i = 0; dbri_supported[i][0] != '\0'; i++)
248 if (strcmp(dbri_supported[i], ver) == 0)
249 return (1);
250
251 return (0);
252 }
253
254 static void
dbri_attach_sbus(device_t parent,device_t self,void * aux)255 dbri_attach_sbus(device_t parent, device_t self, void *aux)
256 {
257 struct dbri_softc *sc = device_private(self);
258 struct sbus_attach_args *sa = aux;
259 bus_space_handle_t ioh;
260 bus_size_t size;
261 int error, rseg, pwr, i;
262 char *ver = &sa->sa_name[9];
263
264 sc->sc_dev = self;
265 sc->sc_iot = sa->sa_bustag;
266 sc->sc_dmat = sa->sa_dmatag;
267 sc->sc_powerstate = 1;
268
269 sc->sc_whack_codec = 0;
270
271 pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0);
272 aprint_normal(": rev %s\n", ver);
273
274 if (pwr) {
275 /*
276 * we can control DBRI power via auxio and we're initially
277 * powered down
278 */
279
280 sc->sc_have_powerctl = 1;
281 sc->sc_powerstate = 0;
282 dbri_set_power(sc, 1);
283 if (!pmf_device_register(self, dbri_suspend, dbri_resume)) {
284 aprint_error_dev(self,
285 "cannot set power mgmt handler\n");
286 }
287 } else {
288 /* we can't control power so we're always up */
289 sc->sc_have_powerctl = 0;
290 sc->sc_powerstate = 1;
291 }
292
293 for (i = 0; i < DBRI_NUM_DESCRIPTORS; i++) {
294 sc->sc_desc[i].softint = softint_establish(SOFTINT_SERIAL,
295 dbri_softint, &sc->sc_desc[i]);
296 sc->sc_desc[i].sc = sc;
297 }
298
299 if (sa->sa_npromvaddrs)
300 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0];
301 else {
302 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot,
303 sa->sa_offset, sa->sa_size,
304 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) {
305 aprint_error("%s @ sbus: cannot map registers\n",
306 device_xname(self));
307 return;
308 }
309 }
310
311 sc->sc_ioh = ioh;
312
313 size = sizeof(struct dbri_dma);
314
315 /* get a DMA handle */
316 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
317 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
318 aprint_error_dev(self, "DMA map create error %d\n",
319 error);
320 return;
321 }
322
323 /* allocate DMA buffer */
324 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg,
325 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
326 aprint_error_dev(self, "DMA buffer alloc error %d\n",
327 error);
328 return;
329 }
330
331 /* map DMA buffer into CPU addressable space */
332 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size,
333 &sc->sc_membase,
334 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
335 aprint_error_dev(self, "DMA buffer map error %d\n",
336 error);
337 return;
338 }
339
340 /* load the buffer */
341 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap,
342 sc->sc_membase, size, NULL,
343 BUS_DMA_NOWAIT)) != 0) {
344 aprint_error_dev(self, "DMA buffer map load error %d\n",
345 error);
346 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size);
347 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg);
348 return;
349 }
350
351 /* map the registers into memory */
352
353 /* kernel virtual address of DMA buffer */
354 sc->sc_dma = (struct dbri_dma *)sc->sc_membase;
355 /* physical address of DMA buffer */
356 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr;
357 sc->sc_bufsiz = size;
358
359 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
360 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO);
361
362 #ifndef DBRI_SPIN
363 cv_init(&sc->sc_cv, "dbricv");
364 #endif
365
366 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_AUDIO, dbri_intr,
367 sc);
368
369 sc->sc_locked = 0;
370 sc->sc_desc_used = 0;
371 sc->sc_playing = 0;
372 sc->sc_recording = 0;
373 sc->sc_init_done = 0;
374 config_finalize_register(self, dbri_config_interrupts);
375
376 return;
377 }
378
379 /*
380 * lowlevel routine to switch power for the DBRI chip
381 */
382 static void
dbri_set_power(struct dbri_softc * sc,int state)383 dbri_set_power(struct dbri_softc *sc, int state)
384 {
385 int s;
386
387 if (sc->sc_have_powerctl == 0)
388 return;
389 if (sc->sc_powerstate == state)
390 return;
391
392 if (state) {
393 DPRINTF("%s: waiting to power up... ",
394 device_xname(sc->sc_dev));
395 s = splhigh();
396 *AUXIO4M_REG |= (AUXIO4M_MMX);
397 splx(s);
398 delay(10000);
399 DPRINTF("done (%02x)\n", *AUXIO4M_REG);
400 } else {
401 DPRINTF("%s: powering down\n", device_xname(sc->sc_dev));
402 s = splhigh();
403 *AUXIO4M_REG &= ~AUXIO4M_MMX;
404 splx(s);
405 DPRINTF("done (%02x})\n", *AUXIO4M_REG);
406 }
407 sc->sc_powerstate = state;
408 }
409
410 /*
411 * power up and re-initialize the chip
412 */
413 static void
dbri_bring_up(struct dbri_softc * sc)414 dbri_bring_up(struct dbri_softc *sc)
415 {
416
417 if (sc->sc_have_powerctl == 0)
418 return;
419
420 if (sc->sc_powerstate == 1)
421 return;
422
423 /* ok, we really need to do something */
424 dbri_set_power(sc, 1);
425
426 /*
427 * re-initialize the chip but skip all the probing, don't overwrite
428 * any other settings either
429 */
430 dbri_init(sc);
431 mmcodec_setgain(sc, 1);
432 mmcodec_pipe_init(sc);
433 mmcodec_init_data(sc);
434 mmcodec_setgain(sc, 0);
435 }
436
437 static int
dbri_config_interrupts(device_t dev)438 dbri_config_interrupts(device_t dev)
439 {
440 struct dbri_softc *sc = device_private(dev);
441
442 mutex_spin_enter(&sc->sc_intr_lock);
443 if (sc->sc_init_done != 0) {
444 mutex_spin_exit(&sc->sc_intr_lock);
445 return 0;
446 }
447 sc->sc_init_done = 1;
448
449 dbri_init(sc);
450
451 /* talking to the codec needs working interrupts */
452 if (mmcodec_init(sc) == -1) {
453 mutex_spin_exit(&sc->sc_intr_lock);
454 printf("%s: no codec detected, aborting\n",
455 device_xname(dev));
456 return 0;
457 }
458 mutex_spin_exit(&sc->sc_intr_lock);
459
460 /* Attach ourselves to the high level audio interface */
461 audio_attach_mi(&dbri_hw_if, sc, sc->sc_dev);
462
463 /* power down until open() */
464 mutex_spin_enter(&sc->sc_intr_lock);
465 dbri_set_power(sc, 0);
466 mutex_spin_exit(&sc->sc_intr_lock);
467
468 return 0;
469 }
470
471 static int
dbri_intr(void * hdl)472 dbri_intr(void *hdl)
473 {
474 struct dbri_softc *sc = hdl;
475 bus_space_tag_t iot = sc->sc_iot;
476 bus_space_handle_t ioh = sc->sc_ioh;
477 int x;
478
479 mutex_spin_enter(&sc->sc_intr_lock);
480
481 /* clear interrupt */
482 x = bus_space_read_4(iot, ioh, DBRI_REG1);
483 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) {
484 uint32_t tmp;
485
486 if (x & DBRI_MRR)
487 aprint_debug_dev(sc->sc_dev,
488 "multiple ack error on sbus\n");
489 if (x & DBRI_MLE)
490 aprint_debug_dev(sc->sc_dev,
491 "multiple late error on sbus\n");
492 if (x & DBRI_LBG)
493 aprint_debug_dev(sc->sc_dev,
494 "lost bus grant on sbus\n");
495 if (x & DBRI_MBE)
496 aprint_debug_dev(sc->sc_dev, "burst error on sbus\n");
497
498 /*
499 * Some of these errors disable the chip's circuitry.
500 * Re-enable the circuitry and keep on going.
501 */
502
503 tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
504 tmp &= ~(DBRI_DISABLE_MASTER);
505 bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
506 }
507
508 #if 0
509 if (!x & 1) /* XXX: DBRI_INTR_REQ */
510 return (1);
511 #endif
512
513 dbri_process_interrupt_buffer(sc);
514
515 mutex_spin_exit(&sc->sc_intr_lock);
516
517 return (1);
518 }
519
520 static void
dbri_softint(void * cookie)521 dbri_softint(void *cookie)
522 {
523 struct dbri_desc *dd = cookie;
524 struct dbri_softc *sc = dd->sc;
525
526 mutex_spin_enter(&sc->sc_intr_lock);
527 if (dd->callback != NULL)
528 dd->callback(dd->callback_args);
529 mutex_spin_exit(&sc->sc_intr_lock);
530 }
531
532 static int
dbri_init(struct dbri_softc * sc)533 dbri_init(struct dbri_softc *sc)
534 {
535 bus_space_tag_t iot = sc->sc_iot;
536 bus_space_handle_t ioh = sc->sc_ioh;
537 uint32_t reg;
538 volatile uint32_t *cmd;
539 bus_addr_t dmaaddr;
540 int n;
541
542 KASSERT(mutex_owned(&sc->sc_intr_lock));
543
544 dbri_reset(sc);
545 sc->sc_mm.status = 0;
546
547 cmd = dbri_command_lock(sc);
548
549 /* XXX: Initialize interrupt ring buffer */
550 sc->sc_dma->intr[0] = (uint32_t)sc->sc_dmabase + dbri_dma_off(intr, 0);
551 sc->sc_irqp = 1;
552
553 /* Initialize pipes */
554 for (n = 0; n < DBRI_PIPE_MAX; n++)
555 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1;
556
557 for (n = 1; n < DBRI_INT_BLOCKS; n++) {
558 sc->sc_dma->intr[n] = 0;
559 }
560
561 /* XXX 16 byte bursts cause errors, the rest works */
562 reg = bus_space_read_4(iot, ioh, DBRI_REG0);
563
564 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/
565 reg |= (DBRI_BURST_4 | DBRI_BURST_8);
566 bus_space_write_4(iot, ioh, DBRI_REG0, reg);
567
568 /* setup interrupt queue */
569 dmaaddr = (uint32_t)sc->sc_dmabase + dbri_dma_off(intr, 0);
570 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0);
571 *(cmd++) = dmaaddr;
572
573 dbri_command_send(sc, cmd);
574
575 return (0);
576 }
577
578 static int
dbri_reset(struct dbri_softc * sc)579 dbri_reset(struct dbri_softc *sc)
580 {
581 int bail = 0;
582
583 bus_space_tag_t iot = sc->sc_iot;
584 bus_space_handle_t ioh = sc->sc_ioh;
585
586 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET);
587 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) &&
588 (bail < 100000)) {
589 bail++;
590 delay(10);
591 }
592 if (bail == 100000)
593 aprint_error_dev(sc->sc_dev, "reset timed out\n");
594 return (0);
595 }
596
597 static volatile uint32_t *
dbri_command_lock(struct dbri_softc * sc)598 dbri_command_lock(struct dbri_softc *sc)
599 {
600
601 if (sc->sc_locked)
602 aprint_debug_dev(sc->sc_dev, "command buffer locked\n");
603
604 sc->sc_locked++;
605
606 return (&sc->sc_dma->command[0]);
607 }
608
609 static void
dbri_command_send(struct dbri_softc * sc,volatile uint32_t * cmd)610 dbri_command_send(struct dbri_softc *sc, volatile uint32_t *cmd)
611 {
612 bus_space_handle_t ioh = sc->sc_ioh;
613 bus_space_tag_t iot = sc->sc_iot;
614 int maxloops = 1000000;
615
616 KASSERT(mutex_owned(&sc->sc_intr_lock));
617
618 sc->sc_locked--;
619
620 if (sc->sc_locked != 0) {
621 aprint_error_dev(sc->sc_dev,
622 "command buffer improperly locked\n");
623 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) {
624 aprint_error_dev(sc->sc_dev, "command buffer overflow\n");
625 } else {
626 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0);
627 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0);
628 sc->sc_waitseen = 0;
629 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase);
630 while ((--maxloops) > 0 &&
631 (bus_space_read_4(iot, ioh, DBRI_REG0)
632 & DBRI_COMMAND_VALID)) {
633 bus_space_barrier(iot, ioh, DBRI_REG0, 4,
634 BUS_SPACE_BARRIER_READ);
635 delay(1000);
636 }
637
638 if (maxloops == 0) {
639 aprint_error_dev(sc->sc_dev,
640 "chip never completed command buffer\n");
641 } else {
642
643 DPRINTF("%s: command completed\n",
644 device_xname(sc->sc_dev));
645
646 while ((--maxloops) > 0 && (!sc->sc_waitseen))
647 dbri_process_interrupt_buffer(sc);
648 if (maxloops == 0) {
649 aprint_error_dev(sc->sc_dev, "chip never acked WAIT\n");
650 }
651 }
652 }
653
654 return;
655 }
656
657 static void
dbri_process_interrupt_buffer(struct dbri_softc * sc)658 dbri_process_interrupt_buffer(struct dbri_softc *sc)
659 {
660 int32_t i;
661 int orig_irqp = sc->sc_irqp;
662
663 KASSERT(mutex_owned(&sc->sc_intr_lock));
664
665 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) {
666 sc->sc_dma->intr[sc->sc_irqp] = 0;
667 sc->sc_irqp++;
668
669 if (sc->sc_irqp == DBRI_INT_BLOCKS)
670 sc->sc_irqp = 1;
671 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0)
672 sc->sc_irqp++;
673
674 dbri_process_interrupt(sc, i);
675
676 /* don't loop more than once. */
677 if (orig_irqp == sc->sc_irqp)
678 break;
679 }
680
681 return;
682 }
683
684 static void
dbri_process_interrupt(struct dbri_softc * sc,int32_t i)685 dbri_process_interrupt(struct dbri_softc *sc, int32_t i)
686 {
687 #if 0
688 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 };
689 #endif
690 int val = DBRI_INTR_GETVAL(i);
691 int channel = DBRI_INTR_GETCHAN(i);
692 int command = DBRI_INTR_GETCMD(i);
693 int code = DBRI_INTR_GETCODE(i);
694 #if 0
695 int rval = DBRI_INTR_GETRVAL(i);
696 #endif
697 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT)
698 sc->sc_waitseen++;
699
700 switch (code) {
701 case DBRI_INTR_XCMP: /* transmission complete */
702 {
703 int td;
704 struct dbri_desc *dd;
705
706 DPRINTF("%s:%d tx complete\n", __func__, channel);
707 td = sc->sc_pipe[channel].desc;
708 dd = &sc->sc_desc[td];
709
710 if (dd->callback != NULL)
711 softint_schedule(dd->softint);
712 break;
713 }
714 case DBRI_INTR_FXDT: /* fixed data change */
715 DPRINTF("%s:%d: Fixed data change: %x\n", __func__, channel,
716 val);
717 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB)
718 val = reverse_bytes(val, sc->sc_pipe[channel].length);
719 if (sc->sc_pipe[channel].prec)
720 *(sc->sc_pipe[channel].prec) = val;
721 #ifndef DBRI_SPIN
722 DPRINTF("%s: cv_broadcast %p\n", device_xname(sc->sc_dev), sc);
723 cv_broadcast(&sc->sc_cv);
724 #endif
725 break;
726 case DBRI_INTR_SBRI:
727 DPRINTF("dbri_intr: SBRI\n");
728 break;
729 case DBRI_INTR_BRDY:
730 {
731 int td;
732 struct dbri_desc *dd;
733
734 DPRINTF("dbri_intr: buffer ready (%d)\n", channel);
735 td = sc->sc_pipe[channel].desc;
736 dd = &sc->sc_desc[td];
737
738 if (dd->callback != NULL)
739 softint_schedule(dd->softint);
740 break;
741 }
742 case DBRI_INTR_UNDR:
743 {
744 volatile uint32_t *cmd;
745 int td = sc->sc_pipe[channel].desc;
746
747 DPRINTF("%s: DBRI_INTR_UNDR\n", device_xname(sc->sc_dev));
748
749 sc->sc_dma->xmit[td].status = 0;
750
751 cmd = dbri_command_lock(sc);
752 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0,
753 sc->sc_pipe[channel].sdp |
754 DBRI_SDP_VALID_POINTER |
755 DBRI_SDP_CLEAR |
756 DBRI_SDP_2SAME);
757 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, td);
758 dbri_command_send(sc, cmd);
759 break;
760 }
761 case DBRI_INTR_CMDI:
762 DPRINTF("ok");
763 break;
764 default:
765
766 aprint_error_dev(sc->sc_dev, "unknown interrupt code %d\n",
767 code);
768 break;
769 }
770
771 return;
772 }
773
774 /*
775 * mmcodec stuff
776 */
777
778 static int
mmcodec_init(struct dbri_softc * sc)779 mmcodec_init(struct dbri_softc *sc)
780 {
781 bus_space_handle_t ioh = sc->sc_ioh;
782 bus_space_tag_t iot = sc->sc_iot;
783 uint32_t reg2;
784 int bail;
785
786 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2);
787 DPRINTF("mmcodec_init: PIO reads %x\n", reg2);
788
789 if (reg2 & DBRI_PIO2) {
790 aprint_normal_dev(sc->sc_dev, " onboard CS4215 detected\n");
791 sc->sc_mm.onboard = 1;
792 }
793
794 if (reg2 & DBRI_PIO0) {
795 aprint_normal_dev(sc->sc_dev, "speakerbox detected\n");
796 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE);
797 sc->sc_mm.onboard = 0;
798 }
799
800 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) {
801 aprint_normal_dev(sc->sc_dev, "using speakerbox\n");
802 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE);
803 sc->sc_mm.onboard = 0;
804 }
805
806 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) {
807 aprint_normal_dev(sc->sc_dev, "no mmcodec found\n");
808 return -1;
809 }
810
811 sc->sc_version = 0xff;
812
813 mmcodec_pipe_init(sc);
814 mmcodec_default(sc);
815
816 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8;
817
818 /*
819 * mmcodec_setcontrol() sometimes fails right after powerup
820 * so we just try again until we either get a useful response or run
821 * out of time
822 */
823 bail = 0;
824 while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) {
825
826 bail++;
827 if (bail > 100) {
828 DPRINTF("%s: cs4215 probe failed at offset %d\n",
829 device_xname(sc->sc_dev), sc->sc_mm.offset);
830 return (-1);
831 }
832 delay(10000);
833 }
834
835 aprint_normal_dev(sc->sc_dev, "cs4215 rev %c found at offset %d\n",
836 0x43 + (sc->sc_version & 0xf), sc->sc_mm.offset);
837
838 /* set some sane defaults for mmcodec_init_data */
839 sc->sc_params.channels = 2;
840 sc->sc_params.precision = 16;
841
842 mmcodec_init_data(sc);
843
844 return (0);
845 }
846
847 static void
mmcodec_init_data(struct dbri_softc * sc)848 mmcodec_init_data(struct dbri_softc *sc)
849 {
850 bus_space_tag_t iot = sc->sc_iot;
851 bus_space_handle_t ioh = sc->sc_ioh;
852 uint32_t tmp;
853 int data_width;
854
855 tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
856 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */
857 bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
858
859 /* switch CS4215 to data mode - set PIO3 to 1 */
860 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3;
861
862 /* XXX */
863 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2);
864
865 bus_space_write_4(iot, ioh, DBRI_REG2, tmp);
866 chi_reset(sc, CHIslave, 128);
867
868 data_width = sc->sc_params.channels * sc->sc_params.precision;
869
870 if ((data_width != 32) && (data_width != 8))
871 aprint_error("%s: data_width is %d\n", __func__, data_width);
872
873 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32);
874 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset);
875 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset);
876 #if 0
877 /* readback for the mixer registers - we don't use that */
878 pipe_ts_link(sc, 21, PIPEinput, 16, 32, sc->sc_mm.offset + 32);
879
880 pipe_receive_fixed(sc, 21, &sc->sc_mm.d.ldata);
881 #endif
882 mmcodec_setgain(sc, 0);
883
884 tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
885 tmp |= DBRI_CHI_ACTIVATE;
886 bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
887
888 return;
889 }
890
891 static void
mmcodec_pipe_init(struct dbri_softc * sc)892 mmcodec_pipe_init(struct dbri_softc *sc)
893 {
894
895 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB);
896 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB);
897 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
898 #if 0
899 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
900 #endif
901 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB);
902 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
903 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
904
905 pipe_receive_fixed(sc, 18, &sc->sc_mm.status);
906 pipe_receive_fixed(sc, 19, &sc->sc_mm.version);
907
908 return;
909 }
910
911 static void
mmcodec_default(struct dbri_softc * sc)912 mmcodec_default(struct dbri_softc *sc)
913 {
914 struct cs4215_state *mm = &sc->sc_mm;
915
916 /*
917 * no action, memory resetting only
918 *
919 * data time slots 5-8
920 * speaker, line and headphone enable. set gain to half.
921 * input is line
922 */
923 mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE;
924 mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE;
925 sc->sc_linp = 128;
926 sc->sc_rinp = 128;
927 sc->sc_monitor = 0;
928 sc->sc_input = 1; /* line */
929 mm->d.bdata[2] = (CS4215_LG((sc->sc_linp >> 4)) & 0x0f) |
930 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1;
931 mm->d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4) & 0x0f)) |
932 CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f));
933
934
935 /*
936 * control time slots 1-4
937 *
938 * 0: default I/O voltage scale
939 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
940 * 2: serial enable, CHI master, 128 bits per frame, clock 1
941 * 3: tests disabled
942 */
943 mm->c.bcontrol[0] = CS4215_ONE | CS4215_MLB;
944 mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
945 mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
946 mm->c.bcontrol[3] = 0;
947
948 return;
949 }
950
951 static void
mmcodec_setgain(struct dbri_softc * sc,int mute)952 mmcodec_setgain(struct dbri_softc *sc, int mute)
953 {
954 if (mute) {
955 /* disable all outputs, max. attenuation */
956 sc->sc_mm.d.bdata[0] = sc->sc_latt | 63;
957 sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63;
958 } else {
959
960 sc->sc_mm.d.bdata[0] = sc->sc_latt;
961 sc->sc_mm.d.bdata[1] = sc->sc_ratt;
962 }
963
964 /* input stuff */
965 sc->sc_mm.d.bdata[2] = CS4215_LG((sc->sc_linp >> 4) & 0x0f) |
966 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1;
967 sc->sc_mm.d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4)) & 0x0f) |
968 (CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f)));
969
970 if (sc->sc_powerstate == 0)
971 return;
972 pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata);
973
974 DPRINTF("mmcodec_setgain: %08x\n", sc->sc_mm.d.ldata);
975 /* give the chip some time to execute the command */
976 delay(250);
977
978 return;
979 }
980
981 static int
mmcodec_setcontrol(struct dbri_softc * sc)982 mmcodec_setcontrol(struct dbri_softc *sc)
983 {
984 bus_space_tag_t iot = sc->sc_iot;
985 bus_space_handle_t ioh = sc->sc_ioh;
986 uint32_t val;
987 uint32_t tmp;
988 int ret = 0;
989 #ifdef DBRI_SPIN
990 int i;
991 #else
992 int error, bail = 0;
993 #endif
994
995 KASSERT(mutex_owned(&sc->sc_intr_lock));
996
997 /*
998 * Temporarily mute outputs and wait 125 us to make sure that it
999 * happens. This avoids clicking noises.
1000 */
1001 mmcodec_setgain(sc, 1);
1002 delay(125);
1003
1004 tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
1005 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */
1006 bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
1007
1008 bus_space_write_4(iot, ioh, DBRI_REG2, 0);
1009 delay(125);
1010
1011 /* enable control mode */
1012 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */
1013
1014 /* XXX */
1015 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2);
1016
1017 bus_space_write_4(iot, ioh, DBRI_REG2, val);
1018 delay(34);
1019
1020 /*
1021 * in control mode, the cs4215 is the slave device, so the
1022 * DBRI must act as the CHI master.
1023 *
1024 * in data mode, the cs4215 must be the CHI master to insure
1025 * that the data stream is in sync with its codec
1026 */
1027 tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
1028 tmp &= ~DBRI_COMMAND_CHI;
1029 bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
1030
1031 chi_reset(sc, CHImaster, 128);
1032
1033 /* control mode */
1034 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset);
1035 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset);
1036 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48);
1037
1038 pipe_receive_fixed(sc, 18, &sc->sc_mm.status);
1039
1040 /* wait for the chip to echo back CLB as zero */
1041 sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB;
1042 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol);
1043
1044 tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
1045 tmp |= DBRI_CHI_ACTIVATE;
1046 bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
1047
1048 #ifdef DBRI_SPIN
1049 i = 1024;
1050 while (((sc->sc_mm.status & 0xe4) != CS4215_ONE) && (i > 0)) {
1051 i--;
1052 delay(125);
1053 }
1054
1055 if (i == 0) {
1056 DPRINTF("%s: cs4215 didn't respond to CLB (0x%02x)\n",
1057 device_xname(sc->sc_dev), sc->sc_mm.status);
1058 ret = -1;
1059 goto fail;
1060 }
1061 #else
1062 while (((sc->sc_mm.status & 0xe4) != CS4215_ONE) && (bail < 10)) {
1063 DPRINTF("%s: cv_wait_sig %p\n", device_xname(sc->sc_dev), sc);
1064 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_intr_lock, hz);
1065 if (error == EINTR) {
1066 DPRINTF("%s: interrupted\n", device_xname(sc->sc_dev));
1067 ret = -1;
1068 goto fail;
1069 }
1070 bail++;
1071 }
1072 if (bail >= 10) {
1073 aprint_error("%s: switching to control mode timed out (%x %x)\n",
1074 device_xname(sc->sc_dev), sc->sc_mm.status,
1075 bus_space_read_4(iot, ioh, DBRI_REG2));
1076 ret = -1;
1077 goto fail;
1078 }
1079 #endif
1080
1081 /* copy the version information before it becomes unreadable again */
1082 sc->sc_version = sc->sc_mm.version;
1083 sc->sc_whack_codec = 0;
1084
1085 fail:
1086 /* terminate cs4215 control mode */
1087 sc->sc_mm.c.bcontrol[0] |= CS4215_CLB;
1088 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol);
1089
1090 /* two frames of control info @ 8kHz frame rate = 250us delay */
1091 delay(250);
1092
1093 mmcodec_setgain(sc, 0);
1094
1095 return ret;
1096
1097 }
1098
1099 /*
1100 * CHI combo
1101 */
1102 static void
chi_reset(struct dbri_softc * sc,enum ms ms,int bpf)1103 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf)
1104 {
1105 volatile uint32_t *cmd;
1106 int val;
1107 int clockrate, divisor;
1108
1109 cmd = dbri_command_lock(sc);
1110
1111 /* set CHI anchor: pipe 16 */
1112 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16);
1113 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
1114 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16);
1115 *(cmd++) = 0;
1116
1117 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16);
1118 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
1119 *(cmd++) = 0;
1120 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16);
1121
1122 sc->sc_pipe[16].sdp = 1;
1123 sc->sc_pipe[16].next = 16;
1124 sc->sc_chi_pipe_in = 16;
1125 sc->sc_chi_pipe_out = 16;
1126
1127 switch (ms) {
1128 case CHIslave:
1129 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0));
1130 break;
1131 case CHImaster:
1132 clockrate = bpf * 8;
1133 divisor = 12288 / clockrate;
1134
1135 if (divisor > 255 || divisor * clockrate != 12288)
1136 aprint_error_dev(sc->sc_dev,
1137 "illegal bits-per-frame %d\n", bpf);
1138
1139 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0,
1140 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf));
1141 break;
1142 default:
1143 aprint_error_dev(sc->sc_dev, "unknown value for ms!\n");
1144 break;
1145 }
1146
1147 sc->sc_chi_bpf = bpf;
1148
1149 /* CHI data mode */
1150 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0);
1151 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0,
1152 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN);
1153
1154 dbri_command_send(sc, cmd);
1155
1156 return;
1157 }
1158
1159 /*
1160 * pipe stuff
1161 */
1162 static void
pipe_setup(struct dbri_softc * sc,int pipe,int sdp)1163 pipe_setup(struct dbri_softc *sc, int pipe, int sdp)
1164 {
1165 DPRINTF("pipe setup: %d\n", pipe);
1166 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) {
1167 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n",
1168 pipe);
1169 return;
1170 }
1171
1172 if ((sdp & 0xf800) != sdp)
1173 aprint_error_dev(sc->sc_dev, "strange SDP value %d\n",
1174 sdp);
1175
1176 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED &&
1177 !(sdp & DBRI_SDP_TO_SER))
1178 sdp |= DBRI_SDP_CHANGE;
1179
1180 sdp |= DBRI_PIPE(pipe);
1181
1182 sc->sc_pipe[pipe].sdp = sdp;
1183 sc->sc_pipe[pipe].desc = -1;
1184
1185 pipe_reset(sc, pipe);
1186
1187 return;
1188 }
1189
1190 static void
pipe_reset(struct dbri_softc * sc,int pipe)1191 pipe_reset(struct dbri_softc *sc, int pipe)
1192 {
1193 struct dbri_desc *dd;
1194 int sdp;
1195 int desc;
1196 volatile uint32_t *cmd;
1197
1198 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) {
1199 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n",
1200 pipe);
1201 return;
1202 }
1203
1204 sdp = sc->sc_pipe[pipe].sdp;
1205 if (sdp == 0) {
1206 aprint_error_dev(sc->sc_dev, "can not reset uninitialized pipe %d\n",
1207 pipe);
1208 return;
1209 }
1210
1211 cmd = dbri_command_lock(sc);
1212 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0,
1213 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER);
1214 *(cmd++) = 0;
1215 dbri_command_send(sc, cmd);
1216
1217 desc = sc->sc_pipe[pipe].desc;
1218
1219 dd = &sc->sc_desc[desc];
1220
1221 dd->busy = 0;
1222
1223 #if 0
1224 if (dd->callback)
1225 softint_schedule(dd->softint);
1226 #endif
1227
1228 sc->sc_pipe[pipe].desc = -1;
1229
1230 return;
1231 }
1232
1233 static void
pipe_receive_fixed(struct dbri_softc * sc,int pipe,volatile uint32_t * prec)1234 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile uint32_t *prec)
1235 {
1236
1237 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) {
1238 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n",
1239 pipe);
1240 return;
1241 }
1242
1243 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) {
1244 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n",
1245 pipe);
1246 return;
1247 }
1248
1249 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) {
1250 aprint_error_dev(sc->sc_dev, "can not receive on transmit pipe %d\b",
1251 pipe);
1252 return;
1253 }
1254
1255 sc->sc_pipe[pipe].prec = prec;
1256
1257 return;
1258 }
1259
1260 static void
pipe_transmit_fixed(struct dbri_softc * sc,int pipe,uint32_t data)1261 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, uint32_t data)
1262 {
1263 volatile uint32_t *cmd;
1264
1265 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) {
1266 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n",
1267 pipe);
1268 return;
1269 }
1270
1271 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) {
1272 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n",
1273 pipe);
1274 return;
1275 }
1276
1277 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) {
1278 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n",
1279 pipe);
1280 return;
1281 }
1282
1283 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) {
1284 aprint_error_dev(sc->sc_dev, "called on receive pipe %d\n",
1285 pipe);
1286 return;
1287 }
1288
1289 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB)
1290 data = reverse_bytes(data, sc->sc_pipe[pipe].length);
1291
1292 cmd = dbri_command_lock(sc);
1293 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe);
1294 *(cmd++) = data;
1295
1296 dbri_command_send(sc, cmd);
1297
1298 return;
1299 }
1300
1301 static void
setup_ring_xmit(struct dbri_softc * sc,int pipe,int which,int num,int blksz,void (* callback)(void *),void * callback_args)1302 setup_ring_xmit(struct dbri_softc *sc, int pipe, int which, int num, int blksz,
1303 void (*callback)(void *), void *callback_args)
1304 {
1305 volatile uint32_t *cmd;
1306 int i;
1307 #if 0
1308 int td;
1309 int td_first, td_last;
1310 #endif
1311 bus_addr_t dmabuf, dmabase;
1312 struct dbri_desc *dd = &sc->sc_desc[which];
1313
1314 switch (pipe) {
1315 case 4:
1316 /* output, offset 0 */
1317 break;
1318 default:
1319 aprint_error("%s: illegal pipe number (%d)\n",
1320 __func__, pipe);
1321 return;
1322 }
1323
1324 #if 0
1325 td = 0;
1326 td_first = td_last = -1;
1327 #endif
1328
1329 if (sc->sc_pipe[pipe].sdp == 0) {
1330 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n",
1331 pipe);
1332 return;
1333 }
1334
1335 dmabuf = dd->dmabase;
1336 dmabase = sc->sc_dmabase;
1337
1338 for (i = 0; i < (num - 1); i++) {
1339
1340 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz)
1341 | TX_EOF | TX_BINT;
1342 sc->sc_dma->xmit[i].ba = dmabuf;
1343 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, i + 1);
1344 sc->sc_dma->xmit[i].status = 0;
1345
1346 #if 0
1347 td_last = td;
1348 #endif
1349 dmabuf += blksz;
1350 }
1351
1352 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT;
1353
1354 sc->sc_dma->xmit[i].ba = dmabuf;
1355 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, 0);
1356 sc->sc_dma->xmit[i].status = 0;
1357
1358 dd->callback = callback;
1359 dd->callback_args = callback_args;
1360
1361 /* the pipe shouldn't be active */
1362 if (pipe_active(sc, pipe)) {
1363 aprint_error("pipe active (CDP)\n");
1364 /* pipe is already active */
1365 #if 0
1366 td_last = sc->sc_pipe[pipe].desc;
1367 while (sc->sc_desc[td_last].next != -1)
1368 td_last = sc->sc_desc[td_last].next;
1369
1370 sc->sc_desc[td_last].next = td_first;
1371 sc->sc_dma->desc[td_last].nda =
1372 sc->sc_dmabase + dbri_dma_off(desc, td_first);
1373
1374 cmd = dbri_command_lock(sc);
1375 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe);
1376 dbri_command_send(sc, cmd);
1377 #endif
1378 } else {
1379 /*
1380 * pipe isn't active - issue an SDP command to start our
1381 * chain of TDs running
1382 */
1383 sc->sc_pipe[pipe].desc = which;
1384 cmd = dbri_command_lock(sc);
1385 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0,
1386 sc->sc_pipe[pipe].sdp |
1387 DBRI_SDP_VALID_POINTER |
1388 DBRI_SDP_EVERY |
1389 DBRI_SDP_CLEAR);
1390 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, 0);
1391 dbri_command_send(sc, cmd);
1392 DPRINTF("%s: starting DMA\n", __func__);
1393 }
1394
1395 return;
1396 }
1397
1398 static void
setup_ring_recv(struct dbri_softc * sc,int pipe,int which,int num,int blksz,void (* callback)(void *),void * callback_args)1399 setup_ring_recv(struct dbri_softc *sc, int pipe, int which, int num, int blksz,
1400 void (*callback)(void *), void *callback_args)
1401 {
1402 volatile uint32_t *cmd;
1403 int i;
1404 #if 0
1405 int td_first, td_last;
1406 #endif
1407 bus_addr_t dmabuf, dmabase;
1408 struct dbri_desc *dd = &sc->sc_desc[which];
1409
1410 switch (pipe) {
1411 case 6:
1412 break;
1413 default:
1414 aprint_error("%s: illegal pipe number (%d)\n",
1415 __func__, pipe);
1416 return;
1417 }
1418
1419 #if 0
1420 td_first = td_last = -1;
1421 #endif
1422
1423 if (sc->sc_pipe[pipe].sdp == 0) {
1424 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n",
1425 pipe);
1426 return;
1427 }
1428
1429 dmabuf = dd->dmabase;
1430 dmabase = sc->sc_dmabase;
1431
1432 for (i = 0; i < (num - 1); i++) {
1433
1434 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL;
1435 sc->sc_dma->recv[i].ba = dmabuf;
1436 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, i + 1);
1437 sc->sc_dma->recv[i].status = RX_EOF;
1438
1439 #if 0
1440 td_last = i;
1441 #endif
1442 dmabuf += blksz;
1443 }
1444
1445 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL;
1446
1447 sc->sc_dma->recv[i].ba = dmabuf;
1448 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, 0);
1449 sc->sc_dma->recv[i].status = RX_EOF;
1450
1451 dd->callback = callback;
1452 dd->callback_args = callback_args;
1453
1454 /* the pipe shouldn't be active */
1455 if (pipe_active(sc, pipe)) {
1456 aprint_error("pipe active (CDP)\n");
1457 /* pipe is already active */
1458 #if 0
1459 td_last = sc->sc_pipe[pipe].desc;
1460 while (sc->sc_desc[td_last].next != -1)
1461 td_last = sc->sc_desc[td_last].next;
1462
1463 sc->sc_desc[td_last].next = td_first;
1464 sc->sc_dma->desc[td_last].nda =
1465 sc->sc_dmabase + dbri_dma_off(desc, td_first);
1466
1467 cmd = dbri_command_lock(sc);
1468 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe);
1469 dbri_command_send(sc, cmd);
1470 #endif
1471 } else {
1472 /*
1473 * pipe isn't active - issue an SDP command to start our
1474 * chain of TDs running
1475 */
1476 sc->sc_pipe[pipe].desc = which;
1477 cmd = dbri_command_lock(sc);
1478 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0,
1479 sc->sc_pipe[pipe].sdp |
1480 DBRI_SDP_VALID_POINTER |
1481 DBRI_SDP_EVERY |
1482 DBRI_SDP_CLEAR);
1483 *(cmd++) = sc->sc_dmabase + dbri_dma_off(recv, 0);
1484 dbri_command_send(sc, cmd);
1485 DPRINTF("%s: starting DMA\n", __func__);
1486 }
1487
1488 return;
1489 }
1490
1491 static void
pipe_ts_link(struct dbri_softc * sc,int pipe,enum io dir,int basepipe,int len,int cycle)1492 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe,
1493 int len, int cycle)
1494 {
1495 volatile uint32_t *cmd;
1496 int prevpipe, nextpipe;
1497 int val;
1498
1499 DPRINTF("%s: %d\n", __func__, pipe);
1500 if (pipe < 0 || pipe >= DBRI_PIPE_MAX ||
1501 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) {
1502 aprint_error_dev(sc->sc_dev, "illegal pipe numbers (%d, %d)\n",
1503 pipe, basepipe);
1504 return;
1505 }
1506
1507 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) {
1508 aprint_error_dev(sc->sc_dev, "uninitialized pipe (%d, %d)\n",
1509 pipe, basepipe);
1510 return;
1511 }
1512
1513 if (basepipe == 16 && dir == PIPEoutput && cycle == 0)
1514 cycle = sc->sc_chi_bpf;
1515
1516 if (basepipe == pipe)
1517 prevpipe = nextpipe = pipe;
1518 else {
1519 if (basepipe == 16) {
1520 if (dir == PIPEinput) {
1521 prevpipe = sc->sc_chi_pipe_in;
1522 } else {
1523 prevpipe = sc->sc_chi_pipe_out;
1524 }
1525 } else
1526 prevpipe = basepipe;
1527
1528 nextpipe = sc->sc_pipe[prevpipe].next;
1529
1530 while (sc->sc_pipe[nextpipe].cycle < cycle &&
1531 sc->sc_pipe[nextpipe].next != basepipe) {
1532 prevpipe = nextpipe;
1533 nextpipe = sc->sc_pipe[nextpipe].next;
1534 }
1535 }
1536
1537 if (prevpipe == 16) {
1538 if (dir == PIPEinput) {
1539 sc->sc_chi_pipe_in = pipe;
1540 } else {
1541 sc->sc_chi_pipe_out = pipe;
1542 }
1543 } else
1544 sc->sc_pipe[prevpipe].next = pipe;
1545
1546 sc->sc_pipe[pipe].next = nextpipe;
1547 sc->sc_pipe[pipe].cycle = cycle;
1548 sc->sc_pipe[pipe].length = len;
1549
1550 cmd = dbri_command_lock(sc);
1551
1552 switch (dir) {
1553 case PIPEinput:
1554 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe);
1555 val |= pipe;
1556 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
1557 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) |
1558 DBRI_TS_NEXT(nextpipe);
1559 *(cmd++) = 0;
1560 break;
1561 case PIPEoutput:
1562 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe);
1563 val |= pipe;
1564 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
1565 *(cmd++) = 0;
1566 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) |
1567 DBRI_TS_NEXT(nextpipe);
1568 break;
1569 default:
1570 DPRINTF("%s: should not have happened!\n",
1571 device_xname(sc->sc_dev));
1572 break;
1573 }
1574
1575 dbri_command_send(sc, cmd);
1576
1577 return;
1578 }
1579
1580 static int
pipe_active(struct dbri_softc * sc,int pipe)1581 pipe_active(struct dbri_softc *sc, int pipe)
1582 {
1583
1584 return (sc->sc_pipe[pipe].desc != -1);
1585 }
1586
1587 /*
1588 * subroutines required to interface with audio(9)
1589 */
1590
1591 static int
dbri_query_format(void * hdl,audio_format_query_t * afp)1592 dbri_query_format(void *hdl, audio_format_query_t *afp)
1593 {
1594
1595 return audio_query_format(dbri_formats, DBRI_NFORMATS, afp);
1596 }
1597
1598 static int
dbri_set_format(void * hdl,int setmode,const audio_params_t * play,const audio_params_t * rec,audio_filter_reg_t * pfil,audio_filter_reg_t * rfil)1599 dbri_set_format(void *hdl, int setmode,
1600 const audio_params_t *play, const audio_params_t *rec,
1601 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil)
1602 {
1603 struct dbri_softc *sc = hdl;
1604 int rate;
1605
1606 /* *play and *rec are the identical because !AUDIO_PROP_INDEPENDENT. */
1607
1608 for (rate = 0; CS4215_FREQ[rate].freq; rate++)
1609 if (CS4215_FREQ[rate].freq == play->sample_rate)
1610 break;
1611
1612 if (CS4215_FREQ[rate].freq == 0)
1613 return EINVAL;
1614
1615 /* set frequency */
1616 sc->sc_mm.c.bcontrol[1] &= ~0x38;
1617 sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[rate].csval;
1618 sc->sc_mm.c.bcontrol[2] &= ~0x70;
1619 sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[rate].xtal;
1620
1621 /* set encoding */
1622 sc->sc_mm.c.bcontrol[1] &= ~3;
1623 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16;
1624
1625 /* set channel */
1626 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO;
1627
1628 sc->sc_whack_codec = 1;
1629 return 0;
1630 }
1631
1632 static int
dbri_round_blocksize(void * hdl,int bs,int mode,const audio_params_t * param)1633 dbri_round_blocksize(void *hdl, int bs, int mode,
1634 const audio_params_t *param)
1635 {
1636
1637 if (bs > 0x1ffc)
1638 return 0x1ffc;
1639 return bs;
1640 }
1641
1642 static int
dbri_halt_output(void * hdl)1643 dbri_halt_output(void *hdl)
1644 {
1645 struct dbri_softc *sc = hdl;
1646
1647 if (!sc->sc_playing)
1648 return 0;
1649
1650 sc->sc_playing = 0;
1651 pipe_reset(sc, 4);
1652 return (0);
1653 }
1654
1655 static int
dbri_getdev(void * hdl,struct audio_device * ret)1656 dbri_getdev(void *hdl, struct audio_device *ret)
1657 {
1658
1659 *ret = dbri_device;
1660 return (0);
1661 }
1662
1663 static int
dbri_set_port(void * hdl,mixer_ctrl_t * mc)1664 dbri_set_port(void *hdl, mixer_ctrl_t *mc)
1665 {
1666 struct dbri_softc *sc = hdl;
1667 int latt = sc->sc_latt, ratt = sc->sc_ratt;
1668
1669 switch (mc->dev) {
1670 case DBRI_VOL_OUTPUT: /* master volume */
1671 latt = (latt & 0xc0) | (63 -
1672 uimin(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63));
1673 ratt = (ratt & 0xc0) | (63 -
1674 uimin(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63));
1675 break;
1676 case DBRI_ENABLE_MONO: /* built-in speaker */
1677 if (mc->un.ord == 1) {
1678 ratt |= CS4215_SE;
1679 } else
1680 ratt &= ~CS4215_SE;
1681 break;
1682 case DBRI_ENABLE_HEADPHONE: /* headphones output */
1683 if (mc->un.ord == 1) {
1684 latt |= CS4215_HE;
1685 } else
1686 latt &= ~CS4215_HE;
1687 break;
1688 case DBRI_ENABLE_LINE: /* line out */
1689 if (mc->un.ord == 1) {
1690 latt |= CS4215_LE;
1691 } else
1692 latt &= ~CS4215_LE;
1693 break;
1694 case DBRI_VOL_MONITOR:
1695 if (mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] ==
1696 sc->sc_monitor)
1697 return 0;
1698 sc->sc_monitor = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT];
1699 break;
1700 case DBRI_INPUT_GAIN:
1701 sc->sc_linp = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT];
1702 sc->sc_rinp = mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT];
1703 break;
1704 case DBRI_INPUT_SELECT:
1705 if (mc->un.mask == sc->sc_input)
1706 return 0;
1707 sc->sc_input = mc->un.mask;
1708 break;
1709 }
1710
1711 sc->sc_latt = latt;
1712 sc->sc_ratt = ratt;
1713
1714 mutex_spin_enter(&sc->sc_intr_lock);
1715 mmcodec_setgain(sc, 0);
1716 mutex_spin_exit(&sc->sc_intr_lock);
1717
1718 return (0);
1719 }
1720
1721 static int
dbri_get_port(void * hdl,mixer_ctrl_t * mc)1722 dbri_get_port(void *hdl, mixer_ctrl_t *mc)
1723 {
1724 struct dbri_softc *sc = hdl;
1725
1726 switch (mc->dev) {
1727 case DBRI_VOL_OUTPUT: /* master volume */
1728 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
1729 (63 - (sc->sc_latt & 0x3f)) << 2;
1730 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] =
1731 (63 - (sc->sc_ratt & 0x3f)) << 2;
1732 return (0);
1733 case DBRI_ENABLE_MONO: /* built-in speaker */
1734 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0;
1735 return 0;
1736 case DBRI_ENABLE_HEADPHONE: /* headphones output */
1737 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0;
1738 return 0;
1739 case DBRI_ENABLE_LINE: /* line out */
1740 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0;
1741 return 0;
1742 case DBRI_VOL_MONITOR:
1743 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_monitor;
1744 return 0;
1745 case DBRI_INPUT_GAIN:
1746 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_linp;
1747 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_rinp;
1748 return 0;
1749 case DBRI_INPUT_SELECT:
1750 mc->un.mask = sc->sc_input;
1751 return 0;
1752 }
1753 return (EINVAL);
1754 }
1755
1756 static int
dbri_query_devinfo(void * hdl,mixer_devinfo_t * di)1757 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di)
1758 {
1759
1760 switch (di->index) {
1761 case DBRI_MONITOR_CLASS:
1762 di->mixer_class = DBRI_MONITOR_CLASS;
1763 strcpy(di->label.name, AudioCmonitor);
1764 di->type = AUDIO_MIXER_CLASS;
1765 di->next = di->prev = AUDIO_MIXER_LAST;
1766 return 0;
1767 case DBRI_OUTPUT_CLASS:
1768 di->mixer_class = DBRI_OUTPUT_CLASS;
1769 strcpy(di->label.name, AudioCoutputs);
1770 di->type = AUDIO_MIXER_CLASS;
1771 di->next = di->prev = AUDIO_MIXER_LAST;
1772 return 0;
1773 case DBRI_INPUT_CLASS:
1774 di->mixer_class = DBRI_INPUT_CLASS;
1775 strcpy(di->label.name, AudioCinputs);
1776 di->type = AUDIO_MIXER_CLASS;
1777 di->next = di->prev = AUDIO_MIXER_LAST;
1778 return 0;
1779 case DBRI_VOL_OUTPUT: /* master volume */
1780 di->mixer_class = DBRI_OUTPUT_CLASS;
1781 di->next = di->prev = AUDIO_MIXER_LAST;
1782 strcpy(di->label.name, AudioNmaster);
1783 di->type = AUDIO_MIXER_VALUE;
1784 di->un.v.num_channels = 2;
1785 di->un.v.delta = 16;
1786 strcpy(di->un.v.units.name, AudioNvolume);
1787 return (0);
1788 case DBRI_INPUT_GAIN: /* input gain */
1789 di->mixer_class = DBRI_INPUT_CLASS;
1790 di->next = di->prev = AUDIO_MIXER_LAST;
1791 strcpy(di->label.name, AudioNrecord);
1792 di->type = AUDIO_MIXER_VALUE;
1793 di->un.v.num_channels = 2;
1794 strcpy(di->un.v.units.name, AudioNvolume);
1795 return (0);
1796 case DBRI_VOL_MONITOR: /* monitor volume */
1797 di->mixer_class = DBRI_MONITOR_CLASS;
1798 di->next = di->prev = AUDIO_MIXER_LAST;
1799 strcpy(di->label.name, AudioNmonitor);
1800 di->type = AUDIO_MIXER_VALUE;
1801 di->un.v.num_channels = 1;
1802 strcpy(di->un.v.units.name, AudioNvolume);
1803 return (0);
1804 case DBRI_ENABLE_MONO: /* built-in speaker */
1805 di->mixer_class = DBRI_OUTPUT_CLASS;
1806 di->next = di->prev = AUDIO_MIXER_LAST;
1807 strcpy(di->label.name, AudioNmono);
1808 di->type = AUDIO_MIXER_ENUM;
1809 di->un.e.num_mem = 2;
1810 strcpy(di->un.e.member[0].label.name, AudioNoff);
1811 di->un.e.member[0].ord = 0;
1812 strcpy(di->un.e.member[1].label.name, AudioNon);
1813 di->un.e.member[1].ord = 1;
1814 return (0);
1815 case DBRI_ENABLE_HEADPHONE: /* headphones output */
1816 di->mixer_class = DBRI_OUTPUT_CLASS;
1817 di->next = di->prev = AUDIO_MIXER_LAST;
1818 strcpy(di->label.name, AudioNheadphone);
1819 di->type = AUDIO_MIXER_ENUM;
1820 di->un.e.num_mem = 2;
1821 strcpy(di->un.e.member[0].label.name, AudioNoff);
1822 di->un.e.member[0].ord = 0;
1823 strcpy(di->un.e.member[1].label.name, AudioNon);
1824 di->un.e.member[1].ord = 1;
1825 return (0);
1826 case DBRI_ENABLE_LINE: /* line out */
1827 di->mixer_class = DBRI_OUTPUT_CLASS;
1828 di->next = di->prev = AUDIO_MIXER_LAST;
1829 strcpy(di->label.name, AudioNline);
1830 di->type = AUDIO_MIXER_ENUM;
1831 di->un.e.num_mem = 2;
1832 strcpy(di->un.e.member[0].label.name, AudioNoff);
1833 di->un.e.member[0].ord = 0;
1834 strcpy(di->un.e.member[1].label.name, AudioNon);
1835 di->un.e.member[1].ord = 1;
1836 return (0);
1837 case DBRI_INPUT_SELECT:
1838 di->mixer_class = DBRI_INPUT_CLASS;
1839 strcpy(di->label.name, AudioNsource);
1840 di->type = AUDIO_MIXER_SET;
1841 di->prev = di->next = AUDIO_MIXER_LAST;
1842 di->un.s.num_mem = 2;
1843 strcpy(di->un.s.member[0].label.name, AudioNline);
1844 di->un.s.member[0].mask = 1 << 0;
1845 strcpy(di->un.s.member[1].label.name, AudioNmicrophone);
1846 di->un.s.member[1].mask = 1 << 1;
1847 return 0;
1848 }
1849
1850 return (ENXIO);
1851 }
1852
1853 static int
dbri_get_props(void * hdl)1854 dbri_get_props(void *hdl)
1855 {
1856
1857 return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE |
1858 AUDIO_PROP_FULLDUPLEX;
1859 }
1860
1861 static int
dbri_commit(void * hdl)1862 dbri_commit(void *hdl)
1863 {
1864 struct dbri_softc *sc = hdl;
1865 int ret = 0;
1866
1867 /*
1868 * we only need to whack the codec if things like sample format or
1869 * frequency changed, not for mixer stuff
1870 */
1871 if (sc->sc_whack_codec == 0)
1872 return 0;
1873
1874 mutex_spin_enter(&sc->sc_intr_lock);
1875 ret = mmcodec_setcontrol(sc);
1876 if (ret) {
1877 DPRINTF("%s: control mode failed. Mutex %s PIL %x\n", __func__,
1878 mutex_owned(&sc->sc_intr_lock) ? "held" : "free",
1879 (getpsr() & PSR_PIL) >> 8);
1880 } else
1881 DPRINTF("%s: control mode ok\n", __func__);
1882 mmcodec_init_data(sc);
1883 mutex_spin_exit(&sc->sc_intr_lock);
1884 return 0;
1885 }
1886
1887 static int
dbri_trigger_output(void * hdl,void * start,void * end,int blksize,void (* intr)(void *),void * intrarg,const struct audio_params * param)1888 dbri_trigger_output(void *hdl, void *start, void *end, int blksize,
1889 void (*intr)(void *), void *intrarg,
1890 const struct audio_params *param)
1891 {
1892 struct dbri_softc *sc = hdl;
1893 unsigned long count, num;
1894
1895 KASSERT(sc->sc_playing == 0);
1896
1897 count = (unsigned long)(((char *)end - (char *)start));
1898 num = count / blksize;
1899
1900 DPRINTF("trigger_output(%lx %lx) : %d %ld %ld\n",
1901 (unsigned long)intr,
1902 (unsigned long)intrarg, blksize, count, num);
1903
1904 sc->sc_params = *param;
1905
1906 /*
1907 * always use DMA descriptor 0 for output
1908 * no need to allocate them dynamically since we only ever have
1909 * exactly one input stream and exactly one output stream
1910 */
1911 setup_ring_xmit(sc, 4, 0, num, blksize, intr, intrarg);
1912 sc->sc_playing = 1;
1913 return 0;
1914 }
1915
1916 static int
dbri_halt_input(void * cookie)1917 dbri_halt_input(void *cookie)
1918 {
1919 struct dbri_softc *sc = cookie;
1920
1921 if (!sc->sc_recording)
1922 return 0;
1923
1924 sc->sc_recording = 0;
1925 pipe_reset(sc, 6);
1926 return 0;
1927 }
1928
1929 static int
dbri_trigger_input(void * hdl,void * start,void * end,int blksize,void (* intr)(void *),void * intrarg,const struct audio_params * param)1930 dbri_trigger_input(void *hdl, void *start, void *end, int blksize,
1931 void (*intr)(void *), void *intrarg,
1932 const struct audio_params *param)
1933 {
1934 struct dbri_softc *sc = hdl;
1935 unsigned long count, num;
1936
1937 KASSERT(sc->sc_recording == 0);
1938
1939 count = (unsigned long)(((char *)end - (char *)start));
1940 num = count / blksize;
1941
1942 DPRINTF("trigger_input(%lx %lx) : %d %ld %ld\n",
1943 (unsigned long)intr,
1944 (unsigned long)intrarg, blksize, count, num);
1945
1946 sc->sc_params = *param;
1947
1948 sc->sc_recording = 1;
1949 setup_ring_recv(sc, 6, 1, num, blksize, intr, intrarg);
1950 return 0;
1951 }
1952
1953 static void
dbri_get_locks(void * opaque,kmutex_t ** intr,kmutex_t ** thread)1954 dbri_get_locks(void *opaque, kmutex_t **intr, kmutex_t **thread)
1955 {
1956 struct dbri_softc *sc = opaque;
1957
1958 *intr = &sc->sc_intr_lock;
1959 *thread = &sc->sc_lock;
1960 }
1961
1962 static uint32_t
reverse_bytes(uint32_t b,int len)1963 reverse_bytes(uint32_t b, int len)
1964 {
1965 switch (len) {
1966 case 32:
1967 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
1968 case 16:
1969 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
1970 case 8:
1971 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
1972 case 4:
1973 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
1974 case 2:
1975 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
1976 case 1:
1977 case 0:
1978 break;
1979 default:
1980 DPRINTF("reverse_bytes: unsupported length\n");
1981 };
1982
1983 return (b);
1984 }
1985
1986 static void *
dbri_malloc(void * v,int dir,size_t s)1987 dbri_malloc(void *v, int dir, size_t s)
1988 {
1989 struct dbri_softc *sc = v;
1990 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used];
1991 int rseg;
1992
1993 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT,
1994 &dd->dmamap) == 0) {
1995 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg,
1996 1, &rseg, BUS_DMA_NOWAIT) == 0) {
1997 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s,
1998 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) {
1999 if (dd->buf != NULL) {
2000 if (bus_dmamap_load(sc->sc_dmat,
2001 dd->dmamap, dd->buf, s, NULL,
2002 BUS_DMA_NOWAIT) == 0) {
2003 dd->len = s;
2004 dd->busy = 0;
2005 dd->callback = NULL;
2006 dd->dmabase =
2007 dd->dmamap->dm_segs[0].ds_addr;
2008 DPRINTF("dbri_malloc: using buffer %d %08x\n",
2009 sc->sc_desc_used, (uint32_t)dd->buf);
2010 sc->sc_desc_used++;
2011 return dd->buf;
2012 } else
2013 aprint_error("dbri_malloc: load failed\n");
2014 } else
2015 aprint_error("dbri_malloc: map returned NULL\n");
2016 } else
2017 aprint_error("dbri_malloc: map failed\n");
2018 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg);
2019 } else
2020 aprint_error("dbri_malloc: malloc() failed\n");
2021 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap);
2022 } else
2023 aprint_error("dbri_malloc: bus_dmamap_create() failed\n");
2024 return NULL;
2025 }
2026
2027 static void
dbri_free(void * v,void * p,size_t size)2028 dbri_free(void *v, void *p, size_t size)
2029 {
2030 struct dbri_softc *sc = v;
2031 struct dbri_desc *dd;
2032 int i;
2033
2034 for (i = 0; i < sc->sc_desc_used; i++) {
2035 dd = &sc->sc_desc[i];
2036 if (dd->buf == p)
2037 break;
2038 }
2039 if (i >= sc->sc_desc_used)
2040 return;
2041 bus_dmamap_unload(sc->sc_dmat, dd->dmamap);
2042 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap);
2043 }
2044
2045 static int
dbri_open(void * cookie,int flags)2046 dbri_open(void *cookie, int flags)
2047 {
2048 struct dbri_softc *sc = cookie;
2049
2050 DPRINTF("%s\n", __func__);
2051
2052 dbri_bring_up(sc);
2053 return 0;
2054 }
2055
2056 static void
dbri_close(void * cookie)2057 dbri_close(void *cookie)
2058 {
2059 struct dbri_softc *sc = cookie;
2060
2061 DPRINTF("%s\n", __func__);
2062 KASSERT(sc->sc_playing == 0);
2063 KASSERT(sc->sc_recording == 0);
2064
2065 dbri_set_power(sc, 0);
2066 }
2067
2068 static bool
dbri_suspend(device_t self,const pmf_qual_t * qual)2069 dbri_suspend(device_t self, const pmf_qual_t *qual)
2070 {
2071 struct dbri_softc *sc = device_private(self);
2072
2073 mutex_spin_enter(&sc->sc_intr_lock);
2074 dbri_set_power(sc, 0);
2075 mutex_spin_exit(&sc->sc_intr_lock);
2076 return true;
2077 }
2078
2079 static bool
dbri_resume(device_t self,const pmf_qual_t * qual)2080 dbri_resume(device_t self, const pmf_qual_t *qual)
2081 {
2082 struct dbri_softc *sc = device_private(self);
2083
2084 if (sc->sc_powerstate != 0)
2085 return true;
2086 aprint_verbose("resume\n");
2087 if (sc->sc_playing) {
2088 volatile uint32_t *cmd;
2089
2090 mutex_spin_enter(&sc->sc_intr_lock);
2091 dbri_bring_up(sc);
2092 cmd = dbri_command_lock(sc);
2093 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP,
2094 0, sc->sc_pipe[4].sdp |
2095 DBRI_SDP_VALID_POINTER |
2096 DBRI_SDP_EVERY | DBRI_SDP_CLEAR);
2097 *(cmd++) = sc->sc_dmabase +
2098 dbri_dma_off(xmit, 0);
2099 dbri_command_send(sc, cmd);
2100 mutex_spin_exit(&sc->sc_intr_lock);
2101 }
2102 return true;
2103 }
2104
2105 #endif /* NAUDIO > 0 */
2106