1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "basics/dc_common.h"
28 #include "dc.h"
29 #include "core_types.h"
30 #include "resource.h"
31 #include "ipp.h"
32 #include "timing_generator.h"
33 #include "dc_dmub_srv.h"
34 #include "dc_state_priv.h"
35 #include "dc_stream_priv.h"
36
37 #define DC_LOGGER dc->ctx->logger
38
39 /*******************************************************************************
40 * Private functions
41 ******************************************************************************/
update_stream_signal(struct dc_stream_state * stream,struct dc_sink * sink)42 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)
43 {
44 if (sink->sink_signal == SIGNAL_TYPE_NONE)
45 stream->signal = stream->link->connector_signal;
46 else
47 stream->signal = sink->sink_signal;
48
49 if (dc_is_dvi_signal(stream->signal)) {
50 if (stream->ctx->dc->caps.dual_link_dvi &&
51 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK &&
52 sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
53 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
54 else
55 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
56 }
57 }
58
dc_stream_construct(struct dc_stream_state * stream,struct dc_sink * dc_sink_data)59 bool dc_stream_construct(struct dc_stream_state *stream,
60 struct dc_sink *dc_sink_data)
61 {
62 uint32_t i = 0;
63
64 stream->sink = dc_sink_data;
65 dc_sink_retain(dc_sink_data);
66
67 stream->ctx = dc_sink_data->ctx;
68 stream->link = dc_sink_data->link;
69 stream->sink_patches = dc_sink_data->edid_caps.panel_patch;
70 stream->converter_disable_audio = dc_sink_data->converter_disable_audio;
71 stream->qs_bit = dc_sink_data->edid_caps.qs_bit;
72 stream->qy_bit = dc_sink_data->edid_caps.qy_bit;
73
74 /* Copy audio modes */
75 /* TODO - Remove this translation */
76 for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++) {
77 stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count;
78 stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code;
79 stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate;
80 stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size;
81 }
82 stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count;
83 stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency;
84 stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency;
85 memmove(
86 stream->audio_info.display_name,
87 dc_sink_data->edid_caps.display_name,
88 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
89 stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id;
90 stream->audio_info.product_id = dc_sink_data->edid_caps.product_id;
91 stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags;
92
93 if (dc_sink_data->dc_container_id != NULL) {
94 struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id;
95
96 stream->audio_info.port_id[0] = dc_container_id->portId[0];
97 stream->audio_info.port_id[1] = dc_container_id->portId[1];
98 } else {
99 /* TODO - WindowDM has implemented,
100 other DMs need Unhardcode port_id */
101 stream->audio_info.port_id[0] = 0x5558859e;
102 stream->audio_info.port_id[1] = 0xd989449;
103 }
104
105 /* EDID CAP translation for HDMI 2.0 */
106 stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
107
108 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
109 stream->timing.dsc_cfg.num_slices_h = 0;
110 stream->timing.dsc_cfg.num_slices_v = 0;
111 stream->timing.dsc_cfg.bits_per_pixel = 128;
112 stream->timing.dsc_cfg.block_pred_enable = 1;
113 stream->timing.dsc_cfg.linebuf_depth = 9;
114 stream->timing.dsc_cfg.version_minor = 2;
115 stream->timing.dsc_cfg.ycbcr422_simple = 0;
116
117 update_stream_signal(stream, dc_sink_data);
118
119 stream->out_transfer_func.type = TF_TYPE_BYPASS;
120
121 dc_stream_assign_stream_id(stream);
122
123 return true;
124 }
125
dc_stream_destruct(struct dc_stream_state * stream)126 void dc_stream_destruct(struct dc_stream_state *stream)
127 {
128 dc_sink_release(stream->sink);
129 }
130
dc_stream_assign_stream_id(struct dc_stream_state * stream)131 void dc_stream_assign_stream_id(struct dc_stream_state *stream)
132 {
133 /* MSB is reserved to indicate phantoms */
134 stream->stream_id = stream->ctx->dc_stream_id_count;
135 stream->ctx->dc_stream_id_count++;
136 }
137
dc_stream_retain(struct dc_stream_state * stream)138 void dc_stream_retain(struct dc_stream_state *stream)
139 {
140 kref_get(&stream->refcount);
141 }
142
dc_stream_free(struct kref * kref)143 static void dc_stream_free(struct kref *kref)
144 {
145 struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount);
146
147 dc_stream_destruct(stream);
148 kfree(stream);
149 }
150
dc_stream_release(struct dc_stream_state * stream)151 void dc_stream_release(struct dc_stream_state *stream)
152 {
153 if (stream != NULL) {
154 kref_put(&stream->refcount, dc_stream_free);
155 }
156 }
157
dc_create_stream_for_sink(struct dc_sink * sink)158 struct dc_stream_state *dc_create_stream_for_sink(
159 struct dc_sink *sink)
160 {
161 struct dc_stream_state *stream;
162
163 if (sink == NULL)
164 return NULL;
165
166 stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);
167 if (stream == NULL)
168 goto alloc_fail;
169
170 if (dc_stream_construct(stream, sink) == false)
171 goto construct_fail;
172
173 kref_init(&stream->refcount);
174
175 return stream;
176
177 construct_fail:
178 kfree(stream);
179
180 alloc_fail:
181 return NULL;
182 }
183
dc_copy_stream(const struct dc_stream_state * stream)184 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream)
185 {
186 struct dc_stream_state *new_stream;
187
188 new_stream = kmemdup(stream, sizeof(struct dc_stream_state), GFP_KERNEL);
189 if (!new_stream)
190 return NULL;
191
192 if (new_stream->sink)
193 dc_sink_retain(new_stream->sink);
194
195 dc_stream_assign_stream_id(new_stream);
196
197 /* If using dynamic encoder assignment, wait till stream committed to assign encoder. */
198 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign)
199 new_stream->link_enc = NULL;
200
201 kref_init(&new_stream->refcount);
202
203 return new_stream;
204 }
205
206 /**
207 * dc_stream_get_status() - Get current stream status of the given stream state
208 * @stream: The stream to get the stream status for.
209 *
210 * The given stream is expected to exist in dc->current_state. Otherwise, NULL
211 * will be returned.
212 */
dc_stream_get_status(struct dc_stream_state * stream)213 struct dc_stream_status *dc_stream_get_status(
214 struct dc_stream_state *stream)
215 {
216 struct dc *dc = stream->ctx->dc;
217 return dc_state_get_stream_status(dc->current_state, stream);
218 }
219
program_cursor_attributes(struct dc * dc,struct dc_stream_state * stream,const struct dc_cursor_attributes * attributes)220 static void program_cursor_attributes(
221 struct dc *dc,
222 struct dc_stream_state *stream,
223 const struct dc_cursor_attributes *attributes)
224 {
225 int i;
226 struct resource_context *res_ctx;
227 struct pipe_ctx *pipe_to_program = NULL;
228
229 if (!stream)
230 return;
231
232 res_ctx = &dc->current_state->res_ctx;
233
234 for (i = 0; i < MAX_PIPES; i++) {
235 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
236
237 if (pipe_ctx->stream != stream)
238 continue;
239
240 if (!pipe_to_program) {
241 pipe_to_program = pipe_ctx;
242 dc->hwss.cursor_lock(dc, pipe_to_program, true);
243 if (pipe_to_program->next_odm_pipe)
244 dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true);
245 }
246
247 dc->hwss.set_cursor_attribute(pipe_ctx);
248 if (dc->ctx->dmub_srv)
249 dc_send_update_cursor_info_to_dmu(pipe_ctx, i);
250 if (dc->hwss.set_cursor_sdr_white_level)
251 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
252 }
253
254 if (pipe_to_program) {
255 dc->hwss.cursor_lock(dc, pipe_to_program, false);
256 if (pipe_to_program->next_odm_pipe)
257 dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false);
258 }
259 }
260
261 /*
262 * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address
263 */
dc_stream_set_cursor_attributes(struct dc_stream_state * stream,const struct dc_cursor_attributes * attributes)264 bool dc_stream_set_cursor_attributes(
265 struct dc_stream_state *stream,
266 const struct dc_cursor_attributes *attributes)
267 {
268 struct dc *dc;
269 bool reset_idle_optimizations = false;
270
271 if (NULL == stream) {
272 dm_error("DC: dc_stream is NULL!\n");
273 return false;
274 }
275 if (NULL == attributes) {
276 dm_error("DC: attributes is NULL!\n");
277 return false;
278 }
279
280 if (attributes->address.quad_part == 0) {
281 dm_output_to_console("DC: Cursor address is 0!\n");
282 return false;
283 }
284
285 dc = stream->ctx->dc;
286
287 /* SubVP is not compatible with HW cursor larger than 64 x 64 x 4.
288 * Therefore, if cursor is greater than 64 x 64 x 4, fallback to SW cursor in the following case:
289 * 1. If the config is a candidate for SubVP high refresh (both single an dual display configs)
290 * 2. If not subvp high refresh, for single display cases, if resolution is >= 5K and refresh rate < 120hz
291 * 3. If not subvp high refresh, for multi display cases, if resolution is >= 4K and refresh rate < 120hz
292 */
293 if (dc->debug.allow_sw_cursor_fallback && attributes->height * attributes->width * 4 > 16384) {
294 if (check_subvp_sw_cursor_fallback_req(dc, stream))
295 return false;
296 }
297
298 stream->cursor_attributes = *attributes;
299
300 dc_z10_restore(dc);
301 /* disable idle optimizations while updating cursor */
302 if (dc->idle_optimizations_allowed) {
303 dc_allow_idle_optimizations(dc, false);
304 reset_idle_optimizations = true;
305 }
306
307 program_cursor_attributes(dc, stream, attributes);
308
309 /* re-enable idle optimizations if necessary */
310 if (reset_idle_optimizations && !dc->debug.disable_dmub_reallow_idle)
311 dc_allow_idle_optimizations(dc, true);
312
313 return true;
314 }
315
program_cursor_position(struct dc * dc,struct dc_stream_state * stream,const struct dc_cursor_position * position)316 static void program_cursor_position(
317 struct dc *dc,
318 struct dc_stream_state *stream,
319 const struct dc_cursor_position *position)
320 {
321 int i;
322 struct resource_context *res_ctx;
323 struct pipe_ctx *pipe_to_program = NULL;
324
325 if (!stream)
326 return;
327
328 res_ctx = &dc->current_state->res_ctx;
329
330 for (i = 0; i < MAX_PIPES; i++) {
331 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
332
333 if (pipe_ctx->stream != stream ||
334 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||
335 !pipe_ctx->plane_state ||
336 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||
337 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))
338 continue;
339
340 if (!pipe_to_program) {
341 pipe_to_program = pipe_ctx;
342 dc->hwss.cursor_lock(dc, pipe_to_program, true);
343 }
344
345 dc->hwss.set_cursor_position(pipe_ctx);
346 if (dc->ctx->dmub_srv)
347 dc_send_update_cursor_info_to_dmu(pipe_ctx, i);
348 }
349
350 if (pipe_to_program)
351 dc->hwss.cursor_lock(dc, pipe_to_program, false);
352 }
353
dc_stream_set_cursor_position(struct dc_stream_state * stream,const struct dc_cursor_position * position)354 bool dc_stream_set_cursor_position(
355 struct dc_stream_state *stream,
356 const struct dc_cursor_position *position)
357 {
358 struct dc *dc;
359 bool reset_idle_optimizations = false;
360
361 if (NULL == stream) {
362 dm_error("DC: dc_stream is NULL!\n");
363 return false;
364 }
365
366 if (NULL == position) {
367 dm_error("DC: cursor position is NULL!\n");
368 return false;
369 }
370
371 dc = stream->ctx->dc;
372 dc_z10_restore(dc);
373
374 /* disable idle optimizations if enabling cursor */
375 if (dc->idle_optimizations_allowed && (!stream->cursor_position.enable || dc->debug.exit_idle_opt_for_cursor_updates)
376 && position->enable) {
377 dc_allow_idle_optimizations(dc, false);
378 reset_idle_optimizations = true;
379 }
380
381 stream->cursor_position = *position;
382
383 program_cursor_position(dc, stream, position);
384 /* re-enable idle optimizations if necessary */
385 if (reset_idle_optimizations && !dc->debug.disable_dmub_reallow_idle)
386 dc_allow_idle_optimizations(dc, true);
387
388 return true;
389 }
390
dc_stream_add_writeback(struct dc * dc,struct dc_stream_state * stream,struct dc_writeback_info * wb_info)391 bool dc_stream_add_writeback(struct dc *dc,
392 struct dc_stream_state *stream,
393 struct dc_writeback_info *wb_info)
394 {
395 bool isDrc = false;
396 int i = 0;
397 struct dwbc *dwb;
398
399 if (stream == NULL) {
400 dm_error("DC: dc_stream is NULL!\n");
401 return false;
402 }
403
404 if (wb_info == NULL) {
405 dm_error("DC: dc_writeback_info is NULL!\n");
406 return false;
407 }
408
409 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) {
410 dm_error("DC: writeback pipe is invalid!\n");
411 return false;
412 }
413
414 dc_exit_ips_for_hw_access(dc);
415
416 wb_info->dwb_params.out_transfer_func = &stream->out_transfer_func;
417
418 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
419 dwb->dwb_is_drc = false;
420
421 /* recalculate and apply DML parameters */
422
423 for (i = 0; i < stream->num_wb_info; i++) {
424 /*dynamic update*/
425 if (stream->writeback_info[i].wb_enabled &&
426 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) {
427 stream->writeback_info[i] = *wb_info;
428 isDrc = true;
429 }
430 }
431
432 if (!isDrc) {
433 ASSERT(stream->num_wb_info + 1 <= MAX_DWB_PIPES);
434 stream->writeback_info[stream->num_wb_info++] = *wb_info;
435 }
436
437 if (dc->hwss.enable_writeback) {
438 struct dc_stream_status *stream_status = dc_stream_get_status(stream);
439 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
440 if (stream_status)
441 dwb->otg_inst = stream_status->primary_otg_inst;
442 }
443
444 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
445 dm_error("DC: update_bandwidth failed!\n");
446 return false;
447 }
448
449 /* enable writeback */
450 if (dc->hwss.enable_writeback) {
451 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
452
453 if (dwb->funcs->is_enabled(dwb)) {
454 /* writeback pipe already enabled, only need to update */
455 dc->hwss.update_writeback(dc, wb_info, dc->current_state);
456 } else {
457 /* Enable writeback pipe from scratch*/
458 dc->hwss.enable_writeback(dc, wb_info, dc->current_state);
459 }
460 }
461
462 return true;
463 }
464
dc_stream_fc_disable_writeback(struct dc * dc,struct dc_stream_state * stream,uint32_t dwb_pipe_inst)465 bool dc_stream_fc_disable_writeback(struct dc *dc,
466 struct dc_stream_state *stream,
467 uint32_t dwb_pipe_inst)
468 {
469 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];
470
471 if (stream == NULL) {
472 dm_error("DC: dc_stream is NULL!\n");
473 return false;
474 }
475
476 if (dwb_pipe_inst >= MAX_DWB_PIPES) {
477 dm_error("DC: writeback pipe is invalid!\n");
478 return false;
479 }
480
481 if (stream->num_wb_info > MAX_DWB_PIPES) {
482 dm_error("DC: num_wb_info is invalid!\n");
483 return false;
484 }
485
486 dc_exit_ips_for_hw_access(dc);
487
488 if (dwb->funcs->set_fc_enable)
489 dwb->funcs->set_fc_enable(dwb, DWB_FRAME_CAPTURE_DISABLE);
490
491 return true;
492 }
493
dc_stream_remove_writeback(struct dc * dc,struct dc_stream_state * stream,uint32_t dwb_pipe_inst)494 bool dc_stream_remove_writeback(struct dc *dc,
495 struct dc_stream_state *stream,
496 uint32_t dwb_pipe_inst)
497 {
498 unsigned int i, j;
499 if (stream == NULL) {
500 dm_error("DC: dc_stream is NULL!\n");
501 return false;
502 }
503
504 if (dwb_pipe_inst >= MAX_DWB_PIPES) {
505 dm_error("DC: writeback pipe is invalid!\n");
506 return false;
507 }
508
509 if (stream->num_wb_info > MAX_DWB_PIPES) {
510 dm_error("DC: num_wb_info is invalid!\n");
511 return false;
512 }
513
514 /* remove writeback info for disabled writeback pipes from stream */
515 for (i = 0, j = 0; i < stream->num_wb_info; i++) {
516 if (stream->writeback_info[i].wb_enabled) {
517
518 if (stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst)
519 stream->writeback_info[i].wb_enabled = false;
520
521 /* trim the array */
522 if (j < i) {
523 memcpy(&stream->writeback_info[j], &stream->writeback_info[i],
524 sizeof(struct dc_writeback_info));
525 j++;
526 }
527 }
528 }
529 stream->num_wb_info = j;
530
531 /* recalculate and apply DML parameters */
532 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
533 dm_error("DC: update_bandwidth failed!\n");
534 return false;
535 }
536
537 dc_exit_ips_for_hw_access(dc);
538
539 /* disable writeback */
540 if (dc->hwss.disable_writeback) {
541 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];
542
543 if (dwb->funcs->is_enabled(dwb))
544 dc->hwss.disable_writeback(dc, dwb_pipe_inst);
545 }
546
547 return true;
548 }
549
dc_stream_warmup_writeback(struct dc * dc,int num_dwb,struct dc_writeback_info * wb_info)550 bool dc_stream_warmup_writeback(struct dc *dc,
551 int num_dwb,
552 struct dc_writeback_info *wb_info)
553 {
554 dc_exit_ips_for_hw_access(dc);
555
556 if (dc->hwss.mmhubbub_warmup)
557 return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info);
558 else
559 return false;
560 }
dc_stream_get_vblank_counter(const struct dc_stream_state * stream)561 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
562 {
563 uint8_t i;
564 struct dc *dc = stream->ctx->dc;
565 struct resource_context *res_ctx =
566 &dc->current_state->res_ctx;
567
568 dc_exit_ips_for_hw_access(dc);
569
570 for (i = 0; i < MAX_PIPES; i++) {
571 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
572
573 if (res_ctx->pipe_ctx[i].stream != stream || !tg)
574 continue;
575
576 return tg->funcs->get_frame_count(tg);
577 }
578
579 return 0;
580 }
581
dc_stream_send_dp_sdp(const struct dc_stream_state * stream,const uint8_t * custom_sdp_message,unsigned int sdp_message_size)582 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
583 const uint8_t *custom_sdp_message,
584 unsigned int sdp_message_size)
585 {
586 int i;
587 struct dc *dc;
588 struct resource_context *res_ctx;
589
590 if (stream == NULL) {
591 dm_error("DC: dc_stream is NULL!\n");
592 return false;
593 }
594
595 dc = stream->ctx->dc;
596 res_ctx = &dc->current_state->res_ctx;
597
598 dc_exit_ips_for_hw_access(dc);
599
600 for (i = 0; i < MAX_PIPES; i++) {
601 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
602
603 if (pipe_ctx->stream != stream)
604 continue;
605
606 if (dc->hwss.send_immediate_sdp_message != NULL)
607 dc->hwss.send_immediate_sdp_message(pipe_ctx,
608 custom_sdp_message,
609 sdp_message_size);
610 else
611 DC_LOG_WARNING("%s:send_immediate_sdp_message not implemented on this ASIC\n",
612 __func__);
613
614 }
615
616 return true;
617 }
618
dc_stream_get_scanoutpos(const struct dc_stream_state * stream,uint32_t * v_blank_start,uint32_t * v_blank_end,uint32_t * h_position,uint32_t * v_position)619 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
620 uint32_t *v_blank_start,
621 uint32_t *v_blank_end,
622 uint32_t *h_position,
623 uint32_t *v_position)
624 {
625 uint8_t i;
626 bool ret = false;
627 struct dc *dc = stream->ctx->dc;
628 struct resource_context *res_ctx =
629 &dc->current_state->res_ctx;
630
631 dc_exit_ips_for_hw_access(dc);
632
633 for (i = 0; i < MAX_PIPES; i++) {
634 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
635
636 if (res_ctx->pipe_ctx[i].stream != stream || !tg)
637 continue;
638
639 tg->funcs->get_scanoutpos(tg,
640 v_blank_start,
641 v_blank_end,
642 h_position,
643 v_position);
644
645 ret = true;
646 break;
647 }
648
649 return ret;
650 }
651
dc_stream_dmdata_status_done(struct dc * dc,struct dc_stream_state * stream)652 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
653 {
654 struct pipe_ctx *pipe = NULL;
655 int i;
656
657 if (!dc->hwss.dmdata_status_done)
658 return false;
659
660 for (i = 0; i < MAX_PIPES; i++) {
661 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
662 if (pipe->stream == stream)
663 break;
664 }
665 /* Stream not found, by default we'll assume HUBP fetched dm data */
666 if (i == MAX_PIPES)
667 return true;
668
669 dc_exit_ips_for_hw_access(dc);
670
671 return dc->hwss.dmdata_status_done(pipe);
672 }
673
dc_stream_set_dynamic_metadata(struct dc * dc,struct dc_stream_state * stream,struct dc_dmdata_attributes * attr)674 bool dc_stream_set_dynamic_metadata(struct dc *dc,
675 struct dc_stream_state *stream,
676 struct dc_dmdata_attributes *attr)
677 {
678 struct pipe_ctx *pipe_ctx = NULL;
679 struct hubp *hubp;
680 int i;
681
682 /* Dynamic metadata is only supported on HDMI or DP */
683 if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal))
684 return false;
685
686 /* Check hardware support */
687 if (!dc->hwss.program_dmdata_engine)
688 return false;
689
690 for (i = 0; i < MAX_PIPES; i++) {
691 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
692 if (pipe_ctx->stream == stream)
693 break;
694 }
695
696 if (i == MAX_PIPES)
697 return false;
698
699 hubp = pipe_ctx->plane_res.hubp;
700 if (hubp == NULL)
701 return false;
702
703 pipe_ctx->stream->dmdata_address = attr->address;
704
705 dc_exit_ips_for_hw_access(dc);
706
707 dc->hwss.program_dmdata_engine(pipe_ctx);
708
709 if (hubp->funcs->dmdata_set_attributes != NULL &&
710 pipe_ctx->stream->dmdata_address.quad_part != 0) {
711 hubp->funcs->dmdata_set_attributes(hubp, attr);
712 }
713
714 return true;
715 }
716
dc_stream_add_dsc_to_resource(struct dc * dc,struct dc_state * state,struct dc_stream_state * stream)717 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,
718 struct dc_state *state,
719 struct dc_stream_state *stream)
720 {
721 if (dc->res_pool->funcs->add_dsc_to_stream_resource) {
722 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream);
723 } else {
724 return DC_NO_DSC_RESOURCE;
725 }
726 }
727
dc_stream_get_pipe_ctx(struct dc_stream_state * stream)728 struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream)
729 {
730 int i = 0;
731
732 for (i = 0; i < MAX_PIPES; i++) {
733 struct pipe_ctx *pipe = &stream->ctx->dc->current_state->res_ctx.pipe_ctx[i];
734
735 if (pipe->stream == stream)
736 return pipe;
737 }
738
739 return NULL;
740 }
741
dc_stream_log(const struct dc * dc,const struct dc_stream_state * stream)742 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
743 {
744 DC_LOG_DC(
745 "core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n",
746 stream,
747 stream->src.x,
748 stream->src.y,
749 stream->src.width,
750 stream->src.height,
751 stream->dst.x,
752 stream->dst.y,
753 stream->dst.width,
754 stream->dst.height,
755 stream->output_color_space);
756 DC_LOG_DC(
757 "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
758 stream->timing.pix_clk_100hz / 10,
759 stream->timing.h_total,
760 stream->timing.v_total,
761 stream->timing.pixel_encoding,
762 stream->timing.display_color_depth);
763 DC_LOG_DC(
764 "\tlink: %d\n",
765 stream->link->link_index);
766
767 DC_LOG_DC(
768 "\tdsc: %d, mst_pbn: %d\n",
769 stream->timing.flags.DSC,
770 stream->timing.dsc_cfg.mst_pbn);
771
772 if (stream->sink) {
773 if (stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
774 stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
775
776 DC_LOG_DC(
777 "\tdispname: %s signal: %x\n",
778 stream->sink->edid_caps.display_name,
779 stream->signal);
780 }
781 }
782 }
783
784