1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "link_encoder.h"
29 #include "stream_encoder.h"
30
31 #include "resource.h"
32 #include "dce110/dce110_resource.h"
33
34 #include "include/irq_service_interface.h"
35 #include "dce/dce_audio.h"
36 #include "dce110/dce110_timing_generator.h"
37 #include "irq/dce110/irq_service_dce110.h"
38 #include "dce110/dce110_timing_generator_v.h"
39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_mem_input.h"
42 #include "dce110/dce110_mem_input_v.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_transform.h"
45 #include "dce110/dce110_transform_v.h"
46 #include "dce/dce_opp.h"
47 #include "dce110/dce110_opp_v.h"
48 #include "dce/dce_clocks.h"
49 #include "dce/dce_clock_source.h"
50 #include "dce/dce_hwseq.h"
51 #include "dce110/dce110_hw_sequencer.h"
52 #include "dce/dce_aux.h"
53 #include "dce/dce_abm.h"
54 #include "dce/dce_dmcu.h"
55
56 #define DC_LOGGER \
57 dc->ctx->logger
58
59 #include "dce110/dce110_compressor.h"
60
61 #include "reg_helper.h"
62
63 #include "dce/dce_11_0_d.h"
64 #include "dce/dce_11_0_sh_mask.h"
65
66 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
67 #include "gmc/gmc_8_2_d.h"
68 #include "gmc/gmc_8_2_sh_mask.h"
69 #endif
70
71 #ifndef mmDP_DPHY_INTERNAL_CTRL
72 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
73 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
75 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
76 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
77 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
78 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
79 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
80 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
81 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
82 #endif
83
84 #ifndef mmBIOS_SCRATCH_2
85 #define mmBIOS_SCRATCH_2 0x05CB
86 #define mmBIOS_SCRATCH_6 0x05CF
87 #endif
88
89 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
90 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
91 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
92 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
93 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
94 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
95 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
96 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
97 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
98 #endif
99
100 #ifndef mmDP_DPHY_FAST_TRAINING
101 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
102 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
103 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
104 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
105 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
106 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
107 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
108 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
109 #endif
110
111 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE
112 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1
113 #endif
114
115 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
116 {
117 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
118 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
119 },
120 {
121 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
122 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
123 },
124 {
125 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
126 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
127 },
128 {
129 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
130 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
131 },
132 {
133 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
134 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
135 },
136 {
137 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
138 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
139 }
140 };
141
142 /* set register offset */
143 #define SR(reg_name)\
144 .reg_name = mm ## reg_name
145
146 /* set register offset with instance */
147 #define SRI(reg_name, block, id)\
148 .reg_name = mm ## block ## id ## _ ## reg_name
149
150 static const struct dccg_registers disp_clk_regs = {
151 CLK_COMMON_REG_LIST_DCE_BASE()
152 };
153
154 static const struct dccg_shift disp_clk_shift = {
155 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
156 };
157
158 static const struct dccg_mask disp_clk_mask = {
159 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
160 };
161
162 static const struct dce_dmcu_registers dmcu_regs = {
163 DMCU_DCE110_COMMON_REG_LIST()
164 };
165
166 static const struct dce_dmcu_shift dmcu_shift = {
167 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
168 };
169
170 static const struct dce_dmcu_mask dmcu_mask = {
171 DMCU_MASK_SH_LIST_DCE110(_MASK)
172 };
173
174 static const struct dce_abm_registers abm_regs = {
175 ABM_DCE110_COMMON_REG_LIST()
176 };
177
178 static const struct dce_abm_shift abm_shift = {
179 ABM_MASK_SH_LIST_DCE110(__SHIFT)
180 };
181
182 static const struct dce_abm_mask abm_mask = {
183 ABM_MASK_SH_LIST_DCE110(_MASK)
184 };
185
186 #define ipp_regs(id)\
187 [id] = {\
188 IPP_DCE110_REG_LIST_DCE_BASE(id)\
189 }
190
191 static const struct dce_ipp_registers ipp_regs[] = {
192 ipp_regs(0),
193 ipp_regs(1),
194 ipp_regs(2)
195 };
196
197 static const struct dce_ipp_shift ipp_shift = {
198 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
199 };
200
201 static const struct dce_ipp_mask ipp_mask = {
202 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
203 };
204
205 #define transform_regs(id)\
206 [id] = {\
207 XFM_COMMON_REG_LIST_DCE110(id)\
208 }
209
210 static const struct dce_transform_registers xfm_regs[] = {
211 transform_regs(0),
212 transform_regs(1),
213 transform_regs(2)
214 };
215
216 static const struct dce_transform_shift xfm_shift = {
217 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
218 };
219
220 static const struct dce_transform_mask xfm_mask = {
221 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
222 };
223
224 #define aux_regs(id)\
225 [id] = {\
226 AUX_REG_LIST(id)\
227 }
228
229 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
230 aux_regs(0),
231 aux_regs(1),
232 aux_regs(2),
233 aux_regs(3),
234 aux_regs(4),
235 aux_regs(5)
236 };
237
238 #define hpd_regs(id)\
239 [id] = {\
240 HPD_REG_LIST(id)\
241 }
242
243 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
244 hpd_regs(0),
245 hpd_regs(1),
246 hpd_regs(2),
247 hpd_regs(3),
248 hpd_regs(4),
249 hpd_regs(5)
250 };
251
252
253 #define link_regs(id)\
254 [id] = {\
255 LE_DCE110_REG_LIST(id)\
256 }
257
258 static const struct dce110_link_enc_registers link_enc_regs[] = {
259 link_regs(0),
260 link_regs(1),
261 link_regs(2),
262 link_regs(3),
263 link_regs(4),
264 link_regs(5),
265 link_regs(6),
266 };
267
268 #define stream_enc_regs(id)\
269 [id] = {\
270 SE_COMMON_REG_LIST(id),\
271 .TMDS_CNTL = 0,\
272 }
273
274 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
275 stream_enc_regs(0),
276 stream_enc_regs(1),
277 stream_enc_regs(2)
278 };
279
280 static const struct dce_stream_encoder_shift se_shift = {
281 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
282 };
283
284 static const struct dce_stream_encoder_mask se_mask = {
285 SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
286 };
287
288 #define opp_regs(id)\
289 [id] = {\
290 OPP_DCE_110_REG_LIST(id),\
291 }
292
293 static const struct dce_opp_registers opp_regs[] = {
294 opp_regs(0),
295 opp_regs(1),
296 opp_regs(2),
297 opp_regs(3),
298 opp_regs(4),
299 opp_regs(5)
300 };
301
302 static const struct dce_opp_shift opp_shift = {
303 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT)
304 };
305
306 static const struct dce_opp_mask opp_mask = {
307 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK)
308 };
309
310 #define aux_engine_regs(id)\
311 [id] = {\
312 AUX_COMMON_REG_LIST(id), \
313 .AUX_RESET_MASK = 0 \
314 }
315
316 static const struct dce110_aux_registers aux_engine_regs[] = {
317 aux_engine_regs(0),
318 aux_engine_regs(1),
319 aux_engine_regs(2),
320 aux_engine_regs(3),
321 aux_engine_regs(4),
322 aux_engine_regs(5)
323 };
324
325 #define audio_regs(id)\
326 [id] = {\
327 AUD_COMMON_REG_LIST(id)\
328 }
329
330 static const struct dce_audio_registers audio_regs[] = {
331 audio_regs(0),
332 audio_regs(1),
333 audio_regs(2),
334 audio_regs(3),
335 audio_regs(4),
336 audio_regs(5),
337 audio_regs(6),
338 };
339
340 static const struct dce_audio_shift audio_shift = {
341 AUD_COMMON_MASK_SH_LIST(__SHIFT)
342 };
343
344 static const struct dce_aduio_mask audio_mask = {
345 AUD_COMMON_MASK_SH_LIST(_MASK)
346 };
347
348 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
349
350
351 #define clk_src_regs(id)\
352 [id] = {\
353 CS_COMMON_REG_LIST_DCE_100_110(id),\
354 }
355
356 static const struct dce110_clk_src_regs clk_src_regs[] = {
357 clk_src_regs(0),
358 clk_src_regs(1),
359 clk_src_regs(2)
360 };
361
362 static const struct dce110_clk_src_shift cs_shift = {
363 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
364 };
365
366 static const struct dce110_clk_src_mask cs_mask = {
367 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
368 };
369
370 static const struct bios_registers bios_regs = {
371 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
372 };
373
374 static const struct resource_caps carrizo_resource_cap = {
375 .num_timing_generator = 3,
376 .num_video_plane = 1,
377 .num_audio = 3,
378 .num_stream_encoder = 3,
379 .num_pll = 2,
380 };
381
382 static const struct resource_caps stoney_resource_cap = {
383 .num_timing_generator = 2,
384 .num_video_plane = 1,
385 .num_audio = 3,
386 .num_stream_encoder = 3,
387 .num_pll = 2,
388 };
389
390 #define CTX ctx
391 #define REG(reg) mm ## reg
392
393 #ifndef mmCC_DC_HDMI_STRAPS
394 #define mmCC_DC_HDMI_STRAPS 0x4819
395 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
396 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
397 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
398 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
399 #endif
400
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)401 static void read_dce_straps(
402 struct dc_context *ctx,
403 struct resource_straps *straps)
404 {
405 REG_GET_2(CC_DC_HDMI_STRAPS,
406 HDMI_DISABLE, &straps->hdmi_disable,
407 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
408
409 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
410 }
411
create_audio(struct dc_context * ctx,unsigned int inst)412 static struct audio *create_audio(
413 struct dc_context *ctx, unsigned int inst)
414 {
415 return dce_audio_create(ctx, inst,
416 &audio_regs[inst], &audio_shift, &audio_mask);
417 }
418
dce110_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)419 static struct timing_generator *dce110_timing_generator_create(
420 struct dc_context *ctx,
421 uint32_t instance,
422 const struct dce110_timing_generator_offsets *offsets)
423 {
424 struct dce110_timing_generator *tg110 =
425 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
426
427 if (!tg110)
428 return NULL;
429
430 dce110_timing_generator_construct(tg110, ctx, instance, offsets);
431 return &tg110->base;
432 }
433
dce110_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)434 static struct stream_encoder *dce110_stream_encoder_create(
435 enum engine_id eng_id,
436 struct dc_context *ctx)
437 {
438 struct dce110_stream_encoder *enc110 =
439 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
440
441 if (!enc110)
442 return NULL;
443
444 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
445 &stream_enc_regs[eng_id],
446 &se_shift, &se_mask);
447 return &enc110->base;
448 }
449
450 #define SRII(reg_name, block, id)\
451 .reg_name[id] = mm ## block ## id ## _ ## reg_name
452
453 static const struct dce_hwseq_registers hwseq_stoney_reg = {
454 HWSEQ_ST_REG_LIST()
455 };
456
457 static const struct dce_hwseq_registers hwseq_cz_reg = {
458 HWSEQ_CZ_REG_LIST()
459 };
460
461 static const struct dce_hwseq_shift hwseq_shift = {
462 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT),
463 };
464
465 static const struct dce_hwseq_mask hwseq_mask = {
466 HWSEQ_DCE11_MASK_SH_LIST(_MASK),
467 };
468
dce110_hwseq_create(struct dc_context * ctx)469 static struct dce_hwseq *dce110_hwseq_create(
470 struct dc_context *ctx)
471 {
472 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
473
474 if (hws) {
475 hws->ctx = ctx;
476 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
477 &hwseq_stoney_reg : &hwseq_cz_reg;
478 hws->shifts = &hwseq_shift;
479 hws->masks = &hwseq_mask;
480 hws->wa.blnd_crtc_trigger = true;
481 }
482 return hws;
483 }
484
485 static const struct resource_create_funcs res_create_funcs = {
486 .read_dce_straps = read_dce_straps,
487 .create_audio = create_audio,
488 .create_stream_encoder = dce110_stream_encoder_create,
489 .create_hwseq = dce110_hwseq_create,
490 };
491
492 #define mi_inst_regs(id) { \
493 MI_DCE11_REG_LIST(id), \
494 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
495 }
496 static const struct dce_mem_input_registers mi_regs[] = {
497 mi_inst_regs(0),
498 mi_inst_regs(1),
499 mi_inst_regs(2),
500 };
501
502 static const struct dce_mem_input_shift mi_shifts = {
503 MI_DCE11_MASK_SH_LIST(__SHIFT),
504 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
505 };
506
507 static const struct dce_mem_input_mask mi_masks = {
508 MI_DCE11_MASK_SH_LIST(_MASK),
509 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
510 };
511
512
dce110_mem_input_create(struct dc_context * ctx,uint32_t inst)513 static struct mem_input *dce110_mem_input_create(
514 struct dc_context *ctx,
515 uint32_t inst)
516 {
517 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
518 GFP_KERNEL);
519
520 if (!dce_mi) {
521 BREAK_TO_DEBUGGER();
522 return NULL;
523 }
524
525 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
526 dce_mi->wa.single_head_rdreq_dmif_limit = 3;
527 return &dce_mi->base;
528 }
529
dce110_transform_destroy(struct transform ** xfm)530 static void dce110_transform_destroy(struct transform **xfm)
531 {
532 kfree(TO_DCE_TRANSFORM(*xfm));
533 *xfm = NULL;
534 }
535
dce110_transform_create(struct dc_context * ctx,uint32_t inst)536 static struct transform *dce110_transform_create(
537 struct dc_context *ctx,
538 uint32_t inst)
539 {
540 struct dce_transform *transform =
541 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
542
543 if (!transform)
544 return NULL;
545
546 dce_transform_construct(transform, ctx, inst,
547 &xfm_regs[inst], &xfm_shift, &xfm_mask);
548 return &transform->base;
549 }
550
dce110_ipp_create(struct dc_context * ctx,uint32_t inst)551 static struct input_pixel_processor *dce110_ipp_create(
552 struct dc_context *ctx, uint32_t inst)
553 {
554 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
555
556 if (!ipp) {
557 BREAK_TO_DEBUGGER();
558 return NULL;
559 }
560
561 dce_ipp_construct(ipp, ctx, inst,
562 &ipp_regs[inst], &ipp_shift, &ipp_mask);
563 return &ipp->base;
564 }
565
566 static const struct encoder_feature_support link_enc_feature = {
567 .max_hdmi_deep_color = COLOR_DEPTH_121212,
568 .max_hdmi_pixel_clock = 594000,
569 .flags.bits.IS_HBR2_CAPABLE = true,
570 .flags.bits.IS_TPS3_CAPABLE = true,
571 .flags.bits.IS_YCBCR_CAPABLE = true
572 };
573
dce110_link_encoder_create(const struct encoder_init_data * enc_init_data)574 static struct link_encoder *dce110_link_encoder_create(
575 const struct encoder_init_data *enc_init_data)
576 {
577 struct dce110_link_encoder *enc110 =
578 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
579
580 if (!enc110)
581 return NULL;
582
583 dce110_link_encoder_construct(enc110,
584 enc_init_data,
585 &link_enc_feature,
586 &link_enc_regs[enc_init_data->transmitter],
587 &link_enc_aux_regs[enc_init_data->channel - 1],
588 &link_enc_hpd_regs[enc_init_data->hpd_source]);
589 return &enc110->base;
590 }
591
dce110_opp_create(struct dc_context * ctx,uint32_t inst)592 static struct output_pixel_processor *dce110_opp_create(
593 struct dc_context *ctx,
594 uint32_t inst)
595 {
596 struct dce110_opp *opp =
597 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
598
599 if (!opp)
600 return NULL;
601
602 dce110_opp_construct(opp,
603 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
604 return &opp->base;
605 }
606
607 static
dce110_aux_engine_create(struct dc_context * ctx,uint32_t inst)608 struct aux_engine *dce110_aux_engine_create(
609 struct dc_context *ctx,
610 uint32_t inst)
611 {
612 struct aux_engine_dce110 *aux_engine =
613 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
614
615 if (!aux_engine)
616 return NULL;
617
618 dce110_aux_engine_construct(aux_engine, ctx, inst,
619 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
620 &aux_engine_regs[inst]);
621
622 return &aux_engine->base;
623 }
624
625 static
dce110_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)626 struct clock_source *dce110_clock_source_create(
627 struct dc_context *ctx,
628 struct dc_bios *bios,
629 enum clock_source_id id,
630 const struct dce110_clk_src_regs *regs,
631 bool dp_clk_src)
632 {
633 struct dce110_clk_src *clk_src =
634 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
635
636 if (!clk_src)
637 return NULL;
638
639 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
640 regs, &cs_shift, &cs_mask)) {
641 clk_src->base.dp_clk_src = dp_clk_src;
642 return &clk_src->base;
643 }
644
645 BREAK_TO_DEBUGGER();
646 return NULL;
647 }
648
649 static
dce110_clock_source_destroy(struct clock_source ** clk_src)650 void dce110_clock_source_destroy(struct clock_source **clk_src)
651 {
652 struct dce110_clk_src *dce110_clk_src;
653
654 if (!clk_src)
655 return;
656
657 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src);
658
659 kfree(dce110_clk_src->dp_ss_params);
660 kfree(dce110_clk_src->hdmi_ss_params);
661 kfree(dce110_clk_src->dvi_ss_params);
662
663 kfree(dce110_clk_src);
664 *clk_src = NULL;
665 }
666
destruct(struct dce110_resource_pool * pool)667 static void destruct(struct dce110_resource_pool *pool)
668 {
669 unsigned int i;
670
671 for (i = 0; i < pool->base.pipe_count; i++) {
672 if (pool->base.opps[i] != NULL)
673 dce110_opp_destroy(&pool->base.opps[i]);
674
675 if (pool->base.transforms[i] != NULL)
676 dce110_transform_destroy(&pool->base.transforms[i]);
677
678 if (pool->base.ipps[i] != NULL)
679 dce_ipp_destroy(&pool->base.ipps[i]);
680
681 if (pool->base.mis[i] != NULL) {
682 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
683 pool->base.mis[i] = NULL;
684 }
685
686 if (pool->base.timing_generators[i] != NULL) {
687 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
688 pool->base.timing_generators[i] = NULL;
689 }
690
691 if (pool->base.engines[i] != NULL)
692 dce110_engine_destroy(&pool->base.engines[i]);
693
694 }
695
696 for (i = 0; i < pool->base.stream_enc_count; i++) {
697 if (pool->base.stream_enc[i] != NULL)
698 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
699 }
700
701 for (i = 0; i < pool->base.clk_src_count; i++) {
702 if (pool->base.clock_sources[i] != NULL) {
703 dce110_clock_source_destroy(&pool->base.clock_sources[i]);
704 }
705 }
706
707 if (pool->base.dp_clock_source != NULL)
708 dce110_clock_source_destroy(&pool->base.dp_clock_source);
709
710 for (i = 0; i < pool->base.audio_count; i++) {
711 if (pool->base.audios[i] != NULL) {
712 dce_aud_destroy(&pool->base.audios[i]);
713 }
714 }
715
716 if (pool->base.abm != NULL)
717 dce_abm_destroy(&pool->base.abm);
718
719 if (pool->base.dmcu != NULL)
720 dce_dmcu_destroy(&pool->base.dmcu);
721
722 if (pool->base.dccg != NULL)
723 dce_dccg_destroy(&pool->base.dccg);
724
725 if (pool->base.irqs != NULL) {
726 dal_irq_service_destroy(&pool->base.irqs);
727 }
728 }
729
730
get_pixel_clock_parameters(const struct pipe_ctx * pipe_ctx,struct pixel_clk_params * pixel_clk_params)731 static void get_pixel_clock_parameters(
732 const struct pipe_ctx *pipe_ctx,
733 struct pixel_clk_params *pixel_clk_params)
734 {
735 const struct dc_stream_state *stream = pipe_ctx->stream;
736
737 /*TODO: is this halved for YCbCr 420? in that case we might want to move
738 * the pixel clock normalization for hdmi up to here instead of doing it
739 * in pll_adjust_pix_clk
740 */
741 pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
742 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
743 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
744 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
745 /* TODO: un-hardcode*/
746 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
747 LINK_RATE_REF_FREQ_IN_KHZ;
748 pixel_clk_params->flags.ENABLE_SS = 0;
749 pixel_clk_params->color_depth =
750 stream->timing.display_color_depth;
751 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
752 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding ==
753 PIXEL_ENCODING_YCBCR420);
754 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
755 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
756 pixel_clk_params->color_depth = COLOR_DEPTH_888;
757 }
758 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
759 pixel_clk_params->requested_pix_clk = pixel_clk_params->requested_pix_clk / 2;
760 }
761 }
762
dce110_resource_build_pipe_hw_param(struct pipe_ctx * pipe_ctx)763 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
764 {
765 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
766 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
767 pipe_ctx->clock_source,
768 &pipe_ctx->stream_res.pix_clk_params,
769 &pipe_ctx->pll_settings);
770 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
771 &pipe_ctx->stream->bit_depth_params);
772 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
773 }
774
is_surface_pixel_format_supported(struct pipe_ctx * pipe_ctx,unsigned int underlay_idx)775 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)
776 {
777 if (pipe_ctx->pipe_idx != underlay_idx)
778 return true;
779 if (!pipe_ctx->plane_state)
780 return false;
781 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
782 return false;
783 return true;
784 }
785
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)786 static enum dc_status build_mapped_resource(
787 const struct dc *dc,
788 struct dc_state *context,
789 struct dc_stream_state *stream)
790 {
791 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
792
793 if (!pipe_ctx)
794 return DC_ERROR_UNEXPECTED;
795
796 if (!is_surface_pixel_format_supported(pipe_ctx,
797 dc->res_pool->underlay_pipe_index))
798 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
799
800 dce110_resource_build_pipe_hw_param(pipe_ctx);
801
802 /* TODO: validate audio ASIC caps, encoder */
803
804 resource_build_info_frame(pipe_ctx);
805
806 return DC_OK;
807 }
808
dce110_validate_bandwidth(struct dc * dc,struct dc_state * context)809 static bool dce110_validate_bandwidth(
810 struct dc *dc,
811 struct dc_state *context)
812 {
813 bool result = false;
814
815 DC_LOG_BANDWIDTH_CALCS(
816 "%s: start",
817 __func__);
818
819 if (bw_calcs(
820 dc->ctx,
821 dc->bw_dceip,
822 dc->bw_vbios,
823 context->res_ctx.pipe_ctx,
824 dc->res_pool->pipe_count,
825 &context->bw.dce))
826 result = true;
827
828 if (!result)
829 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n",
830 __func__,
831 context->streams[0]->timing.h_addressable,
832 context->streams[0]->timing.v_addressable,
833 context->streams[0]->timing.pix_clk_khz);
834
835 if (memcmp(&dc->current_state->bw.dce,
836 &context->bw.dce, sizeof(context->bw.dce))) {
837
838 DC_LOG_BANDWIDTH_CALCS(
839 "%s: finish,\n"
840 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
841 "stutMark_b: %d stutMark_a: %d\n"
842 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
843 "stutMark_b: %d stutMark_a: %d\n"
844 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
845 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
846 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
847 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
848 ,
849 __func__,
850 context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
851 context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
852 context->bw.dce.urgent_wm_ns[0].b_mark,
853 context->bw.dce.urgent_wm_ns[0].a_mark,
854 context->bw.dce.stutter_exit_wm_ns[0].b_mark,
855 context->bw.dce.stutter_exit_wm_ns[0].a_mark,
856 context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
857 context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
858 context->bw.dce.urgent_wm_ns[1].b_mark,
859 context->bw.dce.urgent_wm_ns[1].a_mark,
860 context->bw.dce.stutter_exit_wm_ns[1].b_mark,
861 context->bw.dce.stutter_exit_wm_ns[1].a_mark,
862 context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
863 context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
864 context->bw.dce.urgent_wm_ns[2].b_mark,
865 context->bw.dce.urgent_wm_ns[2].a_mark,
866 context->bw.dce.stutter_exit_wm_ns[2].b_mark,
867 context->bw.dce.stutter_exit_wm_ns[2].a_mark,
868 context->bw.dce.stutter_mode_enable,
869 context->bw.dce.cpuc_state_change_enable,
870 context->bw.dce.cpup_state_change_enable,
871 context->bw.dce.nbp_state_change_enable,
872 context->bw.dce.all_displays_in_sync,
873 context->bw.dce.dispclk_khz,
874 context->bw.dce.sclk_khz,
875 context->bw.dce.sclk_deep_sleep_khz,
876 context->bw.dce.yclk_khz,
877 context->bw.dce.blackout_recovery_time_us);
878 }
879 return result;
880 }
881
882 static
dce110_validate_plane(const struct dc_plane_state * plane_state,struct dc_caps * caps)883 enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
884 struct dc_caps *caps)
885 {
886 if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) ||
887 ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))
888 return DC_FAIL_SURFACE_VALIDATE;
889
890 return DC_OK;
891 }
892
dce110_validate_surface_sets(struct dc_state * context)893 static bool dce110_validate_surface_sets(
894 struct dc_state *context)
895 {
896 int i, j;
897
898 for (i = 0; i < context->stream_count; i++) {
899 if (context->stream_status[i].plane_count == 0)
900 continue;
901
902 if (context->stream_status[i].plane_count > 2)
903 return false;
904
905 for (j = 0; j < context->stream_status[i].plane_count; j++) {
906 struct dc_plane_state *plane =
907 context->stream_status[i].plane_states[j];
908
909 /* underlay validation */
910 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
911
912 if ((plane->src_rect.width > 1920 ||
913 plane->src_rect.height > 1080))
914 return false;
915
916 /* we don't have the logic to support underlay
917 * only yet so block the use case where we get
918 * NV12 plane as top layer
919 */
920 if (j == 0)
921 return false;
922
923 /* irrespective of plane format,
924 * stream should be RGB encoded
925 */
926 if (context->streams[i]->timing.pixel_encoding
927 != PIXEL_ENCODING_RGB)
928 return false;
929
930 }
931
932 }
933 }
934
935 return true;
936 }
937
938 static
dce110_validate_global(struct dc * dc,struct dc_state * context)939 enum dc_status dce110_validate_global(
940 struct dc *dc,
941 struct dc_state *context)
942 {
943 if (!dce110_validate_surface_sets(context))
944 return DC_FAIL_SURFACE_VALIDATE;
945
946 return DC_OK;
947 }
948
dce110_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)949 static enum dc_status dce110_add_stream_to_ctx(
950 struct dc *dc,
951 struct dc_state *new_ctx,
952 struct dc_stream_state *dc_stream)
953 {
954 enum dc_status result = DC_ERROR_UNEXPECTED;
955
956 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
957
958 if (result == DC_OK)
959 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
960
961
962 if (result == DC_OK)
963 result = build_mapped_resource(dc, new_ctx, dc_stream);
964
965 return result;
966 }
967
dce110_acquire_underlay(struct dc_state * context,const struct resource_pool * pool,struct dc_stream_state * stream)968 static struct pipe_ctx *dce110_acquire_underlay(
969 struct dc_state *context,
970 const struct resource_pool *pool,
971 struct dc_stream_state *stream)
972 {
973 struct dc *dc = stream->ctx->dc;
974 struct resource_context *res_ctx = &context->res_ctx;
975 unsigned int underlay_idx = pool->underlay_pipe_index;
976 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];
977
978 if (res_ctx->pipe_ctx[underlay_idx].stream)
979 return NULL;
980
981 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];
982 pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
983 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
984 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
985 pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
986 pipe_ctx->pipe_idx = underlay_idx;
987
988 pipe_ctx->stream = stream;
989
990 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {
991 struct tg_color black_color = {0};
992 struct dc_bios *dcb = dc->ctx->dc_bios;
993
994 dc->hwss.enable_display_power_gating(
995 dc,
996 pipe_ctx->stream_res.tg->inst,
997 dcb, PIPE_GATING_CONTROL_DISABLE);
998
999 /*
1000 * This is for powering on underlay, so crtc does not
1001 * need to be enabled
1002 */
1003
1004 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,
1005 &stream->timing,
1006 false);
1007
1008 pipe_ctx->stream_res.tg->funcs->enable_advanced_request(
1009 pipe_ctx->stream_res.tg,
1010 true,
1011 &stream->timing);
1012
1013 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
1014 stream->timing.h_total,
1015 stream->timing.v_total,
1016 stream->timing.pix_clk_khz,
1017 context->stream_count);
1018
1019 color_space_to_black_color(dc,
1020 COLOR_SPACE_YCBCR601, &black_color);
1021 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1022 pipe_ctx->stream_res.tg,
1023 &black_color);
1024 }
1025
1026 return pipe_ctx;
1027 }
1028
dce110_destroy_resource_pool(struct resource_pool ** pool)1029 static void dce110_destroy_resource_pool(struct resource_pool **pool)
1030 {
1031 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1032
1033 destruct(dce110_pool);
1034 kfree(dce110_pool);
1035 *pool = NULL;
1036 }
1037
1038
1039 static const struct resource_funcs dce110_res_pool_funcs = {
1040 .destroy = dce110_destroy_resource_pool,
1041 .link_enc_create = dce110_link_encoder_create,
1042 .validate_bandwidth = dce110_validate_bandwidth,
1043 .validate_plane = dce110_validate_plane,
1044 .acquire_idle_pipe_for_layer = dce110_acquire_underlay,
1045 .add_stream_to_ctx = dce110_add_stream_to_ctx,
1046 .validate_global = dce110_validate_global
1047 };
1048
underlay_create(struct dc_context * ctx,struct resource_pool * pool)1049 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
1050 {
1051 struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv),
1052 GFP_KERNEL);
1053 struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv),
1054 GFP_KERNEL);
1055 struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv),
1056 GFP_KERNEL);
1057 struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv),
1058 GFP_KERNEL);
1059
1060 if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) {
1061 kfree(dce110_tgv);
1062 kfree(dce110_xfmv);
1063 kfree(dce110_miv);
1064 kfree(dce110_oppv);
1065 return false;
1066 }
1067
1068 dce110_opp_v_construct(dce110_oppv, ctx);
1069
1070 dce110_timing_generator_v_construct(dce110_tgv, ctx);
1071 dce110_mem_input_v_construct(dce110_miv, ctx);
1072 dce110_transform_v_construct(dce110_xfmv, ctx);
1073
1074 pool->opps[pool->pipe_count] = &dce110_oppv->base;
1075 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
1076 pool->mis[pool->pipe_count] = &dce110_miv->base;
1077 pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
1078 pool->pipe_count++;
1079
1080 /* update the public caps to indicate an underlay is available */
1081 ctx->dc->caps.max_slave_planes = 1;
1082 ctx->dc->caps.max_slave_planes = 1;
1083
1084 return true;
1085 }
1086
bw_calcs_data_update_from_pplib(struct dc * dc)1087 static void bw_calcs_data_update_from_pplib(struct dc *dc)
1088 {
1089 struct dm_pp_clock_levels clks = {0};
1090
1091 /*do system clock*/
1092 dm_pp_get_clock_levels_by_type(
1093 dc->ctx,
1094 DM_PP_CLOCK_TYPE_ENGINE_CLK,
1095 &clks);
1096 /* convert all the clock fro kHz to fix point mHz */
1097 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1098 clks.clocks_in_khz[clks.num_levels-1], 1000);
1099 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
1100 clks.clocks_in_khz[clks.num_levels/8], 1000);
1101 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
1102 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1103 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
1104 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1105 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
1106 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1107 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
1108 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1109 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
1110 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1111 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
1112 clks.clocks_in_khz[0], 1000);
1113 dc->sclk_lvls = clks;
1114
1115 /*do display clock*/
1116 dm_pp_get_clock_levels_by_type(
1117 dc->ctx,
1118 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1119 &clks);
1120 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(
1121 clks.clocks_in_khz[clks.num_levels-1], 1000);
1122 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed(
1123 clks.clocks_in_khz[clks.num_levels>>1], 1000);
1124 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed(
1125 clks.clocks_in_khz[0], 1000);
1126
1127 /*do memory clock*/
1128 dm_pp_get_clock_levels_by_type(
1129 dc->ctx,
1130 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1131 &clks);
1132
1133 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1134 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
1135 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1136 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
1137 1000);
1138 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1139 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
1140 1000);
1141 }
1142
1143 static
dce110_resource_cap(struct hw_asic_id * asic_id)1144 const struct resource_caps *dce110_resource_cap(
1145 struct hw_asic_id *asic_id)
1146 {
1147 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
1148 return &stoney_resource_cap;
1149 else
1150 return &carrizo_resource_cap;
1151 }
1152
construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool,struct hw_asic_id asic_id)1153 static bool construct(
1154 uint8_t num_virtual_links,
1155 struct dc *dc,
1156 struct dce110_resource_pool *pool,
1157 struct hw_asic_id asic_id)
1158 {
1159 unsigned int i;
1160 struct dc_context *ctx = dc->ctx;
1161 struct dc_firmware_info info;
1162 struct dc_bios *bp;
1163 struct dm_pp_static_clock_info static_clk_info = {0};
1164
1165 ctx->dc_bios->regs = &bios_regs;
1166
1167 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
1168 pool->base.funcs = &dce110_res_pool_funcs;
1169
1170 /*************************************************
1171 * Resource + asic cap harcoding *
1172 *************************************************/
1173
1174 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1175 pool->base.underlay_pipe_index = pool->base.pipe_count;
1176 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1177 dc->caps.max_downscale_ratio = 150;
1178 dc->caps.i2c_speed_in_khz = 100;
1179 dc->caps.max_cursor_size = 128;
1180 dc->caps.is_apu = true;
1181
1182 /*************************************************
1183 * Create resources *
1184 *************************************************/
1185
1186 bp = ctx->dc_bios;
1187
1188 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
1189 info.external_clock_source_frequency_for_dp != 0) {
1190 pool->base.dp_clock_source =
1191 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1192
1193 pool->base.clock_sources[0] =
1194 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0,
1195 &clk_src_regs[0], false);
1196 pool->base.clock_sources[1] =
1197 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1,
1198 &clk_src_regs[1], false);
1199
1200 pool->base.clk_src_count = 2;
1201
1202 /* TODO: find out if CZ support 3 PLLs */
1203 }
1204
1205 if (pool->base.dp_clock_source == NULL) {
1206 dm_error("DC: failed to create dp clock source!\n");
1207 BREAK_TO_DEBUGGER();
1208 goto res_create_fail;
1209 }
1210
1211 for (i = 0; i < pool->base.clk_src_count; i++) {
1212 if (pool->base.clock_sources[i] == NULL) {
1213 dm_error("DC: failed to create clock sources!\n");
1214 BREAK_TO_DEBUGGER();
1215 goto res_create_fail;
1216 }
1217 }
1218
1219 pool->base.dccg = dce110_dccg_create(ctx,
1220 &disp_clk_regs,
1221 &disp_clk_shift,
1222 &disp_clk_mask);
1223 if (pool->base.dccg == NULL) {
1224 dm_error("DC: failed to create display clock!\n");
1225 BREAK_TO_DEBUGGER();
1226 goto res_create_fail;
1227 }
1228
1229 pool->base.dmcu = dce_dmcu_create(ctx,
1230 &dmcu_regs,
1231 &dmcu_shift,
1232 &dmcu_mask);
1233 if (pool->base.dmcu == NULL) {
1234 dm_error("DC: failed to create dmcu!\n");
1235 BREAK_TO_DEBUGGER();
1236 goto res_create_fail;
1237 }
1238
1239 pool->base.abm = dce_abm_create(ctx,
1240 &abm_regs,
1241 &abm_shift,
1242 &abm_mask);
1243 if (pool->base.abm == NULL) {
1244 dm_error("DC: failed to create abm!\n");
1245 BREAK_TO_DEBUGGER();
1246 goto res_create_fail;
1247 }
1248
1249 /* get static clock information for PPLIB or firmware, save
1250 * max_clock_state
1251 */
1252 if (dm_pp_get_static_clocks(ctx, &static_clk_info))
1253 pool->base.dccg->max_clks_state =
1254 static_clk_info.max_clocks_state;
1255
1256 {
1257 struct irq_service_init_data init_data;
1258 init_data.ctx = dc->ctx;
1259 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1260 if (!pool->base.irqs)
1261 goto res_create_fail;
1262 }
1263
1264 for (i = 0; i < pool->base.pipe_count; i++) {
1265 pool->base.timing_generators[i] = dce110_timing_generator_create(
1266 ctx, i, &dce110_tg_offsets[i]);
1267 if (pool->base.timing_generators[i] == NULL) {
1268 BREAK_TO_DEBUGGER();
1269 dm_error("DC: failed to create tg!\n");
1270 goto res_create_fail;
1271 }
1272
1273 pool->base.mis[i] = dce110_mem_input_create(ctx, i);
1274 if (pool->base.mis[i] == NULL) {
1275 BREAK_TO_DEBUGGER();
1276 dm_error(
1277 "DC: failed to create memory input!\n");
1278 goto res_create_fail;
1279 }
1280
1281 pool->base.ipps[i] = dce110_ipp_create(ctx, i);
1282 if (pool->base.ipps[i] == NULL) {
1283 BREAK_TO_DEBUGGER();
1284 dm_error(
1285 "DC: failed to create input pixel processor!\n");
1286 goto res_create_fail;
1287 }
1288
1289 pool->base.transforms[i] = dce110_transform_create(ctx, i);
1290 if (pool->base.transforms[i] == NULL) {
1291 BREAK_TO_DEBUGGER();
1292 dm_error(
1293 "DC: failed to create transform!\n");
1294 goto res_create_fail;
1295 }
1296
1297 pool->base.opps[i] = dce110_opp_create(ctx, i);
1298 if (pool->base.opps[i] == NULL) {
1299 BREAK_TO_DEBUGGER();
1300 dm_error(
1301 "DC: failed to create output pixel processor!\n");
1302 goto res_create_fail;
1303 }
1304
1305 pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
1306 if (pool->base.engines[i] == NULL) {
1307 BREAK_TO_DEBUGGER();
1308 dm_error(
1309 "DC:failed to create aux engine!!\n");
1310 goto res_create_fail;
1311 }
1312 }
1313
1314 dc->fbc_compressor = dce110_compressor_create(ctx);
1315
1316 if (!underlay_create(ctx, &pool->base))
1317 goto res_create_fail;
1318
1319 if (!resource_construct(num_virtual_links, dc, &pool->base,
1320 &res_create_funcs))
1321 goto res_create_fail;
1322
1323 /* Create hardware sequencer */
1324 dce110_hw_sequencer_construct(dc);
1325
1326 dc->caps.max_planes = pool->base.pipe_count;
1327
1328 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1329
1330 bw_calcs_data_update_from_pplib(dc);
1331
1332 return true;
1333
1334 res_create_fail:
1335 destruct(pool);
1336 return false;
1337 }
1338
dce110_create_resource_pool(uint8_t num_virtual_links,struct dc * dc,struct hw_asic_id asic_id)1339 struct resource_pool *dce110_create_resource_pool(
1340 uint8_t num_virtual_links,
1341 struct dc *dc,
1342 struct hw_asic_id asic_id)
1343 {
1344 struct dce110_resource_pool *pool =
1345 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1346
1347 if (!pool)
1348 return NULL;
1349
1350 if (construct(num_virtual_links, dc, pool, asic_id))
1351 return &pool->base;
1352
1353 kfree(pool);
1354 BREAK_TO_DEBUGGER();
1355 return NULL;
1356 }
1357