1 /* $NetBSD: radeon_dce3_1_afmt.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */
2
3 /*
4 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Copyright 2014 Rafał Miłecki
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: radeon_dce3_1_afmt.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $");
27
28 #include <linux/hdmi.h>
29
30 #include "radeon.h"
31 #include "radeon_asic.h"
32 #include "radeon_audio.h"
33 #include "r600d.h"
34
dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder * encoder,u8 * sadb,int sad_count)35 void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
36 u8 *sadb, int sad_count)
37 {
38 struct radeon_device *rdev = encoder->dev->dev_private;
39 u32 tmp;
40
41 /* program the speaker allocation */
42 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
43 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
44 /* set HDMI mode */
45 tmp |= HDMI_CONNECTION;
46 if (sad_count)
47 tmp |= SPEAKER_ALLOCATION(sadb[0]);
48 else
49 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
50 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
51 }
52
dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder * encoder,u8 * sadb,int sad_count)53 void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
54 u8 *sadb, int sad_count)
55 {
56 struct radeon_device *rdev = encoder->dev->dev_private;
57 u32 tmp;
58
59 /* program the speaker allocation */
60 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
61 tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
62 /* set DP mode */
63 tmp |= DP_CONNECTION;
64 if (sad_count)
65 tmp |= SPEAKER_ALLOCATION(sadb[0]);
66 else
67 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
68 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
69 }
70
dce3_2_afmt_write_sad_regs(struct drm_encoder * encoder,struct cea_sad * sads,int sad_count)71 void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder,
72 struct cea_sad *sads, int sad_count)
73 {
74 int i;
75 struct radeon_device *rdev = encoder->dev->dev_private;
76 static const u16 eld_reg_to_type[][2] = {
77 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
78 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
79 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
80 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
81 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
82 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
83 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
84 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
85 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
86 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
87 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
88 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
89 };
90
91 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
92 u32 value = 0;
93 u8 stereo_freqs = 0;
94 int max_channels = -1;
95 int j;
96
97 for (j = 0; j < sad_count; j++) {
98 struct cea_sad *sad = &sads[j];
99
100 if (sad->format == eld_reg_to_type[i][1]) {
101 if (sad->channels > max_channels) {
102 value = MAX_CHANNELS(sad->channels) |
103 DESCRIPTOR_BYTE_2(sad->byte2) |
104 SUPPORTED_FREQUENCIES(sad->freq);
105 max_channels = sad->channels;
106 }
107
108 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
109 stereo_freqs |= sad->freq;
110 else
111 break;
112 }
113 }
114
115 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
116
117 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
118 }
119 }
120
dce3_2_audio_set_dto(struct radeon_device * rdev,struct radeon_crtc * crtc,unsigned int clock)121 void dce3_2_audio_set_dto(struct radeon_device *rdev,
122 struct radeon_crtc *crtc, unsigned int clock)
123 {
124 struct radeon_encoder *radeon_encoder;
125 struct radeon_encoder_atom_dig *dig;
126 unsigned int max_ratio = clock / 24000;
127 u32 dto_phase;
128 u32 wallclock_ratio;
129 u32 dto_cntl;
130
131 if (!crtc)
132 return;
133
134 radeon_encoder = to_radeon_encoder(crtc->encoder);
135 dig = radeon_encoder->enc_priv;
136
137 if (!dig)
138 return;
139
140 if (max_ratio >= 8) {
141 dto_phase = 192 * 1000;
142 wallclock_ratio = 3;
143 } else if (max_ratio >= 4) {
144 dto_phase = 96 * 1000;
145 wallclock_ratio = 2;
146 } else if (max_ratio >= 2) {
147 dto_phase = 48 * 1000;
148 wallclock_ratio = 1;
149 } else {
150 dto_phase = 24 * 1000;
151 wallclock_ratio = 0;
152 }
153
154 /* Express [24MHz / target pixel clock] as an exact rational
155 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
156 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
157 */
158 if (dig->dig_encoder == 0) {
159 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
160 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
161 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
162 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
163 WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
164 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
165 } else {
166 dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
167 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
168 WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
169 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
170 WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
171 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
172 }
173 }
174
dce3_2_hdmi_update_acr(struct drm_encoder * encoder,long offset,const struct radeon_hdmi_acr * acr)175 void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset,
176 const struct radeon_hdmi_acr *acr)
177 {
178 struct drm_device *dev = encoder->dev;
179 struct radeon_device *rdev = dev->dev_private;
180
181 WREG32(DCE3_HDMI0_ACR_PACKET_CONTROL + offset,
182 HDMI0_ACR_SOURCE | /* select SW CTS value */
183 HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
184
185 WREG32_P(HDMI0_ACR_32_0 + offset,
186 HDMI0_ACR_CTS_32(acr->cts_32khz),
187 ~HDMI0_ACR_CTS_32_MASK);
188 WREG32_P(HDMI0_ACR_32_1 + offset,
189 HDMI0_ACR_N_32(acr->n_32khz),
190 ~HDMI0_ACR_N_32_MASK);
191
192 WREG32_P(HDMI0_ACR_44_0 + offset,
193 HDMI0_ACR_CTS_44(acr->cts_44_1khz),
194 ~HDMI0_ACR_CTS_44_MASK);
195 WREG32_P(HDMI0_ACR_44_1 + offset,
196 HDMI0_ACR_N_44(acr->n_44_1khz),
197 ~HDMI0_ACR_N_44_MASK);
198
199 WREG32_P(HDMI0_ACR_48_0 + offset,
200 HDMI0_ACR_CTS_48(acr->cts_48khz),
201 ~HDMI0_ACR_CTS_48_MASK);
202 WREG32_P(HDMI0_ACR_48_1 + offset,
203 HDMI0_ACR_N_48(acr->n_48khz),
204 ~HDMI0_ACR_N_48_MASK);
205 }
206
dce3_2_set_audio_packet(struct drm_encoder * encoder,u32 offset)207 void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset)
208 {
209 struct drm_device *dev = encoder->dev;
210 struct radeon_device *rdev = dev->dev_private;
211
212 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
213 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
214 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
215
216 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
217 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
218 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
219
220 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
221 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
222 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
223
224 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
225 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
226 }
227
dce3_2_set_mute(struct drm_encoder * encoder,u32 offset,bool mute)228 void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
229 {
230 struct drm_device *dev = encoder->dev;
231 struct radeon_device *rdev = dev->dev_private;
232
233 if (mute)
234 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
235 else
236 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
237 }
238