1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 /* include DCE8 register header files */
29 #include "dce/dce_8_0_d.h"
30 #include "dce/dce_8_0_sh_mask.h"
31
32 #include "dc_types.h"
33
34 #include "include/grph_object_id.h"
35 #include "include/logger_interface.h"
36 #include "../dce110/dce110_timing_generator.h"
37 #include "dce80_timing_generator.h"
38
39 #include "timing_generator.h"
40
41 enum black_color_format {
42 BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0, /* used as index in array */
43 BLACK_COLOR_FORMAT_RGB_LIMITED,
44 BLACK_COLOR_FORMAT_YUV_TV,
45 BLACK_COLOR_FORMAT_YUV_CV,
46 BLACK_COLOR_FORMAT_YUV_SUPER_AA,
47
48 BLACK_COLOR_FORMAT_COUNT
49 };
50
51 static const struct dce110_timing_generator_offsets reg_offsets[] = {
52 {
53 .crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
54 .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
55 },
56 {
57 .crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
58 .dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
59 },
60 {
61 .crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
62 .dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
63 },
64 {
65 .crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
66 .dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
67 },
68 {
69 .crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
70 .dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
71 },
72 {
73 .crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
74 .dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
75 }
76 };
77
78 #define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
79
80 #define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
81 #define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
82
83 #define CRTC_REG(reg) (reg + tg110->offsets.crtc)
84 #define DCP_REG(reg) (reg + tg110->offsets.dcp)
85 #define DMIF_REG(reg) (reg + tg110->offsets.dmif)
86
program_pix_dur(struct timing_generator * tg,uint32_t pix_clk_khz)87 static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
88 {
89 uint64_t pix_dur;
90 uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
91 + DCE110TG_FROM_TG(tg)->offsets.dmif;
92 uint32_t value = dm_read_reg(tg->ctx, addr);
93
94 if (pix_clk_khz == 0)
95 return;
96
97 pix_dur = 1000000000 / pix_clk_khz;
98
99 set_reg_field_value(
100 value,
101 pix_dur,
102 DPG_PIPE_ARBITRATION_CONTROL1,
103 PIXEL_DURATION);
104
105 dm_write_reg(tg->ctx, addr, value);
106 }
107
program_timing(struct timing_generator * tg,const struct dc_crtc_timing * timing,bool use_vbios)108 static void program_timing(struct timing_generator *tg,
109 const struct dc_crtc_timing *timing,
110 bool use_vbios)
111 {
112 if (!use_vbios)
113 program_pix_dur(tg, timing->pix_clk_khz);
114
115 dce110_tg_program_timing(tg, timing, use_vbios);
116 }
117
dce80_timing_generator_enable_advanced_request(struct timing_generator * tg,bool enable,const struct dc_crtc_timing * timing)118 static void dce80_timing_generator_enable_advanced_request(
119 struct timing_generator *tg,
120 bool enable,
121 const struct dc_crtc_timing *timing)
122 {
123 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
124 uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
125 uint32_t value = dm_read_reg(tg->ctx, addr);
126
127 if (enable) {
128 set_reg_field_value(
129 value,
130 0,
131 CRTC_START_LINE_CONTROL,
132 CRTC_LEGACY_REQUESTOR_EN);
133 } else {
134 set_reg_field_value(
135 value,
136 1,
137 CRTC_START_LINE_CONTROL,
138 CRTC_LEGACY_REQUESTOR_EN);
139 }
140
141 if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
142 set_reg_field_value(
143 value,
144 3,
145 CRTC_START_LINE_CONTROL,
146 CRTC_ADVANCED_START_LINE_POSITION);
147 set_reg_field_value(
148 value,
149 0,
150 CRTC_START_LINE_CONTROL,
151 CRTC_PREFETCH_EN);
152 } else {
153 set_reg_field_value(
154 value,
155 4,
156 CRTC_START_LINE_CONTROL,
157 CRTC_ADVANCED_START_LINE_POSITION);
158 set_reg_field_value(
159 value,
160 1,
161 CRTC_START_LINE_CONTROL,
162 CRTC_PREFETCH_EN);
163 }
164
165 set_reg_field_value(
166 value,
167 1,
168 CRTC_START_LINE_CONTROL,
169 CRTC_PROGRESSIVE_START_LINE_EARLY);
170
171 set_reg_field_value(
172 value,
173 1,
174 CRTC_START_LINE_CONTROL,
175 CRTC_INTERLACE_START_LINE_EARLY);
176
177 dm_write_reg(tg->ctx, addr, value);
178 }
179
180 static const struct timing_generator_funcs dce80_tg_funcs = {
181 .validate_timing = dce110_tg_validate_timing,
182 .program_timing = program_timing,
183 .enable_crtc = dce110_timing_generator_enable_crtc,
184 .disable_crtc = dce110_timing_generator_disable_crtc,
185 .is_counter_moving = dce110_timing_generator_is_counter_moving,
186 .get_position = dce110_timing_generator_get_position,
187 .get_frame_count = dce110_timing_generator_get_vblank_counter,
188 .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
189 .set_early_control = dce110_timing_generator_set_early_control,
190 .wait_for_state = dce110_tg_wait_for_state,
191 .set_blank = dce110_tg_set_blank,
192 .is_blanked = dce110_tg_is_blanked,
193 .set_colors = dce110_tg_set_colors,
194 .set_overscan_blank_color =
195 dce110_timing_generator_set_overscan_color_black,
196 .set_blank_color = dce110_timing_generator_program_blank_color,
197 .disable_vga = dce110_timing_generator_disable_vga,
198 .did_triggered_reset_occur =
199 dce110_timing_generator_did_triggered_reset_occur,
200 .setup_global_swap_lock =
201 dce110_timing_generator_setup_global_swap_lock,
202 .enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
203 .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
204 .tear_down_global_swap_lock =
205 dce110_timing_generator_tear_down_global_swap_lock,
206 .set_drr = dce110_timing_generator_set_drr,
207 .set_static_screen_control =
208 dce110_timing_generator_set_static_screen_control,
209 .set_test_pattern = dce110_timing_generator_set_test_pattern,
210 .arm_vert_intr = dce110_arm_vert_intr,
211
212 /* DCE8.0 overrides */
213 .enable_advanced_request =
214 dce80_timing_generator_enable_advanced_request,
215 .configure_crc = dce110_configure_crc,
216 .get_crc = dce110_get_crc,
217 };
218
dce80_timing_generator_construct(struct dce110_timing_generator * tg110,struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)219 void dce80_timing_generator_construct(
220 struct dce110_timing_generator *tg110,
221 struct dc_context *ctx,
222 uint32_t instance,
223 const struct dce110_timing_generator_offsets *offsets)
224 {
225 tg110->controller_id = CONTROLLER_ID_D0 + instance;
226 tg110->base.inst = instance;
227 tg110->offsets = *offsets;
228 tg110->derived_offsets = reg_offsets[instance];
229
230 tg110->base.funcs = &dce80_tg_funcs;
231
232 tg110->base.ctx = ctx;
233 tg110->base.bp = ctx->dc_bios;
234
235 tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
236 tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
237
238 tg110->min_h_blank = 56;
239 tg110->min_h_front_porch = 4;
240 tg110->min_h_back_porch = 4;
241 }
242
243