1 /*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "core_types.h"
27 #include "link_encoder.h"
28 #include "dce_dmcu.h"
29 #include "dm_services.h"
30 #include "reg_helper.h"
31 #include "fixed31_32.h"
32 #include "dc.h"
33
34 #define TO_DCE_DMCU(dmcu)\
35 container_of(dmcu, struct dce_dmcu, base)
36
37 #define REG(reg) \
38 (dmcu_dce->regs->reg)
39
40 #undef FN
41 #define FN(reg_name, field_name) \
42 dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name
43
44 #define CTX \
45 dmcu_dce->base.ctx
46
47 /* PSR related commands */
48 #define PSR_ENABLE 0x20
49 #define PSR_EXIT 0x21
50 #define PSR_SET 0x23
51 #define PSR_SET_WAITLOOP 0x31
52 #define MCP_INIT_DMCU 0x88
53 #define MCP_INIT_IRAM 0x89
54 #define MCP_DMCU_VERSION 0x90
55 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L
56
dce_dmcu_init(struct dmcu * dmcu)57 static bool dce_dmcu_init(struct dmcu *dmcu)
58 {
59 // Do nothing
60 return true;
61 }
62
63 static
dce_dmcu_load_iram(struct dmcu * dmcu,unsigned int start_offset,const char * src,unsigned int bytes)64 bool dce_dmcu_load_iram(struct dmcu *dmcu,
65 unsigned int start_offset,
66 const char *src,
67 unsigned int bytes)
68 {
69 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
70 unsigned int count = 0;
71
72 /* Enable write access to IRAM */
73 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
74 IRAM_HOST_ACCESS_EN, 1,
75 IRAM_WR_ADDR_AUTO_INC, 1);
76
77 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
78
79 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
80
81 for (count = 0; count < bytes; count++)
82 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
83
84 /* Disable write access to IRAM to allow dynamic sleep state */
85 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
86 IRAM_HOST_ACCESS_EN, 0,
87 IRAM_WR_ADDR_AUTO_INC, 0);
88
89 return true;
90 }
91
dce_get_dmcu_psr_state(struct dmcu * dmcu,uint32_t * psr_state)92 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
93 {
94 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
95
96 uint32_t psr_state_offset = 0xf0;
97
98 /* Enable write access to IRAM */
99 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
100
101 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
102
103 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
104 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
105
106 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
107 *psr_state = REG_READ(DMCU_IRAM_RD_DATA);
108
109 /* Disable write access to IRAM after finished using IRAM
110 * in order to allow dynamic sleep state
111 */
112 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
113 }
114
dce_dmcu_set_psr_enable(struct dmcu * dmcu,bool enable,bool wait)115 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
116 {
117 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
118 unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
119 unsigned int dmcu_wait_reg_ready_interval = 100;
120
121 unsigned int retryCount;
122 uint32_t psr_state = 0;
123
124 /* waitDMCUReadyForCmd */
125 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
126 dmcu_wait_reg_ready_interval,
127 dmcu_max_retry_on_wait_reg_ready);
128
129 /* setDMCUParam_Cmd */
130 if (enable)
131 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
132 PSR_ENABLE);
133 else
134 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
135 PSR_EXIT);
136
137 /* notifyDMCUMsg */
138 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
139 if (wait == true) {
140 for (retryCount = 0; retryCount <= 100; retryCount++) {
141 dce_get_dmcu_psr_state(dmcu, &psr_state);
142 if (enable) {
143 if (psr_state != 0)
144 break;
145 } else {
146 if (psr_state == 0)
147 break;
148 }
149 udelay(10);
150 }
151 }
152 }
153
dce_dmcu_setup_psr(struct dmcu * dmcu,struct dc_link * link,struct psr_context * psr_context)154 static bool dce_dmcu_setup_psr(struct dmcu *dmcu,
155 struct dc_link *link,
156 struct psr_context *psr_context)
157 {
158 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
159
160 unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
161 unsigned int dmcu_wait_reg_ready_interval = 100;
162
163 union dce_dmcu_psr_config_data_reg1 masterCmdData1;
164 union dce_dmcu_psr_config_data_reg2 masterCmdData2;
165 union dce_dmcu_psr_config_data_reg3 masterCmdData3;
166
167 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
168 psr_context->psrExitLinkTrainingRequired);
169
170 /* Enable static screen interrupts for PSR supported display */
171 /* Disable the interrupt coming from other displays. */
172 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
173 STATIC_SCREEN1_INT_TO_UC_EN, 0,
174 STATIC_SCREEN2_INT_TO_UC_EN, 0,
175 STATIC_SCREEN3_INT_TO_UC_EN, 0,
176 STATIC_SCREEN4_INT_TO_UC_EN, 0);
177
178 switch (psr_context->controllerId) {
179 /* Driver uses case 1 for unconfigured */
180 case 1:
181 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
182 STATIC_SCREEN1_INT_TO_UC_EN, 1);
183 break;
184 case 2:
185 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
186 STATIC_SCREEN2_INT_TO_UC_EN, 1);
187 break;
188 case 3:
189 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
190 STATIC_SCREEN3_INT_TO_UC_EN, 1);
191 break;
192 case 4:
193 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
194 STATIC_SCREEN4_INT_TO_UC_EN, 1);
195 break;
196 case 5:
197 /* CZ/NL only has 4 CRTC!!
198 * really valid.
199 * There is no interrupt enable mask for these instances.
200 */
201 break;
202 case 6:
203 /* CZ/NL only has 4 CRTC!!
204 * These are here because they are defined in HW regspec,
205 * but not really valid. There is no interrupt enable mask
206 * for these instances.
207 */
208 break;
209 default:
210 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
211 STATIC_SCREEN1_INT_TO_UC_EN, 1);
212 break;
213 }
214
215 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
216 psr_context->sdpTransmitLineNumDeadline);
217
218 if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)
219 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
220
221 /* waitDMCUReadyForCmd */
222 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
223 dmcu_wait_reg_ready_interval,
224 dmcu_max_retry_on_wait_reg_ready);
225
226 /* setDMCUParam_PSRHostConfigData */
227 masterCmdData1.u32All = 0;
228 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
229 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
230 masterCmdData1.bits.rfb_update_auto_en =
231 psr_context->rfb_update_auto_en;
232 masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
233 masterCmdData1.bits.dcp_sel = psr_context->controllerId;
234 masterCmdData1.bits.phy_type = psr_context->phyType;
235 masterCmdData1.bits.frame_cap_ind =
236 psr_context->psrFrameCaptureIndicationReq;
237 masterCmdData1.bits.aux_chan = psr_context->channel;
238 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
239 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
240 masterCmdData1.u32All);
241
242 masterCmdData2.u32All = 0;
243 masterCmdData2.bits.dig_fe = psr_context->engineId;
244 masterCmdData2.bits.dig_be = psr_context->transmitterId;
245 masterCmdData2.bits.skip_wait_for_pll_lock =
246 psr_context->skipPsrWaitForPllLock;
247 masterCmdData2.bits.frame_delay = psr_context->frame_delay;
248 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
249 masterCmdData2.bits.num_of_controllers =
250 psr_context->numberOfControllers;
251 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
252 masterCmdData2.u32All);
253
254 masterCmdData3.u32All = 0;
255 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
256 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
257 masterCmdData3.u32All);
258
259 /* setDMCUParam_Cmd */
260 REG_UPDATE(MASTER_COMM_CMD_REG,
261 MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
262
263 /* notifyDMCUMsg */
264 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
265
266 return true;
267 }
268
dce_is_dmcu_initialized(struct dmcu * dmcu)269 static bool dce_is_dmcu_initialized(struct dmcu *dmcu)
270 {
271 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
272 unsigned int dmcu_uc_reset;
273
274 /* microcontroller is not running */
275 REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset);
276
277 /* DMCU is not running */
278 if (dmcu_uc_reset)
279 return false;
280
281 return true;
282 }
283
dce_psr_wait_loop(struct dmcu * dmcu,unsigned int wait_loop_number)284 static void dce_psr_wait_loop(
285 struct dmcu *dmcu,
286 unsigned int wait_loop_number)
287 {
288 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
289 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
290
291 if (dmcu->cached_wait_loop_number == wait_loop_number)
292 return;
293
294 /* DMCU is not running */
295 if (!dce_is_dmcu_initialized(dmcu))
296 return;
297
298 /* waitDMCUReadyForCmd */
299 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
300
301 masterCmdData1.u32 = 0;
302 masterCmdData1.bits.wait_loop = wait_loop_number;
303 dmcu->cached_wait_loop_number = wait_loop_number;
304 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
305
306 /* setDMCUParam_Cmd */
307 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
308
309 /* notifyDMCUMsg */
310 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
311 }
312
dce_get_psr_wait_loop(struct dmcu * dmcu,unsigned int * psr_wait_loop_number)313 static void dce_get_psr_wait_loop(
314 struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
315 {
316 *psr_wait_loop_number = dmcu->cached_wait_loop_number;
317 return;
318 }
319
320 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
dcn10_get_dmcu_state(struct dmcu * dmcu)321 static void dcn10_get_dmcu_state(struct dmcu *dmcu)
322 {
323 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
324 uint32_t dmcu_state_offset = 0xf6;
325
326 /* Enable write access to IRAM */
327 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
328 IRAM_HOST_ACCESS_EN, 1,
329 IRAM_RD_ADDR_AUTO_INC, 1);
330
331 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
332
333 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
334 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_state_offset);
335
336 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
337 dmcu->dmcu_state = REG_READ(DMCU_IRAM_RD_DATA);
338
339 /* Disable write access to IRAM to allow dynamic sleep state */
340 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
341 IRAM_HOST_ACCESS_EN, 0,
342 IRAM_RD_ADDR_AUTO_INC, 0);
343 }
344
dcn10_get_dmcu_version(struct dmcu * dmcu)345 static void dcn10_get_dmcu_version(struct dmcu *dmcu)
346 {
347 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
348 uint32_t dmcu_version_offset = 0xf1;
349
350 /* Clear scratch */
351 REG_WRITE(DC_DMCU_SCRATCH, 0);
352
353 /* Enable write access to IRAM */
354 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
355 IRAM_HOST_ACCESS_EN, 1,
356 IRAM_RD_ADDR_AUTO_INC, 1);
357
358 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
359
360 /* Write address to IRAM_RD_ADDR and read from DATA register */
361 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);
362 dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);
363 dmcu->dmcu_version.year = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
364 REG_READ(DMCU_IRAM_RD_DATA));
365 dmcu->dmcu_version.month = REG_READ(DMCU_IRAM_RD_DATA);
366 dmcu->dmcu_version.date = REG_READ(DMCU_IRAM_RD_DATA);
367
368 /* Disable write access to IRAM to allow dynamic sleep state */
369 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
370 IRAM_HOST_ACCESS_EN, 0,
371 IRAM_RD_ADDR_AUTO_INC, 0);
372
373 /* Send MCP command message to DMCU to get version reply from FW.
374 * We expect this version should match the one in IRAM, otherwise
375 * something is wrong with DMCU and we should fail and disable UC.
376 */
377 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
378
379 /* Set command to get DMCU version from microcontroller */
380 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
381 MCP_DMCU_VERSION);
382
383 /* Notify microcontroller of new command */
384 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
385
386 /* Ensure command has been executed before continuing */
387 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
388
389 /* Somehow version does not match, so fail and return version 0 */
390 if (dmcu->dmcu_version.interface_version != REG_READ(DC_DMCU_SCRATCH))
391 dmcu->dmcu_version.interface_version = 0;
392 }
393
dcn10_dmcu_init(struct dmcu * dmcu)394 static bool dcn10_dmcu_init(struct dmcu *dmcu)
395 {
396 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
397
398 /* DMCU FW should populate the scratch register if running */
399 if (REG_READ(DC_DMCU_SCRATCH) == 0)
400 return false;
401
402 /* Check state is uninitialized */
403 dcn10_get_dmcu_state(dmcu);
404
405 /* If microcontroller is already initialized, do nothing */
406 if (dmcu->dmcu_state == DMCU_RUNNING)
407 return true;
408
409 /* Retrieve and cache the DMCU firmware version. */
410 dcn10_get_dmcu_version(dmcu);
411
412 /* Check interface version to confirm firmware is loaded and running */
413 if (dmcu->dmcu_version.interface_version == 0)
414 return false;
415
416 /* Wait until microcontroller is ready to process interrupt */
417 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
418
419 /* Set initialized ramping boundary value */
420 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF);
421
422 /* Set command to initialize microcontroller */
423 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
424 MCP_INIT_DMCU);
425
426 /* Notify microcontroller of new command */
427 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
428
429 /* Ensure command has been executed before continuing */
430 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
431
432 // Check state is initialized
433 dcn10_get_dmcu_state(dmcu);
434
435 // If microcontroller is not in running state, fail
436 if (dmcu->dmcu_state != DMCU_RUNNING)
437 return false;
438
439 return true;
440 }
441
dcn10_dmcu_load_iram(struct dmcu * dmcu,unsigned int start_offset,const char * src,unsigned int bytes)442 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
443 unsigned int start_offset,
444 const char *src,
445 unsigned int bytes)
446 {
447 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
448 unsigned int count = 0;
449
450 /* If microcontroller is not running, do nothing */
451 if (dmcu->dmcu_state != DMCU_RUNNING)
452 return false;
453
454 /* Enable write access to IRAM */
455 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
456 IRAM_HOST_ACCESS_EN, 1,
457 IRAM_WR_ADDR_AUTO_INC, 1);
458
459 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
460
461 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
462
463 for (count = 0; count < bytes; count++)
464 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
465
466 /* Disable write access to IRAM to allow dynamic sleep state */
467 REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
468 IRAM_HOST_ACCESS_EN, 0,
469 IRAM_WR_ADDR_AUTO_INC, 0);
470
471 /* Wait until microcontroller is ready to process interrupt */
472 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
473
474 /* Set command to signal IRAM is loaded and to initialize IRAM */
475 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
476 MCP_INIT_IRAM);
477
478 /* Notify microcontroller of new command */
479 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
480
481 /* Ensure command has been executed before continuing */
482 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
483
484 return true;
485 }
486
dcn10_get_dmcu_psr_state(struct dmcu * dmcu,uint32_t * psr_state)487 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
488 {
489 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
490
491 uint32_t psr_state_offset = 0xf0;
492
493 /* If microcontroller is not running, do nothing */
494 if (dmcu->dmcu_state != DMCU_RUNNING)
495 return;
496
497 /* Enable write access to IRAM */
498 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
499
500 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
501
502 /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
503 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
504
505 /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
506 *psr_state = REG_READ(DMCU_IRAM_RD_DATA);
507
508 /* Disable write access to IRAM after finished using IRAM
509 * in order to allow dynamic sleep state
510 */
511 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
512 }
513
dcn10_dmcu_set_psr_enable(struct dmcu * dmcu,bool enable,bool wait)514 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
515 {
516 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
517 unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
518 unsigned int dmcu_wait_reg_ready_interval = 100;
519
520 unsigned int retryCount;
521 uint32_t psr_state = 0;
522
523 /* If microcontroller is not running, do nothing */
524 if (dmcu->dmcu_state != DMCU_RUNNING)
525 return;
526
527 dcn10_get_dmcu_psr_state(dmcu, &psr_state);
528 if (psr_state == 0 && !enable)
529 return;
530 /* waitDMCUReadyForCmd */
531 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
532 dmcu_wait_reg_ready_interval,
533 dmcu_max_retry_on_wait_reg_ready);
534
535 /* setDMCUParam_Cmd */
536 if (enable)
537 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
538 PSR_ENABLE);
539 else
540 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
541 PSR_EXIT);
542
543 /* notifyDMCUMsg */
544 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
545
546 /* Below loops 1000 x 500us = 500 ms.
547 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at
548 * least a few frames. Should never hit the max retry assert below.
549 */
550 if (wait == true) {
551 for (retryCount = 0; retryCount <= 1000; retryCount++) {
552 dcn10_get_dmcu_psr_state(dmcu, &psr_state);
553 if (enable) {
554 if (psr_state != 0)
555 break;
556 } else {
557 if (psr_state == 0)
558 break;
559 }
560 udelay(500);
561 }
562
563 /* assert if max retry hit */
564 if (retryCount >= 1000)
565 ASSERT(0);
566 }
567 }
568
dcn10_dmcu_setup_psr(struct dmcu * dmcu,struct dc_link * link,struct psr_context * psr_context)569 static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,
570 struct dc_link *link,
571 struct psr_context *psr_context)
572 {
573 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
574
575 unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
576 unsigned int dmcu_wait_reg_ready_interval = 100;
577
578 union dce_dmcu_psr_config_data_reg1 masterCmdData1;
579 union dce_dmcu_psr_config_data_reg2 masterCmdData2;
580 union dce_dmcu_psr_config_data_reg3 masterCmdData3;
581
582 /* If microcontroller is not running, do nothing */
583 if (dmcu->dmcu_state != DMCU_RUNNING)
584 return false;
585
586 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
587 psr_context->psrExitLinkTrainingRequired);
588
589 /* Enable static screen interrupts for PSR supported display */
590 /* Disable the interrupt coming from other displays. */
591 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
592 STATIC_SCREEN1_INT_TO_UC_EN, 0,
593 STATIC_SCREEN2_INT_TO_UC_EN, 0,
594 STATIC_SCREEN3_INT_TO_UC_EN, 0,
595 STATIC_SCREEN4_INT_TO_UC_EN, 0);
596
597 switch (psr_context->controllerId) {
598 /* Driver uses case 1 for unconfigured */
599 case 1:
600 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
601 STATIC_SCREEN1_INT_TO_UC_EN, 1);
602 break;
603 case 2:
604 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
605 STATIC_SCREEN2_INT_TO_UC_EN, 1);
606 break;
607 case 3:
608 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
609 STATIC_SCREEN3_INT_TO_UC_EN, 1);
610 break;
611 case 4:
612 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
613 STATIC_SCREEN4_INT_TO_UC_EN, 1);
614 break;
615 case 5:
616 /* CZ/NL only has 4 CRTC!!
617 * really valid.
618 * There is no interrupt enable mask for these instances.
619 */
620 break;
621 case 6:
622 /* CZ/NL only has 4 CRTC!!
623 * These are here because they are defined in HW regspec,
624 * but not really valid. There is no interrupt enable mask
625 * for these instances.
626 */
627 break;
628 default:
629 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
630 STATIC_SCREEN1_INT_TO_UC_EN, 1);
631 break;
632 }
633
634 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
635 psr_context->sdpTransmitLineNumDeadline);
636
637 if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)
638 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
639
640 /* waitDMCUReadyForCmd */
641 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
642 dmcu_wait_reg_ready_interval,
643 dmcu_max_retry_on_wait_reg_ready);
644
645 /* setDMCUParam_PSRHostConfigData */
646 masterCmdData1.u32All = 0;
647 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
648 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
649 masterCmdData1.bits.rfb_update_auto_en =
650 psr_context->rfb_update_auto_en;
651 masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
652 masterCmdData1.bits.dcp_sel = psr_context->controllerId;
653 masterCmdData1.bits.phy_type = psr_context->phyType;
654 masterCmdData1.bits.frame_cap_ind =
655 psr_context->psrFrameCaptureIndicationReq;
656 masterCmdData1.bits.aux_chan = psr_context->channel;
657 masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
658 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
659 masterCmdData1.u32All);
660
661 masterCmdData2.u32All = 0;
662 masterCmdData2.bits.dig_fe = psr_context->engineId;
663 masterCmdData2.bits.dig_be = psr_context->transmitterId;
664 masterCmdData2.bits.skip_wait_for_pll_lock =
665 psr_context->skipPsrWaitForPllLock;
666 masterCmdData2.bits.frame_delay = psr_context->frame_delay;
667 masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
668 masterCmdData2.bits.num_of_controllers =
669 psr_context->numberOfControllers;
670 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
671 masterCmdData2.u32All);
672
673 masterCmdData3.u32All = 0;
674 masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
675 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
676 masterCmdData3.u32All);
677
678 /* setDMCUParam_Cmd */
679 REG_UPDATE(MASTER_COMM_CMD_REG,
680 MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
681
682 /* notifyDMCUMsg */
683 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
684
685 /* waitDMCUReadyForCmd */
686 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
687
688 return true;
689 }
690
dcn10_psr_wait_loop(struct dmcu * dmcu,unsigned int wait_loop_number)691 static void dcn10_psr_wait_loop(
692 struct dmcu *dmcu,
693 unsigned int wait_loop_number)
694 {
695 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
696 union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
697
698 /* If microcontroller is not running, do nothing */
699 if (dmcu->dmcu_state != DMCU_RUNNING)
700 return;
701
702 if (wait_loop_number != 0) {
703 /* waitDMCUReadyForCmd */
704 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
705
706 masterCmdData1.u32 = 0;
707 masterCmdData1.bits.wait_loop = wait_loop_number;
708 dmcu->cached_wait_loop_number = wait_loop_number;
709 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
710
711 /* setDMCUParam_Cmd */
712 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
713
714 /* notifyDMCUMsg */
715 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
716 }
717 }
718
dcn10_get_psr_wait_loop(struct dmcu * dmcu,unsigned int * psr_wait_loop_number)719 static void dcn10_get_psr_wait_loop(
720 struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
721 {
722 *psr_wait_loop_number = dmcu->cached_wait_loop_number;
723 return;
724 }
725
dcn10_is_dmcu_initialized(struct dmcu * dmcu)726 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)
727 {
728 /* microcontroller is not running */
729 if (dmcu->dmcu_state != DMCU_RUNNING)
730 return false;
731 return true;
732 }
733
734 #endif
735
736 static const struct dmcu_funcs dce_funcs = {
737 .dmcu_init = dce_dmcu_init,
738 .load_iram = dce_dmcu_load_iram,
739 .set_psr_enable = dce_dmcu_set_psr_enable,
740 .setup_psr = dce_dmcu_setup_psr,
741 .get_psr_state = dce_get_dmcu_psr_state,
742 .set_psr_wait_loop = dce_psr_wait_loop,
743 .get_psr_wait_loop = dce_get_psr_wait_loop,
744 .is_dmcu_initialized = dce_is_dmcu_initialized
745 };
746
747 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
748 static const struct dmcu_funcs dcn10_funcs = {
749 .dmcu_init = dcn10_dmcu_init,
750 .load_iram = dcn10_dmcu_load_iram,
751 .set_psr_enable = dcn10_dmcu_set_psr_enable,
752 .setup_psr = dcn10_dmcu_setup_psr,
753 .get_psr_state = dcn10_get_dmcu_psr_state,
754 .set_psr_wait_loop = dcn10_psr_wait_loop,
755 .get_psr_wait_loop = dcn10_get_psr_wait_loop,
756 .is_dmcu_initialized = dcn10_is_dmcu_initialized
757 };
758 #endif
759
dce_dmcu_construct(struct dce_dmcu * dmcu_dce,struct dc_context * ctx,const struct dce_dmcu_registers * regs,const struct dce_dmcu_shift * dmcu_shift,const struct dce_dmcu_mask * dmcu_mask)760 static void dce_dmcu_construct(
761 struct dce_dmcu *dmcu_dce,
762 struct dc_context *ctx,
763 const struct dce_dmcu_registers *regs,
764 const struct dce_dmcu_shift *dmcu_shift,
765 const struct dce_dmcu_mask *dmcu_mask)
766 {
767 struct dmcu *base = &dmcu_dce->base;
768
769 base->ctx = ctx;
770 base->funcs = &dce_funcs;
771 base->cached_wait_loop_number = 0;
772
773 dmcu_dce->regs = regs;
774 dmcu_dce->dmcu_shift = dmcu_shift;
775 dmcu_dce->dmcu_mask = dmcu_mask;
776 }
777
dce_dmcu_create(struct dc_context * ctx,const struct dce_dmcu_registers * regs,const struct dce_dmcu_shift * dmcu_shift,const struct dce_dmcu_mask * dmcu_mask)778 struct dmcu *dce_dmcu_create(
779 struct dc_context *ctx,
780 const struct dce_dmcu_registers *regs,
781 const struct dce_dmcu_shift *dmcu_shift,
782 const struct dce_dmcu_mask *dmcu_mask)
783 {
784 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
785
786 if (dmcu_dce == NULL) {
787 BREAK_TO_DEBUGGER();
788 return NULL;
789 }
790
791 dce_dmcu_construct(
792 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
793
794 dmcu_dce->base.funcs = &dce_funcs;
795
796 return &dmcu_dce->base;
797 }
798
799 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
dcn10_dmcu_create(struct dc_context * ctx,const struct dce_dmcu_registers * regs,const struct dce_dmcu_shift * dmcu_shift,const struct dce_dmcu_mask * dmcu_mask)800 struct dmcu *dcn10_dmcu_create(
801 struct dc_context *ctx,
802 const struct dce_dmcu_registers *regs,
803 const struct dce_dmcu_shift *dmcu_shift,
804 const struct dce_dmcu_mask *dmcu_mask)
805 {
806 struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
807
808 if (dmcu_dce == NULL) {
809 BREAK_TO_DEBUGGER();
810 return NULL;
811 }
812
813 dce_dmcu_construct(
814 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
815
816 dmcu_dce->base.funcs = &dcn10_funcs;
817
818 return &dmcu_dce->base;
819 }
820 #endif
821
dce_dmcu_destroy(struct dmcu ** dmcu)822 void dce_dmcu_destroy(struct dmcu **dmcu)
823 {
824 struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
825
826 kfree(dmcu_dce);
827 *dmcu = NULL;
828 }
829