1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 * Copyright 2019 Raptor Engineering, LLC
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn20/dcn20_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn20/dcn20_resource.h"
35
36 #include "dml/dcn20/dcn20_fpu.h"
37
38 #include "dcn10/dcn10_hubp.h"
39 #include "dcn10/dcn10_ipp.h"
40 #include "dcn20/dcn20_hubbub.h"
41 #include "dcn20/dcn20_mpc.h"
42 #include "dcn20/dcn20_hubp.h"
43 #include "irq/dcn20/irq_service_dcn20.h"
44 #include "dcn20/dcn20_dpp.h"
45 #include "dcn20/dcn20_optc.h"
46 #include "dcn20/dcn20_hwseq.h"
47 #include "dce110/dce110_hwseq.h"
48 #include "dcn10/dcn10_resource.h"
49 #include "dcn20/dcn20_opp.h"
50
51 #include "dcn20/dcn20_dsc.h"
52
53 #include "dcn20/dcn20_link_encoder.h"
54 #include "dcn20/dcn20_stream_encoder.h"
55 #include "dce/dce_clock_source.h"
56 #include "dce/dce_audio.h"
57 #include "dce/dce_hwseq.h"
58 #include "virtual/virtual_stream_encoder.h"
59 #include "dce110/dce110_resource.h"
60 #include "dml/display_mode_vba.h"
61 #include "dcn20/dcn20_dccg.h"
62 #include "dcn20/dcn20_vmid.h"
63 #include "dce/dce_panel_cntl.h"
64
65 #include "dcn20/dcn20_dwb.h"
66 #include "dcn20/dcn20_mmhubbub.h"
67
68 #include "navi10_ip_offset.h"
69
70 #include "dcn/dcn_2_0_0_offset.h"
71 #include "dcn/dcn_2_0_0_sh_mask.h"
72 #include "dpcs/dpcs_2_0_0_offset.h"
73 #include "dpcs/dpcs_2_0_0_sh_mask.h"
74
75 #include "nbio/nbio_2_3_offset.h"
76
77 #include "mmhub/mmhub_2_0_0_offset.h"
78 #include "mmhub/mmhub_2_0_0_sh_mask.h"
79
80 #include "reg_helper.h"
81 #include "dce/dce_abm.h"
82 #include "dce/dce_dmcu.h"
83 #include "dce/dce_aux.h"
84 #include "dce/dce_i2c.h"
85 #include "vm_helper.h"
86
87 #include "link_enc_cfg.h"
88 #include "link.h"
89
90 #define DC_LOGGER_INIT(logger)
91
92 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
93 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
94 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
95 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
96 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
97 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
98 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
99 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
100 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
101 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
102 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
103 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
104 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
105 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
106 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
107 #endif
108
109
110 enum dcn20_clk_src_array_id {
111 DCN20_CLK_SRC_PLL0,
112 DCN20_CLK_SRC_PLL1,
113 DCN20_CLK_SRC_PLL2,
114 DCN20_CLK_SRC_PLL3,
115 DCN20_CLK_SRC_PLL4,
116 DCN20_CLK_SRC_PLL5,
117 DCN20_CLK_SRC_TOTAL
118 };
119
120 /* begin *********************
121 * macros to expend register list macro defined in HW object header file */
122
123 /* DCN */
124 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
125
126 #define BASE(seg) BASE_INNER(seg)
127
128 #define SR(reg_name)\
129 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
130 mm ## reg_name
131
132 #define SRI(reg_name, block, id)\
133 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 mm ## block ## id ## _ ## reg_name
135
136 #define SRI2_DWB(reg_name, block, id)\
137 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
138 mm ## reg_name
139 #define SF_DWB(reg_name, field_name, post_fix)\
140 .field_name = reg_name ## __ ## field_name ## post_fix
141
142 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
143 .field_name = reg_name ## __ ## field_name ## post_fix
144
145 #define SRIR(var_name, reg_name, block, id)\
146 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 mm ## block ## id ## _ ## reg_name
148
149 #define SRII(reg_name, block, id)\
150 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 mm ## block ## id ## _ ## reg_name
152
153 #define DCCG_SRII(reg_name, block, id)\
154 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
155 mm ## block ## id ## _ ## reg_name
156
157 #define VUPDATE_SRII(reg_name, block, id)\
158 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
159 mm ## reg_name ## _ ## block ## id
160
161 /* NBIO */
162 #define NBIO_BASE_INNER(seg) \
163 NBIO_BASE__INST0_SEG ## seg
164
165 #define NBIO_BASE(seg) \
166 NBIO_BASE_INNER(seg)
167
168 #define NBIO_SR(reg_name)\
169 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
170 mm ## reg_name
171
172 /* MMHUB */
173 #define MMHUB_BASE_INNER(seg) \
174 MMHUB_BASE__INST0_SEG ## seg
175
176 #define MMHUB_BASE(seg) \
177 MMHUB_BASE_INNER(seg)
178
179 #define MMHUB_SR(reg_name)\
180 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
181 mmMM ## reg_name
182
183 static const struct bios_registers bios_regs = {
184 NBIO_SR(BIOS_SCRATCH_3),
185 NBIO_SR(BIOS_SCRATCH_6)
186 };
187
188 #define clk_src_regs(index, pllid)\
189 [index] = {\
190 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
191 }
192
193 static const struct dce110_clk_src_regs clk_src_regs[] = {
194 clk_src_regs(0, A),
195 clk_src_regs(1, B),
196 clk_src_regs(2, C),
197 clk_src_regs(3, D),
198 clk_src_regs(4, E),
199 clk_src_regs(5, F)
200 };
201
202 static const struct dce110_clk_src_shift cs_shift = {
203 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
204 };
205
206 static const struct dce110_clk_src_mask cs_mask = {
207 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
208 };
209
210 static const struct dce_dmcu_registers dmcu_regs = {
211 DMCU_DCN10_REG_LIST()
212 };
213
214 static const struct dce_dmcu_shift dmcu_shift = {
215 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
216 };
217
218 static const struct dce_dmcu_mask dmcu_mask = {
219 DMCU_MASK_SH_LIST_DCN10(_MASK)
220 };
221
222 static const struct dce_abm_registers abm_regs = {
223 ABM_DCN20_REG_LIST()
224 };
225
226 static const struct dce_abm_shift abm_shift = {
227 ABM_MASK_SH_LIST_DCN20(__SHIFT)
228 };
229
230 static const struct dce_abm_mask abm_mask = {
231 ABM_MASK_SH_LIST_DCN20(_MASK)
232 };
233
234 #define audio_regs(id)\
235 [id] = {\
236 AUD_COMMON_REG_LIST(id)\
237 }
238
239 static const struct dce_audio_registers audio_regs[] = {
240 audio_regs(0),
241 audio_regs(1),
242 audio_regs(2),
243 audio_regs(3),
244 audio_regs(4),
245 audio_regs(5),
246 audio_regs(6),
247 };
248
249 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
250 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
251 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
252 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
253
254 static const struct dce_audio_shift audio_shift = {
255 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
256 };
257
258 static const struct dce_audio_mask audio_mask = {
259 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
260 };
261
262 #define stream_enc_regs(id)\
263 [id] = {\
264 SE_DCN2_REG_LIST(id)\
265 }
266
267 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
268 stream_enc_regs(0),
269 stream_enc_regs(1),
270 stream_enc_regs(2),
271 stream_enc_regs(3),
272 stream_enc_regs(4),
273 stream_enc_regs(5),
274 };
275
276 static const struct dcn10_stream_encoder_shift se_shift = {
277 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
278 };
279
280 static const struct dcn10_stream_encoder_mask se_mask = {
281 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
282 };
283
284
285 #define aux_regs(id)\
286 [id] = {\
287 DCN2_AUX_REG_LIST(id)\
288 }
289
290 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
291 aux_regs(0),
292 aux_regs(1),
293 aux_regs(2),
294 aux_regs(3),
295 aux_regs(4),
296 aux_regs(5)
297 };
298
299 #define hpd_regs(id)\
300 [id] = {\
301 HPD_REG_LIST(id)\
302 }
303
304 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
305 hpd_regs(0),
306 hpd_regs(1),
307 hpd_regs(2),
308 hpd_regs(3),
309 hpd_regs(4),
310 hpd_regs(5)
311 };
312
313 #define link_regs(id, phyid)\
314 [id] = {\
315 LE_DCN10_REG_LIST(id), \
316 UNIPHY_DCN2_REG_LIST(phyid), \
317 DPCS_DCN2_REG_LIST(id), \
318 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
319 }
320
321 static const struct dcn10_link_enc_registers link_enc_regs[] = {
322 link_regs(0, A),
323 link_regs(1, B),
324 link_regs(2, C),
325 link_regs(3, D),
326 link_regs(4, E),
327 link_regs(5, F)
328 };
329
330 static const struct dcn10_link_enc_shift le_shift = {
331 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
332 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
333 };
334
335 static const struct dcn10_link_enc_mask le_mask = {
336 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
337 DPCS_DCN2_MASK_SH_LIST(_MASK)
338 };
339
340 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
341 { DCN_PANEL_CNTL_REG_LIST() }
342 };
343
344 static const struct dce_panel_cntl_shift panel_cntl_shift = {
345 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
346 };
347
348 static const struct dce_panel_cntl_mask panel_cntl_mask = {
349 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
350 };
351
352 #define ipp_regs(id)\
353 [id] = {\
354 IPP_REG_LIST_DCN20(id),\
355 }
356
357 static const struct dcn10_ipp_registers ipp_regs[] = {
358 ipp_regs(0),
359 ipp_regs(1),
360 ipp_regs(2),
361 ipp_regs(3),
362 ipp_regs(4),
363 ipp_regs(5),
364 };
365
366 static const struct dcn10_ipp_shift ipp_shift = {
367 IPP_MASK_SH_LIST_DCN20(__SHIFT)
368 };
369
370 static const struct dcn10_ipp_mask ipp_mask = {
371 IPP_MASK_SH_LIST_DCN20(_MASK),
372 };
373
374 #define opp_regs(id)\
375 [id] = {\
376 OPP_REG_LIST_DCN20(id),\
377 }
378
379 static const struct dcn20_opp_registers opp_regs[] = {
380 opp_regs(0),
381 opp_regs(1),
382 opp_regs(2),
383 opp_regs(3),
384 opp_regs(4),
385 opp_regs(5),
386 };
387
388 static const struct dcn20_opp_shift opp_shift = {
389 OPP_MASK_SH_LIST_DCN20(__SHIFT)
390 };
391
392 static const struct dcn20_opp_mask opp_mask = {
393 OPP_MASK_SH_LIST_DCN20(_MASK)
394 };
395
396 #define aux_engine_regs(id)\
397 [id] = {\
398 AUX_COMMON_REG_LIST0(id), \
399 .AUXN_IMPCAL = 0, \
400 .AUXP_IMPCAL = 0, \
401 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
402 }
403
404 static const struct dce110_aux_registers aux_engine_regs[] = {
405 aux_engine_regs(0),
406 aux_engine_regs(1),
407 aux_engine_regs(2),
408 aux_engine_regs(3),
409 aux_engine_regs(4),
410 aux_engine_regs(5)
411 };
412
413 #define tf_regs(id)\
414 [id] = {\
415 TF_REG_LIST_DCN20(id),\
416 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
417 }
418
419 static const struct dcn2_dpp_registers tf_regs[] = {
420 tf_regs(0),
421 tf_regs(1),
422 tf_regs(2),
423 tf_regs(3),
424 tf_regs(4),
425 tf_regs(5),
426 };
427
428 static const struct dcn2_dpp_shift tf_shift = {
429 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
430 TF_DEBUG_REG_LIST_SH_DCN20
431 };
432
433 static const struct dcn2_dpp_mask tf_mask = {
434 TF_REG_LIST_SH_MASK_DCN20(_MASK),
435 TF_DEBUG_REG_LIST_MASK_DCN20
436 };
437
438 #define dwbc_regs_dcn2(id)\
439 [id] = {\
440 DWBC_COMMON_REG_LIST_DCN2_0(id),\
441 }
442
443 static const struct dcn20_dwbc_registers dwbc20_regs[] = {
444 dwbc_regs_dcn2(0),
445 };
446
447 static const struct dcn20_dwbc_shift dwbc20_shift = {
448 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
449 };
450
451 static const struct dcn20_dwbc_mask dwbc20_mask = {
452 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
453 };
454
455 #define mcif_wb_regs_dcn2(id)\
456 [id] = {\
457 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
458 }
459
460 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
461 mcif_wb_regs_dcn2(0),
462 };
463
464 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
465 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
466 };
467
468 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
469 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
470 };
471
472 static const struct dcn20_mpc_registers mpc_regs = {
473 MPC_REG_LIST_DCN2_0(0),
474 MPC_REG_LIST_DCN2_0(1),
475 MPC_REG_LIST_DCN2_0(2),
476 MPC_REG_LIST_DCN2_0(3),
477 MPC_REG_LIST_DCN2_0(4),
478 MPC_REG_LIST_DCN2_0(5),
479 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
480 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
481 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
482 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
483 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
484 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
485 MPC_DBG_REG_LIST_DCN2_0()
486 };
487
488 static const struct dcn20_mpc_shift mpc_shift = {
489 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
490 MPC_DEBUG_REG_LIST_SH_DCN20
491 };
492
493 static const struct dcn20_mpc_mask mpc_mask = {
494 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
495 MPC_DEBUG_REG_LIST_MASK_DCN20
496 };
497
498 #define tg_regs(id)\
499 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
500
501
502 static const struct dcn_optc_registers tg_regs[] = {
503 tg_regs(0),
504 tg_regs(1),
505 tg_regs(2),
506 tg_regs(3),
507 tg_regs(4),
508 tg_regs(5)
509 };
510
511 static const struct dcn_optc_shift tg_shift = {
512 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
513 };
514
515 static const struct dcn_optc_mask tg_mask = {
516 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
517 };
518
519 #define hubp_regs(id)\
520 [id] = {\
521 HUBP_REG_LIST_DCN20(id)\
522 }
523
524 static const struct dcn_hubp2_registers hubp_regs[] = {
525 hubp_regs(0),
526 hubp_regs(1),
527 hubp_regs(2),
528 hubp_regs(3),
529 hubp_regs(4),
530 hubp_regs(5)
531 };
532
533 static const struct dcn_hubp2_shift hubp_shift = {
534 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
535 };
536
537 static const struct dcn_hubp2_mask hubp_mask = {
538 HUBP_MASK_SH_LIST_DCN20(_MASK)
539 };
540
541 static const struct dcn_hubbub_registers hubbub_reg = {
542 HUBBUB_REG_LIST_DCN20(0)
543 };
544
545 static const struct dcn_hubbub_shift hubbub_shift = {
546 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
547 };
548
549 static const struct dcn_hubbub_mask hubbub_mask = {
550 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
551 };
552
553 #define vmid_regs(id)\
554 [id] = {\
555 DCN20_VMID_REG_LIST(id)\
556 }
557
558 static const struct dcn_vmid_registers vmid_regs[] = {
559 vmid_regs(0),
560 vmid_regs(1),
561 vmid_regs(2),
562 vmid_regs(3),
563 vmid_regs(4),
564 vmid_regs(5),
565 vmid_regs(6),
566 vmid_regs(7),
567 vmid_regs(8),
568 vmid_regs(9),
569 vmid_regs(10),
570 vmid_regs(11),
571 vmid_regs(12),
572 vmid_regs(13),
573 vmid_regs(14),
574 vmid_regs(15)
575 };
576
577 static const struct dcn20_vmid_shift vmid_shifts = {
578 DCN20_VMID_MASK_SH_LIST(__SHIFT)
579 };
580
581 static const struct dcn20_vmid_mask vmid_masks = {
582 DCN20_VMID_MASK_SH_LIST(_MASK)
583 };
584
585 static const struct dce110_aux_registers_shift aux_shift = {
586 DCN_AUX_MASK_SH_LIST(__SHIFT)
587 };
588
589 static const struct dce110_aux_registers_mask aux_mask = {
590 DCN_AUX_MASK_SH_LIST(_MASK)
591 };
592
map_transmitter_id_to_phy_instance(enum transmitter transmitter)593 static int map_transmitter_id_to_phy_instance(
594 enum transmitter transmitter)
595 {
596 switch (transmitter) {
597 case TRANSMITTER_UNIPHY_A:
598 return 0;
599 break;
600 case TRANSMITTER_UNIPHY_B:
601 return 1;
602 break;
603 case TRANSMITTER_UNIPHY_C:
604 return 2;
605 break;
606 case TRANSMITTER_UNIPHY_D:
607 return 3;
608 break;
609 case TRANSMITTER_UNIPHY_E:
610 return 4;
611 break;
612 case TRANSMITTER_UNIPHY_F:
613 return 5;
614 break;
615 default:
616 ASSERT(0);
617 return 0;
618 }
619 }
620
621 #define dsc_regsDCN20(id)\
622 [id] = {\
623 DSC_REG_LIST_DCN20(id)\
624 }
625
626 static const struct dcn20_dsc_registers dsc_regs[] = {
627 dsc_regsDCN20(0),
628 dsc_regsDCN20(1),
629 dsc_regsDCN20(2),
630 dsc_regsDCN20(3),
631 dsc_regsDCN20(4),
632 dsc_regsDCN20(5)
633 };
634
635 static const struct dcn20_dsc_shift dsc_shift = {
636 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
637 };
638
639 static const struct dcn20_dsc_mask dsc_mask = {
640 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
641 };
642
643 static const struct dccg_registers dccg_regs = {
644 DCCG_REG_LIST_DCN2()
645 };
646
647 static const struct dccg_shift dccg_shift = {
648 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
649 };
650
651 static const struct dccg_mask dccg_mask = {
652 DCCG_MASK_SH_LIST_DCN2(_MASK)
653 };
654
655 static const struct resource_caps res_cap_nv10 = {
656 .num_timing_generator = 6,
657 .num_opp = 6,
658 .num_video_plane = 6,
659 .num_audio = 7,
660 .num_stream_encoder = 6,
661 .num_pll = 6,
662 .num_dwb = 1,
663 .num_ddc = 6,
664 .num_vmid = 16,
665 .num_dsc = 6,
666 };
667
668 static const struct dc_plane_cap plane_cap = {
669 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
670 .per_pixel_alpha = true,
671
672 .pixel_format_support = {
673 .argb8888 = true,
674 .nv12 = true,
675 .fp16 = true,
676 .p010 = true
677 },
678
679 .max_upscale_factor = {
680 .argb8888 = 16000,
681 .nv12 = 16000,
682 .fp16 = 1
683 },
684
685 .max_downscale_factor = {
686 .argb8888 = 250,
687 .nv12 = 250,
688 .fp16 = 1
689 },
690 16,
691 16
692 };
693 static const struct resource_caps res_cap_nv14 = {
694 .num_timing_generator = 5,
695 .num_opp = 5,
696 .num_video_plane = 5,
697 .num_audio = 6,
698 .num_stream_encoder = 5,
699 .num_pll = 5,
700 .num_dwb = 1,
701 .num_ddc = 5,
702 .num_vmid = 16,
703 .num_dsc = 5,
704 };
705
706 static const struct dc_debug_options debug_defaults_drv = {
707 .disable_dmcu = false,
708 .force_abm_enable = false,
709 .timing_trace = false,
710 .clock_trace = true,
711 .disable_pplib_clock_request = true,
712 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
713 .force_single_disp_pipe_split = false,
714 .disable_dcc = DCC_ENABLE,
715 .vsr_support = true,
716 .performance_trace = false,
717 .max_downscale_src_width = 5120,/*upto 5K*/
718 .disable_pplib_wm_range = false,
719 .scl_reset_length10 = true,
720 .sanity_checks = false,
721 .underflow_assert_delay_us = 0xFFFFFFFF,
722 .enable_legacy_fast_update = true,
723 .using_dml2 = false,
724 };
725
dcn20_dpp_destroy(struct dpp ** dpp)726 void dcn20_dpp_destroy(struct dpp **dpp)
727 {
728 kfree(TO_DCN20_DPP(*dpp));
729 *dpp = NULL;
730 }
731
dcn20_dpp_create(struct dc_context * ctx,uint32_t inst)732 struct dpp *dcn20_dpp_create(
733 struct dc_context *ctx,
734 uint32_t inst)
735 {
736 struct dcn20_dpp *dpp =
737 kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC);
738
739 if (!dpp)
740 return NULL;
741
742 if (dpp2_construct(dpp, ctx, inst,
743 &tf_regs[inst], &tf_shift, &tf_mask))
744 return &dpp->base;
745
746 BREAK_TO_DEBUGGER();
747 kfree(dpp);
748 return NULL;
749 }
750
dcn20_ipp_create(struct dc_context * ctx,uint32_t inst)751 struct input_pixel_processor *dcn20_ipp_create(
752 struct dc_context *ctx, uint32_t inst)
753 {
754 struct dcn10_ipp *ipp =
755 kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);
756
757 if (!ipp) {
758 BREAK_TO_DEBUGGER();
759 return NULL;
760 }
761
762 dcn20_ipp_construct(ipp, ctx, inst,
763 &ipp_regs[inst], &ipp_shift, &ipp_mask);
764 return &ipp->base;
765 }
766
767
dcn20_opp_create(struct dc_context * ctx,uint32_t inst)768 struct output_pixel_processor *dcn20_opp_create(
769 struct dc_context *ctx, uint32_t inst)
770 {
771 struct dcn20_opp *opp =
772 kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC);
773
774 if (!opp) {
775 BREAK_TO_DEBUGGER();
776 return NULL;
777 }
778
779 dcn20_opp_construct(opp, ctx, inst,
780 &opp_regs[inst], &opp_shift, &opp_mask);
781 return &opp->base;
782 }
783
dcn20_aux_engine_create(struct dc_context * ctx,uint32_t inst)784 struct dce_aux *dcn20_aux_engine_create(
785 struct dc_context *ctx,
786 uint32_t inst)
787 {
788 struct aux_engine_dce110 *aux_engine =
789 kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
790
791 if (!aux_engine)
792 return NULL;
793
794 dce110_aux_engine_construct(aux_engine, ctx, inst,
795 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
796 &aux_engine_regs[inst],
797 &aux_mask,
798 &aux_shift,
799 ctx->dc->caps.extended_aux_timeout_support);
800
801 return &aux_engine->base;
802 }
803 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
804
805 static const struct dce_i2c_registers i2c_hw_regs[] = {
806 i2c_inst_regs(1),
807 i2c_inst_regs(2),
808 i2c_inst_regs(3),
809 i2c_inst_regs(4),
810 i2c_inst_regs(5),
811 i2c_inst_regs(6),
812 };
813
814 static const struct dce_i2c_shift i2c_shifts = {
815 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
816 };
817
818 static const struct dce_i2c_mask i2c_masks = {
819 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
820 };
821
dcn20_i2c_hw_create(struct dc_context * ctx,uint32_t inst)822 struct dce_i2c_hw *dcn20_i2c_hw_create(
823 struct dc_context *ctx,
824 uint32_t inst)
825 {
826 struct dce_i2c_hw *dce_i2c_hw =
827 kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);
828
829 if (!dce_i2c_hw)
830 return NULL;
831
832 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
833 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
834
835 return dce_i2c_hw;
836 }
dcn20_mpc_create(struct dc_context * ctx)837 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
838 {
839 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
840 GFP_ATOMIC);
841
842 if (!mpc20)
843 return NULL;
844
845 dcn20_mpc_construct(mpc20, ctx,
846 &mpc_regs,
847 &mpc_shift,
848 &mpc_mask,
849 6);
850
851 return &mpc20->base;
852 }
853
dcn20_hubbub_create(struct dc_context * ctx)854 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
855 {
856 int i;
857 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
858 GFP_ATOMIC);
859
860 if (!hubbub)
861 return NULL;
862
863 hubbub2_construct(hubbub, ctx,
864 &hubbub_reg,
865 &hubbub_shift,
866 &hubbub_mask);
867
868 for (i = 0; i < res_cap_nv10.num_vmid; i++) {
869 struct dcn20_vmid *vmid = &hubbub->vmid[i];
870
871 vmid->ctx = ctx;
872
873 vmid->regs = &vmid_regs[i];
874 vmid->shifts = &vmid_shifts;
875 vmid->masks = &vmid_masks;
876 }
877
878 return &hubbub->base;
879 }
880
dcn20_timing_generator_create(struct dc_context * ctx,uint32_t instance)881 struct timing_generator *dcn20_timing_generator_create(
882 struct dc_context *ctx,
883 uint32_t instance)
884 {
885 struct optc *tgn10 =
886 kzalloc(sizeof(struct optc), GFP_ATOMIC);
887
888 if (!tgn10)
889 return NULL;
890
891 tgn10->base.inst = instance;
892 tgn10->base.ctx = ctx;
893
894 tgn10->tg_regs = &tg_regs[instance];
895 tgn10->tg_shift = &tg_shift;
896 tgn10->tg_mask = &tg_mask;
897
898 dcn20_timing_generator_init(tgn10);
899
900 return &tgn10->base;
901 }
902
903 static const struct encoder_feature_support link_enc_feature = {
904 .max_hdmi_deep_color = COLOR_DEPTH_121212,
905 .max_hdmi_pixel_clock = 600000,
906 .hdmi_ycbcr420_supported = true,
907 .dp_ycbcr420_supported = true,
908 .fec_supported = true,
909 .flags.bits.IS_HBR2_CAPABLE = true,
910 .flags.bits.IS_HBR3_CAPABLE = true,
911 .flags.bits.IS_TPS3_CAPABLE = true,
912 .flags.bits.IS_TPS4_CAPABLE = true
913 };
914
dcn20_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)915 struct link_encoder *dcn20_link_encoder_create(
916 struct dc_context *ctx,
917 const struct encoder_init_data *enc_init_data)
918 {
919 struct dcn20_link_encoder *enc20 =
920 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
921 int link_regs_id;
922
923 if (!enc20)
924 return NULL;
925
926 link_regs_id =
927 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
928
929 dcn20_link_encoder_construct(enc20,
930 enc_init_data,
931 &link_enc_feature,
932 &link_enc_regs[link_regs_id],
933 &link_enc_aux_regs[enc_init_data->channel - 1],
934 &link_enc_hpd_regs[enc_init_data->hpd_source],
935 &le_shift,
936 &le_mask);
937
938 return &enc20->enc10.base;
939 }
940
dcn20_panel_cntl_create(const struct panel_cntl_init_data * init_data)941 static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data)
942 {
943 struct dce_panel_cntl *panel_cntl =
944 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
945
946 if (!panel_cntl)
947 return NULL;
948
949 dce_panel_cntl_construct(panel_cntl,
950 init_data,
951 &panel_cntl_regs[init_data->inst],
952 &panel_cntl_shift,
953 &panel_cntl_mask);
954
955 return &panel_cntl->base;
956 }
957
dcn20_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)958 static struct clock_source *dcn20_clock_source_create(
959 struct dc_context *ctx,
960 struct dc_bios *bios,
961 enum clock_source_id id,
962 const struct dce110_clk_src_regs *regs,
963 bool dp_clk_src)
964 {
965 struct dce110_clk_src *clk_src =
966 kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);
967
968 if (!clk_src)
969 return NULL;
970
971 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
972 regs, &cs_shift, &cs_mask)) {
973 clk_src->base.dp_clk_src = dp_clk_src;
974 return &clk_src->base;
975 }
976
977 kfree(clk_src);
978 BREAK_TO_DEBUGGER();
979 return NULL;
980 }
981
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)982 static void read_dce_straps(
983 struct dc_context *ctx,
984 struct resource_straps *straps)
985 {
986 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
987 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
988 }
989
dcn20_create_audio(struct dc_context * ctx,unsigned int inst)990 static struct audio *dcn20_create_audio(
991 struct dc_context *ctx, unsigned int inst)
992 {
993 return dce_audio_create(ctx, inst,
994 &audio_regs[inst], &audio_shift, &audio_mask);
995 }
996
dcn20_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)997 struct stream_encoder *dcn20_stream_encoder_create(
998 enum engine_id eng_id,
999 struct dc_context *ctx)
1000 {
1001 struct dcn10_stream_encoder *enc1 =
1002 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1003
1004 if (!enc1)
1005 return NULL;
1006
1007 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1008 if (eng_id >= ENGINE_ID_DIGD)
1009 eng_id++;
1010 }
1011
1012 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1013 &stream_enc_regs[eng_id],
1014 &se_shift, &se_mask);
1015
1016 return &enc1->base;
1017 }
1018
1019 static const struct dce_hwseq_registers hwseq_reg = {
1020 HWSEQ_DCN2_REG_LIST()
1021 };
1022
1023 static const struct dce_hwseq_shift hwseq_shift = {
1024 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1025 };
1026
1027 static const struct dce_hwseq_mask hwseq_mask = {
1028 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1029 };
1030
dcn20_hwseq_create(struct dc_context * ctx)1031 struct dce_hwseq *dcn20_hwseq_create(
1032 struct dc_context *ctx)
1033 {
1034 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1035
1036 if (hws) {
1037 hws->ctx = ctx;
1038 hws->regs = &hwseq_reg;
1039 hws->shifts = &hwseq_shift;
1040 hws->masks = &hwseq_mask;
1041 }
1042 return hws;
1043 }
1044
1045 static const struct resource_create_funcs res_create_funcs = {
1046 .read_dce_straps = read_dce_straps,
1047 .create_audio = dcn20_create_audio,
1048 .create_stream_encoder = dcn20_stream_encoder_create,
1049 .create_hwseq = dcn20_hwseq_create,
1050 };
1051
1052 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1053
dcn20_clock_source_destroy(struct clock_source ** clk_src)1054 void dcn20_clock_source_destroy(struct clock_source **clk_src)
1055 {
1056 kfree(TO_DCE110_CLK_SRC(*clk_src));
1057 *clk_src = NULL;
1058 }
1059
1060
dcn20_dsc_create(struct dc_context * ctx,uint32_t inst)1061 struct display_stream_compressor *dcn20_dsc_create(
1062 struct dc_context *ctx, uint32_t inst)
1063 {
1064 struct dcn20_dsc *dsc =
1065 kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC);
1066
1067 if (!dsc) {
1068 BREAK_TO_DEBUGGER();
1069 return NULL;
1070 }
1071
1072 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1073 return &dsc->base;
1074 }
1075
dcn20_dsc_destroy(struct display_stream_compressor ** dsc)1076 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1077 {
1078 kfree(container_of(*dsc, struct dcn20_dsc, base));
1079 *dsc = NULL;
1080 }
1081
1082
dcn20_resource_destruct(struct dcn20_resource_pool * pool)1083 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
1084 {
1085 unsigned int i;
1086
1087 for (i = 0; i < pool->base.stream_enc_count; i++) {
1088 if (pool->base.stream_enc[i] != NULL) {
1089 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1090 pool->base.stream_enc[i] = NULL;
1091 }
1092 }
1093
1094 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1095 if (pool->base.dscs[i] != NULL)
1096 dcn20_dsc_destroy(&pool->base.dscs[i]);
1097 }
1098
1099 if (pool->base.mpc != NULL) {
1100 kfree(TO_DCN20_MPC(pool->base.mpc));
1101 pool->base.mpc = NULL;
1102 }
1103 if (pool->base.hubbub != NULL) {
1104 kfree(pool->base.hubbub);
1105 pool->base.hubbub = NULL;
1106 }
1107 for (i = 0; i < pool->base.pipe_count; i++) {
1108 if (pool->base.dpps[i] != NULL)
1109 dcn20_dpp_destroy(&pool->base.dpps[i]);
1110
1111 if (pool->base.ipps[i] != NULL)
1112 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1113
1114 if (pool->base.hubps[i] != NULL) {
1115 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1116 pool->base.hubps[i] = NULL;
1117 }
1118
1119 if (pool->base.irqs != NULL) {
1120 dal_irq_service_destroy(&pool->base.irqs);
1121 }
1122 }
1123
1124 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1125 if (pool->base.engines[i] != NULL)
1126 dce110_engine_destroy(&pool->base.engines[i]);
1127 if (pool->base.hw_i2cs[i] != NULL) {
1128 kfree(pool->base.hw_i2cs[i]);
1129 pool->base.hw_i2cs[i] = NULL;
1130 }
1131 if (pool->base.sw_i2cs[i] != NULL) {
1132 kfree(pool->base.sw_i2cs[i]);
1133 pool->base.sw_i2cs[i] = NULL;
1134 }
1135 }
1136
1137 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1138 if (pool->base.opps[i] != NULL)
1139 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1140 }
1141
1142 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1143 if (pool->base.timing_generators[i] != NULL) {
1144 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1145 pool->base.timing_generators[i] = NULL;
1146 }
1147 }
1148
1149 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1150 if (pool->base.dwbc[i] != NULL) {
1151 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1152 pool->base.dwbc[i] = NULL;
1153 }
1154 if (pool->base.mcif_wb[i] != NULL) {
1155 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1156 pool->base.mcif_wb[i] = NULL;
1157 }
1158 }
1159
1160 for (i = 0; i < pool->base.audio_count; i++) {
1161 if (pool->base.audios[i])
1162 dce_aud_destroy(&pool->base.audios[i]);
1163 }
1164
1165 for (i = 0; i < pool->base.clk_src_count; i++) {
1166 if (pool->base.clock_sources[i] != NULL) {
1167 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1168 pool->base.clock_sources[i] = NULL;
1169 }
1170 }
1171
1172 if (pool->base.dp_clock_source != NULL) {
1173 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1174 pool->base.dp_clock_source = NULL;
1175 }
1176
1177
1178 if (pool->base.abm != NULL)
1179 dce_abm_destroy(&pool->base.abm);
1180
1181 if (pool->base.dmcu != NULL)
1182 dce_dmcu_destroy(&pool->base.dmcu);
1183
1184 if (pool->base.dccg != NULL)
1185 dcn_dccg_destroy(&pool->base.dccg);
1186
1187 if (pool->base.pp_smu != NULL)
1188 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1189
1190 if (pool->base.oem_device != NULL) {
1191 struct dc *dc = pool->base.oem_device->ctx->dc;
1192
1193 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1194 }
1195 }
1196
dcn20_hubp_create(struct dc_context * ctx,uint32_t inst)1197 struct hubp *dcn20_hubp_create(
1198 struct dc_context *ctx,
1199 uint32_t inst)
1200 {
1201 struct dcn20_hubp *hubp2 =
1202 kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC);
1203
1204 if (!hubp2)
1205 return NULL;
1206
1207 if (hubp2_construct(hubp2, ctx, inst,
1208 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1209 return &hubp2->base;
1210
1211 BREAK_TO_DEBUGGER();
1212 kfree(hubp2);
1213 return NULL;
1214 }
1215
get_pixel_clock_parameters(struct pipe_ctx * pipe_ctx,struct pixel_clk_params * pixel_clk_params)1216 static void get_pixel_clock_parameters(
1217 struct pipe_ctx *pipe_ctx,
1218 struct pixel_clk_params *pixel_clk_params)
1219 {
1220 const struct dc_stream_state *stream = pipe_ctx->stream;
1221 struct pipe_ctx *odm_pipe;
1222 int opp_cnt = 1;
1223 struct dc_link *link = stream->link;
1224 struct link_encoder *link_enc = NULL;
1225 struct dc *dc = pipe_ctx->stream->ctx->dc;
1226 struct dce_hwseq *hws = dc->hwseq;
1227
1228 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1229 opp_cnt++;
1230
1231 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1232
1233 link_enc = link_enc_cfg_get_link_enc(link);
1234 if (link_enc)
1235 pixel_clk_params->encoder_object_id = link_enc->id;
1236
1237 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1238 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1239 /* TODO: un-hardcode*/
1240 /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */
1241 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1242 LINK_RATE_REF_FREQ_IN_KHZ;
1243 pixel_clk_params->flags.ENABLE_SS = 0;
1244 pixel_clk_params->color_depth =
1245 stream->timing.display_color_depth;
1246 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1247 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1248
1249 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1250 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1251
1252 if (opp_cnt == 4)
1253 pixel_clk_params->requested_pix_clk_100hz /= 4;
1254 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
1255 pixel_clk_params->requested_pix_clk_100hz /= 2;
1256 else if (hws->funcs.is_dp_dig_pixel_rate_div_policy) {
1257 if (hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1258 pixel_clk_params->requested_pix_clk_100hz /= 2;
1259 }
1260
1261 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1262 pixel_clk_params->requested_pix_clk_100hz *= 2;
1263
1264 }
1265
build_clamping_params(struct dc_stream_state * stream)1266 static void build_clamping_params(struct dc_stream_state *stream)
1267 {
1268 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1269 stream->clamping.c_depth = stream->timing.display_color_depth;
1270 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1271 }
1272
dcn20_build_pipe_pix_clk_params(struct pipe_ctx * pipe_ctx)1273 void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
1274 {
1275 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1276 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1277 pipe_ctx->clock_source,
1278 &pipe_ctx->stream_res.pix_clk_params,
1279 &pipe_ctx->pll_settings);
1280 }
1281
build_pipe_hw_param(struct pipe_ctx * pipe_ctx)1282 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1283 {
1284 struct resource_pool *pool = pipe_ctx->stream->ctx->dc->res_pool;
1285
1286 if (pool->funcs->build_pipe_pix_clk_params) {
1287 pool->funcs->build_pipe_pix_clk_params(pipe_ctx);
1288 } else {
1289 dcn20_build_pipe_pix_clk_params(pipe_ctx);
1290 }
1291
1292 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1293
1294 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1295 &pipe_ctx->stream->bit_depth_params);
1296 build_clamping_params(pipe_ctx->stream);
1297
1298 return DC_OK;
1299 }
1300
dcn20_build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)1301 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1302 {
1303 enum dc_status status = DC_OK;
1304 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
1305
1306 if (!pipe_ctx)
1307 return DC_ERROR_UNEXPECTED;
1308
1309
1310 status = build_pipe_hw_param(pipe_ctx);
1311
1312 return status;
1313 }
1314
1315
dcn20_acquire_dsc(const struct dc * dc,struct resource_context * res_ctx,struct display_stream_compressor ** dsc,int pipe_idx)1316 void dcn20_acquire_dsc(const struct dc *dc,
1317 struct resource_context *res_ctx,
1318 struct display_stream_compressor **dsc,
1319 int pipe_idx)
1320 {
1321 int i;
1322 const struct resource_pool *pool = dc->res_pool;
1323 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;
1324
1325 ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */
1326 *dsc = NULL;
1327
1328 /* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */
1329 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1330 *dsc = pool->dscs[pipe_idx];
1331 res_ctx->is_dsc_acquired[pipe_idx] = true;
1332 return;
1333 }
1334
1335 /* Return old DSC to avoid the need for re-programming */
1336 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) {
1337 *dsc = dsc_old;
1338 res_ctx->is_dsc_acquired[dsc_old->inst] = true;
1339 return ;
1340 }
1341
1342 /* Find first free DSC */
1343 for (i = 0; i < pool->res_cap->num_dsc; i++)
1344 if (!res_ctx->is_dsc_acquired[i]) {
1345 *dsc = pool->dscs[i];
1346 res_ctx->is_dsc_acquired[i] = true;
1347 break;
1348 }
1349 }
1350
dcn20_release_dsc(struct resource_context * res_ctx,const struct resource_pool * pool,struct display_stream_compressor ** dsc)1351 void dcn20_release_dsc(struct resource_context *res_ctx,
1352 const struct resource_pool *pool,
1353 struct display_stream_compressor **dsc)
1354 {
1355 int i;
1356
1357 for (i = 0; i < pool->res_cap->num_dsc; i++)
1358 if (pool->dscs[i] == *dsc) {
1359 res_ctx->is_dsc_acquired[i] = false;
1360 *dsc = NULL;
1361 break;
1362 }
1363 }
1364
1365
1366
dcn20_add_dsc_to_stream_resource(struct dc * dc,struct dc_state * dc_ctx,struct dc_stream_state * dc_stream)1367 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
1368 struct dc_state *dc_ctx,
1369 struct dc_stream_state *dc_stream)
1370 {
1371 enum dc_status result = DC_OK;
1372 int i;
1373
1374 /* Get a DSC if required and available */
1375 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1376 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1377
1378 if (pipe_ctx->top_pipe)
1379 continue;
1380
1381 if (pipe_ctx->stream != dc_stream)
1382 continue;
1383
1384 if (pipe_ctx->stream_res.dsc)
1385 continue;
1386
1387 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);
1388
1389 /* The number of DSCs can be less than the number of pipes */
1390 if (!pipe_ctx->stream_res.dsc) {
1391 result = DC_NO_DSC_RESOURCE;
1392 }
1393
1394 break;
1395 }
1396
1397 return result;
1398 }
1399
1400
remove_dsc_from_stream_resource(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1401 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1402 struct dc_state *new_ctx,
1403 struct dc_stream_state *dc_stream)
1404 {
1405 struct pipe_ctx *pipe_ctx = NULL;
1406 int i;
1407
1408 for (i = 0; i < MAX_PIPES; i++) {
1409 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1410 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1411
1412 if (pipe_ctx->stream_res.dsc)
1413 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1414 }
1415 }
1416
1417 if (!pipe_ctx)
1418 return DC_ERROR_UNEXPECTED;
1419 else
1420 return DC_OK;
1421 }
1422
1423
dcn20_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1424 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1425 {
1426 enum dc_status result = DC_ERROR_UNEXPECTED;
1427
1428 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1429
1430 if (result == DC_OK)
1431 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1432
1433 /* Get a DSC if required and available */
1434 if (result == DC_OK && dc_stream->timing.flags.DSC)
1435 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1436
1437 if (result == DC_OK)
1438 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1439
1440 return result;
1441 }
1442
1443
dcn20_remove_stream_from_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1444 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1445 {
1446 enum dc_status result = DC_OK;
1447
1448 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1449
1450 return result;
1451 }
1452
1453 /**
1454 * dcn20_split_stream_for_odm - Check if stream can be splited for ODM
1455 *
1456 * @dc: DC object with resource pool info required for pipe split
1457 * @res_ctx: Persistent state of resources
1458 * @prev_odm_pipe: Reference to the previous ODM pipe
1459 * @next_odm_pipe: Reference to the next ODM pipe
1460 *
1461 * This function takes a logically active pipe and a logically free pipe and
1462 * halves all the scaling parameters that need to be halved while populating
1463 * the free pipe with the required resources and configuring the next/previous
1464 * ODM pipe pointers.
1465 *
1466 * Return:
1467 * Return true if split stream for ODM is possible, otherwise, return false.
1468 */
dcn20_split_stream_for_odm(const struct dc * dc,struct resource_context * res_ctx,struct pipe_ctx * prev_odm_pipe,struct pipe_ctx * next_odm_pipe)1469 bool dcn20_split_stream_for_odm(
1470 const struct dc *dc,
1471 struct resource_context *res_ctx,
1472 struct pipe_ctx *prev_odm_pipe,
1473 struct pipe_ctx *next_odm_pipe)
1474 {
1475 int pipe_idx = next_odm_pipe->pipe_idx;
1476 const struct resource_pool *pool = dc->res_pool;
1477
1478 *next_odm_pipe = *prev_odm_pipe;
1479
1480 next_odm_pipe->pipe_idx = pipe_idx;
1481 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1482 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1483 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1484 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1485 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1486 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1487 next_odm_pipe->stream_res.dsc = NULL;
1488 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
1489 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1490 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1491 }
1492 if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) {
1493 prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe;
1494 next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe;
1495 }
1496 if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) {
1497 prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe;
1498 next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe;
1499 }
1500 prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1501 next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1502
1503 if (prev_odm_pipe->plane_state) {
1504 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1505 int new_width;
1506
1507 /* HACTIVE halved for odm combine */
1508 sd->h_active /= 2;
1509 /* Calculate new vp and recout for left pipe */
1510 /* Need at least 16 pixels width per side */
1511 if (sd->recout.x + 16 >= sd->h_active)
1512 return false;
1513 new_width = sd->h_active - sd->recout.x;
1514 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1515 sd->ratios.horz, sd->recout.width - new_width));
1516 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1517 sd->ratios.horz_c, sd->recout.width - new_width));
1518 sd->recout.width = new_width;
1519
1520 /* Calculate new vp and recout for right pipe */
1521 sd = &next_odm_pipe->plane_res.scl_data;
1522 /* HACTIVE halved for odm combine */
1523 sd->h_active /= 2;
1524 /* Need at least 16 pixels width per side */
1525 if (new_width <= 16)
1526 return false;
1527 new_width = sd->recout.width + sd->recout.x - sd->h_active;
1528 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1529 sd->ratios.horz, sd->recout.width - new_width));
1530 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1531 sd->ratios.horz_c, sd->recout.width - new_width));
1532 sd->recout.width = new_width;
1533 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1534 sd->ratios.horz, sd->h_active - sd->recout.x));
1535 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1536 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1537 sd->recout.x = 0;
1538 }
1539 if (!next_odm_pipe->top_pipe)
1540 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1541 else
1542 next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp;
1543 if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) {
1544 dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
1545 ASSERT(next_odm_pipe->stream_res.dsc);
1546 if (next_odm_pipe->stream_res.dsc == NULL)
1547 return false;
1548 }
1549
1550 return true;
1551 }
1552
dcn20_split_stream_for_mpc(struct resource_context * res_ctx,const struct resource_pool * pool,struct pipe_ctx * primary_pipe,struct pipe_ctx * secondary_pipe)1553 void dcn20_split_stream_for_mpc(
1554 struct resource_context *res_ctx,
1555 const struct resource_pool *pool,
1556 struct pipe_ctx *primary_pipe,
1557 struct pipe_ctx *secondary_pipe)
1558 {
1559 int pipe_idx = secondary_pipe->pipe_idx;
1560 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1561
1562 *secondary_pipe = *primary_pipe;
1563 secondary_pipe->bottom_pipe = sec_bot_pipe;
1564
1565 secondary_pipe->pipe_idx = pipe_idx;
1566 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1567 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1568 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1569 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1570 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1571 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1572 secondary_pipe->stream_res.dsc = NULL;
1573 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1574 ASSERT(!secondary_pipe->bottom_pipe);
1575 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1576 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1577 }
1578 primary_pipe->bottom_pipe = secondary_pipe;
1579 secondary_pipe->top_pipe = primary_pipe;
1580
1581 ASSERT(primary_pipe->plane_state);
1582 }
1583
dcn20_calc_max_scaled_time(unsigned int time_per_pixel,enum mmhubbub_wbif_mode mode,unsigned int urgent_watermark)1584 unsigned int dcn20_calc_max_scaled_time(
1585 unsigned int time_per_pixel,
1586 enum mmhubbub_wbif_mode mode,
1587 unsigned int urgent_watermark)
1588 {
1589 unsigned int time_per_byte = 0;
1590 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
1591 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
1592 unsigned int small_free_entry, max_free_entry;
1593 unsigned int buf_lh_capability;
1594 unsigned int max_scaled_time;
1595
1596 if (mode == PACKED_444) /* packed mode */
1597 time_per_byte = time_per_pixel/4;
1598 else if (mode == PLANAR_420_8BPC)
1599 time_per_byte = time_per_pixel;
1600 else if (mode == PLANAR_420_10BPC) /* p010 */
1601 time_per_byte = time_per_pixel * 819/1024;
1602
1603 if (time_per_byte == 0)
1604 time_per_byte = 1;
1605
1606 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
1607 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
1608 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
1609 max_scaled_time = buf_lh_capability - urgent_watermark;
1610 return max_scaled_time;
1611 }
1612
dcn20_set_mcif_arb_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt)1613 void dcn20_set_mcif_arb_params(
1614 struct dc *dc,
1615 struct dc_state *context,
1616 display_e2e_pipe_params_st *pipes,
1617 int pipe_cnt)
1618 {
1619 enum mmhubbub_wbif_mode wbif_mode;
1620 struct mcif_arb_params *wb_arb_params;
1621 int i, j, dwb_pipe;
1622
1623 /* Writeback MCIF_WB arbitration parameters */
1624 dwb_pipe = 0;
1625 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1626
1627 if (!context->res_ctx.pipe_ctx[i].stream)
1628 continue;
1629
1630 for (j = 0; j < MAX_DWB_PIPES; j++) {
1631 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
1632 continue;
1633
1634 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1635 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1636
1637 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
1638 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1639 wbif_mode = PLANAR_420_8BPC;
1640 else
1641 wbif_mode = PLANAR_420_10BPC;
1642 } else
1643 wbif_mode = PACKED_444;
1644
1645 DC_FP_START();
1646 dcn20_fpu_set_wb_arb_params(wb_arb_params, context, pipes, pipe_cnt, i);
1647 DC_FP_END();
1648
1649 wb_arb_params->slice_lines = 32;
1650 wb_arb_params->arbitration_slice = 2;
1651 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1652 wbif_mode,
1653 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1654
1655 dwb_pipe++;
1656
1657 if (dwb_pipe >= MAX_DWB_PIPES)
1658 return;
1659 }
1660 if (dwb_pipe >= MAX_DWB_PIPES)
1661 return;
1662 }
1663 }
1664
dcn20_validate_dsc(struct dc * dc,struct dc_state * new_ctx)1665 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
1666 {
1667 int i;
1668
1669 /* Validate DSC config, dsc count validation is already done */
1670 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1671 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1672 struct dc_stream_state *stream = pipe_ctx->stream;
1673 struct dsc_config dsc_cfg;
1674 struct pipe_ctx *odm_pipe;
1675 int opp_cnt = 1;
1676
1677 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1678 opp_cnt++;
1679
1680 /* Only need to validate top pipe */
1681 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
1682 continue;
1683
1684 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
1685 + stream->timing.h_border_right) / opp_cnt;
1686 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
1687 + stream->timing.v_border_bottom;
1688 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1689 dsc_cfg.color_depth = stream->timing.display_color_depth;
1690 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
1691 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
1692 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
1693
1694 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
1695 return false;
1696 }
1697 return true;
1698 }
1699
dcn20_find_secondary_pipe(struct dc * dc,struct resource_context * res_ctx,const struct resource_pool * pool,const struct pipe_ctx * primary_pipe)1700 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
1701 struct resource_context *res_ctx,
1702 const struct resource_pool *pool,
1703 const struct pipe_ctx *primary_pipe)
1704 {
1705 struct pipe_ctx *secondary_pipe = NULL;
1706
1707 if (dc && primary_pipe) {
1708 int j;
1709 int preferred_pipe_idx = 0;
1710
1711 /* first check the prev dc state:
1712 * if this primary pipe has a bottom pipe in prev. state
1713 * and if the bottom pipe is still available (which it should be),
1714 * pick that pipe as secondary
1715 * Same logic applies for ODM pipes
1716 */
1717 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
1718 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
1719 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1720 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1721 secondary_pipe->pipe_idx = preferred_pipe_idx;
1722 }
1723 }
1724 if (secondary_pipe == NULL &&
1725 dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
1726 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
1727 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1728 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1729 secondary_pipe->pipe_idx = preferred_pipe_idx;
1730 }
1731 }
1732
1733 /*
1734 * if this primary pipe does not have a bottom pipe in prev. state
1735 * start backward and find a pipe that did not used to be a bottom pipe in
1736 * prev. dc state. This way we make sure we keep the same assignment as
1737 * last state and will not have to reprogram every pipe
1738 */
1739 if (secondary_pipe == NULL) {
1740 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
1741 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
1742 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
1743 preferred_pipe_idx = j;
1744
1745 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1746 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1747 secondary_pipe->pipe_idx = preferred_pipe_idx;
1748 break;
1749 }
1750 }
1751 }
1752 }
1753 /*
1754 * We should never hit this assert unless assignments are shuffled around
1755 * if this happens we will prob. hit a vsync tdr
1756 */
1757 ASSERT(secondary_pipe);
1758 /*
1759 * search backwards for the second pipe to keep pipe
1760 * assignment more consistent
1761 */
1762 if (secondary_pipe == NULL) {
1763 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
1764 preferred_pipe_idx = j;
1765
1766 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1767 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1768 secondary_pipe->pipe_idx = preferred_pipe_idx;
1769 break;
1770 }
1771 }
1772 }
1773 }
1774
1775 return secondary_pipe;
1776 }
1777
dcn20_merge_pipes_for_validate(struct dc * dc,struct dc_state * context)1778 void dcn20_merge_pipes_for_validate(
1779 struct dc *dc,
1780 struct dc_state *context)
1781 {
1782 int i;
1783
1784 /* merge previously split odm pipes since mode support needs to make the decision */
1785 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1786 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1787 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
1788
1789 if (pipe->prev_odm_pipe)
1790 continue;
1791
1792 pipe->next_odm_pipe = NULL;
1793 while (odm_pipe) {
1794 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1795
1796 odm_pipe->plane_state = NULL;
1797 odm_pipe->stream = NULL;
1798 odm_pipe->top_pipe = NULL;
1799 odm_pipe->bottom_pipe = NULL;
1800 odm_pipe->prev_odm_pipe = NULL;
1801 odm_pipe->next_odm_pipe = NULL;
1802 if (odm_pipe->stream_res.dsc)
1803 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
1804 /* Clear plane_res and stream_res */
1805 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
1806 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
1807 odm_pipe = next_odm_pipe;
1808 }
1809 if (pipe->plane_state)
1810 resource_build_scaling_params(pipe);
1811 }
1812
1813 /* merge previously mpc split pipes since mode support needs to make the decision */
1814 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1815 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1816 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1817
1818 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
1819 continue;
1820
1821 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
1822 if (hsplit_pipe->bottom_pipe)
1823 hsplit_pipe->bottom_pipe->top_pipe = pipe;
1824 hsplit_pipe->plane_state = NULL;
1825 hsplit_pipe->stream = NULL;
1826 hsplit_pipe->top_pipe = NULL;
1827 hsplit_pipe->bottom_pipe = NULL;
1828
1829 /* Clear plane_res and stream_res */
1830 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
1831 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
1832 if (pipe->plane_state)
1833 resource_build_scaling_params(pipe);
1834 }
1835 }
1836
dcn20_validate_apply_pipe_split_flags(struct dc * dc,struct dc_state * context,int vlevel,int * split,bool * merge)1837 int dcn20_validate_apply_pipe_split_flags(
1838 struct dc *dc,
1839 struct dc_state *context,
1840 int vlevel,
1841 int *split,
1842 bool *merge)
1843 {
1844 int i, pipe_idx, vlevel_split;
1845 int plane_count = 0;
1846 bool force_split = false;
1847 bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
1848 struct vba_vars_st *v = &context->bw_ctx.dml.vba;
1849 int max_mpc_comb = v->maxMpcComb;
1850
1851 if (context->stream_count > 1) {
1852 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)
1853 avoid_split = true;
1854 } else if (dc->debug.force_single_disp_pipe_split)
1855 force_split = true;
1856
1857 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1858 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1859
1860 /**
1861 * Workaround for avoiding pipe-split in cases where we'd split
1862 * planes that are too small, resulting in splits that aren't
1863 * valid for the scaler.
1864 */
1865 if (pipe->plane_state &&
1866 (pipe->plane_state->dst_rect.width <= 16 ||
1867 pipe->plane_state->dst_rect.height <= 16 ||
1868 pipe->plane_state->src_rect.width <= 16 ||
1869 pipe->plane_state->src_rect.height <= 16))
1870 avoid_split = true;
1871
1872 /* TODO: fix dc bugs and remove this split threshold thing */
1873 if (pipe->stream && !pipe->prev_odm_pipe &&
1874 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
1875 ++plane_count;
1876 }
1877 if (plane_count > dc->res_pool->pipe_count / 2)
1878 avoid_split = true;
1879
1880 /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */
1881 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1882 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1883 struct dc_crtc_timing timing;
1884
1885 if (!pipe->stream)
1886 continue;
1887 else {
1888 timing = pipe->stream->timing;
1889 if (timing.h_border_left + timing.h_border_right
1890 + timing.v_border_top + timing.v_border_bottom > 0) {
1891 avoid_split = true;
1892 break;
1893 }
1894 }
1895 }
1896
1897 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
1898 if (avoid_split) {
1899 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1900 if (!context->res_ctx.pipe_ctx[i].stream)
1901 continue;
1902
1903 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
1904 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
1905 v->ModeSupport[vlevel][0])
1906 break;
1907 /* Impossible to not split this pipe */
1908 if (vlevel > context->bw_ctx.dml.soc.num_states)
1909 vlevel = vlevel_split;
1910 else
1911 max_mpc_comb = 0;
1912 pipe_idx++;
1913 }
1914 v->maxMpcComb = max_mpc_comb;
1915 }
1916
1917 /* Split loop sets which pipe should be split based on dml outputs and dc flags */
1918 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1919 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1920 int pipe_plane = v->pipe_plane[pipe_idx];
1921 bool split4mpc = context->stream_count == 1 && plane_count == 1
1922 && dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4;
1923
1924 if (!context->res_ctx.pipe_ctx[i].stream)
1925 continue;
1926
1927 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
1928 split[i] = 4;
1929 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)
1930 split[i] = 2;
1931
1932 if ((pipe->stream->view_format ==
1933 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
1934 pipe->stream->view_format ==
1935 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
1936 (pipe->stream->timing.timing_3d_format ==
1937 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
1938 pipe->stream->timing.timing_3d_format ==
1939 TIMING_3D_FORMAT_SIDE_BY_SIDE))
1940 split[i] = 2;
1941 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
1942 split[i] = 2;
1943 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
1944 }
1945 if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {
1946 split[i] = 4;
1947 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
1948 }
1949 /*420 format workaround*/
1950 if (pipe->stream->timing.h_addressable > 7680 &&
1951 pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1952 split[i] = 4;
1953 }
1954 v->ODMCombineEnabled[pipe_plane] =
1955 v->ODMCombineEnablePerState[vlevel][pipe_plane];
1956
1957 if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
1958 if (resource_get_mpc_slice_count(pipe) == 2) {
1959 /*If need split for mpc but 2 way split already*/
1960 if (split[i] == 4)
1961 split[i] = 2; /* 2 -> 4 MPC */
1962 else if (split[i] == 2)
1963 split[i] = 0; /* 2 -> 2 MPC */
1964 else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
1965 merge[i] = true; /* 2 -> 1 MPC */
1966 } else if (resource_get_mpc_slice_count(pipe) == 4) {
1967 /*If need split for mpc but 4 way split already*/
1968 if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe)
1969 || !pipe->bottom_pipe)) {
1970 merge[i] = true; /* 4 -> 2 MPC */
1971 } else if (split[i] == 0 && pipe->top_pipe &&
1972 pipe->top_pipe->plane_state == pipe->plane_state)
1973 merge[i] = true; /* 4 -> 1 MPC */
1974 split[i] = 0;
1975 } else if (resource_get_odm_slice_count(pipe) > 1) {
1976 /* ODM -> MPC transition */
1977 if (pipe->prev_odm_pipe) {
1978 split[i] = 0;
1979 merge[i] = true;
1980 }
1981 }
1982 } else {
1983 if (resource_get_odm_slice_count(pipe) == 2) {
1984 /*If need split for odm but 2 way split already*/
1985 if (split[i] == 4)
1986 split[i] = 2; /* 2 -> 4 ODM */
1987 else if (split[i] == 2)
1988 split[i] = 0; /* 2 -> 2 ODM */
1989 else if (pipe->prev_odm_pipe) {
1990 ASSERT(0); /* NOT expected yet */
1991 merge[i] = true; /* exit ODM */
1992 }
1993 } else if (resource_get_odm_slice_count(pipe) == 4) {
1994 /*If need split for odm but 4 way split already*/
1995 if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe)
1996 || !pipe->next_odm_pipe)) {
1997 merge[i] = true; /* 4 -> 2 ODM */
1998 } else if (split[i] == 0 && pipe->prev_odm_pipe) {
1999 ASSERT(0); /* NOT expected yet */
2000 merge[i] = true; /* exit ODM */
2001 }
2002 split[i] = 0;
2003 } else if (resource_get_mpc_slice_count(pipe) > 1) {
2004 /* MPC -> ODM transition */
2005 ASSERT(0); /* NOT expected yet */
2006 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
2007 split[i] = 0;
2008 merge[i] = true;
2009 }
2010 }
2011 }
2012
2013 /* Adjust dppclk when split is forced, do not bother with dispclk */
2014 if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) {
2015 DC_FP_START();
2016 dcn20_fpu_adjust_dppclk(v, vlevel, max_mpc_comb, pipe_idx, false);
2017 DC_FP_END();
2018 }
2019 pipe_idx++;
2020 }
2021
2022 return vlevel;
2023 }
2024
dcn20_fast_validate_bw(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * pipe_cnt_out,int * pipe_split_from,int * vlevel_out,bool fast_validate)2025 bool dcn20_fast_validate_bw(
2026 struct dc *dc,
2027 struct dc_state *context,
2028 display_e2e_pipe_params_st *pipes,
2029 int *pipe_cnt_out,
2030 int *pipe_split_from,
2031 int *vlevel_out,
2032 bool fast_validate)
2033 {
2034 bool out = false;
2035 int split[MAX_PIPES] = { 0 };
2036 int pipe_cnt, i, pipe_idx, vlevel;
2037
2038 ASSERT(pipes);
2039 if (!pipes)
2040 return false;
2041
2042 dcn20_merge_pipes_for_validate(dc, context);
2043
2044 DC_FP_START();
2045 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2046 DC_FP_END();
2047
2048 *pipe_cnt_out = pipe_cnt;
2049
2050 if (!pipe_cnt) {
2051 out = true;
2052 goto validate_out;
2053 }
2054
2055 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2056
2057 if (vlevel > context->bw_ctx.dml.soc.num_states)
2058 goto validate_fail;
2059
2060 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
2061
2062 /*initialize pipe_just_split_from to invalid idx*/
2063 for (i = 0; i < MAX_PIPES; i++)
2064 pipe_split_from[i] = -1;
2065
2066 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2067 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2068 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2069
2070 if (!pipe->stream || pipe_split_from[i] >= 0)
2071 continue;
2072
2073 pipe_idx++;
2074
2075 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2076 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2077 ASSERT(hsplit_pipe);
2078 if (!dcn20_split_stream_for_odm(
2079 dc, &context->res_ctx,
2080 pipe, hsplit_pipe))
2081 goto validate_fail;
2082 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2083 dcn20_build_mapped_resource(dc, context, pipe->stream);
2084 }
2085
2086 if (!pipe->plane_state)
2087 continue;
2088 /* Skip 2nd half of already split pipe */
2089 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2090 continue;
2091
2092 /* We do not support mpo + odm at the moment */
2093 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2094 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2095 goto validate_fail;
2096
2097 if (split[i] == 2) {
2098 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2099 /* pipe not split previously needs split */
2100 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2101 ASSERT(hsplit_pipe);
2102 if (!hsplit_pipe) {
2103 DC_FP_START();
2104 dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);
2105 DC_FP_END();
2106 continue;
2107 }
2108 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2109 if (!dcn20_split_stream_for_odm(
2110 dc, &context->res_ctx,
2111 pipe, hsplit_pipe))
2112 goto validate_fail;
2113 dcn20_build_mapped_resource(dc, context, pipe->stream);
2114 } else {
2115 dcn20_split_stream_for_mpc(
2116 &context->res_ctx, dc->res_pool,
2117 pipe, hsplit_pipe);
2118 resource_build_scaling_params(pipe);
2119 resource_build_scaling_params(hsplit_pipe);
2120 }
2121 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2122 }
2123 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2124 /* merge should already have been done */
2125 ASSERT(0);
2126 }
2127 }
2128 /* Actual dsc count per stream dsc validation*/
2129 if (!dcn20_validate_dsc(dc, context)) {
2130 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2131 DML_FAIL_DSC_VALIDATION_FAILURE;
2132 goto validate_fail;
2133 }
2134
2135 *vlevel_out = vlevel;
2136
2137 out = true;
2138 goto validate_out;
2139
2140 validate_fail:
2141 out = false;
2142
2143 validate_out:
2144 return out;
2145 }
2146
dcn20_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)2147 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
2148 bool fast_validate)
2149 {
2150 bool voltage_supported;
2151 display_e2e_pipe_params_st *pipes;
2152
2153 pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2154 if (!pipes)
2155 return false;
2156
2157 DC_FP_START();
2158 voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate, pipes);
2159 DC_FP_END();
2160
2161 kfree(pipes);
2162 return voltage_supported;
2163 }
2164
dcn20_acquire_free_pipe_for_layer(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * opp_head)2165 struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(
2166 const struct dc_state *cur_ctx,
2167 struct dc_state *new_ctx,
2168 const struct resource_pool *pool,
2169 const struct pipe_ctx *opp_head)
2170 {
2171 struct resource_context *res_ctx = &new_ctx->res_ctx;
2172 struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(res_ctx, opp_head->stream);
2173 struct pipe_ctx *sec_dpp_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, otg_master);
2174
2175 ASSERT(otg_master);
2176
2177 if (!sec_dpp_pipe)
2178 return NULL;
2179
2180 sec_dpp_pipe->stream = opp_head->stream;
2181 sec_dpp_pipe->stream_res.tg = opp_head->stream_res.tg;
2182 sec_dpp_pipe->stream_res.opp = opp_head->stream_res.opp;
2183
2184 sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx];
2185 sec_dpp_pipe->plane_res.ipp = pool->ipps[sec_dpp_pipe->pipe_idx];
2186 sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx];
2187 sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst;
2188
2189 return sec_dpp_pipe;
2190 }
2191
dcn20_get_dcc_compression_cap(const struct dc * dc,const struct dc_dcc_surface_param * input,struct dc_surface_dcc_cap * output)2192 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2193 const struct dc_dcc_surface_param *input,
2194 struct dc_surface_dcc_cap *output)
2195 {
2196 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2197 dc->res_pool->hubbub,
2198 input,
2199 output);
2200 }
2201
dcn20_destroy_resource_pool(struct resource_pool ** pool)2202 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2203 {
2204 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2205
2206 dcn20_resource_destruct(dcn20_pool);
2207 kfree(dcn20_pool);
2208 *pool = NULL;
2209 }
2210
2211
2212 static struct dc_cap_funcs cap_funcs = {
2213 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2214 };
2215
2216
dcn20_patch_unknown_plane_state(struct dc_plane_state * plane_state)2217 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)
2218 {
2219 enum surface_pixel_format surf_pix_format = plane_state->format;
2220 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
2221
2222 plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_S;
2223 if (bpp == 64)
2224 plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_D;
2225
2226 return DC_OK;
2227 }
2228
dcn20_release_pipe(struct dc_state * context,struct pipe_ctx * pipe,const struct resource_pool * pool)2229 void dcn20_release_pipe(struct dc_state *context,
2230 struct pipe_ctx *pipe,
2231 const struct resource_pool *pool)
2232 {
2233 if (resource_is_pipe_type(pipe, OPP_HEAD) && pipe->stream_res.dsc)
2234 dcn20_release_dsc(&context->res_ctx, pool, &pipe->stream_res.dsc);
2235 memset(pipe, 0, sizeof(*pipe));
2236 }
2237
2238 static const struct resource_funcs dcn20_res_pool_funcs = {
2239 .destroy = dcn20_destroy_resource_pool,
2240 .link_enc_create = dcn20_link_encoder_create,
2241 .panel_cntl_create = dcn20_panel_cntl_create,
2242 .validate_bandwidth = dcn20_validate_bandwidth,
2243 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
2244 .release_pipe = dcn20_release_pipe,
2245 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
2246 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2247 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2248 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
2249 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2250 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
2251 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
2252 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
2253 };
2254
dcn20_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)2255 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
2256 {
2257 int i;
2258 uint32_t pipe_count = pool->res_cap->num_dwb;
2259
2260 for (i = 0; i < pipe_count; i++) {
2261 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
2262 GFP_KERNEL);
2263
2264 if (!dwbc20) {
2265 dm_error("DC: failed to create dwbc20!\n");
2266 return false;
2267 }
2268 dcn20_dwbc_construct(dwbc20, ctx,
2269 &dwbc20_regs[i],
2270 &dwbc20_shift,
2271 &dwbc20_mask,
2272 i);
2273 pool->dwbc[i] = &dwbc20->base;
2274 }
2275 return true;
2276 }
2277
dcn20_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)2278 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
2279 {
2280 int i;
2281 uint32_t pipe_count = pool->res_cap->num_dwb;
2282
2283 ASSERT(pipe_count > 0);
2284
2285 for (i = 0; i < pipe_count; i++) {
2286 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
2287 GFP_KERNEL);
2288
2289 if (!mcif_wb20) {
2290 dm_error("DC: failed to create mcif_wb20!\n");
2291 return false;
2292 }
2293
2294 dcn20_mmhubbub_construct(mcif_wb20, ctx,
2295 &mcif_wb20_regs[i],
2296 &mcif_wb20_shift,
2297 &mcif_wb20_mask,
2298 i);
2299
2300 pool->mcif_wb[i] = &mcif_wb20->base;
2301 }
2302 return true;
2303 }
2304
dcn20_pp_smu_create(struct dc_context * ctx)2305 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
2306 {
2307 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC);
2308
2309 if (!pp_smu)
2310 return pp_smu;
2311
2312 dm_pp_get_funcs(ctx, pp_smu);
2313
2314 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
2315 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
2316
2317 return pp_smu;
2318 }
2319
dcn20_pp_smu_destroy(struct pp_smu_funcs ** pp_smu)2320 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
2321 {
2322 if (pp_smu && *pp_smu) {
2323 kfree(*pp_smu);
2324 *pp_smu = NULL;
2325 }
2326 }
2327
get_asic_rev_soc_bb(uint32_t hw_internal_rev)2328 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
2329 uint32_t hw_internal_rev)
2330 {
2331 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
2332 return &dcn2_0_nv14_soc;
2333
2334 if (ASICREV_IS_NAVI12_P(hw_internal_rev))
2335 return &dcn2_0_nv12_soc;
2336
2337 return &dcn2_0_soc;
2338 }
2339
get_asic_rev_ip_params(uint32_t hw_internal_rev)2340 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
2341 uint32_t hw_internal_rev)
2342 {
2343 /* NV14 */
2344 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
2345 return &dcn2_0_nv14_ip;
2346
2347 /* NV12 and NV10 */
2348 return &dcn2_0_ip;
2349 }
2350
get_dml_project_version(uint32_t hw_internal_rev)2351 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
2352 {
2353 return DML_PROJECT_NAVI10v2;
2354 }
2355
init_soc_bounding_box(struct dc * dc,struct dcn20_resource_pool * pool)2356 static bool init_soc_bounding_box(struct dc *dc,
2357 struct dcn20_resource_pool *pool)
2358 {
2359 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
2360 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
2361 struct _vcs_dpi_ip_params_st *loaded_ip =
2362 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
2363
2364 DC_LOGGER_INIT(dc->ctx->logger);
2365
2366 if (pool->base.pp_smu) {
2367 struct pp_smu_nv_clock_table max_clocks = {0};
2368 unsigned int uclk_states[8] = {0};
2369 unsigned int num_states = 0;
2370 enum pp_smu_status status;
2371 bool clock_limits_available = false;
2372 bool uclk_states_available = false;
2373
2374 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
2375 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
2376 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
2377
2378 uclk_states_available = (status == PP_SMU_RESULT_OK);
2379 }
2380
2381 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
2382 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
2383 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
2384 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
2385 */
2386 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
2387 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
2388 clock_limits_available = (status == PP_SMU_RESULT_OK);
2389 }
2390
2391 if (clock_limits_available && uclk_states_available && num_states) {
2392 DC_FP_START();
2393 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
2394 DC_FP_END();
2395 } else if (clock_limits_available) {
2396 DC_FP_START();
2397 dcn20_cap_soc_clocks(loaded_bb, max_clocks);
2398 DC_FP_END();
2399 }
2400 }
2401
2402 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
2403 loaded_ip->max_num_dpp = pool->base.pipe_count;
2404 DC_FP_START();
2405 dcn20_patch_bounding_box(dc, loaded_bb);
2406 DC_FP_END();
2407 return true;
2408 }
2409
dcn20_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn20_resource_pool * pool)2410 static bool dcn20_resource_construct(
2411 uint8_t num_virtual_links,
2412 struct dc *dc,
2413 struct dcn20_resource_pool *pool)
2414 {
2415 int i;
2416 struct dc_context *ctx = dc->ctx;
2417 struct irq_service_init_data init_data;
2418 struct ddc_service_init_data ddc_init_data = {0};
2419 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
2420 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
2421 struct _vcs_dpi_ip_params_st *loaded_ip =
2422 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
2423 enum dml_project dml_project_version =
2424 get_dml_project_version(ctx->asic_id.hw_internal_rev);
2425
2426 ctx->dc_bios->regs = &bios_regs;
2427 pool->base.funcs = &dcn20_res_pool_funcs;
2428
2429 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
2430 pool->base.res_cap = &res_cap_nv14;
2431 pool->base.pipe_count = 5;
2432 pool->base.mpcc_count = 5;
2433 } else {
2434 pool->base.res_cap = &res_cap_nv10;
2435 pool->base.pipe_count = 6;
2436 pool->base.mpcc_count = 6;
2437 }
2438 /*************************************************
2439 * Resource + asic cap harcoding *
2440 *************************************************/
2441 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2442
2443 dc->caps.max_downscale_ratio = 200;
2444 dc->caps.i2c_speed_in_khz = 100;
2445 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2446 dc->caps.max_cursor_size = 256;
2447 dc->caps.min_horizontal_blanking_period = 80;
2448 dc->caps.dmdata_alloc_size = 2048;
2449
2450 dc->caps.max_slave_planes = 1;
2451 dc->caps.max_slave_yuv_planes = 1;
2452 dc->caps.max_slave_rgb_planes = 1;
2453 dc->caps.post_blend_color_processing = true;
2454 dc->caps.force_dp_tps4_for_cp2520 = true;
2455 dc->caps.extended_aux_timeout_support = true;
2456 dc->caps.dmcub_support = true;
2457
2458 /* Color pipeline capabilities */
2459 dc->caps.color.dpp.dcn_arch = 1;
2460 dc->caps.color.dpp.input_lut_shared = 0;
2461 dc->caps.color.dpp.icsc = 1;
2462 dc->caps.color.dpp.dgam_ram = 1;
2463 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2464 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2465 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
2466 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
2467 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
2468 dc->caps.color.dpp.post_csc = 0;
2469 dc->caps.color.dpp.gamma_corr = 0;
2470 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
2471
2472 dc->caps.color.dpp.hw_3d_lut = 1;
2473 dc->caps.color.dpp.ogam_ram = 1;
2474 // no OGAM ROM on DCN2, only MPC ROM
2475 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2476 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2477 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2478 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2479 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2480 dc->caps.color.dpp.ocsc = 0;
2481
2482 dc->caps.color.mpc.gamut_remap = 0;
2483 dc->caps.color.mpc.num_3dluts = 0;
2484 dc->caps.color.mpc.shared_3d_lut = 0;
2485 dc->caps.color.mpc.ogam_ram = 1;
2486 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2487 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2488 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2489 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2490 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2491 dc->caps.color.mpc.ocsc = 1;
2492
2493 dc->caps.dp_hdmi21_pcon_support = true;
2494
2495 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2496 dc->debug = debug_defaults_drv;
2497
2498 //dcn2.0x
2499 dc->work_arounds.dedcn20_305_wa = true;
2500
2501 // Init the vm_helper
2502 if (dc->vm_helper)
2503 vm_helper_init(dc->vm_helper, 16);
2504
2505 /*************************************************
2506 * Create resources *
2507 *************************************************/
2508
2509 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
2510 dcn20_clock_source_create(ctx, ctx->dc_bios,
2511 CLOCK_SOURCE_COMBO_PHY_PLL0,
2512 &clk_src_regs[0], false);
2513 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
2514 dcn20_clock_source_create(ctx, ctx->dc_bios,
2515 CLOCK_SOURCE_COMBO_PHY_PLL1,
2516 &clk_src_regs[1], false);
2517 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
2518 dcn20_clock_source_create(ctx, ctx->dc_bios,
2519 CLOCK_SOURCE_COMBO_PHY_PLL2,
2520 &clk_src_regs[2], false);
2521 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
2522 dcn20_clock_source_create(ctx, ctx->dc_bios,
2523 CLOCK_SOURCE_COMBO_PHY_PLL3,
2524 &clk_src_regs[3], false);
2525 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
2526 dcn20_clock_source_create(ctx, ctx->dc_bios,
2527 CLOCK_SOURCE_COMBO_PHY_PLL4,
2528 &clk_src_regs[4], false);
2529 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
2530 dcn20_clock_source_create(ctx, ctx->dc_bios,
2531 CLOCK_SOURCE_COMBO_PHY_PLL5,
2532 &clk_src_regs[5], false);
2533 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
2534 /* todo: not reuse phy_pll registers */
2535 pool->base.dp_clock_source =
2536 dcn20_clock_source_create(ctx, ctx->dc_bios,
2537 CLOCK_SOURCE_ID_DP_DTO,
2538 &clk_src_regs[0], true);
2539
2540 for (i = 0; i < pool->base.clk_src_count; i++) {
2541 if (pool->base.clock_sources[i] == NULL) {
2542 dm_error("DC: failed to create clock sources!\n");
2543 BREAK_TO_DEBUGGER();
2544 goto create_fail;
2545 }
2546 }
2547
2548 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2549 if (pool->base.dccg == NULL) {
2550 dm_error("DC: failed to create dccg!\n");
2551 BREAK_TO_DEBUGGER();
2552 goto create_fail;
2553 }
2554
2555 pool->base.dmcu = dcn20_dmcu_create(ctx,
2556 &dmcu_regs,
2557 &dmcu_shift,
2558 &dmcu_mask);
2559 if (pool->base.dmcu == NULL) {
2560 dm_error("DC: failed to create dmcu!\n");
2561 BREAK_TO_DEBUGGER();
2562 goto create_fail;
2563 }
2564
2565 pool->base.abm = dce_abm_create(ctx,
2566 &abm_regs,
2567 &abm_shift,
2568 &abm_mask);
2569 if (pool->base.abm == NULL) {
2570 dm_error("DC: failed to create abm!\n");
2571 BREAK_TO_DEBUGGER();
2572 goto create_fail;
2573 }
2574
2575 pool->base.pp_smu = dcn20_pp_smu_create(ctx);
2576
2577
2578 if (!init_soc_bounding_box(dc, pool)) {
2579 dm_error("DC: failed to initialize soc bounding box!\n");
2580 BREAK_TO_DEBUGGER();
2581 goto create_fail;
2582 }
2583
2584 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
2585
2586 if (!dc->debug.disable_pplib_wm_range) {
2587 struct pp_smu_wm_range_sets ranges = {0};
2588 int i = 0;
2589
2590 ranges.num_reader_wm_sets = 0;
2591
2592 if (loaded_bb->num_states == 1) {
2593 ranges.reader_wm_sets[0].wm_inst = i;
2594 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2595 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2596 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2597 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2598
2599 ranges.num_reader_wm_sets = 1;
2600 } else if (loaded_bb->num_states > 1) {
2601 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
2602 ranges.reader_wm_sets[i].wm_inst = i;
2603 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2604 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2605 DC_FP_START();
2606 dcn20_fpu_set_wm_ranges(i, &ranges, loaded_bb);
2607 DC_FP_END();
2608
2609 ranges.num_reader_wm_sets = i + 1;
2610 }
2611
2612 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2613 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2614 }
2615
2616 ranges.num_writer_wm_sets = 1;
2617
2618 ranges.writer_wm_sets[0].wm_inst = 0;
2619 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2620 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2621 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2622 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2623
2624 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
2625 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
2626 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
2627 }
2628
2629 init_data.ctx = dc->ctx;
2630 pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
2631 if (!pool->base.irqs)
2632 goto create_fail;
2633
2634 /* mem input -> ipp -> dpp -> opp -> TG */
2635 for (i = 0; i < pool->base.pipe_count; i++) {
2636 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
2637 if (pool->base.hubps[i] == NULL) {
2638 BREAK_TO_DEBUGGER();
2639 dm_error(
2640 "DC: failed to create memory input!\n");
2641 goto create_fail;
2642 }
2643
2644 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
2645 if (pool->base.ipps[i] == NULL) {
2646 BREAK_TO_DEBUGGER();
2647 dm_error(
2648 "DC: failed to create input pixel processor!\n");
2649 goto create_fail;
2650 }
2651
2652 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
2653 if (pool->base.dpps[i] == NULL) {
2654 BREAK_TO_DEBUGGER();
2655 dm_error(
2656 "DC: failed to create dpps!\n");
2657 goto create_fail;
2658 }
2659 }
2660 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2661 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
2662 if (pool->base.engines[i] == NULL) {
2663 BREAK_TO_DEBUGGER();
2664 dm_error(
2665 "DC:failed to create aux engine!!\n");
2666 goto create_fail;
2667 }
2668 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
2669 if (pool->base.hw_i2cs[i] == NULL) {
2670 BREAK_TO_DEBUGGER();
2671 dm_error(
2672 "DC:failed to create hw i2c!!\n");
2673 goto create_fail;
2674 }
2675 pool->base.sw_i2cs[i] = NULL;
2676 }
2677
2678 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2679 pool->base.opps[i] = dcn20_opp_create(ctx, i);
2680 if (pool->base.opps[i] == NULL) {
2681 BREAK_TO_DEBUGGER();
2682 dm_error(
2683 "DC: failed to create output pixel processor!\n");
2684 goto create_fail;
2685 }
2686 }
2687
2688 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2689 pool->base.timing_generators[i] = dcn20_timing_generator_create(
2690 ctx, i);
2691 if (pool->base.timing_generators[i] == NULL) {
2692 BREAK_TO_DEBUGGER();
2693 dm_error("DC: failed to create tg!\n");
2694 goto create_fail;
2695 }
2696 }
2697
2698 pool->base.timing_generator_count = i;
2699
2700 pool->base.mpc = dcn20_mpc_create(ctx);
2701 if (pool->base.mpc == NULL) {
2702 BREAK_TO_DEBUGGER();
2703 dm_error("DC: failed to create mpc!\n");
2704 goto create_fail;
2705 }
2706
2707 pool->base.hubbub = dcn20_hubbub_create(ctx);
2708 if (pool->base.hubbub == NULL) {
2709 BREAK_TO_DEBUGGER();
2710 dm_error("DC: failed to create hubbub!\n");
2711 goto create_fail;
2712 }
2713
2714 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2715 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
2716 if (pool->base.dscs[i] == NULL) {
2717 BREAK_TO_DEBUGGER();
2718 dm_error("DC: failed to create display stream compressor %d!\n", i);
2719 goto create_fail;
2720 }
2721 }
2722
2723 if (!dcn20_dwbc_create(ctx, &pool->base)) {
2724 BREAK_TO_DEBUGGER();
2725 dm_error("DC: failed to create dwbc!\n");
2726 goto create_fail;
2727 }
2728 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
2729 BREAK_TO_DEBUGGER();
2730 dm_error("DC: failed to create mcif_wb!\n");
2731 goto create_fail;
2732 }
2733
2734 if (!resource_construct(num_virtual_links, dc, &pool->base,
2735 &res_create_funcs))
2736 goto create_fail;
2737
2738 dcn20_hw_sequencer_construct(dc);
2739
2740 // IF NV12, set PG function pointer to NULL. It's not that
2741 // PG isn't supported for NV12, it's that we don't want to
2742 // program the registers because that will cause more power
2743 // to be consumed. We could have created dcn20_init_hw to get
2744 // the same effect by checking ASIC rev, but there was a
2745 // request at some point to not check ASIC rev on hw sequencer.
2746 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
2747 dc->hwseq->funcs.enable_power_gating_plane = NULL;
2748 dc->debug.disable_dpp_power_gate = true;
2749 dc->debug.disable_hubp_power_gate = true;
2750 }
2751
2752
2753 dc->caps.max_planes = pool->base.pipe_count;
2754
2755 for (i = 0; i < dc->caps.max_planes; ++i)
2756 dc->caps.planes[i] = plane_cap;
2757
2758 dc->cap_funcs = cap_funcs;
2759
2760 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2761 ddc_init_data.ctx = dc->ctx;
2762 ddc_init_data.link = NULL;
2763 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2764 ddc_init_data.id.enum_id = 0;
2765 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2766 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2767 } else {
2768 pool->base.oem_device = NULL;
2769 }
2770
2771 return true;
2772
2773 create_fail:
2774
2775 dcn20_resource_destruct(pool);
2776
2777 return false;
2778 }
2779
dcn20_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2780 struct resource_pool *dcn20_create_resource_pool(
2781 const struct dc_init_data *init_data,
2782 struct dc *dc)
2783 {
2784 struct dcn20_resource_pool *pool =
2785 kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC);
2786
2787 if (!pool)
2788 return NULL;
2789
2790 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
2791 return &pool->base;
2792
2793 BREAK_TO_DEBUGGER();
2794 kfree(pool);
2795 return NULL;
2796 }
2797