1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 *
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/debugfs.h>
9 #include <linux/device.h>
10 #include <linux/dma-direction.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/idr.h>
13 #include <linux/interrupt.h>
14 #include <linux/list.h>
15 #include <linux/mhi.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/wait.h>
21 #include "internal.h"
22
23 #define CREATE_TRACE_POINTS
24 #include "trace.h"
25
26 static DEFINE_IDA(mhi_controller_ida);
27
28 #undef mhi_ee
29 #undef mhi_ee_end
30
31 #define mhi_ee(a, b) [MHI_EE_##a] = b,
32 #define mhi_ee_end(a, b) [MHI_EE_##a] = b,
33
34 const char * const mhi_ee_str[MHI_EE_MAX] = {
35 MHI_EE_LIST
36 };
37
38 #undef dev_st_trans
39 #undef dev_st_trans_end
40
41 #define dev_st_trans(a, b) [DEV_ST_TRANSITION_##a] = b,
42 #define dev_st_trans_end(a, b) [DEV_ST_TRANSITION_##a] = b,
43
44 const char * const dev_state_tran_str[DEV_ST_TRANSITION_MAX] = {
45 DEV_ST_TRANSITION_LIST
46 };
47
48 #undef ch_state_type
49 #undef ch_state_type_end
50
51 #define ch_state_type(a, b) [MHI_CH_STATE_TYPE_##a] = b,
52 #define ch_state_type_end(a, b) [MHI_CH_STATE_TYPE_##a] = b,
53
54 const char * const mhi_ch_state_type_str[MHI_CH_STATE_TYPE_MAX] = {
55 MHI_CH_STATE_TYPE_LIST
56 };
57
58 #undef mhi_pm_state
59 #undef mhi_pm_state_end
60
61 #define mhi_pm_state(a, b) [MHI_PM_STATE_##a] = b,
62 #define mhi_pm_state_end(a, b) [MHI_PM_STATE_##a] = b,
63
64 static const char * const mhi_pm_state_str[] = {
65 MHI_PM_STATE_LIST
66 };
67
to_mhi_pm_state_str(u32 state)68 const char *to_mhi_pm_state_str(u32 state)
69 {
70 int index;
71
72 if (state)
73 index = __fls(state);
74
75 if (!state || index >= ARRAY_SIZE(mhi_pm_state_str))
76 return "Invalid State";
77
78 return mhi_pm_state_str[index];
79 }
80
serial_number_show(struct device * dev,struct device_attribute * attr,char * buf)81 static ssize_t serial_number_show(struct device *dev,
82 struct device_attribute *attr,
83 char *buf)
84 {
85 struct mhi_device *mhi_dev = to_mhi_device(dev);
86 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
87
88 return sysfs_emit(buf, "Serial Number: %u\n",
89 mhi_cntrl->serial_number);
90 }
91 static DEVICE_ATTR_RO(serial_number);
92
oem_pk_hash_show(struct device * dev,struct device_attribute * attr,char * buf)93 static ssize_t oem_pk_hash_show(struct device *dev,
94 struct device_attribute *attr,
95 char *buf)
96 {
97 struct mhi_device *mhi_dev = to_mhi_device(dev);
98 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
99 u32 hash_segment[MHI_MAX_OEM_PK_HASH_SEGMENTS];
100 int i, cnt = 0, ret;
101
102 for (i = 0; i < MHI_MAX_OEM_PK_HASH_SEGMENTS; i++) {
103 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_OEMPKHASH(i), &hash_segment[i]);
104 if (ret) {
105 dev_err(dev, "Could not capture OEM PK HASH\n");
106 return ret;
107 }
108 }
109
110 for (i = 0; i < MHI_MAX_OEM_PK_HASH_SEGMENTS; i++)
111 cnt += sysfs_emit_at(buf, cnt, "OEMPKHASH[%d]: 0x%x\n", i, hash_segment[i]);
112
113 return cnt;
114 }
115 static DEVICE_ATTR_RO(oem_pk_hash);
116
soc_reset_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)117 static ssize_t soc_reset_store(struct device *dev,
118 struct device_attribute *attr,
119 const char *buf,
120 size_t count)
121 {
122 struct mhi_device *mhi_dev = to_mhi_device(dev);
123 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
124
125 mhi_soc_reset(mhi_cntrl);
126 return count;
127 }
128 static DEVICE_ATTR_WO(soc_reset);
129
trigger_edl_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)130 static ssize_t trigger_edl_store(struct device *dev,
131 struct device_attribute *attr,
132 const char *buf, size_t count)
133 {
134 struct mhi_device *mhi_dev = to_mhi_device(dev);
135 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
136 unsigned long val;
137 int ret;
138
139 ret = kstrtoul(buf, 10, &val);
140 if (ret < 0)
141 return ret;
142
143 if (!val)
144 return -EINVAL;
145
146 ret = mhi_cntrl->edl_trigger(mhi_cntrl);
147 if (ret)
148 return ret;
149
150 return count;
151 }
152 static DEVICE_ATTR_WO(trigger_edl);
153
154 static struct attribute *mhi_dev_attrs[] = {
155 &dev_attr_serial_number.attr,
156 &dev_attr_oem_pk_hash.attr,
157 &dev_attr_soc_reset.attr,
158 NULL,
159 };
160 ATTRIBUTE_GROUPS(mhi_dev);
161
162 /* MHI protocol requires the transfer ring to be aligned with ring length */
mhi_alloc_aligned_ring(struct mhi_controller * mhi_cntrl,struct mhi_ring * ring,u64 len)163 static int mhi_alloc_aligned_ring(struct mhi_controller *mhi_cntrl,
164 struct mhi_ring *ring,
165 u64 len)
166 {
167 ring->alloc_size = len + (len - 1);
168 ring->pre_aligned = dma_alloc_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
169 &ring->dma_handle, GFP_KERNEL);
170 if (!ring->pre_aligned)
171 return -ENOMEM;
172
173 ring->iommu_base = (ring->dma_handle + (len - 1)) & ~(len - 1);
174 ring->base = ring->pre_aligned + (ring->iommu_base - ring->dma_handle);
175
176 return 0;
177 }
178
mhi_deinit_free_irq(struct mhi_controller * mhi_cntrl)179 void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl)
180 {
181 int i;
182 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
183
184 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
185 if (mhi_event->offload_ev)
186 continue;
187
188 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);
189 }
190
191 free_irq(mhi_cntrl->irq[0], mhi_cntrl);
192 }
193
mhi_init_irq_setup(struct mhi_controller * mhi_cntrl)194 int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl)
195 {
196 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
197 struct device *dev = &mhi_cntrl->mhi_dev->dev;
198 unsigned long irq_flags = IRQF_SHARED | IRQF_NO_SUSPEND;
199 int i, ret;
200
201 /* if controller driver has set irq_flags, use it */
202 if (mhi_cntrl->irq_flags)
203 irq_flags = mhi_cntrl->irq_flags;
204
205 /* Setup BHI_INTVEC IRQ */
206 ret = request_threaded_irq(mhi_cntrl->irq[0], mhi_intvec_handler,
207 mhi_intvec_threaded_handler,
208 irq_flags,
209 "bhi", mhi_cntrl);
210 if (ret)
211 return ret;
212 /*
213 * IRQs should be enabled during mhi_async_power_up(), so disable them explicitly here.
214 * Due to the use of IRQF_SHARED flag as default while requesting IRQs, we assume that
215 * IRQ_NOAUTOEN is not applicable.
216 */
217 disable_irq(mhi_cntrl->irq[0]);
218
219 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
220 if (mhi_event->offload_ev)
221 continue;
222
223 if (mhi_event->irq >= mhi_cntrl->nr_irqs) {
224 dev_err(dev, "irq %d not available for event ring\n",
225 mhi_event->irq);
226 ret = -EINVAL;
227 goto error_request;
228 }
229
230 ret = request_irq(mhi_cntrl->irq[mhi_event->irq],
231 mhi_irq_handler,
232 irq_flags,
233 "mhi", mhi_event);
234 if (ret) {
235 dev_err(dev, "Error requesting irq:%d for ev:%d\n",
236 mhi_cntrl->irq[mhi_event->irq], i);
237 goto error_request;
238 }
239
240 disable_irq(mhi_cntrl->irq[mhi_event->irq]);
241 }
242
243 return 0;
244
245 error_request:
246 for (--i, --mhi_event; i >= 0; i--, mhi_event--) {
247 if (mhi_event->offload_ev)
248 continue;
249
250 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);
251 }
252 free_irq(mhi_cntrl->irq[0], mhi_cntrl);
253
254 return ret;
255 }
256
mhi_deinit_dev_ctxt(struct mhi_controller * mhi_cntrl)257 void mhi_deinit_dev_ctxt(struct mhi_controller *mhi_cntrl)
258 {
259 int i;
260 struct mhi_ctxt *mhi_ctxt = mhi_cntrl->mhi_ctxt;
261 struct mhi_cmd *mhi_cmd;
262 struct mhi_event *mhi_event;
263 struct mhi_ring *ring;
264
265 mhi_cmd = mhi_cntrl->mhi_cmd;
266 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++) {
267 ring = &mhi_cmd->ring;
268 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
269 ring->pre_aligned, ring->dma_handle);
270 ring->base = NULL;
271 ring->iommu_base = 0;
272 }
273
274 dma_free_coherent(mhi_cntrl->cntrl_dev,
275 sizeof(*mhi_ctxt->cmd_ctxt) * NR_OF_CMD_RINGS,
276 mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr);
277
278 mhi_event = mhi_cntrl->mhi_event;
279 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
280 if (mhi_event->offload_ev)
281 continue;
282
283 ring = &mhi_event->ring;
284 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
285 ring->pre_aligned, ring->dma_handle);
286 ring->base = NULL;
287 ring->iommu_base = 0;
288 }
289
290 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->er_ctxt) *
291 mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt,
292 mhi_ctxt->er_ctxt_addr);
293
294 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->chan_ctxt) *
295 mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt,
296 mhi_ctxt->chan_ctxt_addr);
297
298 kfree(mhi_ctxt);
299 mhi_cntrl->mhi_ctxt = NULL;
300 }
301
mhi_init_dev_ctxt(struct mhi_controller * mhi_cntrl)302 int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl)
303 {
304 struct mhi_ctxt *mhi_ctxt;
305 struct mhi_chan_ctxt *chan_ctxt;
306 struct mhi_event_ctxt *er_ctxt;
307 struct mhi_cmd_ctxt *cmd_ctxt;
308 struct mhi_chan *mhi_chan;
309 struct mhi_event *mhi_event;
310 struct mhi_cmd *mhi_cmd;
311 u32 tmp;
312 int ret = -ENOMEM, i;
313
314 atomic_set(&mhi_cntrl->dev_wake, 0);
315 atomic_set(&mhi_cntrl->pending_pkts, 0);
316
317 mhi_ctxt = kzalloc(sizeof(*mhi_ctxt), GFP_KERNEL);
318 if (!mhi_ctxt)
319 return -ENOMEM;
320
321 /* Setup channel ctxt */
322 mhi_ctxt->chan_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,
323 sizeof(*mhi_ctxt->chan_ctxt) *
324 mhi_cntrl->max_chan,
325 &mhi_ctxt->chan_ctxt_addr,
326 GFP_KERNEL);
327 if (!mhi_ctxt->chan_ctxt)
328 goto error_alloc_chan_ctxt;
329
330 mhi_chan = mhi_cntrl->mhi_chan;
331 chan_ctxt = mhi_ctxt->chan_ctxt;
332 for (i = 0; i < mhi_cntrl->max_chan; i++, chan_ctxt++, mhi_chan++) {
333 /* Skip if it is an offload channel */
334 if (mhi_chan->offload_ch)
335 continue;
336
337 tmp = le32_to_cpu(chan_ctxt->chcfg);
338 tmp &= ~CHAN_CTX_CHSTATE_MASK;
339 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_DISABLED);
340 tmp &= ~CHAN_CTX_BRSTMODE_MASK;
341 tmp |= FIELD_PREP(CHAN_CTX_BRSTMODE_MASK, mhi_chan->db_cfg.brstmode);
342 tmp &= ~CHAN_CTX_POLLCFG_MASK;
343 tmp |= FIELD_PREP(CHAN_CTX_POLLCFG_MASK, mhi_chan->db_cfg.pollcfg);
344 chan_ctxt->chcfg = cpu_to_le32(tmp);
345
346 chan_ctxt->chtype = cpu_to_le32(mhi_chan->type);
347 chan_ctxt->erindex = cpu_to_le32(mhi_chan->er_index);
348
349 mhi_chan->ch_state = MHI_CH_STATE_DISABLED;
350 mhi_chan->tre_ring.db_addr = (void __iomem *)&chan_ctxt->wp;
351 }
352
353 /* Setup event context */
354 mhi_ctxt->er_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,
355 sizeof(*mhi_ctxt->er_ctxt) *
356 mhi_cntrl->total_ev_rings,
357 &mhi_ctxt->er_ctxt_addr,
358 GFP_KERNEL);
359 if (!mhi_ctxt->er_ctxt)
360 goto error_alloc_er_ctxt;
361
362 er_ctxt = mhi_ctxt->er_ctxt;
363 mhi_event = mhi_cntrl->mhi_event;
364 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
365 mhi_event++) {
366 struct mhi_ring *ring = &mhi_event->ring;
367
368 /* Skip if it is an offload event */
369 if (mhi_event->offload_ev)
370 continue;
371
372 tmp = le32_to_cpu(er_ctxt->intmod);
373 tmp &= ~EV_CTX_INTMODC_MASK;
374 tmp &= ~EV_CTX_INTMODT_MASK;
375 tmp |= FIELD_PREP(EV_CTX_INTMODT_MASK, mhi_event->intmod);
376 er_ctxt->intmod = cpu_to_le32(tmp);
377
378 er_ctxt->ertype = cpu_to_le32(MHI_ER_TYPE_VALID);
379 er_ctxt->msivec = cpu_to_le32(mhi_event->irq);
380 mhi_event->db_cfg.db_mode = true;
381
382 ring->el_size = sizeof(struct mhi_ring_element);
383 ring->len = ring->el_size * ring->elements;
384 ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len);
385 if (ret)
386 goto error_alloc_er;
387
388 /*
389 * If the read pointer equals to the write pointer, then the
390 * ring is empty
391 */
392 ring->rp = ring->wp = ring->base;
393 er_ctxt->rbase = cpu_to_le64(ring->iommu_base);
394 er_ctxt->rp = er_ctxt->wp = er_ctxt->rbase;
395 er_ctxt->rlen = cpu_to_le64(ring->len);
396 ring->ctxt_wp = &er_ctxt->wp;
397 }
398
399 /* Setup cmd context */
400 ret = -ENOMEM;
401 mhi_ctxt->cmd_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev,
402 sizeof(*mhi_ctxt->cmd_ctxt) *
403 NR_OF_CMD_RINGS,
404 &mhi_ctxt->cmd_ctxt_addr,
405 GFP_KERNEL);
406 if (!mhi_ctxt->cmd_ctxt)
407 goto error_alloc_er;
408
409 mhi_cmd = mhi_cntrl->mhi_cmd;
410 cmd_ctxt = mhi_ctxt->cmd_ctxt;
411 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
412 struct mhi_ring *ring = &mhi_cmd->ring;
413
414 ring->el_size = sizeof(struct mhi_ring_element);
415 ring->elements = CMD_EL_PER_RING;
416 ring->len = ring->el_size * ring->elements;
417 ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len);
418 if (ret)
419 goto error_alloc_cmd;
420
421 ring->rp = ring->wp = ring->base;
422 cmd_ctxt->rbase = cpu_to_le64(ring->iommu_base);
423 cmd_ctxt->rp = cmd_ctxt->wp = cmd_ctxt->rbase;
424 cmd_ctxt->rlen = cpu_to_le64(ring->len);
425 ring->ctxt_wp = &cmd_ctxt->wp;
426 }
427
428 mhi_cntrl->mhi_ctxt = mhi_ctxt;
429
430 return 0;
431
432 error_alloc_cmd:
433 for (--i, --mhi_cmd; i >= 0; i--, mhi_cmd--) {
434 struct mhi_ring *ring = &mhi_cmd->ring;
435
436 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
437 ring->pre_aligned, ring->dma_handle);
438 }
439 dma_free_coherent(mhi_cntrl->cntrl_dev,
440 sizeof(*mhi_ctxt->cmd_ctxt) * NR_OF_CMD_RINGS,
441 mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr);
442 i = mhi_cntrl->total_ev_rings;
443 mhi_event = mhi_cntrl->mhi_event + i;
444
445 error_alloc_er:
446 for (--i, --mhi_event; i >= 0; i--, mhi_event--) {
447 struct mhi_ring *ring = &mhi_event->ring;
448
449 if (mhi_event->offload_ev)
450 continue;
451
452 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size,
453 ring->pre_aligned, ring->dma_handle);
454 }
455 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->er_ctxt) *
456 mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt,
457 mhi_ctxt->er_ctxt_addr);
458
459 error_alloc_er_ctxt:
460 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->chan_ctxt) *
461 mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt,
462 mhi_ctxt->chan_ctxt_addr);
463
464 error_alloc_chan_ctxt:
465 kfree(mhi_ctxt);
466
467 return ret;
468 }
469
mhi_init_mmio(struct mhi_controller * mhi_cntrl)470 int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
471 {
472 u32 val;
473 int i, ret;
474 struct mhi_chan *mhi_chan;
475 struct mhi_event *mhi_event;
476 void __iomem *base = mhi_cntrl->regs;
477 struct device *dev = &mhi_cntrl->mhi_dev->dev;
478 struct {
479 u32 offset;
480 u32 val;
481 } reg_info[] = {
482 {
483 CCABAP_HIGHER,
484 upper_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
485 },
486 {
487 CCABAP_LOWER,
488 lower_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
489 },
490 {
491 ECABAP_HIGHER,
492 upper_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
493 },
494 {
495 ECABAP_LOWER,
496 lower_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
497 },
498 {
499 CRCBAP_HIGHER,
500 upper_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
501 },
502 {
503 CRCBAP_LOWER,
504 lower_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
505 },
506 {
507 MHICTRLBASE_HIGHER,
508 upper_32_bits(mhi_cntrl->iova_start),
509 },
510 {
511 MHICTRLBASE_LOWER,
512 lower_32_bits(mhi_cntrl->iova_start),
513 },
514 {
515 MHIDATABASE_HIGHER,
516 upper_32_bits(mhi_cntrl->iova_start),
517 },
518 {
519 MHIDATABASE_LOWER,
520 lower_32_bits(mhi_cntrl->iova_start),
521 },
522 {
523 MHICTRLLIMIT_HIGHER,
524 upper_32_bits(mhi_cntrl->iova_stop),
525 },
526 {
527 MHICTRLLIMIT_LOWER,
528 lower_32_bits(mhi_cntrl->iova_stop),
529 },
530 {
531 MHIDATALIMIT_HIGHER,
532 upper_32_bits(mhi_cntrl->iova_stop),
533 },
534 {
535 MHIDATALIMIT_LOWER,
536 lower_32_bits(mhi_cntrl->iova_stop),
537 },
538 {0, 0}
539 };
540
541 dev_dbg(dev, "Initializing MHI registers\n");
542
543 /* Read channel db offset */
544 ret = mhi_get_channel_doorbell_offset(mhi_cntrl, &val);
545 if (ret)
546 return ret;
547
548 if (val >= mhi_cntrl->reg_len - (8 * MHI_DEV_WAKE_DB)) {
549 dev_err(dev, "CHDB offset: 0x%x is out of range: 0x%zx\n",
550 val, mhi_cntrl->reg_len - (8 * MHI_DEV_WAKE_DB));
551 return -ERANGE;
552 }
553
554 /* Setup wake db */
555 mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB);
556 mhi_cntrl->wake_set = false;
557
558 /* Setup channel db address for each channel in tre_ring */
559 mhi_chan = mhi_cntrl->mhi_chan;
560 for (i = 0; i < mhi_cntrl->max_chan; i++, val += 8, mhi_chan++)
561 mhi_chan->tre_ring.db_addr = base + val;
562
563 /* Read event ring db offset */
564 ret = mhi_read_reg(mhi_cntrl, base, ERDBOFF, &val);
565 if (ret) {
566 dev_err(dev, "Unable to read ERDBOFF register\n");
567 return -EIO;
568 }
569
570 if (val >= mhi_cntrl->reg_len - (8 * mhi_cntrl->total_ev_rings)) {
571 dev_err(dev, "ERDB offset: 0x%x is out of range: 0x%zx\n",
572 val, mhi_cntrl->reg_len - (8 * mhi_cntrl->total_ev_rings));
573 return -ERANGE;
574 }
575
576 /* Setup event db address for each ev_ring */
577 mhi_event = mhi_cntrl->mhi_event;
578 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, val += 8, mhi_event++) {
579 if (mhi_event->offload_ev)
580 continue;
581
582 mhi_event->ring.db_addr = base + val;
583 }
584
585 /* Setup DB register for primary CMD rings */
586 mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING].ring.db_addr = base + CRDB_LOWER;
587
588 /* Write to MMIO registers */
589 for (i = 0; reg_info[i].offset; i++)
590 mhi_write_reg(mhi_cntrl, base, reg_info[i].offset,
591 reg_info[i].val);
592
593 ret = mhi_write_reg_field(mhi_cntrl, base, MHICFG, MHICFG_NER_MASK,
594 mhi_cntrl->total_ev_rings);
595 if (ret) {
596 dev_err(dev, "Unable to write MHICFG register\n");
597 return ret;
598 }
599
600 ret = mhi_write_reg_field(mhi_cntrl, base, MHICFG, MHICFG_NHWER_MASK,
601 mhi_cntrl->hw_ev_rings);
602 if (ret) {
603 dev_err(dev, "Unable to write MHICFG register\n");
604 return ret;
605 }
606
607 return 0;
608 }
609
mhi_deinit_chan_ctxt(struct mhi_controller * mhi_cntrl,struct mhi_chan * mhi_chan)610 void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl,
611 struct mhi_chan *mhi_chan)
612 {
613 struct mhi_ring *buf_ring;
614 struct mhi_ring *tre_ring;
615 struct mhi_chan_ctxt *chan_ctxt;
616 u32 tmp;
617
618 buf_ring = &mhi_chan->buf_ring;
619 tre_ring = &mhi_chan->tre_ring;
620 chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan];
621
622 if (!chan_ctxt->rbase) /* Already uninitialized */
623 return;
624
625 dma_free_coherent(mhi_cntrl->cntrl_dev, tre_ring->alloc_size,
626 tre_ring->pre_aligned, tre_ring->dma_handle);
627 vfree(buf_ring->base);
628
629 buf_ring->base = tre_ring->base = NULL;
630 tre_ring->ctxt_wp = NULL;
631 chan_ctxt->rbase = 0;
632 chan_ctxt->rlen = 0;
633 chan_ctxt->rp = 0;
634 chan_ctxt->wp = 0;
635
636 tmp = le32_to_cpu(chan_ctxt->chcfg);
637 tmp &= ~CHAN_CTX_CHSTATE_MASK;
638 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_DISABLED);
639 chan_ctxt->chcfg = cpu_to_le32(tmp);
640
641 /* Update to all cores */
642 smp_wmb();
643 }
644
mhi_init_chan_ctxt(struct mhi_controller * mhi_cntrl,struct mhi_chan * mhi_chan)645 int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl,
646 struct mhi_chan *mhi_chan)
647 {
648 struct mhi_ring *buf_ring;
649 struct mhi_ring *tre_ring;
650 struct mhi_chan_ctxt *chan_ctxt;
651 u32 tmp;
652 int ret;
653
654 buf_ring = &mhi_chan->buf_ring;
655 tre_ring = &mhi_chan->tre_ring;
656 tre_ring->el_size = sizeof(struct mhi_ring_element);
657 tre_ring->len = tre_ring->el_size * tre_ring->elements;
658 chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan];
659 ret = mhi_alloc_aligned_ring(mhi_cntrl, tre_ring, tre_ring->len);
660 if (ret)
661 return -ENOMEM;
662
663 buf_ring->el_size = sizeof(struct mhi_buf_info);
664 buf_ring->len = buf_ring->el_size * buf_ring->elements;
665 buf_ring->base = vzalloc(buf_ring->len);
666
667 if (!buf_ring->base) {
668 dma_free_coherent(mhi_cntrl->cntrl_dev, tre_ring->alloc_size,
669 tre_ring->pre_aligned, tre_ring->dma_handle);
670 return -ENOMEM;
671 }
672
673 tmp = le32_to_cpu(chan_ctxt->chcfg);
674 tmp &= ~CHAN_CTX_CHSTATE_MASK;
675 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_ENABLED);
676 chan_ctxt->chcfg = cpu_to_le32(tmp);
677
678 chan_ctxt->rbase = cpu_to_le64(tre_ring->iommu_base);
679 chan_ctxt->rp = chan_ctxt->wp = chan_ctxt->rbase;
680 chan_ctxt->rlen = cpu_to_le64(tre_ring->len);
681 tre_ring->ctxt_wp = &chan_ctxt->wp;
682
683 tre_ring->rp = tre_ring->wp = tre_ring->base;
684 buf_ring->rp = buf_ring->wp = buf_ring->base;
685 mhi_chan->db_cfg.db_mode = 1;
686
687 /* Update to all cores */
688 smp_wmb();
689
690 return 0;
691 }
692
parse_ev_cfg(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)693 static int parse_ev_cfg(struct mhi_controller *mhi_cntrl,
694 const struct mhi_controller_config *config)
695 {
696 struct mhi_event *mhi_event;
697 const struct mhi_event_config *event_cfg;
698 struct device *dev = mhi_cntrl->cntrl_dev;
699 int i, num;
700
701 num = config->num_events;
702 mhi_cntrl->total_ev_rings = num;
703 mhi_cntrl->mhi_event = kcalloc(num, sizeof(*mhi_cntrl->mhi_event),
704 GFP_KERNEL);
705 if (!mhi_cntrl->mhi_event)
706 return -ENOMEM;
707
708 /* Populate event ring */
709 mhi_event = mhi_cntrl->mhi_event;
710 for (i = 0; i < num; i++) {
711 event_cfg = &config->event_cfg[i];
712
713 mhi_event->er_index = i;
714 mhi_event->ring.elements = event_cfg->num_elements;
715 mhi_event->intmod = event_cfg->irq_moderation_ms;
716 mhi_event->irq = event_cfg->irq;
717
718 if (event_cfg->channel != U32_MAX) {
719 /* This event ring has a dedicated channel */
720 mhi_event->chan = event_cfg->channel;
721 if (mhi_event->chan >= mhi_cntrl->max_chan) {
722 dev_err(dev,
723 "Event Ring channel not available\n");
724 goto error_ev_cfg;
725 }
726
727 mhi_event->mhi_chan =
728 &mhi_cntrl->mhi_chan[mhi_event->chan];
729 }
730
731 /* Priority is fixed to 1 for now */
732 mhi_event->priority = 1;
733
734 mhi_event->db_cfg.brstmode = event_cfg->mode;
735 if (MHI_INVALID_BRSTMODE(mhi_event->db_cfg.brstmode))
736 goto error_ev_cfg;
737
738 if (mhi_event->db_cfg.brstmode == MHI_DB_BRST_ENABLE)
739 mhi_event->db_cfg.process_db = mhi_db_brstmode;
740 else
741 mhi_event->db_cfg.process_db = mhi_db_brstmode_disable;
742
743 mhi_event->data_type = event_cfg->data_type;
744
745 switch (mhi_event->data_type) {
746 case MHI_ER_DATA:
747 mhi_event->process_event = mhi_process_data_event_ring;
748 break;
749 case MHI_ER_CTRL:
750 mhi_event->process_event = mhi_process_ctrl_ev_ring;
751 break;
752 default:
753 dev_err(dev, "Event Ring type not supported\n");
754 goto error_ev_cfg;
755 }
756
757 mhi_event->hw_ring = event_cfg->hardware_event;
758 if (mhi_event->hw_ring)
759 mhi_cntrl->hw_ev_rings++;
760 else
761 mhi_cntrl->sw_ev_rings++;
762
763 mhi_event->cl_manage = event_cfg->client_managed;
764 mhi_event->offload_ev = event_cfg->offload_channel;
765 mhi_event++;
766 }
767
768 return 0;
769
770 error_ev_cfg:
771
772 kfree(mhi_cntrl->mhi_event);
773 return -EINVAL;
774 }
775
parse_ch_cfg(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)776 static int parse_ch_cfg(struct mhi_controller *mhi_cntrl,
777 const struct mhi_controller_config *config)
778 {
779 const struct mhi_channel_config *ch_cfg;
780 struct device *dev = mhi_cntrl->cntrl_dev;
781 int i;
782 u32 chan;
783
784 mhi_cntrl->max_chan = config->max_channels;
785
786 /*
787 * The allocation of MHI channels can exceed 32KB in some scenarios,
788 * so to avoid any memory possible allocation failures, vzalloc is
789 * used here
790 */
791 mhi_cntrl->mhi_chan = vcalloc(mhi_cntrl->max_chan,
792 sizeof(*mhi_cntrl->mhi_chan));
793 if (!mhi_cntrl->mhi_chan)
794 return -ENOMEM;
795
796 INIT_LIST_HEAD(&mhi_cntrl->lpm_chans);
797
798 /* Populate channel configurations */
799 for (i = 0; i < config->num_channels; i++) {
800 struct mhi_chan *mhi_chan;
801
802 ch_cfg = &config->ch_cfg[i];
803
804 chan = ch_cfg->num;
805 if (chan >= mhi_cntrl->max_chan) {
806 dev_err(dev, "Channel %d not available\n", chan);
807 goto error_chan_cfg;
808 }
809
810 mhi_chan = &mhi_cntrl->mhi_chan[chan];
811 mhi_chan->name = ch_cfg->name;
812 mhi_chan->chan = chan;
813
814 mhi_chan->tre_ring.elements = ch_cfg->num_elements;
815 if (!mhi_chan->tre_ring.elements)
816 goto error_chan_cfg;
817
818 /*
819 * For some channels, local ring length should be bigger than
820 * the transfer ring length due to internal logical channels
821 * in device. So host can queue much more buffers than transfer
822 * ring length. Example, RSC channels should have a larger local
823 * channel length than transfer ring length.
824 */
825 mhi_chan->buf_ring.elements = ch_cfg->local_elements;
826 if (!mhi_chan->buf_ring.elements)
827 mhi_chan->buf_ring.elements = mhi_chan->tre_ring.elements;
828 mhi_chan->er_index = ch_cfg->event_ring;
829 mhi_chan->dir = ch_cfg->dir;
830
831 /*
832 * For most channels, chtype is identical to channel directions.
833 * So, if it is not defined then assign channel direction to
834 * chtype
835 */
836 mhi_chan->type = ch_cfg->type;
837 if (!mhi_chan->type)
838 mhi_chan->type = (enum mhi_ch_type)mhi_chan->dir;
839
840 mhi_chan->ee_mask = ch_cfg->ee_mask;
841 mhi_chan->db_cfg.pollcfg = ch_cfg->pollcfg;
842 mhi_chan->lpm_notify = ch_cfg->lpm_notify;
843 mhi_chan->offload_ch = ch_cfg->offload_channel;
844 mhi_chan->db_cfg.reset_req = ch_cfg->doorbell_mode_switch;
845 mhi_chan->pre_alloc = ch_cfg->auto_queue;
846 mhi_chan->wake_capable = ch_cfg->wake_capable;
847
848 /*
849 * If MHI host allocates buffers, then the channel direction
850 * should be DMA_FROM_DEVICE
851 */
852 if (mhi_chan->pre_alloc && mhi_chan->dir != DMA_FROM_DEVICE) {
853 dev_err(dev, "Invalid channel configuration\n");
854 goto error_chan_cfg;
855 }
856
857 /*
858 * Bi-directional and direction less channel must be an
859 * offload channel
860 */
861 if ((mhi_chan->dir == DMA_BIDIRECTIONAL ||
862 mhi_chan->dir == DMA_NONE) && !mhi_chan->offload_ch) {
863 dev_err(dev, "Invalid channel configuration\n");
864 goto error_chan_cfg;
865 }
866
867 if (!mhi_chan->offload_ch) {
868 mhi_chan->db_cfg.brstmode = ch_cfg->doorbell;
869 if (MHI_INVALID_BRSTMODE(mhi_chan->db_cfg.brstmode)) {
870 dev_err(dev, "Invalid Door bell mode\n");
871 goto error_chan_cfg;
872 }
873 }
874
875 if (mhi_chan->db_cfg.brstmode == MHI_DB_BRST_ENABLE)
876 mhi_chan->db_cfg.process_db = mhi_db_brstmode;
877 else
878 mhi_chan->db_cfg.process_db = mhi_db_brstmode_disable;
879
880 mhi_chan->configured = true;
881
882 if (mhi_chan->lpm_notify)
883 list_add_tail(&mhi_chan->node, &mhi_cntrl->lpm_chans);
884 }
885
886 return 0;
887
888 error_chan_cfg:
889 vfree(mhi_cntrl->mhi_chan);
890
891 return -EINVAL;
892 }
893
parse_config(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)894 static int parse_config(struct mhi_controller *mhi_cntrl,
895 const struct mhi_controller_config *config)
896 {
897 int ret;
898
899 /* Parse MHI channel configuration */
900 ret = parse_ch_cfg(mhi_cntrl, config);
901 if (ret)
902 return ret;
903
904 /* Parse MHI event configuration */
905 ret = parse_ev_cfg(mhi_cntrl, config);
906 if (ret)
907 goto error_ev_cfg;
908
909 mhi_cntrl->timeout_ms = config->timeout_ms;
910 if (!mhi_cntrl->timeout_ms)
911 mhi_cntrl->timeout_ms = MHI_TIMEOUT_MS;
912
913 mhi_cntrl->ready_timeout_ms = config->ready_timeout_ms;
914 mhi_cntrl->bounce_buf = config->use_bounce_buf;
915 mhi_cntrl->buffer_len = config->buf_len;
916 if (!mhi_cntrl->buffer_len)
917 mhi_cntrl->buffer_len = MHI_MAX_MTU;
918
919 /* By default, host is allowed to ring DB in both M0 and M2 states */
920 mhi_cntrl->db_access = MHI_PM_M0 | MHI_PM_M2;
921 if (config->m2_no_db)
922 mhi_cntrl->db_access &= ~MHI_PM_M2;
923
924 return 0;
925
926 error_ev_cfg:
927 vfree(mhi_cntrl->mhi_chan);
928
929 return ret;
930 }
931
mhi_register_controller(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * config)932 int mhi_register_controller(struct mhi_controller *mhi_cntrl,
933 const struct mhi_controller_config *config)
934 {
935 struct mhi_event *mhi_event;
936 struct mhi_chan *mhi_chan;
937 struct mhi_cmd *mhi_cmd;
938 struct mhi_device *mhi_dev;
939 int ret, i;
940
941 if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs ||
942 !mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||
943 !mhi_cntrl->status_cb || !mhi_cntrl->read_reg ||
944 !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs ||
945 !mhi_cntrl->irq || !mhi_cntrl->reg_len)
946 return -EINVAL;
947
948 ret = parse_config(mhi_cntrl, config);
949 if (ret)
950 return -EINVAL;
951
952 mhi_cntrl->mhi_cmd = kcalloc(NR_OF_CMD_RINGS,
953 sizeof(*mhi_cntrl->mhi_cmd), GFP_KERNEL);
954 if (!mhi_cntrl->mhi_cmd) {
955 ret = -ENOMEM;
956 goto err_free_event;
957 }
958
959 INIT_LIST_HEAD(&mhi_cntrl->transition_list);
960 mutex_init(&mhi_cntrl->pm_mutex);
961 rwlock_init(&mhi_cntrl->pm_lock);
962 spin_lock_init(&mhi_cntrl->transition_lock);
963 spin_lock_init(&mhi_cntrl->wlock);
964 INIT_WORK(&mhi_cntrl->st_worker, mhi_pm_st_worker);
965 init_waitqueue_head(&mhi_cntrl->state_event);
966
967 mhi_cntrl->hiprio_wq = alloc_ordered_workqueue("mhi_hiprio_wq", WQ_HIGHPRI);
968 if (!mhi_cntrl->hiprio_wq) {
969 dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate workqueue\n");
970 ret = -ENOMEM;
971 goto err_free_cmd;
972 }
973
974 mhi_cmd = mhi_cntrl->mhi_cmd;
975 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++)
976 spin_lock_init(&mhi_cmd->lock);
977
978 mhi_event = mhi_cntrl->mhi_event;
979 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
980 /* Skip for offload events */
981 if (mhi_event->offload_ev)
982 continue;
983
984 mhi_event->mhi_cntrl = mhi_cntrl;
985 spin_lock_init(&mhi_event->lock);
986 if (mhi_event->data_type == MHI_ER_CTRL)
987 tasklet_init(&mhi_event->task, mhi_ctrl_ev_task,
988 (ulong)mhi_event);
989 else
990 tasklet_init(&mhi_event->task, mhi_ev_task,
991 (ulong)mhi_event);
992 }
993
994 mhi_chan = mhi_cntrl->mhi_chan;
995 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
996 mutex_init(&mhi_chan->mutex);
997 init_completion(&mhi_chan->completion);
998 rwlock_init(&mhi_chan->lock);
999
1000 /* used in setting bei field of TRE */
1001 mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index];
1002 mhi_chan->intmod = mhi_event->intmod;
1003 }
1004
1005 if (mhi_cntrl->bounce_buf) {
1006 mhi_cntrl->map_single = mhi_map_single_use_bb;
1007 mhi_cntrl->unmap_single = mhi_unmap_single_use_bb;
1008 } else {
1009 mhi_cntrl->map_single = mhi_map_single_no_bb;
1010 mhi_cntrl->unmap_single = mhi_unmap_single_no_bb;
1011 }
1012
1013 mhi_cntrl->index = ida_alloc(&mhi_controller_ida, GFP_KERNEL);
1014 if (mhi_cntrl->index < 0) {
1015 ret = mhi_cntrl->index;
1016 goto err_destroy_wq;
1017 }
1018
1019 ret = mhi_init_irq_setup(mhi_cntrl);
1020 if (ret)
1021 goto err_ida_free;
1022
1023 /* Register controller with MHI bus */
1024 mhi_dev = mhi_alloc_device(mhi_cntrl);
1025 if (IS_ERR(mhi_dev)) {
1026 dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate MHI device\n");
1027 ret = PTR_ERR(mhi_dev);
1028 goto error_setup_irq;
1029 }
1030
1031 mhi_dev->dev_type = MHI_DEVICE_CONTROLLER;
1032 mhi_dev->mhi_cntrl = mhi_cntrl;
1033 dev_set_name(&mhi_dev->dev, "mhi%d", mhi_cntrl->index);
1034 mhi_dev->name = dev_name(&mhi_dev->dev);
1035
1036 /* Init wakeup source */
1037 device_init_wakeup(&mhi_dev->dev, true);
1038
1039 ret = device_add(&mhi_dev->dev);
1040 if (ret)
1041 goto err_release_dev;
1042
1043 if (mhi_cntrl->edl_trigger) {
1044 ret = sysfs_create_file(&mhi_dev->dev.kobj, &dev_attr_trigger_edl.attr);
1045 if (ret)
1046 goto err_release_dev;
1047 }
1048
1049 mhi_cntrl->mhi_dev = mhi_dev;
1050
1051 mhi_create_debugfs(mhi_cntrl);
1052
1053 return 0;
1054
1055 err_release_dev:
1056 put_device(&mhi_dev->dev);
1057 error_setup_irq:
1058 mhi_deinit_free_irq(mhi_cntrl);
1059 err_ida_free:
1060 ida_free(&mhi_controller_ida, mhi_cntrl->index);
1061 err_destroy_wq:
1062 destroy_workqueue(mhi_cntrl->hiprio_wq);
1063 err_free_cmd:
1064 kfree(mhi_cntrl->mhi_cmd);
1065 err_free_event:
1066 kfree(mhi_cntrl->mhi_event);
1067 vfree(mhi_cntrl->mhi_chan);
1068
1069 return ret;
1070 }
1071 EXPORT_SYMBOL_GPL(mhi_register_controller);
1072
mhi_unregister_controller(struct mhi_controller * mhi_cntrl)1073 void mhi_unregister_controller(struct mhi_controller *mhi_cntrl)
1074 {
1075 struct mhi_device *mhi_dev = mhi_cntrl->mhi_dev;
1076 struct mhi_chan *mhi_chan = mhi_cntrl->mhi_chan;
1077 unsigned int i;
1078
1079 mhi_deinit_free_irq(mhi_cntrl);
1080 mhi_destroy_debugfs(mhi_cntrl);
1081
1082 if (mhi_cntrl->edl_trigger)
1083 sysfs_remove_file(&mhi_dev->dev.kobj, &dev_attr_trigger_edl.attr);
1084
1085 destroy_workqueue(mhi_cntrl->hiprio_wq);
1086 kfree(mhi_cntrl->mhi_cmd);
1087 kfree(mhi_cntrl->mhi_event);
1088
1089 /* Drop the references to MHI devices created for channels */
1090 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
1091 if (!mhi_chan->mhi_dev)
1092 continue;
1093
1094 put_device(&mhi_chan->mhi_dev->dev);
1095 }
1096 vfree(mhi_cntrl->mhi_chan);
1097
1098 device_del(&mhi_dev->dev);
1099 put_device(&mhi_dev->dev);
1100
1101 ida_free(&mhi_controller_ida, mhi_cntrl->index);
1102 }
1103 EXPORT_SYMBOL_GPL(mhi_unregister_controller);
1104
mhi_alloc_controller(void)1105 struct mhi_controller *mhi_alloc_controller(void)
1106 {
1107 struct mhi_controller *mhi_cntrl;
1108
1109 mhi_cntrl = kzalloc(sizeof(*mhi_cntrl), GFP_KERNEL);
1110
1111 return mhi_cntrl;
1112 }
1113 EXPORT_SYMBOL_GPL(mhi_alloc_controller);
1114
mhi_free_controller(struct mhi_controller * mhi_cntrl)1115 void mhi_free_controller(struct mhi_controller *mhi_cntrl)
1116 {
1117 kfree(mhi_cntrl);
1118 }
1119 EXPORT_SYMBOL_GPL(mhi_free_controller);
1120
mhi_prepare_for_power_up(struct mhi_controller * mhi_cntrl)1121 int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
1122 {
1123 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1124 u32 bhi_off, bhie_off;
1125 int ret;
1126
1127 mutex_lock(&mhi_cntrl->pm_mutex);
1128
1129 ret = mhi_init_dev_ctxt(mhi_cntrl);
1130 if (ret)
1131 goto error_dev_ctxt;
1132
1133 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &bhi_off);
1134 if (ret) {
1135 dev_err(dev, "Error getting BHI offset\n");
1136 goto error_reg_offset;
1137 }
1138
1139 if (bhi_off >= mhi_cntrl->reg_len) {
1140 dev_err(dev, "BHI offset: 0x%x is out of range: 0x%zx\n",
1141 bhi_off, mhi_cntrl->reg_len);
1142 ret = -ERANGE;
1143 goto error_reg_offset;
1144 }
1145 mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
1146
1147 if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {
1148 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF,
1149 &bhie_off);
1150 if (ret) {
1151 dev_err(dev, "Error getting BHIE offset\n");
1152 goto error_reg_offset;
1153 }
1154
1155 if (bhie_off >= mhi_cntrl->reg_len) {
1156 dev_err(dev,
1157 "BHIe offset: 0x%x is out of range: 0x%zx\n",
1158 bhie_off, mhi_cntrl->reg_len);
1159 ret = -ERANGE;
1160 goto error_reg_offset;
1161 }
1162 mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
1163 }
1164
1165 if (mhi_cntrl->rddm_size) {
1166 /*
1167 * This controller supports RDDM, so we need to manually clear
1168 * BHIE RX registers since POR values are undefined.
1169 */
1170 memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS,
1171 0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS +
1172 4);
1173 /*
1174 * Allocate RDDM table for debugging purpose if specified
1175 */
1176 mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
1177 mhi_cntrl->rddm_size);
1178 if (mhi_cntrl->rddm_image) {
1179 ret = mhi_rddm_prepare(mhi_cntrl,
1180 mhi_cntrl->rddm_image);
1181 if (ret) {
1182 mhi_free_bhie_table(mhi_cntrl,
1183 mhi_cntrl->rddm_image);
1184 goto error_reg_offset;
1185 }
1186 }
1187 }
1188
1189 mutex_unlock(&mhi_cntrl->pm_mutex);
1190
1191 return 0;
1192
1193 error_reg_offset:
1194 mhi_deinit_dev_ctxt(mhi_cntrl);
1195
1196 error_dev_ctxt:
1197 mutex_unlock(&mhi_cntrl->pm_mutex);
1198
1199 return ret;
1200 }
1201 EXPORT_SYMBOL_GPL(mhi_prepare_for_power_up);
1202
mhi_unprepare_after_power_down(struct mhi_controller * mhi_cntrl)1203 void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl)
1204 {
1205 if (mhi_cntrl->fbc_image) {
1206 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image);
1207 mhi_cntrl->fbc_image = NULL;
1208 }
1209
1210 if (mhi_cntrl->rddm_image) {
1211 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image);
1212 mhi_cntrl->rddm_image = NULL;
1213 }
1214
1215 mhi_cntrl->bhi = NULL;
1216 mhi_cntrl->bhie = NULL;
1217
1218 mhi_deinit_dev_ctxt(mhi_cntrl);
1219 }
1220 EXPORT_SYMBOL_GPL(mhi_unprepare_after_power_down);
1221
mhi_release_device(struct device * dev)1222 static void mhi_release_device(struct device *dev)
1223 {
1224 struct mhi_device *mhi_dev = to_mhi_device(dev);
1225
1226 /*
1227 * We need to set the mhi_chan->mhi_dev to NULL here since the MHI
1228 * devices for the channels will only get created if the mhi_dev
1229 * associated with it is NULL. This scenario will happen during the
1230 * controller suspend and resume.
1231 */
1232 if (mhi_dev->ul_chan)
1233 mhi_dev->ul_chan->mhi_dev = NULL;
1234
1235 if (mhi_dev->dl_chan)
1236 mhi_dev->dl_chan->mhi_dev = NULL;
1237
1238 kfree(mhi_dev);
1239 }
1240
mhi_alloc_device(struct mhi_controller * mhi_cntrl)1241 struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl)
1242 {
1243 struct mhi_device *mhi_dev;
1244 struct device *dev;
1245
1246 mhi_dev = kzalloc(sizeof(*mhi_dev), GFP_KERNEL);
1247 if (!mhi_dev)
1248 return ERR_PTR(-ENOMEM);
1249
1250 dev = &mhi_dev->dev;
1251 device_initialize(dev);
1252 dev->bus = &mhi_bus_type;
1253 dev->release = mhi_release_device;
1254
1255 if (mhi_cntrl->mhi_dev) {
1256 /* for MHI client devices, parent is the MHI controller device */
1257 dev->parent = &mhi_cntrl->mhi_dev->dev;
1258 } else {
1259 /* for MHI controller device, parent is the bus device (e.g. pci device) */
1260 dev->parent = mhi_cntrl->cntrl_dev;
1261 }
1262
1263 mhi_dev->mhi_cntrl = mhi_cntrl;
1264 mhi_dev->dev_wake = 0;
1265
1266 return mhi_dev;
1267 }
1268
mhi_driver_probe(struct device * dev)1269 static int mhi_driver_probe(struct device *dev)
1270 {
1271 struct mhi_device *mhi_dev = to_mhi_device(dev);
1272 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1273 struct device_driver *drv = dev->driver;
1274 struct mhi_driver *mhi_drv = to_mhi_driver(drv);
1275 struct mhi_event *mhi_event;
1276 struct mhi_chan *ul_chan = mhi_dev->ul_chan;
1277 struct mhi_chan *dl_chan = mhi_dev->dl_chan;
1278 int ret;
1279
1280 /* Bring device out of LPM */
1281 ret = mhi_device_get_sync(mhi_dev);
1282 if (ret)
1283 return ret;
1284
1285 ret = -EINVAL;
1286
1287 if (ul_chan) {
1288 /*
1289 * If channel supports LPM notifications then status_cb should
1290 * be provided
1291 */
1292 if (ul_chan->lpm_notify && !mhi_drv->status_cb)
1293 goto exit_probe;
1294
1295 /* For non-offload channels then xfer_cb should be provided */
1296 if (!ul_chan->offload_ch && !mhi_drv->ul_xfer_cb)
1297 goto exit_probe;
1298
1299 ul_chan->xfer_cb = mhi_drv->ul_xfer_cb;
1300 }
1301
1302 ret = -EINVAL;
1303 if (dl_chan) {
1304 /*
1305 * If channel supports LPM notifications then status_cb should
1306 * be provided
1307 */
1308 if (dl_chan->lpm_notify && !mhi_drv->status_cb)
1309 goto exit_probe;
1310
1311 /* For non-offload channels then xfer_cb should be provided */
1312 if (!dl_chan->offload_ch && !mhi_drv->dl_xfer_cb)
1313 goto exit_probe;
1314
1315 mhi_event = &mhi_cntrl->mhi_event[dl_chan->er_index];
1316
1317 /*
1318 * If the channel event ring is managed by client, then
1319 * status_cb must be provided so that the framework can
1320 * notify pending data
1321 */
1322 if (mhi_event->cl_manage && !mhi_drv->status_cb)
1323 goto exit_probe;
1324
1325 dl_chan->xfer_cb = mhi_drv->dl_xfer_cb;
1326 }
1327
1328 /* Call the user provided probe function */
1329 ret = mhi_drv->probe(mhi_dev, mhi_dev->id);
1330 if (ret)
1331 goto exit_probe;
1332
1333 mhi_device_put(mhi_dev);
1334
1335 return ret;
1336
1337 exit_probe:
1338 mhi_unprepare_from_transfer(mhi_dev);
1339
1340 mhi_device_put(mhi_dev);
1341
1342 return ret;
1343 }
1344
mhi_driver_remove(struct device * dev)1345 static int mhi_driver_remove(struct device *dev)
1346 {
1347 struct mhi_device *mhi_dev = to_mhi_device(dev);
1348 struct mhi_driver *mhi_drv = to_mhi_driver(dev->driver);
1349 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1350 struct mhi_chan *mhi_chan;
1351 enum mhi_ch_state ch_state[] = {
1352 MHI_CH_STATE_DISABLED,
1353 MHI_CH_STATE_DISABLED
1354 };
1355 int dir;
1356
1357 /* Skip if it is a controller device */
1358 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER)
1359 return 0;
1360
1361 /* Reset both channels */
1362 for (dir = 0; dir < 2; dir++) {
1363 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan;
1364
1365 if (!mhi_chan)
1366 continue;
1367
1368 /* Wake all threads waiting for completion */
1369 write_lock_irq(&mhi_chan->lock);
1370 mhi_chan->ccs = MHI_EV_CC_INVALID;
1371 complete_all(&mhi_chan->completion);
1372 write_unlock_irq(&mhi_chan->lock);
1373
1374 /* Set the channel state to disabled */
1375 mutex_lock(&mhi_chan->mutex);
1376 write_lock_irq(&mhi_chan->lock);
1377 ch_state[dir] = mhi_chan->ch_state;
1378 mhi_chan->ch_state = MHI_CH_STATE_SUSPENDED;
1379 write_unlock_irq(&mhi_chan->lock);
1380
1381 /* Reset the non-offload channel */
1382 if (!mhi_chan->offload_ch)
1383 mhi_reset_chan(mhi_cntrl, mhi_chan);
1384
1385 mutex_unlock(&mhi_chan->mutex);
1386 }
1387
1388 mhi_drv->remove(mhi_dev);
1389
1390 /* De-init channel if it was enabled */
1391 for (dir = 0; dir < 2; dir++) {
1392 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan;
1393
1394 if (!mhi_chan)
1395 continue;
1396
1397 mutex_lock(&mhi_chan->mutex);
1398
1399 if ((ch_state[dir] == MHI_CH_STATE_ENABLED ||
1400 ch_state[dir] == MHI_CH_STATE_STOP) &&
1401 !mhi_chan->offload_ch)
1402 mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan);
1403
1404 mhi_chan->ch_state = MHI_CH_STATE_DISABLED;
1405
1406 mutex_unlock(&mhi_chan->mutex);
1407 }
1408
1409 while (mhi_dev->dev_wake)
1410 mhi_device_put(mhi_dev);
1411
1412 return 0;
1413 }
1414
__mhi_driver_register(struct mhi_driver * mhi_drv,struct module * owner)1415 int __mhi_driver_register(struct mhi_driver *mhi_drv, struct module *owner)
1416 {
1417 struct device_driver *driver = &mhi_drv->driver;
1418
1419 if (!mhi_drv->probe || !mhi_drv->remove)
1420 return -EINVAL;
1421
1422 driver->bus = &mhi_bus_type;
1423 driver->owner = owner;
1424 driver->probe = mhi_driver_probe;
1425 driver->remove = mhi_driver_remove;
1426
1427 return driver_register(driver);
1428 }
1429 EXPORT_SYMBOL_GPL(__mhi_driver_register);
1430
mhi_driver_unregister(struct mhi_driver * mhi_drv)1431 void mhi_driver_unregister(struct mhi_driver *mhi_drv)
1432 {
1433 driver_unregister(&mhi_drv->driver);
1434 }
1435 EXPORT_SYMBOL_GPL(mhi_driver_unregister);
1436
mhi_uevent(const struct device * dev,struct kobj_uevent_env * env)1437 static int mhi_uevent(const struct device *dev, struct kobj_uevent_env *env)
1438 {
1439 const struct mhi_device *mhi_dev = to_mhi_device(dev);
1440
1441 return add_uevent_var(env, "MODALIAS=" MHI_DEVICE_MODALIAS_FMT,
1442 mhi_dev->name);
1443 }
1444
mhi_match(struct device * dev,struct device_driver * drv)1445 static int mhi_match(struct device *dev, struct device_driver *drv)
1446 {
1447 struct mhi_device *mhi_dev = to_mhi_device(dev);
1448 struct mhi_driver *mhi_drv = to_mhi_driver(drv);
1449 const struct mhi_device_id *id;
1450
1451 /*
1452 * If the device is a controller type then there is no client driver
1453 * associated with it
1454 */
1455 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER)
1456 return 0;
1457
1458 for (id = mhi_drv->id_table; id->chan[0]; id++)
1459 if (!strcmp(mhi_dev->name, id->chan)) {
1460 mhi_dev->id = id;
1461 return 1;
1462 }
1463
1464 return 0;
1465 };
1466
1467 struct bus_type mhi_bus_type = {
1468 .name = "mhi",
1469 .dev_name = "mhi",
1470 .match = mhi_match,
1471 .uevent = mhi_uevent,
1472 .dev_groups = mhi_dev_groups,
1473 };
1474
mhi_init(void)1475 static int __init mhi_init(void)
1476 {
1477 mhi_debugfs_init();
1478 return bus_register(&mhi_bus_type);
1479 }
1480
mhi_exit(void)1481 static void __exit mhi_exit(void)
1482 {
1483 mhi_debugfs_exit();
1484 bus_unregister(&mhi_bus_type);
1485 }
1486
1487 postcore_initcall(mhi_init);
1488 module_exit(mhi_exit);
1489
1490 MODULE_LICENSE("GPL v2");
1491 MODULE_DESCRIPTION("Modem Host Interface");
1492