1 /*
2 * ARM mach-virt emulation
3 *
4 * Copyright (c) 2013 Linaro Limited
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
44 #include "net/net.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/runstate.h"
48 #include "sysemu/tpm.h"
49 #include "sysemu/tcg.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "sysemu/qtest.h"
53 #include "hw/loader.h"
54 #include "qapi/error.h"
55 #include "qemu/bitops.h"
56 #include "qemu/error-report.h"
57 #include "qemu/module.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/arm/fdt.h"
64 #include "hw/intc/arm_gic.h"
65 #include "hw/intc/arm_gicv3_common.h"
66 #include "hw/intc/arm_gicv3_its_common.h"
67 #include "hw/irq.h"
68 #include "kvm_arm.h"
69 #include "hw/firmware/smbios.h"
70 #include "qapi/visitor.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "qapi/qmp/qlist.h"
73 #include "standard-headers/linux/input.h"
74 #include "hw/arm/smmuv3.h"
75 #include "hw/acpi/acpi.h"
76 #include "target/arm/cpu-qom.h"
77 #include "target/arm/internals.h"
78 #include "target/arm/multiprocessing.h"
79 #include "target/arm/gtimer.h"
80 #include "hw/mem/pc-dimm.h"
81 #include "hw/mem/nvdimm.h"
82 #include "hw/acpi/generic_event_device.h"
83 #include "hw/virtio/virtio-md-pci.h"
84 #include "hw/virtio/virtio-iommu.h"
85 #include "hw/char/pl011.h"
86 #include "qemu/guest-random.h"
87
88 static GlobalProperty arm_virt_compat[] = {
89 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" },
90 };
91 static const size_t arm_virt_compat_len = G_N_ELEMENTS(arm_virt_compat);
92
93 /*
94 * This cannot be called from the virt_machine_class_init() because
95 * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new()
96 * only is called on virt non abstract class init.
97 */
arm_virt_compat_set(MachineClass * mc)98 static void arm_virt_compat_set(MachineClass *mc)
99 {
100 compat_props_add(mc->compat_props, arm_virt_compat,
101 arm_virt_compat_len);
102 }
103
104 #define DEFINE_VIRT_MACHINE_IMPL(latest, ...) \
105 static void MACHINE_VER_SYM(class_init, virt, __VA_ARGS__)( \
106 ObjectClass *oc, \
107 void *data) \
108 { \
109 MachineClass *mc = MACHINE_CLASS(oc); \
110 arm_virt_compat_set(mc); \
111 MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \
112 mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Machine"; \
113 MACHINE_VER_DEPRECATION(__VA_ARGS__); \
114 if (latest) { \
115 mc->alias = "virt"; \
116 } \
117 } \
118 static const TypeInfo MACHINE_VER_SYM(info, virt, __VA_ARGS__) = \
119 { \
120 .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \
121 .parent = TYPE_VIRT_MACHINE, \
122 .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \
123 }; \
124 static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \
125 { \
126 MACHINE_VER_DELETION(__VA_ARGS__); \
127 type_register_static(&MACHINE_VER_SYM(info, virt, __VA_ARGS__)); \
128 } \
129 type_init(MACHINE_VER_SYM(register, virt, __VA_ARGS__));
130
131 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
132 DEFINE_VIRT_MACHINE_IMPL(true, major, minor)
133 #define DEFINE_VIRT_MACHINE(major, minor) \
134 DEFINE_VIRT_MACHINE_IMPL(false, major, minor)
135
136
137 /* Number of external interrupt lines to configure the GIC with */
138 #define NUM_IRQS 256
139
140 #define PLATFORM_BUS_NUM_IRQS 64
141
142 /* Legacy RAM limit in GB (< version 4.0) */
143 #define LEGACY_RAMLIMIT_GB 255
144 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
145
146 /* Addresses and sizes of our components.
147 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
148 * 128MB..256MB is used for miscellaneous device I/O.
149 * 256MB..1GB is reserved for possible future PCI support (ie where the
150 * PCI memory window will go if we add a PCI host controller).
151 * 1GB and up is RAM (which may happily spill over into the
152 * high memory region beyond 4GB).
153 * This represents a compromise between how much RAM can be given to
154 * a 32 bit VM and leaving space for expansion and in particular for PCI.
155 * Note that devices should generally be placed at multiples of 0x10000,
156 * to accommodate guests using 64K pages.
157 */
158 static const MemMapEntry base_memmap[] = {
159 /* Space up to 0x8000000 is reserved for a boot ROM */
160 [VIRT_FLASH] = { 0, 0x08000000 },
161 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
162 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
163 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
164 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
165 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
166 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
167 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
168 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
169 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
170 /* This redistributor space allows up to 2*64kB*123 CPUs */
171 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
172 [VIRT_UART0] = { 0x09000000, 0x00001000 },
173 [VIRT_RTC] = { 0x09010000, 0x00001000 },
174 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
175 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
176 [VIRT_UART1] = { 0x09040000, 0x00001000 },
177 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
178 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
179 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
180 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
181 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
182 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
183 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
184 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
185 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
186 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
187 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
188 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
189 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
190 /* Actual RAM size depends on initial RAM and device memory settings */
191 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
192 };
193
194 /*
195 * Highmem IO Regions: This memory map is floating, located after the RAM.
196 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
197 * top of the RAM, so that its base get the same alignment as the size,
198 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
199 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
200 * Note the extended_memmap is sized so that it eventually also includes the
201 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
202 * index of base_memmap).
203 *
204 * The memory map for these Highmem IO Regions can be in legacy or compact
205 * layout, depending on 'compact-highmem' property. With legacy layout, the
206 * PA space for one specific region is always reserved, even if the region
207 * has been disabled or doesn't fit into the PA space. However, the PA space
208 * for the region won't be reserved in these circumstances with compact layout.
209 */
210 static MemMapEntry extended_memmap[] = {
211 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
212 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
213 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
214 /* Second PCIe window */
215 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
216 };
217
218 static const int a15irqmap[] = {
219 [VIRT_UART0] = 1,
220 [VIRT_RTC] = 2,
221 [VIRT_PCIE] = 3, /* ... to 6 */
222 [VIRT_GPIO] = 7,
223 [VIRT_UART1] = 8,
224 [VIRT_ACPI_GED] = 9,
225 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
226 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
227 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
228 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
229 };
230
create_randomness(MachineState * ms,const char * node)231 static void create_randomness(MachineState *ms, const char *node)
232 {
233 struct {
234 uint64_t kaslr;
235 uint8_t rng[32];
236 } seed;
237
238 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
239 return;
240 }
241 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr);
242 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
243 }
244
245 /*
246 * The CPU object always exposes the NS EL2 virt timer IRQ line,
247 * but we don't want to advertise it to the guest in the dtb or ACPI
248 * table unless it's really going to do something.
249 */
ns_el2_virt_timer_present(void)250 static bool ns_el2_virt_timer_present(void)
251 {
252 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
253 CPUARMState *env = &cpu->env;
254
255 return arm_feature(env, ARM_FEATURE_AARCH64) &&
256 arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
257 }
258
create_fdt(VirtMachineState * vms)259 static void create_fdt(VirtMachineState *vms)
260 {
261 MachineState *ms = MACHINE(vms);
262 int nb_numa_nodes = ms->numa_state->num_nodes;
263 void *fdt = create_device_tree(&vms->fdt_size);
264
265 if (!fdt) {
266 error_report("create_device_tree() failed");
267 exit(1);
268 }
269
270 ms->fdt = fdt;
271
272 /* Header */
273 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
274 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
275 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
276 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
277
278 /*
279 * For QEMU, all DMA is coherent. Advertising this in the root node
280 * has two benefits:
281 *
282 * - It avoids potential bugs where we forget to mark a DMA
283 * capable device as being dma-coherent
284 * - It avoids spurious warnings from the Linux kernel about
285 * devices which can't do DMA at all
286 */
287 qemu_fdt_setprop(fdt, "/", "dma-coherent", NULL, 0);
288
289 /* /chosen must exist for load_dtb to fill in necessary properties later */
290 qemu_fdt_add_subnode(fdt, "/chosen");
291 if (vms->dtb_randomness) {
292 create_randomness(ms, "/chosen");
293 }
294
295 if (vms->secure) {
296 qemu_fdt_add_subnode(fdt, "/secure-chosen");
297 if (vms->dtb_randomness) {
298 create_randomness(ms, "/secure-chosen");
299 }
300 }
301
302 qemu_fdt_add_subnode(fdt, "/aliases");
303
304 /* Clock node, for the benefit of the UART. The kernel device tree
305 * binding documentation claims the PL011 node clock properties are
306 * optional but in practice if you omit them the kernel refuses to
307 * probe for the device.
308 */
309 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
310 qemu_fdt_add_subnode(fdt, "/apb-pclk");
311 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
312 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
313 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
314 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
315 "clk24mhz");
316 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
317
318 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
319 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
320 uint32_t *matrix = g_malloc0(size);
321 int idx, i, j;
322
323 for (i = 0; i < nb_numa_nodes; i++) {
324 for (j = 0; j < nb_numa_nodes; j++) {
325 idx = (i * nb_numa_nodes + j) * 3;
326 matrix[idx + 0] = cpu_to_be32(i);
327 matrix[idx + 1] = cpu_to_be32(j);
328 matrix[idx + 2] =
329 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
330 }
331 }
332
333 qemu_fdt_add_subnode(fdt, "/distance-map");
334 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
335 "numa-distance-map-v1");
336 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
337 matrix, size);
338 g_free(matrix);
339 }
340 }
341
fdt_add_timer_nodes(const VirtMachineState * vms)342 static void fdt_add_timer_nodes(const VirtMachineState *vms)
343 {
344 /* On real hardware these interrupts are level-triggered.
345 * On KVM they were edge-triggered before host kernel version 4.4,
346 * and level-triggered afterwards.
347 * On emulated QEMU they are level-triggered.
348 *
349 * Getting the DTB info about them wrong is awkward for some
350 * guest kernels:
351 * pre-4.8 ignore the DT and leave the interrupt configured
352 * with whatever the GIC reset value (or the bootloader) left it at
353 * 4.8 before rc6 honour the incorrect data by programming it back
354 * into the GIC, causing problems
355 * 4.8rc6 and later ignore the DT and always write "level triggered"
356 * into the GIC
357 *
358 * For backwards-compatibility, virt-2.8 and earlier will continue
359 * to say these are edge-triggered, but later machines will report
360 * the correct information.
361 */
362 ARMCPU *armcpu;
363 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
364 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
365 MachineState *ms = MACHINE(vms);
366
367 if (vmc->claim_edge_triggered_timers) {
368 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
369 }
370
371 if (vms->gic_version == VIRT_GIC_VERSION_2) {
372 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
373 GIC_FDT_IRQ_PPI_CPU_WIDTH,
374 (1 << MACHINE(vms)->smp.cpus) - 1);
375 }
376
377 qemu_fdt_add_subnode(ms->fdt, "/timer");
378
379 armcpu = ARM_CPU(qemu_get_cpu(0));
380 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
381 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
382 qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
383 compat, sizeof(compat));
384 } else {
385 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
386 "arm,armv7-timer");
387 }
388 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
389 if (vms->ns_el2_virt_timer_irq) {
390 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
391 GIC_FDT_IRQ_TYPE_PPI,
392 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
393 GIC_FDT_IRQ_TYPE_PPI,
394 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
395 GIC_FDT_IRQ_TYPE_PPI,
396 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
397 GIC_FDT_IRQ_TYPE_PPI,
398 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
399 GIC_FDT_IRQ_TYPE_PPI,
400 INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
401 } else {
402 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
403 GIC_FDT_IRQ_TYPE_PPI,
404 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
405 GIC_FDT_IRQ_TYPE_PPI,
406 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
407 GIC_FDT_IRQ_TYPE_PPI,
408 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
409 GIC_FDT_IRQ_TYPE_PPI,
410 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
411 }
412 }
413
fdt_add_cpu_nodes(const VirtMachineState * vms)414 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
415 {
416 int cpu;
417 int addr_cells = 1;
418 const MachineState *ms = MACHINE(vms);
419 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
420 int smp_cpus = ms->smp.cpus;
421
422 /*
423 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
424 * On ARM v8 64-bit systems value should be set to 2,
425 * that corresponds to the MPIDR_EL1 register size.
426 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
427 * in the system, #address-cells can be set to 1, since
428 * MPIDR_EL1[63:32] bits are not used for CPUs
429 * identification.
430 *
431 * Here we actually don't know whether our system is 32- or 64-bit one.
432 * The simplest way to go is to examine affinity IDs of all our CPUs. If
433 * at least one of them has Aff3 populated, we set #address-cells to 2.
434 */
435 for (cpu = 0; cpu < smp_cpus; cpu++) {
436 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
437
438 if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) {
439 addr_cells = 2;
440 break;
441 }
442 }
443
444 qemu_fdt_add_subnode(ms->fdt, "/cpus");
445 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
446 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
447
448 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
449 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
450 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
451 CPUState *cs = CPU(armcpu);
452
453 qemu_fdt_add_subnode(ms->fdt, nodename);
454 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
455 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
456 armcpu->dtb_compatible);
457
458 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
459 qemu_fdt_setprop_string(ms->fdt, nodename,
460 "enable-method", "psci");
461 }
462
463 if (addr_cells == 2) {
464 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
465 arm_cpu_mp_affinity(armcpu));
466 } else {
467 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
468 arm_cpu_mp_affinity(armcpu));
469 }
470
471 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
472 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
473 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
474 }
475
476 if (!vmc->no_cpu_topology) {
477 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
478 qemu_fdt_alloc_phandle(ms->fdt));
479 }
480
481 g_free(nodename);
482 }
483
484 if (!vmc->no_cpu_topology) {
485 /*
486 * Add vCPU topology description through fdt node cpu-map.
487 *
488 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
489 * In a SMP system, the hierarchy of CPUs can be defined through
490 * four entities that are used to describe the layout of CPUs in
491 * the system: socket/cluster/core/thread.
492 *
493 * A socket node represents the boundary of system physical package
494 * and its child nodes must be one or more cluster nodes. A system
495 * can contain several layers of clustering within a single physical
496 * package and cluster nodes can be contained in parent cluster nodes.
497 *
498 * Note: currently we only support one layer of clustering within
499 * each physical package.
500 */
501 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
502
503 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
504 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu);
505 char *map_path;
506
507 if (ms->smp.threads > 1) {
508 map_path = g_strdup_printf(
509 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
510 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads),
511 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters,
512 (cpu / ms->smp.threads) % ms->smp.cores,
513 cpu % ms->smp.threads);
514 } else {
515 map_path = g_strdup_printf(
516 "/cpus/cpu-map/socket%d/cluster%d/core%d",
517 cpu / (ms->smp.clusters * ms->smp.cores),
518 (cpu / ms->smp.cores) % ms->smp.clusters,
519 cpu % ms->smp.cores);
520 }
521 qemu_fdt_add_path(ms->fdt, map_path);
522 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
523
524 g_free(map_path);
525 g_free(cpu_path);
526 }
527 }
528 }
529
fdt_add_its_gic_node(VirtMachineState * vms)530 static void fdt_add_its_gic_node(VirtMachineState *vms)
531 {
532 char *nodename;
533 MachineState *ms = MACHINE(vms);
534
535 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
536 nodename = g_strdup_printf("/intc/its@%" PRIx64,
537 vms->memmap[VIRT_GIC_ITS].base);
538 qemu_fdt_add_subnode(ms->fdt, nodename);
539 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
540 "arm,gic-v3-its");
541 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
542 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
543 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
544 2, vms->memmap[VIRT_GIC_ITS].base,
545 2, vms->memmap[VIRT_GIC_ITS].size);
546 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
547 g_free(nodename);
548 }
549
fdt_add_v2m_gic_node(VirtMachineState * vms)550 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
551 {
552 MachineState *ms = MACHINE(vms);
553 char *nodename;
554
555 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
556 vms->memmap[VIRT_GIC_V2M].base);
557 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
558 qemu_fdt_add_subnode(ms->fdt, nodename);
559 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
560 "arm,gic-v2m-frame");
561 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
562 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
563 2, vms->memmap[VIRT_GIC_V2M].base,
564 2, vms->memmap[VIRT_GIC_V2M].size);
565 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
566 g_free(nodename);
567 }
568
fdt_add_gic_node(VirtMachineState * vms)569 static void fdt_add_gic_node(VirtMachineState *vms)
570 {
571 MachineState *ms = MACHINE(vms);
572 char *nodename;
573
574 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
575 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
576
577 nodename = g_strdup_printf("/intc@%" PRIx64,
578 vms->memmap[VIRT_GIC_DIST].base);
579 qemu_fdt_add_subnode(ms->fdt, nodename);
580 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
581 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
582 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
583 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
584 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
585 if (vms->gic_version != VIRT_GIC_VERSION_2) {
586 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
587
588 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
589 "arm,gic-v3");
590
591 qemu_fdt_setprop_cell(ms->fdt, nodename,
592 "#redistributor-regions", nb_redist_regions);
593
594 if (nb_redist_regions == 1) {
595 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
596 2, vms->memmap[VIRT_GIC_DIST].base,
597 2, vms->memmap[VIRT_GIC_DIST].size,
598 2, vms->memmap[VIRT_GIC_REDIST].base,
599 2, vms->memmap[VIRT_GIC_REDIST].size);
600 } else {
601 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
602 2, vms->memmap[VIRT_GIC_DIST].base,
603 2, vms->memmap[VIRT_GIC_DIST].size,
604 2, vms->memmap[VIRT_GIC_REDIST].base,
605 2, vms->memmap[VIRT_GIC_REDIST].size,
606 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
607 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
608 }
609
610 if (vms->virt) {
611 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
612 GIC_FDT_IRQ_TYPE_PPI,
613 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
614 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
615 }
616 } else {
617 /* 'cortex-a15-gic' means 'GIC v2' */
618 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
619 "arm,cortex-a15-gic");
620 if (!vms->virt) {
621 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
622 2, vms->memmap[VIRT_GIC_DIST].base,
623 2, vms->memmap[VIRT_GIC_DIST].size,
624 2, vms->memmap[VIRT_GIC_CPU].base,
625 2, vms->memmap[VIRT_GIC_CPU].size);
626 } else {
627 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
628 2, vms->memmap[VIRT_GIC_DIST].base,
629 2, vms->memmap[VIRT_GIC_DIST].size,
630 2, vms->memmap[VIRT_GIC_CPU].base,
631 2, vms->memmap[VIRT_GIC_CPU].size,
632 2, vms->memmap[VIRT_GIC_HYP].base,
633 2, vms->memmap[VIRT_GIC_HYP].size,
634 2, vms->memmap[VIRT_GIC_VCPU].base,
635 2, vms->memmap[VIRT_GIC_VCPU].size);
636 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
637 GIC_FDT_IRQ_TYPE_PPI,
638 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
639 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
640 }
641 }
642
643 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
644 g_free(nodename);
645 }
646
fdt_add_pmu_nodes(const VirtMachineState * vms)647 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
648 {
649 ARMCPU *armcpu = ARM_CPU(first_cpu);
650 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
651 MachineState *ms = MACHINE(vms);
652
653 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
654 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
655 return;
656 }
657
658 if (vms->gic_version == VIRT_GIC_VERSION_2) {
659 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
660 GIC_FDT_IRQ_PPI_CPU_WIDTH,
661 (1 << MACHINE(vms)->smp.cpus) - 1);
662 }
663
664 qemu_fdt_add_subnode(ms->fdt, "/pmu");
665 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
666 const char compat[] = "arm,armv8-pmuv3";
667 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
668 compat, sizeof(compat));
669 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
670 GIC_FDT_IRQ_TYPE_PPI,
671 INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags);
672 }
673 }
674
create_acpi_ged(VirtMachineState * vms)675 static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
676 {
677 DeviceState *dev;
678 MachineState *ms = MACHINE(vms);
679 int irq = vms->irqmap[VIRT_ACPI_GED];
680 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
681
682 if (ms->ram_slots) {
683 event |= ACPI_GED_MEM_HOTPLUG_EVT;
684 }
685
686 if (ms->nvdimms_state->is_enabled) {
687 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
688 }
689
690 dev = qdev_new(TYPE_ACPI_GED);
691 qdev_prop_set_uint32(dev, "ged-event", event);
692 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
693
694 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
695 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
696 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
697
698 return dev;
699 }
700
create_its(VirtMachineState * vms)701 static void create_its(VirtMachineState *vms)
702 {
703 const char *itsclass = its_class_name();
704 DeviceState *dev;
705
706 if (!strcmp(itsclass, "arm-gicv3-its")) {
707 if (!vms->tcg_its) {
708 itsclass = NULL;
709 }
710 }
711
712 if (!itsclass) {
713 /* Do nothing if not supported */
714 return;
715 }
716
717 dev = qdev_new(itsclass);
718
719 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
720 &error_abort);
721 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
722 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
723
724 fdt_add_its_gic_node(vms);
725 vms->msi_controller = VIRT_MSI_CTRL_ITS;
726 }
727
create_v2m(VirtMachineState * vms)728 static void create_v2m(VirtMachineState *vms)
729 {
730 int i;
731 int irq = vms->irqmap[VIRT_GIC_V2M];
732 DeviceState *dev;
733
734 dev = qdev_new("arm-gicv2m");
735 qdev_prop_set_uint32(dev, "base-spi", irq);
736 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
737 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
738 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
739
740 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
741 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
742 qdev_get_gpio_in(vms->gic, irq + i));
743 }
744
745 fdt_add_v2m_gic_node(vms);
746 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
747 }
748
749 /*
750 * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too.
751 * It's permitted to have a configuration with NMI in the CPU (and thus the
752 * GICv3 CPU interface) but not in the distributor/redistributors, but it's
753 * not very useful.
754 */
gicv3_nmi_present(VirtMachineState * vms)755 static bool gicv3_nmi_present(VirtMachineState *vms)
756 {
757 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
758
759 return tcg_enabled() && cpu_isar_feature(aa64_nmi, cpu) &&
760 (vms->gic_version != VIRT_GIC_VERSION_2);
761 }
762
create_gic(VirtMachineState * vms,MemoryRegion * mem)763 static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
764 {
765 MachineState *ms = MACHINE(vms);
766 /* We create a standalone GIC */
767 SysBusDevice *gicbusdev;
768 const char *gictype;
769 int i;
770 unsigned int smp_cpus = ms->smp.cpus;
771 uint32_t nb_redist_regions = 0;
772 int revision;
773
774 if (vms->gic_version == VIRT_GIC_VERSION_2) {
775 gictype = gic_class_name();
776 } else {
777 gictype = gicv3_class_name();
778 }
779
780 switch (vms->gic_version) {
781 case VIRT_GIC_VERSION_2:
782 revision = 2;
783 break;
784 case VIRT_GIC_VERSION_3:
785 revision = 3;
786 break;
787 case VIRT_GIC_VERSION_4:
788 revision = 4;
789 break;
790 default:
791 g_assert_not_reached();
792 }
793 vms->gic = qdev_new(gictype);
794 qdev_prop_set_uint32(vms->gic, "revision", revision);
795 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
796 /* Note that the num-irq property counts both internal and external
797 * interrupts; there are always 32 of the former (mandated by GIC spec).
798 */
799 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
800 if (!kvm_irqchip_in_kernel()) {
801 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
802 }
803
804 if (vms->gic_version != VIRT_GIC_VERSION_2) {
805 QList *redist_region_count;
806 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST);
807 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
808
809 nb_redist_regions = virt_gicv3_redist_region_count(vms);
810
811 redist_region_count = qlist_new();
812 qlist_append_int(redist_region_count, redist0_count);
813 if (nb_redist_regions == 2) {
814 uint32_t redist1_capacity =
815 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
816
817 qlist_append_int(redist_region_count,
818 MIN(smp_cpus - redist0_count, redist1_capacity));
819 }
820 qdev_prop_set_array(vms->gic, "redist-region-count",
821 redist_region_count);
822
823 if (!kvm_irqchip_in_kernel()) {
824 if (vms->tcg_its) {
825 object_property_set_link(OBJECT(vms->gic), "sysmem",
826 OBJECT(mem), &error_fatal);
827 qdev_prop_set_bit(vms->gic, "has-lpi", true);
828 }
829 }
830 } else {
831 if (!kvm_irqchip_in_kernel()) {
832 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
833 vms->virt);
834 }
835 }
836
837 if (gicv3_nmi_present(vms)) {
838 qdev_prop_set_bit(vms->gic, "has-nmi", true);
839 }
840
841 gicbusdev = SYS_BUS_DEVICE(vms->gic);
842 sysbus_realize_and_unref(gicbusdev, &error_fatal);
843 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
844 if (vms->gic_version != VIRT_GIC_VERSION_2) {
845 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
846 if (nb_redist_regions == 2) {
847 sysbus_mmio_map(gicbusdev, 2,
848 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
849 }
850 } else {
851 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
852 if (vms->virt) {
853 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
854 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
855 }
856 }
857
858 /* Wire the outputs from each CPU's generic timer and the GICv3
859 * maintenance interrupt signal to the appropriate GIC PPI inputs,
860 * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the
861 * CPU's inputs.
862 */
863 for (i = 0; i < smp_cpus; i++) {
864 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
865 int intidbase = NUM_IRQS + i * GIC_INTERNAL;
866 /* Mapping from the output timer irq lines from the CPU to the
867 * GIC PPI inputs we use for the virt board.
868 */
869 const int timer_irq[] = {
870 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
871 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
872 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
873 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
874 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
875 };
876
877 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
878 qdev_connect_gpio_out(cpudev, irq,
879 qdev_get_gpio_in(vms->gic,
880 intidbase + timer_irq[irq]));
881 }
882
883 if (vms->gic_version != VIRT_GIC_VERSION_2) {
884 qemu_irq irq = qdev_get_gpio_in(vms->gic,
885 intidbase + ARCH_GIC_MAINT_IRQ);
886 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
887 0, irq);
888 } else if (vms->virt) {
889 qemu_irq irq = qdev_get_gpio_in(vms->gic,
890 intidbase + ARCH_GIC_MAINT_IRQ);
891 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
892 }
893
894 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
895 qdev_get_gpio_in(vms->gic, intidbase
896 + VIRTUAL_PMU_IRQ));
897
898 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
899 sysbus_connect_irq(gicbusdev, i + smp_cpus,
900 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
901 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
902 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
903 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
904 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
905
906 if (vms->gic_version != VIRT_GIC_VERSION_2) {
907 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus,
908 qdev_get_gpio_in(cpudev, ARM_CPU_NMI));
909 sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus,
910 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI));
911 }
912 }
913
914 fdt_add_gic_node(vms);
915
916 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) {
917 create_its(vms);
918 } else if (vms->gic_version == VIRT_GIC_VERSION_2) {
919 create_v2m(vms);
920 }
921 }
922
create_uart(const VirtMachineState * vms,int uart,MemoryRegion * mem,Chardev * chr,bool secure)923 static void create_uart(const VirtMachineState *vms, int uart,
924 MemoryRegion *mem, Chardev *chr, bool secure)
925 {
926 char *nodename;
927 hwaddr base = vms->memmap[uart].base;
928 hwaddr size = vms->memmap[uart].size;
929 int irq = vms->irqmap[uart];
930 const char compat[] = "arm,pl011\0arm,primecell";
931 const char clocknames[] = "uartclk\0apb_pclk";
932 DeviceState *dev = qdev_new(TYPE_PL011);
933 SysBusDevice *s = SYS_BUS_DEVICE(dev);
934 MachineState *ms = MACHINE(vms);
935
936 qdev_prop_set_chr(dev, "chardev", chr);
937 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
938 memory_region_add_subregion(mem, base,
939 sysbus_mmio_get_region(s, 0));
940 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
941
942 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
943 qemu_fdt_add_subnode(ms->fdt, nodename);
944 /* Note that we can't use setprop_string because of the embedded NUL */
945 qemu_fdt_setprop(ms->fdt, nodename, "compatible",
946 compat, sizeof(compat));
947 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
948 2, base, 2, size);
949 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
950 GIC_FDT_IRQ_TYPE_SPI, irq,
951 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
952 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
953 vms->clock_phandle, vms->clock_phandle);
954 qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
955 clocknames, sizeof(clocknames));
956
957 if (uart == VIRT_UART0) {
958 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
959 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename);
960 } else {
961 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename);
962 }
963 if (secure) {
964 /* Mark as not usable by the normal world */
965 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
966 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
967
968 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
969 nodename);
970 }
971
972 g_free(nodename);
973 }
974
create_rtc(const VirtMachineState * vms)975 static void create_rtc(const VirtMachineState *vms)
976 {
977 char *nodename;
978 hwaddr base = vms->memmap[VIRT_RTC].base;
979 hwaddr size = vms->memmap[VIRT_RTC].size;
980 int irq = vms->irqmap[VIRT_RTC];
981 const char compat[] = "arm,pl031\0arm,primecell";
982 MachineState *ms = MACHINE(vms);
983
984 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
985
986 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
987 qemu_fdt_add_subnode(ms->fdt, nodename);
988 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
989 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
990 2, base, 2, size);
991 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
992 GIC_FDT_IRQ_TYPE_SPI, irq,
993 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
994 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
995 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
996 g_free(nodename);
997 }
998
999 static DeviceState *gpio_key_dev;
virt_powerdown_req(Notifier * n,void * opaque)1000 static void virt_powerdown_req(Notifier *n, void *opaque)
1001 {
1002 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
1003
1004 if (s->acpi_dev) {
1005 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
1006 } else {
1007 /* use gpio Pin 3 for power button event */
1008 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
1009 }
1010 }
1011
create_gpio_keys(char * fdt,DeviceState * pl061_dev,uint32_t phandle)1012 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
1013 uint32_t phandle)
1014 {
1015 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
1016 qdev_get_gpio_in(pl061_dev, 3));
1017
1018 qemu_fdt_add_subnode(fdt, "/gpio-keys");
1019 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
1020
1021 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
1022 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
1023 "label", "GPIO Key Poweroff");
1024 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
1025 KEY_POWER);
1026 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
1027 "gpios", phandle, 3, 0);
1028 }
1029
1030 #define SECURE_GPIO_POWEROFF 0
1031 #define SECURE_GPIO_RESET 1
1032
create_secure_gpio_pwr(char * fdt,DeviceState * pl061_dev,uint32_t phandle)1033 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,
1034 uint32_t phandle)
1035 {
1036 DeviceState *gpio_pwr_dev;
1037
1038 /* gpio-pwr */
1039 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
1040
1041 /* connect secure pl061 to gpio-pwr */
1042 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
1043 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
1044 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
1045 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
1046
1047 qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
1048 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
1049 "gpio-poweroff");
1050 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
1051 "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
1052 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
1053 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
1054 "okay");
1055
1056 qemu_fdt_add_subnode(fdt, "/gpio-restart");
1057 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
1058 "gpio-restart");
1059 qemu_fdt_setprop_cells(fdt, "/gpio-restart",
1060 "gpios", phandle, SECURE_GPIO_RESET, 0);
1061 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
1062 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
1063 "okay");
1064 }
1065
create_gpio_devices(const VirtMachineState * vms,int gpio,MemoryRegion * mem)1066 static void create_gpio_devices(const VirtMachineState *vms, int gpio,
1067 MemoryRegion *mem)
1068 {
1069 char *nodename;
1070 DeviceState *pl061_dev;
1071 hwaddr base = vms->memmap[gpio].base;
1072 hwaddr size = vms->memmap[gpio].size;
1073 int irq = vms->irqmap[gpio];
1074 const char compat[] = "arm,pl061\0arm,primecell";
1075 SysBusDevice *s;
1076 MachineState *ms = MACHINE(vms);
1077
1078 pl061_dev = qdev_new("pl061");
1079 /* Pull lines down to 0 if not driven by the PL061 */
1080 qdev_prop_set_uint32(pl061_dev, "pullups", 0);
1081 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
1082 s = SYS_BUS_DEVICE(pl061_dev);
1083 sysbus_realize_and_unref(s, &error_fatal);
1084 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
1085 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
1086
1087 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
1088 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
1089 qemu_fdt_add_subnode(ms->fdt, nodename);
1090 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1091 2, base, 2, size);
1092 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1093 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
1094 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
1095 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1096 GIC_FDT_IRQ_TYPE_SPI, irq,
1097 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1098 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1099 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1100 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
1101
1102 if (gpio != VIRT_GPIO) {
1103 /* Mark as not usable by the normal world */
1104 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1105 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1106 }
1107 g_free(nodename);
1108
1109 /* Child gpio devices */
1110 if (gpio == VIRT_GPIO) {
1111 create_gpio_keys(ms->fdt, pl061_dev, phandle);
1112 } else {
1113 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
1114 }
1115 }
1116
create_virtio_devices(const VirtMachineState * vms)1117 static void create_virtio_devices(const VirtMachineState *vms)
1118 {
1119 int i;
1120 hwaddr size = vms->memmap[VIRT_MMIO].size;
1121 MachineState *ms = MACHINE(vms);
1122
1123 /* We create the transports in forwards order. Since qbus_realize()
1124 * prepends (not appends) new child buses, the incrementing loop below will
1125 * create a list of virtio-mmio buses with decreasing base addresses.
1126 *
1127 * When a -device option is processed from the command line,
1128 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1129 * order. The upshot is that -device options in increasing command line
1130 * order are mapped to virtio-mmio buses with decreasing base addresses.
1131 *
1132 * When this code was originally written, that arrangement ensured that the
1133 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1134 * the first -device on the command line. (The end-to-end order is a
1135 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1136 * guest kernel's name-to-address assignment strategy.)
1137 *
1138 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1139 * the message, if not necessarily the code, of commit 70161ff336.
1140 * Therefore the loop now establishes the inverse of the original intent.
1141 *
1142 * Unfortunately, we can't counteract the kernel change by reversing the
1143 * loop; it would break existing command lines.
1144 *
1145 * In any case, the kernel makes no guarantee about the stability of
1146 * enumeration order of virtio devices (as demonstrated by it changing
1147 * between kernel versions). For reliable and stable identification
1148 * of disks users must use UUIDs or similar mechanisms.
1149 */
1150 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
1151 int irq = vms->irqmap[VIRT_MMIO] + i;
1152 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1153
1154 sysbus_create_simple("virtio-mmio", base,
1155 qdev_get_gpio_in(vms->gic, irq));
1156 }
1157
1158 /* We add dtb nodes in reverse order so that they appear in the finished
1159 * device tree lowest address first.
1160 *
1161 * Note that this mapping is independent of the loop above. The previous
1162 * loop influences virtio device to virtio transport assignment, whereas
1163 * this loop controls how virtio transports are laid out in the dtb.
1164 */
1165 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
1166 char *nodename;
1167 int irq = vms->irqmap[VIRT_MMIO] + i;
1168 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1169
1170 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
1171 qemu_fdt_add_subnode(ms->fdt, nodename);
1172 qemu_fdt_setprop_string(ms->fdt, nodename,
1173 "compatible", "virtio,mmio");
1174 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1175 2, base, 2, size);
1176 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1177 GIC_FDT_IRQ_TYPE_SPI, irq,
1178 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1179 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1180 g_free(nodename);
1181 }
1182 }
1183
1184 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1185
virt_flash_create1(VirtMachineState * vms,const char * name,const char * alias_prop_name)1186 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
1187 const char *name,
1188 const char *alias_prop_name)
1189 {
1190 /*
1191 * Create a single flash device. We use the same parameters as
1192 * the flash devices on the Versatile Express board.
1193 */
1194 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1195
1196 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1197 qdev_prop_set_uint8(dev, "width", 4);
1198 qdev_prop_set_uint8(dev, "device-width", 2);
1199 qdev_prop_set_bit(dev, "big-endian", false);
1200 qdev_prop_set_uint16(dev, "id0", 0x89);
1201 qdev_prop_set_uint16(dev, "id1", 0x18);
1202 qdev_prop_set_uint16(dev, "id2", 0x00);
1203 qdev_prop_set_uint16(dev, "id3", 0x00);
1204 qdev_prop_set_string(dev, "name", name);
1205 object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1206 object_property_add_alias(OBJECT(vms), alias_prop_name,
1207 OBJECT(dev), "drive");
1208 return PFLASH_CFI01(dev);
1209 }
1210
virt_flash_create(VirtMachineState * vms)1211 static void virt_flash_create(VirtMachineState *vms)
1212 {
1213 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1214 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1215 }
1216
virt_flash_map1(PFlashCFI01 * flash,hwaddr base,hwaddr size,MemoryRegion * sysmem)1217 static void virt_flash_map1(PFlashCFI01 *flash,
1218 hwaddr base, hwaddr size,
1219 MemoryRegion *sysmem)
1220 {
1221 DeviceState *dev = DEVICE(flash);
1222
1223 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1224 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1225 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1226 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1227
1228 memory_region_add_subregion(sysmem, base,
1229 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1230 0));
1231 }
1232
virt_flash_map(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1233 static void virt_flash_map(VirtMachineState *vms,
1234 MemoryRegion *sysmem,
1235 MemoryRegion *secure_sysmem)
1236 {
1237 /*
1238 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1239 * sysmem is the system memory space. secure_sysmem is the secure view
1240 * of the system, and the first flash device should be made visible only
1241 * there. The second flash device is visible to both secure and nonsecure.
1242 * If sysmem == secure_sysmem this means there is no separate Secure
1243 * address space and both flash devices are generally visible.
1244 */
1245 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1246 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1247
1248 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1249 secure_sysmem);
1250 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1251 sysmem);
1252 }
1253
virt_flash_fdt(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1254 static void virt_flash_fdt(VirtMachineState *vms,
1255 MemoryRegion *sysmem,
1256 MemoryRegion *secure_sysmem)
1257 {
1258 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1259 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1260 MachineState *ms = MACHINE(vms);
1261 char *nodename;
1262
1263 if (sysmem == secure_sysmem) {
1264 /* Report both flash devices as a single node in the DT */
1265 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1266 qemu_fdt_add_subnode(ms->fdt, nodename);
1267 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1268 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1269 2, flashbase, 2, flashsize,
1270 2, flashbase + flashsize, 2, flashsize);
1271 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1272 g_free(nodename);
1273 } else {
1274 /*
1275 * Report the devices as separate nodes so we can mark one as
1276 * only visible to the secure world.
1277 */
1278 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1279 qemu_fdt_add_subnode(ms->fdt, nodename);
1280 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1281 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1282 2, flashbase, 2, flashsize);
1283 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1284 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1285 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1286 g_free(nodename);
1287
1288 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize);
1289 qemu_fdt_add_subnode(ms->fdt, nodename);
1290 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1291 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1292 2, flashbase + flashsize, 2, flashsize);
1293 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1294 g_free(nodename);
1295 }
1296 }
1297
virt_firmware_init(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1298 static bool virt_firmware_init(VirtMachineState *vms,
1299 MemoryRegion *sysmem,
1300 MemoryRegion *secure_sysmem)
1301 {
1302 int i;
1303 const char *bios_name;
1304 BlockBackend *pflash_blk0;
1305
1306 /* Map legacy -drive if=pflash to machine properties */
1307 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1308 pflash_cfi01_legacy_drive(vms->flash[i],
1309 drive_get(IF_PFLASH, 0, i));
1310 }
1311
1312 virt_flash_map(vms, sysmem, secure_sysmem);
1313
1314 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1315
1316 bios_name = MACHINE(vms)->firmware;
1317 if (bios_name) {
1318 char *fname;
1319 MemoryRegion *mr;
1320 int image_size;
1321
1322 if (pflash_blk0) {
1323 error_report("The contents of the first flash device may be "
1324 "specified with -bios or with -drive if=pflash... "
1325 "but you cannot use both options at once");
1326 exit(1);
1327 }
1328
1329 /* Fall back to -bios */
1330
1331 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1332 if (!fname) {
1333 error_report("Could not find ROM image '%s'", bios_name);
1334 exit(1);
1335 }
1336 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1337 image_size = load_image_mr(fname, mr);
1338 g_free(fname);
1339 if (image_size < 0) {
1340 error_report("Could not load ROM image '%s'", bios_name);
1341 exit(1);
1342 }
1343 }
1344
1345 return pflash_blk0 || bios_name;
1346 }
1347
create_fw_cfg(const VirtMachineState * vms,AddressSpace * as)1348 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1349 {
1350 MachineState *ms = MACHINE(vms);
1351 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1352 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1353 FWCfgState *fw_cfg;
1354 char *nodename;
1355
1356 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1357 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1358
1359 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1360 qemu_fdt_add_subnode(ms->fdt, nodename);
1361 qemu_fdt_setprop_string(ms->fdt, nodename,
1362 "compatible", "qemu,fw-cfg-mmio");
1363 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1364 2, base, 2, size);
1365 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1366 g_free(nodename);
1367 return fw_cfg;
1368 }
1369
create_pcie_irq_map(const MachineState * ms,uint32_t gic_phandle,int first_irq,const char * nodename)1370 static void create_pcie_irq_map(const MachineState *ms,
1371 uint32_t gic_phandle,
1372 int first_irq, const char *nodename)
1373 {
1374 int devfn, pin;
1375 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1376 uint32_t *irq_map = full_irq_map;
1377
1378 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1379 for (pin = 0; pin < 4; pin++) {
1380 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1381 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1382 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1383 int i;
1384
1385 uint32_t map[] = {
1386 devfn << 8, 0, 0, /* devfn */
1387 pin + 1, /* PCI pin */
1388 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1389
1390 /* Convert map to big endian */
1391 for (i = 0; i < 10; i++) {
1392 irq_map[i] = cpu_to_be32(map[i]);
1393 }
1394 irq_map += 10;
1395 }
1396 }
1397
1398 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1399 full_irq_map, sizeof(full_irq_map));
1400
1401 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1402 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1403 0, 0,
1404 0x7 /* PCI irq */);
1405 }
1406
create_smmu(const VirtMachineState * vms,PCIBus * bus)1407 static void create_smmu(const VirtMachineState *vms,
1408 PCIBus *bus)
1409 {
1410 char *node;
1411 const char compat[] = "arm,smmu-v3";
1412 int irq = vms->irqmap[VIRT_SMMU];
1413 int i;
1414 hwaddr base = vms->memmap[VIRT_SMMU].base;
1415 hwaddr size = vms->memmap[VIRT_SMMU].size;
1416 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1417 DeviceState *dev;
1418 MachineState *ms = MACHINE(vms);
1419
1420 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1421 return;
1422 }
1423
1424 dev = qdev_new(TYPE_ARM_SMMUV3);
1425
1426 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1427 &error_abort);
1428 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1429 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1430 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1431 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1432 qdev_get_gpio_in(vms->gic, irq + i));
1433 }
1434
1435 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1436 qemu_fdt_add_subnode(ms->fdt, node);
1437 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1438 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1439
1440 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1441 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1442 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1443 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1444 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1445
1446 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1447 sizeof(irq_names));
1448
1449 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1450
1451 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1452
1453 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1454 g_free(node);
1455 }
1456
create_virtio_iommu_dt_bindings(VirtMachineState * vms)1457 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1458 {
1459 const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
1460 uint16_t bdf = vms->virtio_iommu_bdf;
1461 MachineState *ms = MACHINE(vms);
1462 char *node;
1463
1464 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1465
1466 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename,
1467 PCI_SLOT(bdf), PCI_FUNC(bdf));
1468 qemu_fdt_add_subnode(ms->fdt, node);
1469 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1470 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1471 1, bdf << 8, 1, 0, 1, 0,
1472 1, 0, 1, 0);
1473
1474 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1475 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1476 g_free(node);
1477
1478 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1479 0x0, vms->iommu_phandle, 0x0, bdf,
1480 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1481 }
1482
create_pcie(VirtMachineState * vms)1483 static void create_pcie(VirtMachineState *vms)
1484 {
1485 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1486 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1487 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1488 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1489 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1490 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1491 hwaddr base_ecam, size_ecam;
1492 hwaddr base = base_mmio;
1493 int nr_pcie_buses;
1494 int irq = vms->irqmap[VIRT_PCIE];
1495 MemoryRegion *mmio_alias;
1496 MemoryRegion *mmio_reg;
1497 MemoryRegion *ecam_alias;
1498 MemoryRegion *ecam_reg;
1499 DeviceState *dev;
1500 char *nodename;
1501 int i, ecam_id;
1502 PCIHostState *pci;
1503 MachineState *ms = MACHINE(vms);
1504 MachineClass *mc = MACHINE_GET_CLASS(ms);
1505
1506 dev = qdev_new(TYPE_GPEX_HOST);
1507 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1508
1509 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1510 base_ecam = vms->memmap[ecam_id].base;
1511 size_ecam = vms->memmap[ecam_id].size;
1512 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1513 /* Map only the first size_ecam bytes of ECAM space */
1514 ecam_alias = g_new0(MemoryRegion, 1);
1515 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1516 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1517 ecam_reg, 0, size_ecam);
1518 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1519
1520 /* Map the MMIO window into system address space so as to expose
1521 * the section of PCI MMIO space which starts at the same base address
1522 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1523 * the window).
1524 */
1525 mmio_alias = g_new0(MemoryRegion, 1);
1526 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1527 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1528 mmio_reg, base_mmio, size_mmio);
1529 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1530
1531 if (vms->highmem_mmio) {
1532 /* Map high MMIO space */
1533 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1534
1535 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1536 mmio_reg, base_mmio_high, size_mmio_high);
1537 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1538 high_mmio_alias);
1539 }
1540
1541 /* Map IO port space */
1542 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1543
1544 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1545 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1546 qdev_get_gpio_in(vms->gic, irq + i));
1547 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1548 }
1549
1550 pci = PCI_HOST_BRIDGE(dev);
1551 pci->bypass_iommu = vms->default_bus_bypass_iommu;
1552 vms->bus = pci->bus;
1553 if (vms->bus) {
1554 pci_init_nic_devices(pci->bus, mc->default_nic);
1555 }
1556
1557 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1558 qemu_fdt_add_subnode(ms->fdt, nodename);
1559 qemu_fdt_setprop_string(ms->fdt, nodename,
1560 "compatible", "pci-host-ecam-generic");
1561 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1562 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1563 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1564 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1565 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1566 nr_pcie_buses - 1);
1567 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1568
1569 if (vms->msi_phandle) {
1570 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
1571 0, vms->msi_phandle, 0, 0x10000);
1572 }
1573
1574 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1575 2, base_ecam, 2, size_ecam);
1576
1577 if (vms->highmem_mmio) {
1578 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1579 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1580 2, base_pio, 2, size_pio,
1581 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1582 2, base_mmio, 2, size_mmio,
1583 1, FDT_PCI_RANGE_MMIO_64BIT,
1584 2, base_mmio_high,
1585 2, base_mmio_high, 2, size_mmio_high);
1586 } else {
1587 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1588 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1589 2, base_pio, 2, size_pio,
1590 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1591 2, base_mmio, 2, size_mmio);
1592 }
1593
1594 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1595 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1596
1597 if (vms->iommu) {
1598 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1599
1600 switch (vms->iommu) {
1601 case VIRT_IOMMU_SMMUV3:
1602 create_smmu(vms, vms->bus);
1603 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1604 0x0, vms->iommu_phandle, 0x0, 0x10000);
1605 break;
1606 default:
1607 g_assert_not_reached();
1608 }
1609 }
1610 }
1611
create_platform_bus(VirtMachineState * vms)1612 static void create_platform_bus(VirtMachineState *vms)
1613 {
1614 DeviceState *dev;
1615 SysBusDevice *s;
1616 int i;
1617 MemoryRegion *sysmem = get_system_memory();
1618
1619 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1620 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1621 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1622 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1623 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1624 vms->platform_bus_dev = dev;
1625
1626 s = SYS_BUS_DEVICE(dev);
1627 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1628 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1629 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1630 }
1631
1632 memory_region_add_subregion(sysmem,
1633 vms->memmap[VIRT_PLATFORM_BUS].base,
1634 sysbus_mmio_get_region(s, 0));
1635 }
1636
create_tag_ram(MemoryRegion * tag_sysmem,hwaddr base,hwaddr size,const char * name)1637 static void create_tag_ram(MemoryRegion *tag_sysmem,
1638 hwaddr base, hwaddr size,
1639 const char *name)
1640 {
1641 MemoryRegion *tagram = g_new(MemoryRegion, 1);
1642
1643 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1644 memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1645 }
1646
create_secure_ram(VirtMachineState * vms,MemoryRegion * secure_sysmem,MemoryRegion * secure_tag_sysmem)1647 static void create_secure_ram(VirtMachineState *vms,
1648 MemoryRegion *secure_sysmem,
1649 MemoryRegion *secure_tag_sysmem)
1650 {
1651 MemoryRegion *secram = g_new(MemoryRegion, 1);
1652 char *nodename;
1653 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1654 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1655 MachineState *ms = MACHINE(vms);
1656
1657 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1658 &error_fatal);
1659 memory_region_add_subregion(secure_sysmem, base, secram);
1660
1661 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1662 qemu_fdt_add_subnode(ms->fdt, nodename);
1663 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1664 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1665 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1666 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1667
1668 if (secure_tag_sysmem) {
1669 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1670 }
1671
1672 g_free(nodename);
1673 }
1674
machvirt_dtb(const struct arm_boot_info * binfo,int * fdt_size)1675 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1676 {
1677 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1678 bootinfo);
1679 MachineState *ms = MACHINE(board);
1680
1681
1682 *fdt_size = board->fdt_size;
1683 return ms->fdt;
1684 }
1685
virt_build_smbios(VirtMachineState * vms)1686 static void virt_build_smbios(VirtMachineState *vms)
1687 {
1688 MachineClass *mc = MACHINE_GET_CLASS(vms);
1689 MachineState *ms = MACHINE(vms);
1690 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1691 uint8_t *smbios_tables, *smbios_anchor;
1692 size_t smbios_tables_len, smbios_anchor_len;
1693 struct smbios_phys_mem_area mem_array;
1694 const char *product = "QEMU Virtual Machine";
1695
1696 if (kvm_enabled()) {
1697 product = "KVM Virtual Machine";
1698 }
1699
1700 smbios_set_defaults("QEMU", product,
1701 vmc->smbios_old_sys_ver ? "1.0" : mc->name);
1702
1703 /* build the array of physical mem area from base_memmap */
1704 mem_array.address = vms->memmap[VIRT_MEM].base;
1705 mem_array.length = ms->ram_size;
1706
1707 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, &mem_array, 1,
1708 &smbios_tables, &smbios_tables_len,
1709 &smbios_anchor, &smbios_anchor_len,
1710 &error_fatal);
1711
1712 if (smbios_anchor) {
1713 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1714 smbios_tables, smbios_tables_len);
1715 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1716 smbios_anchor, smbios_anchor_len);
1717 }
1718 }
1719
1720 static
virt_machine_done(Notifier * notifier,void * data)1721 void virt_machine_done(Notifier *notifier, void *data)
1722 {
1723 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1724 machine_done);
1725 MachineState *ms = MACHINE(vms);
1726 ARMCPU *cpu = ARM_CPU(first_cpu);
1727 struct arm_boot_info *info = &vms->bootinfo;
1728 AddressSpace *as = arm_boot_address_space(cpu, info);
1729
1730 /*
1731 * If the user provided a dtb, we assume the dynamic sysbus nodes
1732 * already are integrated there. This corresponds to a use case where
1733 * the dynamic sysbus nodes are complex and their generation is not yet
1734 * supported. In that case the user can take charge of the guest dt
1735 * while qemu takes charge of the qom stuff.
1736 */
1737 if (info->dtb_filename == NULL) {
1738 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1739 vms->memmap[VIRT_PLATFORM_BUS].base,
1740 vms->memmap[VIRT_PLATFORM_BUS].size,
1741 vms->irqmap[VIRT_PLATFORM_BUS]);
1742 }
1743 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1744 exit(1);
1745 }
1746
1747 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg);
1748
1749 virt_acpi_setup(vms);
1750 virt_build_smbios(vms);
1751 }
1752
virt_cpu_mp_affinity(VirtMachineState * vms,int idx)1753 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1754 {
1755 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1756 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1757
1758 if (!vmc->disallow_affinity_adjustment) {
1759 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1760 * GIC's target-list limitations. 32-bit KVM hosts currently
1761 * always create clusters of 4 CPUs, but that is expected to
1762 * change when they gain support for gicv3. When KVM is enabled
1763 * it will override the changes we make here, therefore our
1764 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1765 * and to improve SGI efficiency.
1766 */
1767 if (vms->gic_version == VIRT_GIC_VERSION_2) {
1768 clustersz = GIC_TARGETLIST_BITS;
1769 } else {
1770 clustersz = GICV3_TARGETLIST_BITS;
1771 }
1772 }
1773 return arm_build_mp_affinity(idx, clustersz);
1774 }
1775
virt_get_high_memmap_enabled(VirtMachineState * vms,int index)1776 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
1777 int index)
1778 {
1779 bool *enabled_array[] = {
1780 &vms->highmem_redists,
1781 &vms->highmem_ecam,
1782 &vms->highmem_mmio,
1783 };
1784
1785 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
1786 ARRAY_SIZE(enabled_array));
1787 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
1788
1789 return enabled_array[index - VIRT_LOWMEMMAP_LAST];
1790 }
1791
virt_set_high_memmap(VirtMachineState * vms,hwaddr base,int pa_bits)1792 static void virt_set_high_memmap(VirtMachineState *vms,
1793 hwaddr base, int pa_bits)
1794 {
1795 hwaddr region_base, region_size;
1796 bool *region_enabled, fits;
1797 int i;
1798
1799 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1800 region_enabled = virt_get_high_memmap_enabled(vms, i);
1801 region_base = ROUND_UP(base, extended_memmap[i].size);
1802 region_size = extended_memmap[i].size;
1803
1804 vms->memmap[i].base = region_base;
1805 vms->memmap[i].size = region_size;
1806
1807 /*
1808 * Check each device to see if it fits in the PA space,
1809 * moving highest_gpa as we go. For compatibility, move
1810 * highest_gpa for disabled fitting devices as well, if
1811 * the compact layout has been disabled.
1812 *
1813 * For each device that doesn't fit, disable it.
1814 */
1815 fits = (region_base + region_size) <= BIT_ULL(pa_bits);
1816 *region_enabled &= fits;
1817 if (vms->highmem_compact && !*region_enabled) {
1818 continue;
1819 }
1820
1821 base = region_base + region_size;
1822 if (fits) {
1823 vms->highest_gpa = base - 1;
1824 }
1825 }
1826 }
1827
virt_set_memmap(VirtMachineState * vms,int pa_bits)1828 static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
1829 {
1830 MachineState *ms = MACHINE(vms);
1831 hwaddr base, device_memory_base, device_memory_size, memtop;
1832 int i;
1833
1834 vms->memmap = extended_memmap;
1835
1836 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1837 vms->memmap[i] = base_memmap[i];
1838 }
1839
1840 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1841 error_report("unsupported number of memory slots: %"PRIu64,
1842 ms->ram_slots);
1843 exit(EXIT_FAILURE);
1844 }
1845
1846 /*
1847 * !highmem is exactly the same as limiting the PA space to 32bit,
1848 * irrespective of the underlying capabilities of the HW.
1849 */
1850 if (!vms->highmem) {
1851 pa_bits = 32;
1852 }
1853
1854 /*
1855 * We compute the base of the high IO region depending on the
1856 * amount of initial and device memory. The device memory start/size
1857 * is aligned on 1GiB. We never put the high IO region below 256GiB
1858 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1859 * The device region size assumes 1GiB page max alignment per slot.
1860 */
1861 device_memory_base =
1862 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1863 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1864
1865 /* Base address of the high IO region */
1866 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1867 if (memtop > BIT_ULL(pa_bits)) {
1868 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes",
1869 pa_bits, memtop - BIT_ULL(pa_bits));
1870 exit(EXIT_FAILURE);
1871 }
1872 if (base < device_memory_base) {
1873 error_report("maxmem/slots too huge");
1874 exit(EXIT_FAILURE);
1875 }
1876 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1877 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1878 }
1879
1880 /* We know for sure that at least the memory fits in the PA space */
1881 vms->highest_gpa = memtop - 1;
1882
1883 virt_set_high_memmap(vms, base, pa_bits);
1884
1885 if (device_memory_size > 0) {
1886 machine_memory_devices_init(ms, device_memory_base, device_memory_size);
1887 }
1888 }
1889
finalize_gic_version_do(const char * accel_name,VirtGICType gic_version,int gics_supported,unsigned int max_cpus)1890 static VirtGICType finalize_gic_version_do(const char *accel_name,
1891 VirtGICType gic_version,
1892 int gics_supported,
1893 unsigned int max_cpus)
1894 {
1895 /* Convert host/max/nosel to GIC version number */
1896 switch (gic_version) {
1897 case VIRT_GIC_VERSION_HOST:
1898 if (!kvm_enabled()) {
1899 error_report("gic-version=host requires KVM");
1900 exit(1);
1901 }
1902
1903 /* For KVM, gic-version=host means gic-version=max */
1904 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
1905 gics_supported, max_cpus);
1906 case VIRT_GIC_VERSION_MAX:
1907 if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
1908 gic_version = VIRT_GIC_VERSION_4;
1909 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1910 gic_version = VIRT_GIC_VERSION_3;
1911 } else {
1912 gic_version = VIRT_GIC_VERSION_2;
1913 }
1914 break;
1915 case VIRT_GIC_VERSION_NOSEL:
1916 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
1917 max_cpus <= GIC_NCPU) {
1918 gic_version = VIRT_GIC_VERSION_2;
1919 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1920 /*
1921 * in case the host does not support v2 emulation or
1922 * the end-user requested more than 8 VCPUs we now default
1923 * to v3. In any case defaulting to v2 would be broken.
1924 */
1925 gic_version = VIRT_GIC_VERSION_3;
1926 } else if (max_cpus > GIC_NCPU) {
1927 error_report("%s only supports GICv2 emulation but more than 8 "
1928 "vcpus are requested", accel_name);
1929 exit(1);
1930 }
1931 break;
1932 case VIRT_GIC_VERSION_2:
1933 case VIRT_GIC_VERSION_3:
1934 case VIRT_GIC_VERSION_4:
1935 break;
1936 }
1937
1938 /* Check chosen version is effectively supported */
1939 switch (gic_version) {
1940 case VIRT_GIC_VERSION_2:
1941 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
1942 error_report("%s does not support GICv2 emulation", accel_name);
1943 exit(1);
1944 }
1945 break;
1946 case VIRT_GIC_VERSION_3:
1947 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
1948 error_report("%s does not support GICv3 emulation", accel_name);
1949 exit(1);
1950 }
1951 break;
1952 case VIRT_GIC_VERSION_4:
1953 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
1954 error_report("%s does not support GICv4 emulation, is virtualization=on?",
1955 accel_name);
1956 exit(1);
1957 }
1958 break;
1959 default:
1960 error_report("logic error in finalize_gic_version");
1961 exit(1);
1962 break;
1963 }
1964
1965 return gic_version;
1966 }
1967
1968 /*
1969 * finalize_gic_version - Determines the final gic_version
1970 * according to the gic-version property
1971 *
1972 * Default GIC type is v2
1973 */
finalize_gic_version(VirtMachineState * vms)1974 static void finalize_gic_version(VirtMachineState *vms)
1975 {
1976 const char *accel_name = current_accel_name();
1977 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1978 int gics_supported = 0;
1979
1980 /* Determine which GIC versions the current environment supports */
1981 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1982 int probe_bitmap = kvm_arm_vgic_probe();
1983
1984 if (!probe_bitmap) {
1985 error_report("Unable to determine GIC version supported by host");
1986 exit(1);
1987 }
1988
1989 if (probe_bitmap & KVM_ARM_VGIC_V2) {
1990 gics_supported |= VIRT_GIC_VERSION_2_MASK;
1991 }
1992 if (probe_bitmap & KVM_ARM_VGIC_V3) {
1993 gics_supported |= VIRT_GIC_VERSION_3_MASK;
1994 }
1995 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
1996 /* KVM w/o kernel irqchip can only deal with GICv2 */
1997 gics_supported |= VIRT_GIC_VERSION_2_MASK;
1998 accel_name = "KVM with kernel-irqchip=off";
1999 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
2000 gics_supported |= VIRT_GIC_VERSION_2_MASK;
2001 if (module_object_class_by_name("arm-gicv3")) {
2002 gics_supported |= VIRT_GIC_VERSION_3_MASK;
2003 if (vms->virt) {
2004 /* GICv4 only makes sense if CPU has EL2 */
2005 gics_supported |= VIRT_GIC_VERSION_4_MASK;
2006 }
2007 }
2008 } else {
2009 error_report("Unsupported accelerator, can not determine GIC support");
2010 exit(1);
2011 }
2012
2013 /*
2014 * Then convert helpers like host/max to concrete GIC versions and ensure
2015 * the desired version is supported
2016 */
2017 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
2018 gics_supported, max_cpus);
2019 }
2020
2021 /*
2022 * virt_cpu_post_init() must be called after the CPUs have
2023 * been realized and the GIC has been created.
2024 */
virt_cpu_post_init(VirtMachineState * vms,MemoryRegion * sysmem)2025 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
2026 {
2027 int max_cpus = MACHINE(vms)->smp.max_cpus;
2028 bool aarch64, pmu, steal_time;
2029 CPUState *cpu;
2030
2031 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
2032 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
2033 steal_time = object_property_get_bool(OBJECT(first_cpu),
2034 "kvm-steal-time", NULL);
2035
2036 if (kvm_enabled()) {
2037 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
2038 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
2039
2040 if (steal_time) {
2041 MemoryRegion *pvtime = g_new(MemoryRegion, 1);
2042 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
2043
2044 /* The memory region size must be a multiple of host page size. */
2045 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
2046
2047 if (pvtime_size > pvtime_reg_size) {
2048 error_report("pvtime requires a %" HWADDR_PRId
2049 " byte memory region for %d CPUs,"
2050 " but only %" HWADDR_PRId " has been reserved",
2051 pvtime_size, max_cpus, pvtime_reg_size);
2052 exit(1);
2053 }
2054
2055 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
2056 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
2057 }
2058
2059 CPU_FOREACH(cpu) {
2060 if (pmu) {
2061 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
2062 if (kvm_irqchip_in_kernel()) {
2063 kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ);
2064 }
2065 kvm_arm_pmu_init(ARM_CPU(cpu));
2066 }
2067 if (steal_time) {
2068 kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base
2069 + cpu->cpu_index
2070 * PVTIME_SIZE_PER_CPU);
2071 }
2072 }
2073 } else {
2074 if (aarch64 && vms->highmem) {
2075 int requested_pa_size = 64 - clz64(vms->highest_gpa);
2076 int pamax = arm_pamax(ARM_CPU(first_cpu));
2077
2078 if (pamax < requested_pa_size) {
2079 error_report("VCPU supports less PA bits (%d) than "
2080 "requested by the memory map (%d)",
2081 pamax, requested_pa_size);
2082 exit(1);
2083 }
2084 }
2085 }
2086 }
2087
machvirt_init(MachineState * machine)2088 static void machvirt_init(MachineState *machine)
2089 {
2090 VirtMachineState *vms = VIRT_MACHINE(machine);
2091 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
2092 MachineClass *mc = MACHINE_GET_CLASS(machine);
2093 const CPUArchIdList *possible_cpus;
2094 MemoryRegion *sysmem = get_system_memory();
2095 MemoryRegion *secure_sysmem = NULL;
2096 MemoryRegion *tag_sysmem = NULL;
2097 MemoryRegion *secure_tag_sysmem = NULL;
2098 int n, virt_max_cpus;
2099 bool firmware_loaded;
2100 bool aarch64 = true;
2101 bool has_ged = !vmc->no_ged;
2102 unsigned int smp_cpus = machine->smp.cpus;
2103 unsigned int max_cpus = machine->smp.max_cpus;
2104
2105 possible_cpus = mc->possible_cpu_arch_ids(machine);
2106
2107 /*
2108 * In accelerated mode, the memory map is computed earlier in kvm_type()
2109 * to create a VM with the right number of IPA bits.
2110 */
2111 if (!vms->memmap) {
2112 Object *cpuobj;
2113 ARMCPU *armcpu;
2114 int pa_bits;
2115
2116 /*
2117 * Instantiate a temporary CPU object to find out about what
2118 * we are about to deal with. Once this is done, get rid of
2119 * the object.
2120 */
2121 cpuobj = object_new(possible_cpus->cpus[0].type);
2122 armcpu = ARM_CPU(cpuobj);
2123
2124 pa_bits = arm_pamax(armcpu);
2125
2126 object_unref(cpuobj);
2127
2128 virt_set_memmap(vms, pa_bits);
2129 }
2130
2131 /* We can probe only here because during property set
2132 * KVM is not available yet
2133 */
2134 finalize_gic_version(vms);
2135
2136 if (vms->secure) {
2137 /*
2138 * The Secure view of the world is the same as the NonSecure,
2139 * but with a few extra devices. Create it as a container region
2140 * containing the system memory at low priority; any secure-only
2141 * devices go in at higher priority and take precedence.
2142 */
2143 secure_sysmem = g_new(MemoryRegion, 1);
2144 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
2145 UINT64_MAX);
2146 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
2147 }
2148
2149 firmware_loaded = virt_firmware_init(vms, sysmem,
2150 secure_sysmem ?: sysmem);
2151
2152 /* If we have an EL3 boot ROM then the assumption is that it will
2153 * implement PSCI itself, so disable QEMU's internal implementation
2154 * so it doesn't get in the way. Instead of starting secondary
2155 * CPUs in PSCI powerdown state we will start them all running and
2156 * let the boot ROM sort them out.
2157 * The usual case is that we do use QEMU's PSCI implementation;
2158 * if the guest has EL2 then we will use SMC as the conduit,
2159 * and otherwise we will use HVC (for backwards compatibility and
2160 * because if we're using KVM then we must use HVC).
2161 */
2162 if (vms->secure && firmware_loaded) {
2163 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
2164 } else if (vms->virt) {
2165 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
2166 } else {
2167 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
2168 }
2169
2170 /*
2171 * The maximum number of CPUs depends on the GIC version, or on how
2172 * many redistributors we can fit into the memory map (which in turn
2173 * depends on whether this is a GICv3 or v4).
2174 */
2175 if (vms->gic_version == VIRT_GIC_VERSION_2) {
2176 virt_max_cpus = GIC_NCPU;
2177 } else {
2178 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);
2179 if (vms->highmem_redists) {
2180 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
2181 }
2182 }
2183
2184 if (max_cpus > virt_max_cpus) {
2185 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2186 "supported by machine 'mach-virt' (%d)",
2187 max_cpus, virt_max_cpus);
2188 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
2189 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2190 }
2191
2192 exit(1);
2193 }
2194
2195 if (vms->secure && (kvm_enabled() || hvf_enabled())) {
2196 error_report("mach-virt: %s does not support providing "
2197 "Security extensions (TrustZone) to the guest CPU",
2198 current_accel_name());
2199 exit(1);
2200 }
2201
2202 if (vms->virt && (kvm_enabled() || hvf_enabled())) {
2203 error_report("mach-virt: %s does not support providing "
2204 "Virtualization extensions to the guest CPU",
2205 current_accel_name());
2206 exit(1);
2207 }
2208
2209 if (vms->mte && (kvm_enabled() || hvf_enabled())) {
2210 error_report("mach-virt: %s does not support providing "
2211 "MTE to the guest CPU",
2212 current_accel_name());
2213 exit(1);
2214 }
2215
2216 create_fdt(vms);
2217
2218 assert(possible_cpus->len == max_cpus);
2219 for (n = 0; n < possible_cpus->len; n++) {
2220 Object *cpuobj;
2221 CPUState *cs;
2222
2223 if (n >= smp_cpus) {
2224 break;
2225 }
2226
2227 cpuobj = object_new(possible_cpus->cpus[n].type);
2228 object_property_set_int(cpuobj, "mp-affinity",
2229 possible_cpus->cpus[n].arch_id, NULL);
2230
2231 cs = CPU(cpuobj);
2232 cs->cpu_index = n;
2233
2234 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
2235 &error_fatal);
2236
2237 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
2238
2239 if (!vms->secure) {
2240 object_property_set_bool(cpuobj, "has_el3", false, NULL);
2241 }
2242
2243 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
2244 object_property_set_bool(cpuobj, "has_el2", false, NULL);
2245 }
2246
2247 if (vmc->kvm_no_adjvtime &&
2248 object_property_find(cpuobj, "kvm-no-adjvtime")) {
2249 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
2250 }
2251
2252 if (vmc->no_kvm_steal_time &&
2253 object_property_find(cpuobj, "kvm-steal-time")) {
2254 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
2255 }
2256
2257 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
2258 object_property_set_bool(cpuobj, "pmu", false, NULL);
2259 }
2260
2261 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {
2262 object_property_set_bool(cpuobj, "lpa2", false, NULL);
2263 }
2264
2265 if (object_property_find(cpuobj, "reset-cbar")) {
2266 object_property_set_int(cpuobj, "reset-cbar",
2267 vms->memmap[VIRT_CPUPERIPHS].base,
2268 &error_abort);
2269 }
2270
2271 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
2272 &error_abort);
2273 if (vms->secure) {
2274 object_property_set_link(cpuobj, "secure-memory",
2275 OBJECT(secure_sysmem), &error_abort);
2276 }
2277
2278 if (vms->mte) {
2279 /* Create the memory region only once, but link to all cpus. */
2280 if (!tag_sysmem) {
2281 /*
2282 * The property exists only if MemTag is supported.
2283 * If it is, we must allocate the ram to back that up.
2284 */
2285 if (!object_property_find(cpuobj, "tag-memory")) {
2286 error_report("MTE requested, but not supported "
2287 "by the guest CPU");
2288 exit(1);
2289 }
2290
2291 tag_sysmem = g_new(MemoryRegion, 1);
2292 memory_region_init(tag_sysmem, OBJECT(machine),
2293 "tag-memory", UINT64_MAX / 32);
2294
2295 if (vms->secure) {
2296 secure_tag_sysmem = g_new(MemoryRegion, 1);
2297 memory_region_init(secure_tag_sysmem, OBJECT(machine),
2298 "secure-tag-memory", UINT64_MAX / 32);
2299
2300 /* As with ram, secure-tag takes precedence over tag. */
2301 memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
2302 tag_sysmem, -1);
2303 }
2304 }
2305
2306 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem),
2307 &error_abort);
2308 if (vms->secure) {
2309 object_property_set_link(cpuobj, "secure-tag-memory",
2310 OBJECT(secure_tag_sysmem),
2311 &error_abort);
2312 }
2313 }
2314
2315 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
2316 object_unref(cpuobj);
2317 }
2318
2319 /* Now we've created the CPUs we can see if they have the hypvirt timer */
2320 vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
2321 !vmc->no_ns_el2_virt_timer_irq;
2322
2323 fdt_add_timer_nodes(vms);
2324 fdt_add_cpu_nodes(vms);
2325
2326 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2327 machine->ram);
2328
2329 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
2330
2331 create_gic(vms, sysmem);
2332
2333 virt_cpu_post_init(vms, sysmem);
2334
2335 fdt_add_pmu_nodes(vms);
2336
2337 /*
2338 * The first UART always exists. If the security extensions are
2339 * enabled, the second UART also always exists. Otherwise, it only exists
2340 * if a backend is configured explicitly via '-serial <backend>'.
2341 * This avoids potentially breaking existing user setups that expect
2342 * only one NonSecure UART to be present (for instance, older EDK2
2343 * binaries).
2344 *
2345 * The nodes end up in the DTB in reverse order of creation, so we must
2346 * create UART0 last to ensure it appears as the first node in the DTB,
2347 * for compatibility with guest software that just iterates through the
2348 * DTB to find the first UART, as older versions of EDK2 do.
2349 * DTB readers that follow the spec, as Linux does, should honour the
2350 * aliases node information and /chosen/stdout-path regardless of
2351 * the order that nodes appear in the DTB.
2352 *
2353 * For similar back-compatibility reasons, if UART1 is the secure UART
2354 * we create it second (and so it appears first in the DTB), because
2355 * that's what QEMU has always done.
2356 */
2357 if (!vms->secure) {
2358 Chardev *serial1 = serial_hd(1);
2359
2360 if (serial1) {
2361 vms->second_ns_uart_present = true;
2362 create_uart(vms, VIRT_UART1, sysmem, serial1, false);
2363 }
2364 }
2365 create_uart(vms, VIRT_UART0, sysmem, serial_hd(0), false);
2366 if (vms->secure) {
2367 create_uart(vms, VIRT_UART1, secure_sysmem, serial_hd(1), true);
2368 }
2369
2370 if (vms->secure) {
2371 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
2372 }
2373
2374 if (tag_sysmem) {
2375 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2376 machine->ram_size, "mach-virt.tag");
2377 }
2378
2379 vms->highmem_ecam &= (!firmware_loaded || aarch64);
2380
2381 create_rtc(vms);
2382
2383 create_pcie(vms);
2384
2385 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2386 vms->acpi_dev = create_acpi_ged(vms);
2387 } else {
2388 create_gpio_devices(vms, VIRT_GPIO, sysmem);
2389 }
2390
2391 if (vms->secure && !vmc->no_secure_gpio) {
2392 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
2393 }
2394
2395 /* connect powerdown request */
2396 vms->powerdown_notifier.notify = virt_powerdown_req;
2397 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2398
2399 /* Create mmio transports, so the user can create virtio backends
2400 * (which will be automatically plugged in to the transports). If
2401 * no backend is created the transport will just sit harmlessly idle.
2402 */
2403 create_virtio_devices(vms);
2404
2405 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2406 rom_set_fw(vms->fw_cfg);
2407
2408 create_platform_bus(vms);
2409
2410 if (machine->nvdimms_state->is_enabled) {
2411 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2412 .space_id = AML_AS_SYSTEM_MEMORY,
2413 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2414 .bit_width = NVDIMM_ACPI_IO_LEN << 3
2415 };
2416
2417 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2418 arm_virt_nvdimm_acpi_dsmio,
2419 vms->fw_cfg, OBJECT(vms));
2420 }
2421
2422 vms->bootinfo.ram_size = machine->ram_size;
2423 vms->bootinfo.board_id = -1;
2424 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2425 vms->bootinfo.get_dtb = machvirt_dtb;
2426 vms->bootinfo.skip_dtb_autoload = true;
2427 vms->bootinfo.firmware_loaded = firmware_loaded;
2428 vms->bootinfo.psci_conduit = vms->psci_conduit;
2429 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2430
2431 vms->machine_done.notify = virt_machine_done;
2432 qemu_add_machine_init_done_notifier(&vms->machine_done);
2433 }
2434
virt_get_secure(Object * obj,Error ** errp)2435 static bool virt_get_secure(Object *obj, Error **errp)
2436 {
2437 VirtMachineState *vms = VIRT_MACHINE(obj);
2438
2439 return vms->secure;
2440 }
2441
virt_set_secure(Object * obj,bool value,Error ** errp)2442 static void virt_set_secure(Object *obj, bool value, Error **errp)
2443 {
2444 VirtMachineState *vms = VIRT_MACHINE(obj);
2445
2446 vms->secure = value;
2447 }
2448
virt_get_virt(Object * obj,Error ** errp)2449 static bool virt_get_virt(Object *obj, Error **errp)
2450 {
2451 VirtMachineState *vms = VIRT_MACHINE(obj);
2452
2453 return vms->virt;
2454 }
2455
virt_set_virt(Object * obj,bool value,Error ** errp)2456 static void virt_set_virt(Object *obj, bool value, Error **errp)
2457 {
2458 VirtMachineState *vms = VIRT_MACHINE(obj);
2459
2460 vms->virt = value;
2461 }
2462
virt_get_highmem(Object * obj,Error ** errp)2463 static bool virt_get_highmem(Object *obj, Error **errp)
2464 {
2465 VirtMachineState *vms = VIRT_MACHINE(obj);
2466
2467 return vms->highmem;
2468 }
2469
virt_set_highmem(Object * obj,bool value,Error ** errp)2470 static void virt_set_highmem(Object *obj, bool value, Error **errp)
2471 {
2472 VirtMachineState *vms = VIRT_MACHINE(obj);
2473
2474 vms->highmem = value;
2475 }
2476
virt_get_compact_highmem(Object * obj,Error ** errp)2477 static bool virt_get_compact_highmem(Object *obj, Error **errp)
2478 {
2479 VirtMachineState *vms = VIRT_MACHINE(obj);
2480
2481 return vms->highmem_compact;
2482 }
2483
virt_set_compact_highmem(Object * obj,bool value,Error ** errp)2484 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
2485 {
2486 VirtMachineState *vms = VIRT_MACHINE(obj);
2487
2488 vms->highmem_compact = value;
2489 }
2490
virt_get_highmem_redists(Object * obj,Error ** errp)2491 static bool virt_get_highmem_redists(Object *obj, Error **errp)
2492 {
2493 VirtMachineState *vms = VIRT_MACHINE(obj);
2494
2495 return vms->highmem_redists;
2496 }
2497
virt_set_highmem_redists(Object * obj,bool value,Error ** errp)2498 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp)
2499 {
2500 VirtMachineState *vms = VIRT_MACHINE(obj);
2501
2502 vms->highmem_redists = value;
2503 }
2504
virt_get_highmem_ecam(Object * obj,Error ** errp)2505 static bool virt_get_highmem_ecam(Object *obj, Error **errp)
2506 {
2507 VirtMachineState *vms = VIRT_MACHINE(obj);
2508
2509 return vms->highmem_ecam;
2510 }
2511
virt_set_highmem_ecam(Object * obj,bool value,Error ** errp)2512 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp)
2513 {
2514 VirtMachineState *vms = VIRT_MACHINE(obj);
2515
2516 vms->highmem_ecam = value;
2517 }
2518
virt_get_highmem_mmio(Object * obj,Error ** errp)2519 static bool virt_get_highmem_mmio(Object *obj, Error **errp)
2520 {
2521 VirtMachineState *vms = VIRT_MACHINE(obj);
2522
2523 return vms->highmem_mmio;
2524 }
2525
virt_set_highmem_mmio(Object * obj,bool value,Error ** errp)2526 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp)
2527 {
2528 VirtMachineState *vms = VIRT_MACHINE(obj);
2529
2530 vms->highmem_mmio = value;
2531 }
2532
2533
virt_get_its(Object * obj,Error ** errp)2534 static bool virt_get_its(Object *obj, Error **errp)
2535 {
2536 VirtMachineState *vms = VIRT_MACHINE(obj);
2537
2538 return vms->its;
2539 }
2540
virt_set_its(Object * obj,bool value,Error ** errp)2541 static void virt_set_its(Object *obj, bool value, Error **errp)
2542 {
2543 VirtMachineState *vms = VIRT_MACHINE(obj);
2544
2545 vms->its = value;
2546 }
2547
virt_get_dtb_randomness(Object * obj,Error ** errp)2548 static bool virt_get_dtb_randomness(Object *obj, Error **errp)
2549 {
2550 VirtMachineState *vms = VIRT_MACHINE(obj);
2551
2552 return vms->dtb_randomness;
2553 }
2554
virt_set_dtb_randomness(Object * obj,bool value,Error ** errp)2555 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp)
2556 {
2557 VirtMachineState *vms = VIRT_MACHINE(obj);
2558
2559 vms->dtb_randomness = value;
2560 }
2561
virt_get_oem_id(Object * obj,Error ** errp)2562 static char *virt_get_oem_id(Object *obj, Error **errp)
2563 {
2564 VirtMachineState *vms = VIRT_MACHINE(obj);
2565
2566 return g_strdup(vms->oem_id);
2567 }
2568
virt_set_oem_id(Object * obj,const char * value,Error ** errp)2569 static void virt_set_oem_id(Object *obj, const char *value, Error **errp)
2570 {
2571 VirtMachineState *vms = VIRT_MACHINE(obj);
2572 size_t len = strlen(value);
2573
2574 if (len > 6) {
2575 error_setg(errp,
2576 "User specified oem-id value is bigger than 6 bytes in size");
2577 return;
2578 }
2579
2580 strncpy(vms->oem_id, value, 6);
2581 }
2582
virt_get_oem_table_id(Object * obj,Error ** errp)2583 static char *virt_get_oem_table_id(Object *obj, Error **errp)
2584 {
2585 VirtMachineState *vms = VIRT_MACHINE(obj);
2586
2587 return g_strdup(vms->oem_table_id);
2588 }
2589
virt_set_oem_table_id(Object * obj,const char * value,Error ** errp)2590 static void virt_set_oem_table_id(Object *obj, const char *value,
2591 Error **errp)
2592 {
2593 VirtMachineState *vms = VIRT_MACHINE(obj);
2594 size_t len = strlen(value);
2595
2596 if (len > 8) {
2597 error_setg(errp,
2598 "User specified oem-table-id value is bigger than 8 bytes in size");
2599 return;
2600 }
2601 strncpy(vms->oem_table_id, value, 8);
2602 }
2603
2604
virt_is_acpi_enabled(VirtMachineState * vms)2605 bool virt_is_acpi_enabled(VirtMachineState *vms)
2606 {
2607 if (vms->acpi == ON_OFF_AUTO_OFF) {
2608 return false;
2609 }
2610 return true;
2611 }
2612
virt_get_acpi(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2613 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2614 void *opaque, Error **errp)
2615 {
2616 VirtMachineState *vms = VIRT_MACHINE(obj);
2617 OnOffAuto acpi = vms->acpi;
2618
2619 visit_type_OnOffAuto(v, name, &acpi, errp);
2620 }
2621
virt_set_acpi(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2622 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2623 void *opaque, Error **errp)
2624 {
2625 VirtMachineState *vms = VIRT_MACHINE(obj);
2626
2627 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2628 }
2629
virt_get_ras(Object * obj,Error ** errp)2630 static bool virt_get_ras(Object *obj, Error **errp)
2631 {
2632 VirtMachineState *vms = VIRT_MACHINE(obj);
2633
2634 return vms->ras;
2635 }
2636
virt_set_ras(Object * obj,bool value,Error ** errp)2637 static void virt_set_ras(Object *obj, bool value, Error **errp)
2638 {
2639 VirtMachineState *vms = VIRT_MACHINE(obj);
2640
2641 vms->ras = value;
2642 }
2643
virt_get_mte(Object * obj,Error ** errp)2644 static bool virt_get_mte(Object *obj, Error **errp)
2645 {
2646 VirtMachineState *vms = VIRT_MACHINE(obj);
2647
2648 return vms->mte;
2649 }
2650
virt_set_mte(Object * obj,bool value,Error ** errp)2651 static void virt_set_mte(Object *obj, bool value, Error **errp)
2652 {
2653 VirtMachineState *vms = VIRT_MACHINE(obj);
2654
2655 vms->mte = value;
2656 }
2657
virt_get_gic_version(Object * obj,Error ** errp)2658 static char *virt_get_gic_version(Object *obj, Error **errp)
2659 {
2660 VirtMachineState *vms = VIRT_MACHINE(obj);
2661 const char *val;
2662
2663 switch (vms->gic_version) {
2664 case VIRT_GIC_VERSION_4:
2665 val = "4";
2666 break;
2667 case VIRT_GIC_VERSION_3:
2668 val = "3";
2669 break;
2670 default:
2671 val = "2";
2672 break;
2673 }
2674 return g_strdup(val);
2675 }
2676
virt_set_gic_version(Object * obj,const char * value,Error ** errp)2677 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2678 {
2679 VirtMachineState *vms = VIRT_MACHINE(obj);
2680
2681 if (!strcmp(value, "4")) {
2682 vms->gic_version = VIRT_GIC_VERSION_4;
2683 } else if (!strcmp(value, "3")) {
2684 vms->gic_version = VIRT_GIC_VERSION_3;
2685 } else if (!strcmp(value, "2")) {
2686 vms->gic_version = VIRT_GIC_VERSION_2;
2687 } else if (!strcmp(value, "host")) {
2688 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
2689 } else if (!strcmp(value, "max")) {
2690 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
2691 } else {
2692 error_setg(errp, "Invalid gic-version value");
2693 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2694 }
2695 }
2696
virt_get_iommu(Object * obj,Error ** errp)2697 static char *virt_get_iommu(Object *obj, Error **errp)
2698 {
2699 VirtMachineState *vms = VIRT_MACHINE(obj);
2700
2701 switch (vms->iommu) {
2702 case VIRT_IOMMU_NONE:
2703 return g_strdup("none");
2704 case VIRT_IOMMU_SMMUV3:
2705 return g_strdup("smmuv3");
2706 default:
2707 g_assert_not_reached();
2708 }
2709 }
2710
virt_set_iommu(Object * obj,const char * value,Error ** errp)2711 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2712 {
2713 VirtMachineState *vms = VIRT_MACHINE(obj);
2714
2715 if (!strcmp(value, "smmuv3")) {
2716 vms->iommu = VIRT_IOMMU_SMMUV3;
2717 } else if (!strcmp(value, "none")) {
2718 vms->iommu = VIRT_IOMMU_NONE;
2719 } else {
2720 error_setg(errp, "Invalid iommu value");
2721 error_append_hint(errp, "Valid values are none, smmuv3.\n");
2722 }
2723 }
2724
virt_get_default_bus_bypass_iommu(Object * obj,Error ** errp)2725 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp)
2726 {
2727 VirtMachineState *vms = VIRT_MACHINE(obj);
2728
2729 return vms->default_bus_bypass_iommu;
2730 }
2731
virt_set_default_bus_bypass_iommu(Object * obj,bool value,Error ** errp)2732 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
2733 Error **errp)
2734 {
2735 VirtMachineState *vms = VIRT_MACHINE(obj);
2736
2737 vms->default_bus_bypass_iommu = value;
2738 }
2739
2740 static CpuInstanceProperties
virt_cpu_index_to_props(MachineState * ms,unsigned cpu_index)2741 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2742 {
2743 MachineClass *mc = MACHINE_GET_CLASS(ms);
2744 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2745
2746 assert(cpu_index < possible_cpus->len);
2747 return possible_cpus->cpus[cpu_index].props;
2748 }
2749
virt_get_default_cpu_node_id(const MachineState * ms,int idx)2750 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2751 {
2752 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
2753
2754 return socket_id % ms->numa_state->num_nodes;
2755 }
2756
virt_possible_cpu_arch_ids(MachineState * ms)2757 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2758 {
2759 int n;
2760 unsigned int max_cpus = ms->smp.max_cpus;
2761 VirtMachineState *vms = VIRT_MACHINE(ms);
2762 MachineClass *mc = MACHINE_GET_CLASS(vms);
2763
2764 if (ms->possible_cpus) {
2765 assert(ms->possible_cpus->len == max_cpus);
2766 return ms->possible_cpus;
2767 }
2768
2769 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2770 sizeof(CPUArchId) * max_cpus);
2771 ms->possible_cpus->len = max_cpus;
2772 for (n = 0; n < ms->possible_cpus->len; n++) {
2773 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2774 ms->possible_cpus->cpus[n].arch_id =
2775 virt_cpu_mp_affinity(vms, n);
2776
2777 assert(!mc->smp_props.dies_supported);
2778 ms->possible_cpus->cpus[n].props.has_socket_id = true;
2779 ms->possible_cpus->cpus[n].props.socket_id =
2780 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
2781 ms->possible_cpus->cpus[n].props.has_cluster_id = true;
2782 ms->possible_cpus->cpus[n].props.cluster_id =
2783 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
2784 ms->possible_cpus->cpus[n].props.has_core_id = true;
2785 ms->possible_cpus->cpus[n].props.core_id =
2786 (n / ms->smp.threads) % ms->smp.cores;
2787 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2788 ms->possible_cpus->cpus[n].props.thread_id =
2789 n % ms->smp.threads;
2790 }
2791 return ms->possible_cpus;
2792 }
2793
virt_memory_pre_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2794 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2795 Error **errp)
2796 {
2797 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2798 const MachineState *ms = MACHINE(hotplug_dev);
2799 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2800
2801 if (!vms->acpi_dev) {
2802 error_setg(errp,
2803 "memory hotplug is not enabled: missing acpi-ged device");
2804 return;
2805 }
2806
2807 if (vms->mte) {
2808 error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2809 return;
2810 }
2811
2812 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2813 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2814 return;
2815 }
2816
2817 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp);
2818 }
2819
virt_memory_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2820 static void virt_memory_plug(HotplugHandler *hotplug_dev,
2821 DeviceState *dev, Error **errp)
2822 {
2823 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2824 MachineState *ms = MACHINE(hotplug_dev);
2825 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2826
2827 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
2828
2829 if (is_nvdimm) {
2830 nvdimm_plug(ms->nvdimms_state);
2831 }
2832
2833 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2834 dev, &error_abort);
2835 }
2836
virt_machine_device_pre_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2837 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2838 DeviceState *dev, Error **errp)
2839 {
2840 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2841
2842 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2843 virt_memory_pre_plug(hotplug_dev, dev, errp);
2844 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2845 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2846 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2847 hwaddr db_start = 0, db_end = 0;
2848 QList *reserved_regions;
2849 char *resv_prop_str;
2850
2851 if (vms->iommu != VIRT_IOMMU_NONE) {
2852 error_setg(errp, "virt machine does not support multiple IOMMUs");
2853 return;
2854 }
2855
2856 switch (vms->msi_controller) {
2857 case VIRT_MSI_CTRL_NONE:
2858 return;
2859 case VIRT_MSI_CTRL_ITS:
2860 /* GITS_TRANSLATER page */
2861 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2862 db_end = base_memmap[VIRT_GIC_ITS].base +
2863 base_memmap[VIRT_GIC_ITS].size - 1;
2864 break;
2865 case VIRT_MSI_CTRL_GICV2M:
2866 /* MSI_SETSPI_NS page */
2867 db_start = base_memmap[VIRT_GIC_V2M].base;
2868 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2869 break;
2870 }
2871 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2872 db_start, db_end,
2873 VIRTIO_IOMMU_RESV_MEM_T_MSI);
2874
2875 reserved_regions = qlist_new();
2876 qlist_append_str(reserved_regions, resv_prop_str);
2877 qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
2878 g_free(resv_prop_str);
2879 }
2880 }
2881
virt_machine_device_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2882 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2883 DeviceState *dev, Error **errp)
2884 {
2885 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2886
2887 if (vms->platform_bus_dev) {
2888 MachineClass *mc = MACHINE_GET_CLASS(vms);
2889
2890 if (device_is_dynamic_sysbus(mc, dev)) {
2891 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2892 SYS_BUS_DEVICE(dev));
2893 }
2894 }
2895
2896 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2897 virt_memory_plug(hotplug_dev, dev, errp);
2898 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2899 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2900 }
2901
2902 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2903 PCIDevice *pdev = PCI_DEVICE(dev);
2904
2905 vms->iommu = VIRT_IOMMU_VIRTIO;
2906 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2907 create_virtio_iommu_dt_bindings(vms);
2908 }
2909 }
2910
virt_dimm_unplug_request(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2911 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2912 DeviceState *dev, Error **errp)
2913 {
2914 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2915
2916 if (!vms->acpi_dev) {
2917 error_setg(errp,
2918 "memory hotplug is not enabled: missing acpi-ged device");
2919 return;
2920 }
2921
2922 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2923 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
2924 return;
2925 }
2926
2927 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2928 errp);
2929 }
2930
virt_dimm_unplug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2931 static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2932 DeviceState *dev, Error **errp)
2933 {
2934 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2935 Error *local_err = NULL;
2936
2937 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
2938 if (local_err) {
2939 goto out;
2940 }
2941
2942 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
2943 qdev_unrealize(dev);
2944
2945 out:
2946 error_propagate(errp, local_err);
2947 }
2948
virt_machine_device_unplug_request_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2949 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2950 DeviceState *dev, Error **errp)
2951 {
2952 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2953 virt_dimm_unplug_request(hotplug_dev, dev, errp);
2954 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2955 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
2956 errp);
2957 } else {
2958 error_setg(errp, "device unplug request for unsupported device"
2959 " type: %s", object_get_typename(OBJECT(dev)));
2960 }
2961 }
2962
virt_machine_device_unplug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2963 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2964 DeviceState *dev, Error **errp)
2965 {
2966 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2967 virt_dimm_unplug(hotplug_dev, dev, errp);
2968 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2969 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2970 } else {
2971 error_setg(errp, "virt: device unplug for unsupported device"
2972 " type: %s", object_get_typename(OBJECT(dev)));
2973 }
2974 }
2975
virt_machine_get_hotplug_handler(MachineState * machine,DeviceState * dev)2976 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
2977 DeviceState *dev)
2978 {
2979 MachineClass *mc = MACHINE_GET_CLASS(machine);
2980
2981 if (device_is_dynamic_sysbus(mc, dev) ||
2982 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2983 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
2984 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2985 return HOTPLUG_HANDLER(machine);
2986 }
2987 return NULL;
2988 }
2989
2990 /*
2991 * for arm64 kvm_type [7-0] encodes the requested number of bits
2992 * in the IPA address space
2993 */
virt_kvm_type(MachineState * ms,const char * type_str)2994 static int virt_kvm_type(MachineState *ms, const char *type_str)
2995 {
2996 VirtMachineState *vms = VIRT_MACHINE(ms);
2997 int max_vm_pa_size, requested_pa_size;
2998 bool fixed_ipa;
2999
3000 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
3001
3002 /* we freeze the memory map to compute the highest gpa */
3003 virt_set_memmap(vms, max_vm_pa_size);
3004
3005 requested_pa_size = 64 - clz64(vms->highest_gpa);
3006
3007 /*
3008 * KVM requires the IPA size to be at least 32 bits.
3009 */
3010 if (requested_pa_size < 32) {
3011 requested_pa_size = 32;
3012 }
3013
3014 if (requested_pa_size > max_vm_pa_size) {
3015 error_report("-m and ,maxmem option values "
3016 "require an IPA range (%d bits) larger than "
3017 "the one supported by the host (%d bits)",
3018 requested_pa_size, max_vm_pa_size);
3019 return -1;
3020 }
3021 /*
3022 * We return the requested PA log size, unless KVM only supports
3023 * the implicit legacy 40b IPA setting, in which case the kvm_type
3024 * must be 0.
3025 */
3026 return fixed_ipa ? 0 : requested_pa_size;
3027 }
3028
virt_machine_class_init(ObjectClass * oc,void * data)3029 static void virt_machine_class_init(ObjectClass *oc, void *data)
3030 {
3031 MachineClass *mc = MACHINE_CLASS(oc);
3032 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3033 static const char * const valid_cpu_types[] = {
3034 #ifdef CONFIG_TCG
3035 ARM_CPU_TYPE_NAME("cortex-a7"),
3036 ARM_CPU_TYPE_NAME("cortex-a15"),
3037 #ifdef TARGET_AARCH64
3038 ARM_CPU_TYPE_NAME("cortex-a35"),
3039 ARM_CPU_TYPE_NAME("cortex-a55"),
3040 ARM_CPU_TYPE_NAME("cortex-a72"),
3041 ARM_CPU_TYPE_NAME("cortex-a76"),
3042 ARM_CPU_TYPE_NAME("cortex-a710"),
3043 ARM_CPU_TYPE_NAME("a64fx"),
3044 ARM_CPU_TYPE_NAME("neoverse-n1"),
3045 ARM_CPU_TYPE_NAME("neoverse-v1"),
3046 ARM_CPU_TYPE_NAME("neoverse-n2"),
3047 #endif /* TARGET_AARCH64 */
3048 #endif /* CONFIG_TCG */
3049 #ifdef TARGET_AARCH64
3050 ARM_CPU_TYPE_NAME("cortex-a53"),
3051 ARM_CPU_TYPE_NAME("cortex-a57"),
3052 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
3053 ARM_CPU_TYPE_NAME("host"),
3054 #endif /* CONFIG_KVM || CONFIG_HVF */
3055 #endif /* TARGET_AARCH64 */
3056 ARM_CPU_TYPE_NAME("max"),
3057 NULL
3058 };
3059
3060 mc->init = machvirt_init;
3061 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
3062 * The value may be reduced later when we have more information about the
3063 * configuration of the particular instance.
3064 */
3065 mc->max_cpus = 512;
3066 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
3067 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
3068 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
3069 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
3070 #ifdef CONFIG_TPM
3071 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
3072 #endif
3073 mc->block_default_type = IF_VIRTIO;
3074 mc->no_cdrom = 1;
3075 mc->pci_allow_0_address = true;
3076 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
3077 mc->minimum_page_bits = 12;
3078 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
3079 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
3080 #ifdef CONFIG_TCG
3081 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
3082 #else
3083 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
3084 #endif
3085 mc->valid_cpu_types = valid_cpu_types;
3086 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
3087 mc->kvm_type = virt_kvm_type;
3088 assert(!mc->get_hotplug_handler);
3089 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
3090 hc->pre_plug = virt_machine_device_pre_plug_cb;
3091 hc->plug = virt_machine_device_plug_cb;
3092 hc->unplug_request = virt_machine_device_unplug_request_cb;
3093 hc->unplug = virt_machine_device_unplug_cb;
3094 mc->nvdimm_supported = true;
3095 mc->smp_props.clusters_supported = true;
3096 mc->auto_enable_numa_with_memhp = true;
3097 mc->auto_enable_numa_with_memdev = true;
3098 /* platform instead of architectural choice */
3099 mc->cpu_cluster_has_numa_boundary = true;
3100 mc->default_ram_id = "mach-virt.ram";
3101 mc->default_nic = "virtio-net-pci";
3102
3103 object_class_property_add(oc, "acpi", "OnOffAuto",
3104 virt_get_acpi, virt_set_acpi,
3105 NULL, NULL);
3106 object_class_property_set_description(oc, "acpi",
3107 "Enable ACPI");
3108 object_class_property_add_bool(oc, "secure", virt_get_secure,
3109 virt_set_secure);
3110 object_class_property_set_description(oc, "secure",
3111 "Set on/off to enable/disable the ARM "
3112 "Security Extensions (TrustZone)");
3113
3114 object_class_property_add_bool(oc, "virtualization", virt_get_virt,
3115 virt_set_virt);
3116 object_class_property_set_description(oc, "virtualization",
3117 "Set on/off to enable/disable emulating a "
3118 "guest CPU which implements the ARM "
3119 "Virtualization Extensions");
3120
3121 object_class_property_add_bool(oc, "highmem", virt_get_highmem,
3122 virt_set_highmem);
3123 object_class_property_set_description(oc, "highmem",
3124 "Set on/off to enable/disable using "
3125 "physical address space above 32 bits");
3126
3127 object_class_property_add_bool(oc, "compact-highmem",
3128 virt_get_compact_highmem,
3129 virt_set_compact_highmem);
3130 object_class_property_set_description(oc, "compact-highmem",
3131 "Set on/off to enable/disable compact "
3132 "layout for high memory regions");
3133
3134 object_class_property_add_bool(oc, "highmem-redists",
3135 virt_get_highmem_redists,
3136 virt_set_highmem_redists);
3137 object_class_property_set_description(oc, "highmem-redists",
3138 "Set on/off to enable/disable high "
3139 "memory region for GICv3 or GICv4 "
3140 "redistributor");
3141
3142 object_class_property_add_bool(oc, "highmem-ecam",
3143 virt_get_highmem_ecam,
3144 virt_set_highmem_ecam);
3145 object_class_property_set_description(oc, "highmem-ecam",
3146 "Set on/off to enable/disable high "
3147 "memory region for PCI ECAM");
3148
3149 object_class_property_add_bool(oc, "highmem-mmio",
3150 virt_get_highmem_mmio,
3151 virt_set_highmem_mmio);
3152 object_class_property_set_description(oc, "highmem-mmio",
3153 "Set on/off to enable/disable high "
3154 "memory region for PCI MMIO");
3155
3156 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
3157 virt_set_gic_version);
3158 object_class_property_set_description(oc, "gic-version",
3159 "Set GIC version. "
3160 "Valid values are 2, 3, 4, host and max");
3161
3162 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
3163 object_class_property_set_description(oc, "iommu",
3164 "Set the IOMMU type. "
3165 "Valid values are none and smmuv3");
3166
3167 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
3168 virt_get_default_bus_bypass_iommu,
3169 virt_set_default_bus_bypass_iommu);
3170 object_class_property_set_description(oc, "default-bus-bypass-iommu",
3171 "Set on/off to enable/disable "
3172 "bypass_iommu for default root bus");
3173
3174 object_class_property_add_bool(oc, "ras", virt_get_ras,
3175 virt_set_ras);
3176 object_class_property_set_description(oc, "ras",
3177 "Set on/off to enable/disable reporting host memory errors "
3178 "to a KVM guest using ACPI and guest external abort exceptions");
3179
3180 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
3181 object_class_property_set_description(oc, "mte",
3182 "Set on/off to enable/disable emulating a "
3183 "guest CPU which implements the ARM "
3184 "Memory Tagging Extension");
3185
3186 object_class_property_add_bool(oc, "its", virt_get_its,
3187 virt_set_its);
3188 object_class_property_set_description(oc, "its",
3189 "Set on/off to enable/disable "
3190 "ITS instantiation");
3191
3192 object_class_property_add_bool(oc, "dtb-randomness",
3193 virt_get_dtb_randomness,
3194 virt_set_dtb_randomness);
3195 object_class_property_set_description(oc, "dtb-randomness",
3196 "Set off to disable passing random or "
3197 "non-deterministic dtb nodes to guest");
3198
3199 object_class_property_add_bool(oc, "dtb-kaslr-seed",
3200 virt_get_dtb_randomness,
3201 virt_set_dtb_randomness);
3202 object_class_property_set_description(oc, "dtb-kaslr-seed",
3203 "Deprecated synonym of dtb-randomness");
3204
3205 object_class_property_add_str(oc, "x-oem-id",
3206 virt_get_oem_id,
3207 virt_set_oem_id);
3208 object_class_property_set_description(oc, "x-oem-id",
3209 "Override the default value of field OEMID "
3210 "in ACPI table header."
3211 "The string may be up to 6 bytes in size");
3212
3213
3214 object_class_property_add_str(oc, "x-oem-table-id",
3215 virt_get_oem_table_id,
3216 virt_set_oem_table_id);
3217 object_class_property_set_description(oc, "x-oem-table-id",
3218 "Override the default value of field OEM Table ID "
3219 "in ACPI table header."
3220 "The string may be up to 8 bytes in size");
3221
3222 }
3223
virt_instance_init(Object * obj)3224 static void virt_instance_init(Object *obj)
3225 {
3226 VirtMachineState *vms = VIRT_MACHINE(obj);
3227 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
3228
3229 /* EL3 is disabled by default on virt: this makes us consistent
3230 * between KVM and TCG for this board, and it also allows us to
3231 * boot UEFI blobs which assume no TrustZone support.
3232 */
3233 vms->secure = false;
3234
3235 /* EL2 is also disabled by default, for similar reasons */
3236 vms->virt = false;
3237
3238 /* High memory is enabled by default */
3239 vms->highmem = true;
3240 vms->highmem_compact = !vmc->no_highmem_compact;
3241 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
3242
3243 vms->highmem_ecam = !vmc->no_highmem_ecam;
3244 vms->highmem_mmio = true;
3245 vms->highmem_redists = true;
3246
3247 if (vmc->no_its) {
3248 vms->its = false;
3249 } else {
3250 /* Default allows ITS instantiation */
3251 vms->its = true;
3252
3253 if (vmc->no_tcg_its) {
3254 vms->tcg_its = false;
3255 } else {
3256 vms->tcg_its = true;
3257 }
3258 }
3259
3260 /* Default disallows iommu instantiation */
3261 vms->iommu = VIRT_IOMMU_NONE;
3262
3263 /* The default root bus is attached to iommu by default */
3264 vms->default_bus_bypass_iommu = false;
3265
3266 /* Default disallows RAS instantiation */
3267 vms->ras = false;
3268
3269 /* MTE is disabled by default. */
3270 vms->mte = false;
3271
3272 /* Supply kaslr-seed and rng-seed by default */
3273 vms->dtb_randomness = true;
3274
3275 vms->irqmap = a15irqmap;
3276
3277 virt_flash_create(vms);
3278
3279 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
3280 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
3281 }
3282
3283 static const TypeInfo virt_machine_info = {
3284 .name = TYPE_VIRT_MACHINE,
3285 .parent = TYPE_MACHINE,
3286 .abstract = true,
3287 .instance_size = sizeof(VirtMachineState),
3288 .class_size = sizeof(VirtMachineClass),
3289 .class_init = virt_machine_class_init,
3290 .instance_init = virt_instance_init,
3291 .interfaces = (InterfaceInfo[]) {
3292 { TYPE_HOTPLUG_HANDLER },
3293 { }
3294 },
3295 };
3296
machvirt_machine_init(void)3297 static void machvirt_machine_init(void)
3298 {
3299 type_register_static(&virt_machine_info);
3300 }
3301 type_init(machvirt_machine_init);
3302
virt_machine_9_1_options(MachineClass * mc)3303 static void virt_machine_9_1_options(MachineClass *mc)
3304 {
3305 }
3306 DEFINE_VIRT_MACHINE_AS_LATEST(9, 1)
3307
virt_machine_9_0_options(MachineClass * mc)3308 static void virt_machine_9_0_options(MachineClass *mc)
3309 {
3310 virt_machine_9_1_options(mc);
3311 mc->smbios_memory_device_size = 16 * GiB;
3312 compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len);
3313 }
3314 DEFINE_VIRT_MACHINE(9, 0)
3315
virt_machine_8_2_options(MachineClass * mc)3316 static void virt_machine_8_2_options(MachineClass *mc)
3317 {
3318 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3319
3320 virt_machine_9_0_options(mc);
3321 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
3322 /*
3323 * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
3324 * earlier machines. (Exposing it tickles a bug in older EDK2
3325 * guest BIOS binaries.)
3326 */
3327 vmc->no_ns_el2_virt_timer_irq = true;
3328 }
3329 DEFINE_VIRT_MACHINE(8, 2)
3330
virt_machine_8_1_options(MachineClass * mc)3331 static void virt_machine_8_1_options(MachineClass *mc)
3332 {
3333 virt_machine_8_2_options(mc);
3334 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len);
3335 }
3336 DEFINE_VIRT_MACHINE(8, 1)
3337
virt_machine_8_0_options(MachineClass * mc)3338 static void virt_machine_8_0_options(MachineClass *mc)
3339 {
3340 virt_machine_8_1_options(mc);
3341 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len);
3342 }
3343 DEFINE_VIRT_MACHINE(8, 0)
3344
virt_machine_7_2_options(MachineClass * mc)3345 static void virt_machine_7_2_options(MachineClass *mc)
3346 {
3347 virt_machine_8_0_options(mc);
3348 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len);
3349 }
3350 DEFINE_VIRT_MACHINE(7, 2)
3351
virt_machine_7_1_options(MachineClass * mc)3352 static void virt_machine_7_1_options(MachineClass *mc)
3353 {
3354 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3355
3356 virt_machine_7_2_options(mc);
3357 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
3358 /* Compact layout for high memory regions was introduced with 7.2 */
3359 vmc->no_highmem_compact = true;
3360 }
3361 DEFINE_VIRT_MACHINE(7, 1)
3362
virt_machine_7_0_options(MachineClass * mc)3363 static void virt_machine_7_0_options(MachineClass *mc)
3364 {
3365 virt_machine_7_1_options(mc);
3366 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len);
3367 }
3368 DEFINE_VIRT_MACHINE(7, 0)
3369
virt_machine_6_2_options(MachineClass * mc)3370 static void virt_machine_6_2_options(MachineClass *mc)
3371 {
3372 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3373
3374 virt_machine_7_0_options(mc);
3375 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);
3376 vmc->no_tcg_lpa2 = true;
3377 }
3378 DEFINE_VIRT_MACHINE(6, 2)
3379
virt_machine_6_1_options(MachineClass * mc)3380 static void virt_machine_6_1_options(MachineClass *mc)
3381 {
3382 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3383
3384 virt_machine_6_2_options(mc);
3385 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
3386 mc->smp_props.prefer_sockets = true;
3387 vmc->no_cpu_topology = true;
3388
3389 /* qemu ITS was introduced with 6.2 */
3390 vmc->no_tcg_its = true;
3391 }
3392 DEFINE_VIRT_MACHINE(6, 1)
3393
virt_machine_6_0_options(MachineClass * mc)3394 static void virt_machine_6_0_options(MachineClass *mc)
3395 {
3396 virt_machine_6_1_options(mc);
3397 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
3398 }
3399 DEFINE_VIRT_MACHINE(6, 0)
3400
virt_machine_5_2_options(MachineClass * mc)3401 static void virt_machine_5_2_options(MachineClass *mc)
3402 {
3403 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3404
3405 virt_machine_6_0_options(mc);
3406 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
3407 vmc->no_secure_gpio = true;
3408 }
3409 DEFINE_VIRT_MACHINE(5, 2)
3410
virt_machine_5_1_options(MachineClass * mc)3411 static void virt_machine_5_1_options(MachineClass *mc)
3412 {
3413 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3414
3415 virt_machine_5_2_options(mc);
3416 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
3417 vmc->no_kvm_steal_time = true;
3418 }
3419 DEFINE_VIRT_MACHINE(5, 1)
3420
virt_machine_5_0_options(MachineClass * mc)3421 static void virt_machine_5_0_options(MachineClass *mc)
3422 {
3423 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3424
3425 virt_machine_5_1_options(mc);
3426 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
3427 mc->numa_mem_supported = true;
3428 vmc->acpi_expose_flash = true;
3429 mc->auto_enable_numa_with_memdev = false;
3430 }
3431 DEFINE_VIRT_MACHINE(5, 0)
3432
virt_machine_4_2_options(MachineClass * mc)3433 static void virt_machine_4_2_options(MachineClass *mc)
3434 {
3435 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3436
3437 virt_machine_5_0_options(mc);
3438 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
3439 vmc->kvm_no_adjvtime = true;
3440 }
3441 DEFINE_VIRT_MACHINE(4, 2)
3442
virt_machine_4_1_options(MachineClass * mc)3443 static void virt_machine_4_1_options(MachineClass *mc)
3444 {
3445 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3446
3447 virt_machine_4_2_options(mc);
3448 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
3449 vmc->no_ged = true;
3450 mc->auto_enable_numa_with_memhp = false;
3451 }
3452 DEFINE_VIRT_MACHINE(4, 1)
3453
virt_machine_4_0_options(MachineClass * mc)3454 static void virt_machine_4_0_options(MachineClass *mc)
3455 {
3456 virt_machine_4_1_options(mc);
3457 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
3458 }
3459 DEFINE_VIRT_MACHINE(4, 0)
3460
virt_machine_3_1_options(MachineClass * mc)3461 static void virt_machine_3_1_options(MachineClass *mc)
3462 {
3463 virt_machine_4_0_options(mc);
3464 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
3465 }
3466 DEFINE_VIRT_MACHINE(3, 1)
3467
virt_machine_3_0_options(MachineClass * mc)3468 static void virt_machine_3_0_options(MachineClass *mc)
3469 {
3470 virt_machine_3_1_options(mc);
3471 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
3472 }
3473 DEFINE_VIRT_MACHINE(3, 0)
3474
virt_machine_2_12_options(MachineClass * mc)3475 static void virt_machine_2_12_options(MachineClass *mc)
3476 {
3477 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3478
3479 virt_machine_3_0_options(mc);
3480 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
3481 vmc->no_highmem_ecam = true;
3482 mc->max_cpus = 255;
3483 }
3484 DEFINE_VIRT_MACHINE(2, 12)
3485
virt_machine_2_11_options(MachineClass * mc)3486 static void virt_machine_2_11_options(MachineClass *mc)
3487 {
3488 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3489
3490 virt_machine_2_12_options(mc);
3491 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
3492 vmc->smbios_old_sys_ver = true;
3493 }
3494 DEFINE_VIRT_MACHINE(2, 11)
3495
virt_machine_2_10_options(MachineClass * mc)3496 static void virt_machine_2_10_options(MachineClass *mc)
3497 {
3498 virt_machine_2_11_options(mc);
3499 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
3500 /* before 2.11 we never faulted accesses to bad addresses */
3501 mc->ignore_memory_transaction_failures = true;
3502 }
3503 DEFINE_VIRT_MACHINE(2, 10)
3504
virt_machine_2_9_options(MachineClass * mc)3505 static void virt_machine_2_9_options(MachineClass *mc)
3506 {
3507 virt_machine_2_10_options(mc);
3508 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
3509 }
3510 DEFINE_VIRT_MACHINE(2, 9)
3511
virt_machine_2_8_options(MachineClass * mc)3512 static void virt_machine_2_8_options(MachineClass *mc)
3513 {
3514 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3515
3516 virt_machine_2_9_options(mc);
3517 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
3518 /* For 2.8 and earlier we falsely claimed in the DT that
3519 * our timers were edge-triggered, not level-triggered.
3520 */
3521 vmc->claim_edge_triggered_timers = true;
3522 }
3523 DEFINE_VIRT_MACHINE(2, 8)
3524
virt_machine_2_7_options(MachineClass * mc)3525 static void virt_machine_2_7_options(MachineClass *mc)
3526 {
3527 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3528
3529 virt_machine_2_8_options(mc);
3530 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
3531 /* ITS was introduced with 2.8 */
3532 vmc->no_its = true;
3533 /* Stick with 1K pages for migration compatibility */
3534 mc->minimum_page_bits = 0;
3535 }
3536 DEFINE_VIRT_MACHINE(2, 7)
3537
virt_machine_2_6_options(MachineClass * mc)3538 static void virt_machine_2_6_options(MachineClass *mc)
3539 {
3540 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3541
3542 virt_machine_2_7_options(mc);
3543 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
3544 vmc->disallow_affinity_adjustment = true;
3545 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3546 vmc->no_pmu = true;
3547 }
3548 DEFINE_VIRT_MACHINE(2, 6)
3549