1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 #ifndef __DISPLAY_MODE_ENUMS_H__
26 #define __DISPLAY_MODE_ENUMS_H__
27 
28 enum output_encoder_class {
29 	dm_dp = 0,
30 	dm_hdmi = 1,
31 	dm_wb = 2,
32 	dm_edp = 3,
33 	dm_dp2p0 = 5,
34 };
35 enum output_format_class {
36 	dm_444 = 0, dm_420 = 1, dm_n422, dm_s422
37 };
38 enum source_format_class {
39 	dm_444_16 = 0,
40 	dm_444_32 = 1,
41 	dm_444_64 = 2,
42 	dm_420_8 = 3,
43 	dm_420_10 = 4,
44 	dm_420_12 = 5,
45 	dm_422_8 = 6,
46 	dm_422_10 = 7,
47 	dm_444_8 = 8,
48 	dm_mono_8 = dm_444_8,
49 	dm_mono_16 = dm_444_16,
50 	dm_rgbe = 9,
51 	dm_rgbe_alpha = 10,
52 };
53 enum output_bpc_class {
54 	dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4
55 };
56 enum scan_direction_class {
57 	dm_horz = 0, dm_vert = 1
58 };
59 enum dm_swizzle_mode {
60 	dm_sw_linear = 0,
61 	dm_sw_256b_s = 1,
62 	dm_sw_256b_d = 2,
63 	dm_sw_SPARE_0 = 3,
64 	dm_sw_SPARE_1 = 4,
65 	dm_sw_4kb_s = 5,
66 	dm_sw_4kb_d = 6,
67 	dm_sw_SPARE_2 = 7,
68 	dm_sw_SPARE_3 = 8,
69 	dm_sw_64kb_s = 9,
70 	dm_sw_64kb_d = 10,
71 	dm_sw_SPARE_4 = 11,
72 	dm_sw_SPARE_5 = 12,
73 	dm_sw_var_s = 13,
74 	dm_sw_var_d = 14,
75 	dm_sw_SPARE_6 = 15,
76 	dm_sw_SPARE_7 = 16,
77 	dm_sw_64kb_s_t = 17,
78 	dm_sw_64kb_d_t = 18,
79 	dm_sw_SPARE_10 = 19,
80 	dm_sw_SPARE_11 = 20,
81 	dm_sw_4kb_s_x = 21,
82 	dm_sw_4kb_d_x = 22,
83 	dm_sw_SPARE_12 = 23,
84 	dm_sw_SPARE_13 = 24,
85 	dm_sw_64kb_s_x = 25,
86 	dm_sw_64kb_d_x = 26,
87 	dm_sw_64kb_r_x = 27,
88 	dm_sw_SPARE_15 = 28,
89 	dm_sw_var_s_x = 29,
90 	dm_sw_var_d_x = 30,
91 	dm_sw_var_r_x = 31,
92 	dm_sw_gfx7_2d_thin_l_vp,
93 	dm_sw_gfx7_2d_thin_gl,
94 };
95 enum lb_depth {
96 	dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
97 	dm_lb_19 = 5
98 };
99 enum voltage_state {
100 	dm_vmin = 0, dm_vmid = 1, dm_vnom = 2, dm_vmax = 3
101 };
102 enum source_macro_tile_size {
103 	dm_4k_tile = 0, dm_64k_tile = 1, dm_256k_tile = 2
104 };
105 enum cursor_bpp {
106 	dm_cur_2bit = 0, dm_cur_32bit = 1, dm_cur_64bit = 2
107 };
108 
109 /**
110  * @enum clock_change_support - It represents possible reasons to change the DRAM clock.
111  *
112  * DC may change the DRAM clock during its execution, and this enum tracks all
113  * the available methods. Note that every ASIC has their specific way to deal
114  * with these clock switch.
115  */
116 enum clock_change_support {
117 	/**
118 	 * @dm_dram_clock_change_uninitialized: If you see this, we might have
119 	 * a code initialization issue
120 	 */
121 	dm_dram_clock_change_uninitialized = 0,
122 
123 	/**
124 	 * @dm_dram_clock_change_vactive: Support DRAM switch in VActive
125 	 */
126 	dm_dram_clock_change_vactive,
127 
128 	/**
129 	 * @dm_dram_clock_change_vblank: Support DRAM switch in VBlank
130 	 */
131 	dm_dram_clock_change_vblank,
132 
133 	dm_dram_clock_change_vactive_w_mall_full_frame,
134 	dm_dram_clock_change_vactive_w_mall_sub_vp,
135 	dm_dram_clock_change_vblank_w_mall_full_frame,
136 	dm_dram_clock_change_vblank_w_mall_sub_vp,
137 
138 	/**
139 	 * @dm_dram_clock_change_unsupported: Do not support DRAM switch
140 	 */
141 	dm_dram_clock_change_unsupported
142 };
143 
144 enum output_standard {
145 	dm_std_uninitialized = 0,
146 	dm_std_cvtr2,
147 	dm_std_cvt
148 };
149 
150 enum mpc_combine_affinity {
151 	dm_mpc_always_when_possible,
152 	dm_mpc_reduce_voltage,
153 	dm_mpc_reduce_voltage_and_clocks,
154 	dm_mpc_never
155 };
156 
157 enum RequestType {
158 	REQ_256Bytes, REQ_128BytesNonContiguous, REQ_128BytesContiguous, REQ_NA
159 };
160 
161 enum self_refresh_affinity {
162 	dm_try_to_allow_self_refresh_and_mclk_switch,
163 	dm_allow_self_refresh_and_mclk_switch,
164 	dm_allow_self_refresh,
165 	dm_neither_self_refresh_nor_mclk_switch
166 };
167 
168 enum dm_validation_status {
169 	DML_VALIDATION_OK,
170 	DML_FAIL_SCALE_RATIO_TAP,
171 	DML_FAIL_SOURCE_PIXEL_FORMAT,
172 	DML_FAIL_VIEWPORT_SIZE,
173 	DML_FAIL_TOTAL_V_ACTIVE_BW,
174 	DML_FAIL_DIO_SUPPORT,
175 	DML_FAIL_NOT_ENOUGH_DSC,
176 	DML_FAIL_DSC_CLK_REQUIRED,
177 	DML_FAIL_DSC_VALIDATION_FAILURE,
178 	DML_FAIL_URGENT_LATENCY,
179 	DML_FAIL_REORDERING_BUFFER,
180 	DML_FAIL_DISPCLK_DPPCLK,
181 	DML_FAIL_TOTAL_AVAILABLE_PIPES,
182 	DML_FAIL_NUM_OTG,
183 	DML_FAIL_WRITEBACK_MODE,
184 	DML_FAIL_WRITEBACK_LATENCY,
185 	DML_FAIL_WRITEBACK_SCALE_RATIO_TAP,
186 	DML_FAIL_CURSOR_SUPPORT,
187 	DML_FAIL_PITCH_SUPPORT,
188 	DML_FAIL_PTE_BUFFER_SIZE,
189 	DML_FAIL_HOST_VM_IMMEDIATE_FLIP,
190 	DML_FAIL_DSC_INPUT_BPC,
191 	DML_FAIL_PREFETCH_SUPPORT,
192 	DML_FAIL_V_RATIO_PREFETCH,
193 	DML_FAIL_P2I_WITH_420,
194 	DML_FAIL_DSC_ONLY_IF_NECESSARY_WITH_BPP,
195 	DML_FAIL_NOT_DSC422_NATIVE,
196 	DML_FAIL_ODM_COMBINE4TO1,
197 	DML_FAIL_ENOUGH_WRITEBACK_UNITS,
198 	DML_FAIL_VIEWPORT_EXCEEDS_SURFACE,
199 	DML_FAIL_DYNAMIC_METADATA,
200 	DML_FAIL_FMT_BUFFER_EXCEEDED,
201 };
202 
203 enum writeback_config {
204 	dm_normal,
205 	dm_whole_buffer_for_single_stream_no_interleave,
206 	dm_whole_buffer_for_single_stream_interleave,
207 };
208 
209 enum odm_combine_mode {
210 	dm_odm_combine_mode_disabled,
211 	dm_odm_combine_mode_2to1,
212 	dm_odm_combine_mode_4to1,
213 	dm_odm_split_mode_1to2,
214 	dm_odm_mode_mso_1to2,
215 	dm_odm_mode_mso_1to4
216 };
217 
218 enum odm_combine_policy {
219 	dm_odm_combine_policy_dal,
220 	dm_odm_combine_policy_none,
221 	dm_odm_combine_policy_2to1,
222 	dm_odm_combine_policy_4to1,
223 	dm_odm_split_policy_1to2,
224 	dm_odm_mso_policy_1to2,
225 	dm_odm_mso_policy_1to4,
226 };
227 
228 enum immediate_flip_requirement {
229 	dm_immediate_flip_not_required,
230 	dm_immediate_flip_required,
231 	dm_immediate_flip_opportunistic,
232 };
233 
234 enum unbounded_requesting_policy {
235 	dm_unbounded_requesting,
236 	dm_unbounded_requesting_edp_only,
237 	dm_unbounded_requesting_disable
238 };
239 
240 enum dm_rotation_angle {
241 	dm_rotation_0,
242 	dm_rotation_90,
243 	dm_rotation_180,
244 	dm_rotation_270,
245 	dm_rotation_0m,
246 	dm_rotation_90m,
247 	dm_rotation_180m,
248 	dm_rotation_270m,
249 };
250 
251 enum dm_use_mall_for_pstate_change_mode {
252 	dm_use_mall_pstate_change_disable,
253 	dm_use_mall_pstate_change_full_frame,
254 	dm_use_mall_pstate_change_sub_viewport,
255 	dm_use_mall_pstate_change_phantom_pipe
256 };
257 
258 enum dm_use_mall_for_static_screen_mode {
259 	dm_use_mall_static_screen_disable,
260 	dm_use_mall_static_screen_optimize,
261 	dm_use_mall_static_screen_enable,
262 };
263 
264 enum dm_output_link_dp_rate {
265 	dm_dp_rate_na,
266 	dm_dp_rate_hbr,
267 	dm_dp_rate_hbr2,
268 	dm_dp_rate_hbr3,
269 	dm_dp_rate_uhbr10,
270 	dm_dp_rate_uhbr13p5,
271 	dm_dp_rate_uhbr20,
272 };
273 
274 enum dm_fclock_change_support {
275 	dm_fclock_change_vactive,
276 	dm_fclock_change_vblank,
277 	dm_fclock_change_unsupported,
278 };
279 
280 enum dm_prefetch_modes {
281 	dm_prefetch_support_uclk_fclk_and_stutter_if_possible,
282 	dm_prefetch_support_uclk_fclk_and_stutter,
283 	dm_prefetch_support_fclk_and_stutter,
284 	dm_prefetch_support_stutter,
285 	dm_prefetch_support_none,
286 };
287 enum dm_output_type {
288 	dm_output_type_unknown,
289 	dm_output_type_dp,
290 	dm_output_type_edp,
291 	dm_output_type_dp2p0,
292 	dm_output_type_hdmi,
293 	dm_output_type_hdmifrl,
294 };
295 
296 enum dm_output_rate {
297 	dm_output_rate_unknown,
298 	dm_output_rate_dp_rate_hbr,
299 	dm_output_rate_dp_rate_hbr2,
300 	dm_output_rate_dp_rate_hbr3,
301 	dm_output_rate_dp_rate_uhbr10,
302 	dm_output_rate_dp_rate_uhbr13p5,
303 	dm_output_rate_dp_rate_uhbr20,
304 	dm_output_rate_hdmi_rate_3x3,
305 	dm_output_rate_hdmi_rate_6x3,
306 	dm_output_rate_hdmi_rate_6x4,
307 	dm_output_rate_hdmi_rate_8x4,
308 	dm_output_rate_hdmi_rate_10x4,
309 	dm_output_rate_hdmi_rate_12x4,
310 };
311 #endif
312