1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 The FreeBSD Foundation
5 *
6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
7 * under sponsorship from the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #include <sys/param.h>
32 #include <sys/bus.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/malloc.h>
36 #include <sys/memdesc.h>
37 #include <sys/mutex.h>
38 #include <sys/proc.h>
39 #include <sys/queue.h>
40 #include <sys/rman.h>
41 #include <sys/rwlock.h>
42 #include <sys/sched.h>
43 #include <sys/sf_buf.h>
44 #include <sys/sysctl.h>
45 #include <sys/systm.h>
46 #include <sys/taskqueue.h>
47 #include <sys/time.h>
48 #include <sys/tree.h>
49 #include <sys/vmem.h>
50 #include <vm/vm.h>
51 #include <vm/vm_extern.h>
52 #include <vm/vm_kern.h>
53 #include <vm/vm_object.h>
54 #include <vm/vm_page.h>
55 #include <vm/vm_map.h>
56 #include <vm/vm_pageout.h>
57 #include <dev/pci/pcireg.h>
58 #include <dev/pci/pcivar.h>
59 #include <machine/bus.h>
60 #include <machine/cpu.h>
61 #include <machine/intr_machdep.h>
62 #include <x86/include/apicvar.h>
63 #include <x86/include/busdma_impl.h>
64 #include <dev/iommu/busdma_iommu.h>
65 #include <x86/iommu/intel_reg.h>
66 #include <x86/iommu/intel_dmar.h>
67
68 u_int
dmar_nd2mask(u_int nd)69 dmar_nd2mask(u_int nd)
70 {
71 static const u_int masks[] = {
72 0x000f, /* nd == 0 */
73 0x002f, /* nd == 1 */
74 0x00ff, /* nd == 2 */
75 0x02ff, /* nd == 3 */
76 0x0fff, /* nd == 4 */
77 0x2fff, /* nd == 5 */
78 0xffff, /* nd == 6 */
79 0x0000, /* nd == 7 reserved */
80 };
81
82 KASSERT(nd <= 6, ("number of domains %d", nd));
83 return (masks[nd]);
84 }
85
86 static const struct sagaw_bits_tag {
87 int agaw;
88 int cap;
89 int awlvl;
90 int pglvl;
91 } sagaw_bits[] = {
92 {.agaw = 30, .cap = DMAR_CAP_SAGAW_2LVL, .awlvl = DMAR_CTX2_AW_2LVL,
93 .pglvl = 2},
94 {.agaw = 39, .cap = DMAR_CAP_SAGAW_3LVL, .awlvl = DMAR_CTX2_AW_3LVL,
95 .pglvl = 3},
96 {.agaw = 48, .cap = DMAR_CAP_SAGAW_4LVL, .awlvl = DMAR_CTX2_AW_4LVL,
97 .pglvl = 4},
98 {.agaw = 57, .cap = DMAR_CAP_SAGAW_5LVL, .awlvl = DMAR_CTX2_AW_5LVL,
99 .pglvl = 5}
100 /*
101 * 6-level paging (DMAR_CAP_SAGAW_6LVL) is not supported on any
102 * current VT-d hardware and its SAGAW field value is listed as
103 * reserved in the VT-d spec. If support is added in the future,
104 * this structure and the logic in dmar_maxaddr2mgaw() will need
105 * to change to avoid attempted comparison against 1ULL << 64.
106 */
107 };
108
109 bool
dmar_pglvl_supported(struct dmar_unit * unit,int pglvl)110 dmar_pglvl_supported(struct dmar_unit *unit, int pglvl)
111 {
112 int i;
113
114 for (i = 0; i < nitems(sagaw_bits); i++) {
115 if (sagaw_bits[i].pglvl != pglvl)
116 continue;
117 if ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0)
118 return (true);
119 }
120 return (false);
121 }
122
123 int
domain_set_agaw(struct dmar_domain * domain,int mgaw)124 domain_set_agaw(struct dmar_domain *domain, int mgaw)
125 {
126 int sagaw, i;
127
128 domain->mgaw = mgaw;
129 sagaw = DMAR_CAP_SAGAW(domain->dmar->hw_cap);
130 for (i = 0; i < nitems(sagaw_bits); i++) {
131 if (sagaw_bits[i].agaw >= mgaw) {
132 domain->agaw = sagaw_bits[i].agaw;
133 domain->pglvl = sagaw_bits[i].pglvl;
134 domain->awlvl = sagaw_bits[i].awlvl;
135 return (0);
136 }
137 }
138 device_printf(domain->dmar->dev,
139 "context request mgaw %d: no agaw found, sagaw %x\n",
140 mgaw, sagaw);
141 return (EINVAL);
142 }
143
144 /*
145 * Find a best fit mgaw for the given maxaddr:
146 * - if allow_less is false, must find sagaw which maps all requested
147 * addresses (used by identity mappings);
148 * - if allow_less is true, and no supported sagaw can map all requested
149 * address space, accept the biggest sagaw, whatever is it.
150 */
151 int
dmar_maxaddr2mgaw(struct dmar_unit * unit,iommu_gaddr_t maxaddr,bool allow_less)152 dmar_maxaddr2mgaw(struct dmar_unit *unit, iommu_gaddr_t maxaddr, bool allow_less)
153 {
154 int i;
155
156 for (i = 0; i < nitems(sagaw_bits); i++) {
157 if ((1ULL << sagaw_bits[i].agaw) >= maxaddr &&
158 (DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0)
159 break;
160 }
161 if (allow_less && i == nitems(sagaw_bits)) {
162 do {
163 i--;
164 } while ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap)
165 == 0);
166 }
167 if (i < nitems(sagaw_bits))
168 return (sagaw_bits[i].agaw);
169 KASSERT(0, ("no mgaw for maxaddr %jx allow_less %d",
170 (uintmax_t) maxaddr, allow_less));
171 return (-1);
172 }
173
174 /*
175 * Calculate the total amount of page table pages needed to map the
176 * whole bus address space on the context with the selected agaw.
177 */
178 vm_pindex_t
pglvl_max_pages(int pglvl)179 pglvl_max_pages(int pglvl)
180 {
181 vm_pindex_t res;
182 int i;
183
184 for (res = 0, i = pglvl; i > 0; i--) {
185 res *= DMAR_NPTEPG;
186 res++;
187 }
188 return (res);
189 }
190
191 /*
192 * Return true if the page table level lvl supports the superpage for
193 * the context ctx.
194 */
195 int
domain_is_sp_lvl(struct dmar_domain * domain,int lvl)196 domain_is_sp_lvl(struct dmar_domain *domain, int lvl)
197 {
198 int alvl, cap_sps;
199 static const int sagaw_sp[] = {
200 DMAR_CAP_SPS_2M,
201 DMAR_CAP_SPS_1G,
202 DMAR_CAP_SPS_512G,
203 DMAR_CAP_SPS_1T
204 };
205
206 alvl = domain->pglvl - lvl - 1;
207 cap_sps = DMAR_CAP_SPS(domain->dmar->hw_cap);
208 return (alvl < nitems(sagaw_sp) && (sagaw_sp[alvl] & cap_sps) != 0);
209 }
210
211 iommu_gaddr_t
pglvl_page_size(int total_pglvl,int lvl)212 pglvl_page_size(int total_pglvl, int lvl)
213 {
214 int rlvl;
215 static const iommu_gaddr_t pg_sz[] = {
216 (iommu_gaddr_t)DMAR_PAGE_SIZE,
217 (iommu_gaddr_t)DMAR_PAGE_SIZE << DMAR_NPTEPGSHIFT,
218 (iommu_gaddr_t)DMAR_PAGE_SIZE << (2 * DMAR_NPTEPGSHIFT),
219 (iommu_gaddr_t)DMAR_PAGE_SIZE << (3 * DMAR_NPTEPGSHIFT),
220 (iommu_gaddr_t)DMAR_PAGE_SIZE << (4 * DMAR_NPTEPGSHIFT),
221 (iommu_gaddr_t)DMAR_PAGE_SIZE << (5 * DMAR_NPTEPGSHIFT)
222 };
223
224 KASSERT(lvl >= 0 && lvl < total_pglvl,
225 ("total %d lvl %d", total_pglvl, lvl));
226 rlvl = total_pglvl - lvl - 1;
227 KASSERT(rlvl < nitems(pg_sz), ("sizeof pg_sz lvl %d", lvl));
228 return (pg_sz[rlvl]);
229 }
230
231 iommu_gaddr_t
domain_page_size(struct dmar_domain * domain,int lvl)232 domain_page_size(struct dmar_domain *domain, int lvl)
233 {
234
235 return (pglvl_page_size(domain->pglvl, lvl));
236 }
237
238 int
calc_am(struct dmar_unit * unit,iommu_gaddr_t base,iommu_gaddr_t size,iommu_gaddr_t * isizep)239 calc_am(struct dmar_unit *unit, iommu_gaddr_t base, iommu_gaddr_t size,
240 iommu_gaddr_t *isizep)
241 {
242 iommu_gaddr_t isize;
243 int am;
244
245 for (am = DMAR_CAP_MAMV(unit->hw_cap);; am--) {
246 isize = 1ULL << (am + DMAR_PAGE_SHIFT);
247 if ((base & (isize - 1)) == 0 && size >= isize)
248 break;
249 if (am == 0)
250 break;
251 }
252 *isizep = isize;
253 return (am);
254 }
255
256 iommu_haddr_t dmar_high;
257 int haw;
258 int dmar_tbl_pagecnt;
259
260 vm_page_t
dmar_pgalloc(vm_object_t obj,vm_pindex_t idx,int flags)261 dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags)
262 {
263 vm_page_t m;
264 int zeroed, aflags;
265
266 zeroed = (flags & IOMMU_PGF_ZERO) != 0 ? VM_ALLOC_ZERO : 0;
267 aflags = zeroed | VM_ALLOC_NOBUSY | VM_ALLOC_SYSTEM | VM_ALLOC_NODUMP |
268 ((flags & IOMMU_PGF_WAITOK) != 0 ? VM_ALLOC_WAITFAIL :
269 VM_ALLOC_NOWAIT);
270 for (;;) {
271 if ((flags & IOMMU_PGF_OBJL) == 0)
272 VM_OBJECT_WLOCK(obj);
273 m = vm_page_lookup(obj, idx);
274 if ((flags & IOMMU_PGF_NOALLOC) != 0 || m != NULL) {
275 if ((flags & IOMMU_PGF_OBJL) == 0)
276 VM_OBJECT_WUNLOCK(obj);
277 break;
278 }
279 m = vm_page_alloc_contig(obj, idx, aflags, 1, 0,
280 dmar_high, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
281 if ((flags & IOMMU_PGF_OBJL) == 0)
282 VM_OBJECT_WUNLOCK(obj);
283 if (m != NULL) {
284 if (zeroed && (m->flags & PG_ZERO) == 0)
285 pmap_zero_page(m);
286 atomic_add_int(&dmar_tbl_pagecnt, 1);
287 break;
288 }
289 if ((flags & IOMMU_PGF_WAITOK) == 0)
290 break;
291 }
292 return (m);
293 }
294
295 void
dmar_pgfree(vm_object_t obj,vm_pindex_t idx,int flags)296 dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags)
297 {
298 vm_page_t m;
299
300 if ((flags & IOMMU_PGF_OBJL) == 0)
301 VM_OBJECT_WLOCK(obj);
302 m = vm_page_grab(obj, idx, VM_ALLOC_NOCREAT);
303 if (m != NULL) {
304 vm_page_free(m);
305 atomic_subtract_int(&dmar_tbl_pagecnt, 1);
306 }
307 if ((flags & IOMMU_PGF_OBJL) == 0)
308 VM_OBJECT_WUNLOCK(obj);
309 }
310
311 void *
dmar_map_pgtbl(vm_object_t obj,vm_pindex_t idx,int flags,struct sf_buf ** sf)312 dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags,
313 struct sf_buf **sf)
314 {
315 vm_page_t m;
316 bool allocated;
317
318 if ((flags & IOMMU_PGF_OBJL) == 0)
319 VM_OBJECT_WLOCK(obj);
320 m = vm_page_lookup(obj, idx);
321 if (m == NULL && (flags & IOMMU_PGF_ALLOC) != 0) {
322 m = dmar_pgalloc(obj, idx, flags | IOMMU_PGF_OBJL);
323 allocated = true;
324 } else
325 allocated = false;
326 if (m == NULL) {
327 if ((flags & IOMMU_PGF_OBJL) == 0)
328 VM_OBJECT_WUNLOCK(obj);
329 return (NULL);
330 }
331 /* Sleepable allocations cannot fail. */
332 if ((flags & IOMMU_PGF_WAITOK) != 0)
333 VM_OBJECT_WUNLOCK(obj);
334 sched_pin();
335 *sf = sf_buf_alloc(m, SFB_CPUPRIVATE | ((flags & IOMMU_PGF_WAITOK)
336 == 0 ? SFB_NOWAIT : 0));
337 if (*sf == NULL) {
338 sched_unpin();
339 if (allocated) {
340 VM_OBJECT_ASSERT_WLOCKED(obj);
341 dmar_pgfree(obj, m->pindex, flags | IOMMU_PGF_OBJL);
342 }
343 if ((flags & IOMMU_PGF_OBJL) == 0)
344 VM_OBJECT_WUNLOCK(obj);
345 return (NULL);
346 }
347 if ((flags & (IOMMU_PGF_WAITOK | IOMMU_PGF_OBJL)) ==
348 (IOMMU_PGF_WAITOK | IOMMU_PGF_OBJL))
349 VM_OBJECT_WLOCK(obj);
350 else if ((flags & (IOMMU_PGF_WAITOK | IOMMU_PGF_OBJL)) == 0)
351 VM_OBJECT_WUNLOCK(obj);
352 return ((void *)sf_buf_kva(*sf));
353 }
354
355 void
dmar_unmap_pgtbl(struct sf_buf * sf)356 dmar_unmap_pgtbl(struct sf_buf *sf)
357 {
358
359 sf_buf_free(sf);
360 sched_unpin();
361 }
362
363 static void
dmar_flush_transl_to_ram(struct dmar_unit * unit,void * dst,size_t sz)364 dmar_flush_transl_to_ram(struct dmar_unit *unit, void *dst, size_t sz)
365 {
366
367 if (DMAR_IS_COHERENT(unit))
368 return;
369 /*
370 * If DMAR does not snoop paging structures accesses, flush
371 * CPU cache to memory.
372 */
373 pmap_force_invalidate_cache_range((uintptr_t)dst, (uintptr_t)dst + sz);
374 }
375
376 void
dmar_flush_pte_to_ram(struct dmar_unit * unit,dmar_pte_t * dst)377 dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst)
378 {
379
380 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
381 }
382
383 void
dmar_flush_ctx_to_ram(struct dmar_unit * unit,dmar_ctx_entry_t * dst)384 dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst)
385 {
386
387 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
388 }
389
390 void
dmar_flush_root_to_ram(struct dmar_unit * unit,dmar_root_entry_t * dst)391 dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst)
392 {
393
394 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
395 }
396
397 /*
398 * Load the root entry pointer into the hardware, busily waiting for
399 * the completion.
400 */
401 int
dmar_load_root_entry_ptr(struct dmar_unit * unit)402 dmar_load_root_entry_ptr(struct dmar_unit *unit)
403 {
404 vm_page_t root_entry;
405 int error;
406
407 /*
408 * Access to the GCMD register must be serialized while the
409 * command is submitted.
410 */
411 DMAR_ASSERT_LOCKED(unit);
412
413 VM_OBJECT_RLOCK(unit->ctx_obj);
414 root_entry = vm_page_lookup(unit->ctx_obj, 0);
415 VM_OBJECT_RUNLOCK(unit->ctx_obj);
416 dmar_write8(unit, DMAR_RTADDR_REG, VM_PAGE_TO_PHYS(root_entry));
417 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SRTP);
418 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_RTPS)
419 != 0));
420 return (error);
421 }
422
423 /*
424 * Globally invalidate the context entries cache, busily waiting for
425 * the completion.
426 */
427 int
dmar_inv_ctx_glob(struct dmar_unit * unit)428 dmar_inv_ctx_glob(struct dmar_unit *unit)
429 {
430 int error;
431
432 /*
433 * Access to the CCMD register must be serialized while the
434 * command is submitted.
435 */
436 DMAR_ASSERT_LOCKED(unit);
437 KASSERT(!unit->qi_enabled, ("QI enabled"));
438
439 /*
440 * The DMAR_CCMD_ICC bit in the upper dword should be written
441 * after the low dword write is completed. Amd64
442 * dmar_write8() does not have this issue, i386 dmar_write8()
443 * writes the upper dword last.
444 */
445 dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB);
446 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_CCMD_REG + 4) & DMAR_CCMD_ICC32)
447 == 0));
448 return (error);
449 }
450
451 /*
452 * Globally invalidate the IOTLB, busily waiting for the completion.
453 */
454 int
dmar_inv_iotlb_glob(struct dmar_unit * unit)455 dmar_inv_iotlb_glob(struct dmar_unit *unit)
456 {
457 int error, reg;
458
459 DMAR_ASSERT_LOCKED(unit);
460 KASSERT(!unit->qi_enabled, ("QI enabled"));
461
462 reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap);
463 /* See a comment about DMAR_CCMD_ICC in dmar_inv_ctx_glob. */
464 dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT |
465 DMAR_IOTLB_IIRG_GLB | DMAR_IOTLB_DR | DMAR_IOTLB_DW);
466 DMAR_WAIT_UNTIL(((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) &
467 DMAR_IOTLB_IVT32) == 0));
468 return (error);
469 }
470
471 /*
472 * Flush the chipset write buffers. See 11.1 "Write Buffer Flushing"
473 * in the architecture specification.
474 */
475 int
dmar_flush_write_bufs(struct dmar_unit * unit)476 dmar_flush_write_bufs(struct dmar_unit *unit)
477 {
478 int error;
479
480 DMAR_ASSERT_LOCKED(unit);
481
482 /*
483 * DMAR_GCMD_WBF is only valid when CAP_RWBF is reported.
484 */
485 KASSERT((unit->hw_cap & DMAR_CAP_RWBF) != 0,
486 ("dmar%d: no RWBF", unit->iommu.unit));
487
488 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_WBF);
489 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_WBFS)
490 != 0));
491 return (error);
492 }
493
494 /*
495 * Some BIOSes protect memory region they reside in by using DMAR to
496 * prevent devices from doing any DMA transactions to that part of RAM.
497 * AMI refers to this as "DMA Control Guarantee".
498 * We need to disable this when address translation is enabled.
499 */
500 int
dmar_disable_protected_regions(struct dmar_unit * unit)501 dmar_disable_protected_regions(struct dmar_unit *unit)
502 {
503 uint32_t reg;
504 int error;
505
506 DMAR_ASSERT_LOCKED(unit);
507
508 /* Check if we support the feature. */
509 if ((unit->hw_cap & (DMAR_CAP_PLMR | DMAR_CAP_PHMR)) == 0)
510 return (0);
511
512 reg = dmar_read4(unit, DMAR_PMEN_REG);
513 if ((reg & DMAR_PMEN_EPM) == 0)
514 return (0);
515
516 reg &= ~DMAR_PMEN_EPM;
517 dmar_write4(unit, DMAR_PMEN_REG, reg);
518 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_PMEN_REG) & DMAR_PMEN_PRS)
519 != 0));
520
521 return (error);
522 }
523
524 int
dmar_enable_translation(struct dmar_unit * unit)525 dmar_enable_translation(struct dmar_unit *unit)
526 {
527 int error;
528
529 DMAR_ASSERT_LOCKED(unit);
530 unit->hw_gcmd |= DMAR_GCMD_TE;
531 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
532 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES)
533 != 0));
534 return (error);
535 }
536
537 int
dmar_disable_translation(struct dmar_unit * unit)538 dmar_disable_translation(struct dmar_unit *unit)
539 {
540 int error;
541
542 DMAR_ASSERT_LOCKED(unit);
543 unit->hw_gcmd &= ~DMAR_GCMD_TE;
544 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
545 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES)
546 == 0));
547 return (error);
548 }
549
550 int
dmar_load_irt_ptr(struct dmar_unit * unit)551 dmar_load_irt_ptr(struct dmar_unit *unit)
552 {
553 uint64_t irta, s;
554 int error;
555
556 DMAR_ASSERT_LOCKED(unit);
557 irta = unit->irt_phys;
558 if (DMAR_X2APIC(unit))
559 irta |= DMAR_IRTA_EIME;
560 s = fls(unit->irte_cnt) - 2;
561 KASSERT(unit->irte_cnt >= 2 && s <= DMAR_IRTA_S_MASK &&
562 powerof2(unit->irte_cnt),
563 ("IRTA_REG_S overflow %x", unit->irte_cnt));
564 irta |= s;
565 dmar_write8(unit, DMAR_IRTA_REG, irta);
566 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SIRTP);
567 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRTPS)
568 != 0));
569 return (error);
570 }
571
572 int
dmar_enable_ir(struct dmar_unit * unit)573 dmar_enable_ir(struct dmar_unit *unit)
574 {
575 int error;
576
577 DMAR_ASSERT_LOCKED(unit);
578 unit->hw_gcmd |= DMAR_GCMD_IRE;
579 unit->hw_gcmd &= ~DMAR_GCMD_CFI;
580 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
581 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES)
582 != 0));
583 return (error);
584 }
585
586 int
dmar_disable_ir(struct dmar_unit * unit)587 dmar_disable_ir(struct dmar_unit *unit)
588 {
589 int error;
590
591 DMAR_ASSERT_LOCKED(unit);
592 unit->hw_gcmd &= ~DMAR_GCMD_IRE;
593 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
594 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES)
595 == 0));
596 return (error);
597 }
598
599 #define BARRIER_F \
600 u_int f_done, f_inproc, f_wakeup; \
601 \
602 f_done = 1 << (barrier_id * 3); \
603 f_inproc = 1 << (barrier_id * 3 + 1); \
604 f_wakeup = 1 << (barrier_id * 3 + 2)
605
606 bool
dmar_barrier_enter(struct dmar_unit * dmar,u_int barrier_id)607 dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id)
608 {
609 BARRIER_F;
610
611 DMAR_LOCK(dmar);
612 if ((dmar->barrier_flags & f_done) != 0) {
613 DMAR_UNLOCK(dmar);
614 return (false);
615 }
616
617 if ((dmar->barrier_flags & f_inproc) != 0) {
618 while ((dmar->barrier_flags & f_inproc) != 0) {
619 dmar->barrier_flags |= f_wakeup;
620 msleep(&dmar->barrier_flags, &dmar->iommu.lock, 0,
621 "dmarb", 0);
622 }
623 KASSERT((dmar->barrier_flags & f_done) != 0,
624 ("dmar%d barrier %d missing done", dmar->iommu.unit,
625 barrier_id));
626 DMAR_UNLOCK(dmar);
627 return (false);
628 }
629
630 dmar->barrier_flags |= f_inproc;
631 DMAR_UNLOCK(dmar);
632 return (true);
633 }
634
635 void
dmar_barrier_exit(struct dmar_unit * dmar,u_int barrier_id)636 dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id)
637 {
638 BARRIER_F;
639
640 DMAR_ASSERT_LOCKED(dmar);
641 KASSERT((dmar->barrier_flags & (f_done | f_inproc)) == f_inproc,
642 ("dmar%d barrier %d missed entry", dmar->iommu.unit, barrier_id));
643 dmar->barrier_flags |= f_done;
644 if ((dmar->barrier_flags & f_wakeup) != 0)
645 wakeup(&dmar->barrier_flags);
646 dmar->barrier_flags &= ~(f_inproc | f_wakeup);
647 DMAR_UNLOCK(dmar);
648 }
649
650 int dmar_batch_coalesce = 100;
651 struct timespec dmar_hw_timeout = {
652 .tv_sec = 0,
653 .tv_nsec = 1000000
654 };
655
656 static const uint64_t d = 1000000000;
657
658 void
dmar_update_timeout(uint64_t newval)659 dmar_update_timeout(uint64_t newval)
660 {
661
662 /* XXXKIB not atomic */
663 dmar_hw_timeout.tv_sec = newval / d;
664 dmar_hw_timeout.tv_nsec = newval % d;
665 }
666
667 uint64_t
dmar_get_timeout(void)668 dmar_get_timeout(void)
669 {
670
671 return ((uint64_t)dmar_hw_timeout.tv_sec * d +
672 dmar_hw_timeout.tv_nsec);
673 }
674
675 static int
dmar_timeout_sysctl(SYSCTL_HANDLER_ARGS)676 dmar_timeout_sysctl(SYSCTL_HANDLER_ARGS)
677 {
678 uint64_t val;
679 int error;
680
681 val = dmar_get_timeout();
682 error = sysctl_handle_long(oidp, &val, 0, req);
683 if (error != 0 || req->newptr == NULL)
684 return (error);
685 dmar_update_timeout(val);
686 return (error);
687 }
688
689 static SYSCTL_NODE(_hw_iommu, OID_AUTO, dmar, CTLFLAG_RD | CTLFLAG_MPSAFE,
690 NULL, "");
691 SYSCTL_INT(_hw_iommu_dmar, OID_AUTO, tbl_pagecnt, CTLFLAG_RD,
692 &dmar_tbl_pagecnt, 0,
693 "Count of pages used for DMAR pagetables");
694 SYSCTL_INT(_hw_iommu_dmar, OID_AUTO, batch_coalesce, CTLFLAG_RWTUN,
695 &dmar_batch_coalesce, 0,
696 "Number of qi batches between interrupt");
697 SYSCTL_PROC(_hw_iommu_dmar, OID_AUTO, timeout,
698 CTLTYPE_U64 | CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 0,
699 dmar_timeout_sysctl, "QU",
700 "Timeout for command wait, in nanoseconds");
701