1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
9
10 #include <linux/debugfs.h>
11 #include <linux/dma-buf.h>
12
13 #include <drm/drm_atomic.h>
14 #include <drm/drm_atomic_uapi.h>
15 #include <drm/drm_blend.h>
16 #include <drm/drm_damage_helper.h>
17 #include <drm/drm_framebuffer.h>
18 #include <drm/drm_gem_atomic_helper.h>
19
20 #include "msm_drv.h"
21 #include "dpu_kms.h"
22 #include "dpu_formats.h"
23 #include "dpu_hw_sspp.h"
24 #include "dpu_hw_util.h"
25 #include "dpu_trace.h"
26 #include "dpu_crtc.h"
27 #include "dpu_vbif.h"
28 #include "dpu_plane.h"
29
30 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\
31 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
32
33 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\
34 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
35
36 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
37 #define PHASE_STEP_SHIFT 21
38 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
39 #define PHASE_RESIDUAL 15
40
41 #define SHARP_STRENGTH_DEFAULT 32
42 #define SHARP_EDGE_THR_DEFAULT 112
43 #define SHARP_SMOOTH_THR_DEFAULT 8
44 #define SHARP_NOISE_THR_DEFAULT 2
45
46 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31)
47 #define DPU_ZPOS_MAX 255
48
49 /*
50 * Default Preload Values
51 */
52 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4
53 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3
54 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2
55 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4
56
57 #define DEFAULT_REFRESH_RATE 60
58
59 static const uint32_t qcom_compressed_supported_formats[] = {
60 DRM_FORMAT_ABGR8888,
61 DRM_FORMAT_ARGB8888,
62 DRM_FORMAT_XBGR8888,
63 DRM_FORMAT_XRGB8888,
64 DRM_FORMAT_ARGB2101010,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_BGR565,
67
68 DRM_FORMAT_NV12,
69 DRM_FORMAT_P010,
70 };
71
72 /*
73 * struct dpu_plane - local dpu plane structure
74 * @aspace: address space pointer
75 * @csc_ptr: Points to dpu_csc_cfg structure to use for current
76 * @catalog: Points to dpu catalog structure
77 * @revalidate: force revalidation of all the plane properties
78 */
79 struct dpu_plane {
80 struct drm_plane base;
81
82 enum dpu_sspp pipe;
83
84 uint32_t color_fill;
85 bool is_error;
86 bool is_rt_pipe;
87 const struct dpu_mdss_cfg *catalog;
88 };
89
90 static const uint64_t supported_format_modifiers[] = {
91 DRM_FORMAT_MOD_QCOM_COMPRESSED,
92 DRM_FORMAT_MOD_LINEAR,
93 DRM_FORMAT_MOD_INVALID
94 };
95
96 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base)
97
_dpu_plane_get_kms(struct drm_plane * plane)98 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
99 {
100 struct msm_drm_private *priv = plane->dev->dev_private;
101
102 return to_dpu_kms(priv->kms);
103 }
104
105 /**
106 * _dpu_plane_calc_bw - calculate bandwidth required for a plane
107 * @catalog: Points to dpu catalog structure
108 * @fmt: Pointer to source buffer format
109 * @mode: Pointer to drm display mode
110 * @pipe_cfg: Pointer to pipe configuration
111 * Result: Updates calculated bandwidth in the plane state.
112 * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest)
113 * Prefill BW Equation: line src bytes * line_time
114 */
_dpu_plane_calc_bw(const struct dpu_mdss_cfg * catalog,const struct msm_format * fmt,const struct drm_display_mode * mode,struct dpu_sw_pipe_cfg * pipe_cfg)115 static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog,
116 const struct msm_format *fmt,
117 const struct drm_display_mode *mode,
118 struct dpu_sw_pipe_cfg *pipe_cfg)
119 {
120 int src_width, src_height, dst_height, fps;
121 u64 plane_pixel_rate, plane_bit_rate;
122 u64 plane_prefill_bw;
123 u64 plane_bw;
124 u32 hw_latency_lines;
125 u64 scale_factor;
126 int vbp, vpw, vfp;
127
128 src_width = drm_rect_width(&pipe_cfg->src_rect);
129 src_height = drm_rect_height(&pipe_cfg->src_rect);
130 dst_height = drm_rect_height(&pipe_cfg->dst_rect);
131 fps = drm_mode_vrefresh(mode);
132 vbp = mode->vtotal - mode->vsync_end;
133 vpw = mode->vsync_end - mode->vsync_start;
134 vfp = mode->vsync_start - mode->vdisplay;
135 hw_latency_lines = catalog->perf->min_prefill_lines;
136 scale_factor = src_height > dst_height ?
137 mult_frac(src_height, 1, dst_height) : 1;
138
139 plane_pixel_rate = src_width * mode->vtotal * fps;
140 plane_bit_rate = plane_pixel_rate * fmt->bpp;
141
142 plane_bw = plane_bit_rate * scale_factor;
143
144 plane_prefill_bw = plane_bw * hw_latency_lines;
145
146 if ((vbp+vpw) > hw_latency_lines)
147 do_div(plane_prefill_bw, (vbp+vpw));
148 else if ((vbp+vpw+vfp) < hw_latency_lines)
149 do_div(plane_prefill_bw, (vbp+vpw+vfp));
150 else
151 do_div(plane_prefill_bw, hw_latency_lines);
152
153
154 return max(plane_bw, plane_prefill_bw);
155 }
156
157 /**
158 * _dpu_plane_calc_clk - calculate clock required for a plane
159 * @mode: Pointer to drm display mode
160 * @pipe_cfg: Pointer to pipe configuration
161 * Result: Updates calculated clock in the plane state.
162 * Clock equation: dst_w * v_total * fps * (src_h / dst_h)
163 */
_dpu_plane_calc_clk(const struct drm_display_mode * mode,struct dpu_sw_pipe_cfg * pipe_cfg)164 static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode,
165 struct dpu_sw_pipe_cfg *pipe_cfg)
166 {
167 int dst_width, src_height, dst_height, fps;
168 u64 plane_clk;
169
170 src_height = drm_rect_height(&pipe_cfg->src_rect);
171 dst_width = drm_rect_width(&pipe_cfg->dst_rect);
172 dst_height = drm_rect_height(&pipe_cfg->dst_rect);
173 fps = drm_mode_vrefresh(mode);
174
175 plane_clk =
176 dst_width * mode->vtotal * fps;
177
178 if (src_height > dst_height) {
179 plane_clk *= src_height;
180 do_div(plane_clk, dst_height);
181 }
182
183 return plane_clk;
184 }
185
186 /**
187 * _dpu_plane_calc_fill_level - calculate fill level of the given source format
188 * @plane: Pointer to drm plane
189 * @pipe: Pointer to software pipe
190 * @lut_usage: LUT usecase
191 * @fmt: Pointer to source buffer format
192 * @src_width: width of source buffer
193 * Return: fill level corresponding to the source buffer/format or 0 if error
194 */
_dpu_plane_calc_fill_level(struct drm_plane * plane,struct dpu_sw_pipe * pipe,enum dpu_qos_lut_usage lut_usage,const struct msm_format * fmt,u32 src_width)195 static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
196 struct dpu_sw_pipe *pipe,
197 enum dpu_qos_lut_usage lut_usage,
198 const struct msm_format *fmt, u32 src_width)
199 {
200 struct dpu_plane *pdpu;
201 u32 fixed_buff_size;
202 u32 total_fl;
203
204 if (!fmt || !pipe || !src_width || !fmt->bpp) {
205 DPU_ERROR("invalid arguments\n");
206 return 0;
207 }
208
209 if (lut_usage == DPU_QOS_LUT_USAGE_NRT)
210 return 0;
211
212 pdpu = to_dpu_plane(plane);
213 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size;
214
215 /* FIXME: in multirect case account for the src_width of all the planes */
216
217 if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) {
218 if (fmt->chroma_sample == CHROMA_420) {
219 /* NV12 */
220 total_fl = (fixed_buff_size / 2) /
221 ((src_width + 32) * fmt->bpp);
222 } else {
223 /* non NV12 */
224 total_fl = (fixed_buff_size / 2) * 2 /
225 ((src_width + 32) * fmt->bpp);
226 }
227 } else {
228 if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
229 total_fl = (fixed_buff_size / 2) * 2 /
230 ((src_width + 32) * fmt->bpp);
231 } else {
232 total_fl = (fixed_buff_size) * 2 /
233 ((src_width + 32) * fmt->bpp);
234 }
235 }
236
237 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc w:%u fl:%u\n",
238 pipe->sspp->idx - SSPP_VIG0,
239 &fmt->pixel_format,
240 src_width, total_fl);
241
242 return total_fl;
243 }
244
245 /**
246 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane
247 * @plane: Pointer to drm plane
248 * @pipe: Pointer to software pipe
249 * @fmt: Pointer to source buffer format
250 * @pipe_cfg: Pointer to pipe configuration
251 */
_dpu_plane_set_qos_lut(struct drm_plane * plane,struct dpu_sw_pipe * pipe,const struct msm_format * fmt,struct dpu_sw_pipe_cfg * pipe_cfg)252 static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
253 struct dpu_sw_pipe *pipe,
254 const struct msm_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg)
255 {
256 struct dpu_plane *pdpu = to_dpu_plane(plane);
257 struct dpu_hw_qos_cfg cfg;
258 u32 total_fl, lut_usage;
259
260 if (!pdpu->is_rt_pipe) {
261 lut_usage = DPU_QOS_LUT_USAGE_NRT;
262 } else {
263 if (fmt && MSM_FORMAT_IS_LINEAR(fmt))
264 lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
265 else
266 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
267 }
268
269 total_fl = _dpu_plane_calc_fill_level(plane, pipe, lut_usage, fmt,
270 drm_rect_width(&pipe_cfg->src_rect));
271
272 cfg.creq_lut = _dpu_hw_get_qos_lut(&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl);
273 cfg.danger_lut = pdpu->catalog->perf->danger_lut_tbl[lut_usage];
274 cfg.safe_lut = pdpu->catalog->perf->safe_lut_tbl[lut_usage];
275
276 if (pipe->sspp->idx != SSPP_CURSOR0 &&
277 pipe->sspp->idx != SSPP_CURSOR1 &&
278 pdpu->is_rt_pipe)
279 cfg.danger_safe_en = true;
280
281 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n",
282 pdpu->pipe - SSPP_VIG0,
283 cfg.danger_safe_en,
284 pdpu->is_rt_pipe);
285
286 trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0,
287 (fmt) ? fmt->pixel_format : 0,
288 pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage);
289
290 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc rt:%d fl:%u lut:0x%llx\n",
291 pdpu->pipe - SSPP_VIG0,
292 fmt ? &fmt->pixel_format : NULL,
293 pdpu->is_rt_pipe, total_fl, cfg.creq_lut);
294
295 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
296 (fmt) ? fmt->pixel_format : 0,
297 (fmt) ? fmt->fetch_mode : 0,
298 cfg.danger_lut,
299 cfg.safe_lut);
300
301 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc mode:%d luts[0x%x, 0x%x]\n",
302 pdpu->pipe - SSPP_VIG0,
303 fmt ? &fmt->pixel_format : NULL,
304 fmt ? fmt->fetch_mode : -1,
305 cfg.danger_lut,
306 cfg.safe_lut);
307
308 pipe->sspp->ops.setup_qos_lut(pipe->sspp, &cfg);
309 }
310
311 /**
312 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane
313 * @plane: Pointer to drm plane
314 * @pipe: Pointer to software pipe
315 * @enable: true to enable QoS control
316 */
_dpu_plane_set_qos_ctrl(struct drm_plane * plane,struct dpu_sw_pipe * pipe,bool enable)317 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
318 struct dpu_sw_pipe *pipe,
319 bool enable)
320 {
321 struct dpu_plane *pdpu = to_dpu_plane(plane);
322
323 if (!pdpu->is_rt_pipe)
324 enable = false;
325
326 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n",
327 pdpu->pipe - SSPP_VIG0,
328 enable,
329 pdpu->is_rt_pipe);
330
331 pipe->sspp->ops.setup_qos_ctrl(pipe->sspp,
332 enable);
333 }
334
_dpu_plane_sspp_clk_force_ctrl(struct dpu_hw_sspp * sspp,struct dpu_hw_mdp * mdp,bool enable,bool * forced_on)335 static bool _dpu_plane_sspp_clk_force_ctrl(struct dpu_hw_sspp *sspp,
336 struct dpu_hw_mdp *mdp,
337 bool enable, bool *forced_on)
338 {
339 if (sspp->ops.setup_clk_force_ctrl) {
340 *forced_on = sspp->ops.setup_clk_force_ctrl(sspp, enable);
341 return true;
342 }
343
344 if (mdp->ops.setup_clk_force_ctrl) {
345 *forced_on = mdp->ops.setup_clk_force_ctrl(mdp, sspp->cap->clk_ctrl, enable);
346 return true;
347 }
348
349 return false;
350 }
351
352 /**
353 * _dpu_plane_set_ot_limit - set OT limit for the given plane
354 * @plane: Pointer to drm plane
355 * @pipe: Pointer to software pipe
356 * @pipe_cfg: Pointer to pipe configuration
357 * @frame_rate: CRTC's frame rate
358 */
_dpu_plane_set_ot_limit(struct drm_plane * plane,struct dpu_sw_pipe * pipe,struct dpu_sw_pipe_cfg * pipe_cfg,int frame_rate)359 static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
360 struct dpu_sw_pipe *pipe,
361 struct dpu_sw_pipe_cfg *pipe_cfg,
362 int frame_rate)
363 {
364 struct dpu_plane *pdpu = to_dpu_plane(plane);
365 struct dpu_vbif_set_ot_params ot_params;
366 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
367 bool forced_on = false;
368
369 memset(&ot_params, 0, sizeof(ot_params));
370 ot_params.xin_id = pipe->sspp->cap->xin_id;
371 ot_params.num = pipe->sspp->idx - SSPP_NONE;
372 ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
373 ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
374 ot_params.is_wfd = !pdpu->is_rt_pipe;
375 ot_params.frame_rate = frame_rate;
376 ot_params.vbif_idx = VBIF_RT;
377 ot_params.rd = true;
378
379 if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,
380 true, &forced_on))
381 return;
382
383 dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
384
385 if (forced_on)
386 _dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,
387 false, &forced_on);
388 }
389
390 /**
391 * _dpu_plane_set_qos_remap - set vbif QoS for the given plane
392 * @plane: Pointer to drm plane
393 * @pipe: Pointer to software pipe
394 */
_dpu_plane_set_qos_remap(struct drm_plane * plane,struct dpu_sw_pipe * pipe)395 static void _dpu_plane_set_qos_remap(struct drm_plane *plane,
396 struct dpu_sw_pipe *pipe)
397 {
398 struct dpu_plane *pdpu = to_dpu_plane(plane);
399 struct dpu_vbif_set_qos_params qos_params;
400 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
401 bool forced_on = false;
402
403 memset(&qos_params, 0, sizeof(qos_params));
404 qos_params.vbif_idx = VBIF_RT;
405 qos_params.xin_id = pipe->sspp->cap->xin_id;
406 qos_params.num = pipe->sspp->idx - SSPP_VIG0;
407 qos_params.is_rt = pdpu->is_rt_pipe;
408
409 DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d\n",
410 qos_params.num,
411 qos_params.vbif_idx,
412 qos_params.xin_id, qos_params.is_rt);
413
414 if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,
415 true, &forced_on))
416 return;
417
418 dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
419
420 if (forced_on)
421 _dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,
422 false, &forced_on);
423 }
424
_dpu_plane_setup_scaler3(struct dpu_hw_sspp * pipe_hw,uint32_t src_w,uint32_t src_h,uint32_t dst_w,uint32_t dst_h,struct dpu_hw_scaler3_cfg * scale_cfg,const struct msm_format * fmt,uint32_t chroma_subsmpl_h,uint32_t chroma_subsmpl_v,unsigned int rotation)425 static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
426 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
427 struct dpu_hw_scaler3_cfg *scale_cfg,
428 const struct msm_format *fmt,
429 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v,
430 unsigned int rotation)
431 {
432 uint32_t i;
433 bool inline_rotation = rotation & DRM_MODE_ROTATE_90;
434
435 /*
436 * For inline rotation cases, scaler config is post-rotation,
437 * so swap the dimensions here. However, pixel extension will
438 * need pre-rotation settings.
439 */
440 if (inline_rotation)
441 swap(src_w, src_h);
442
443 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] =
444 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w);
445 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] =
446 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h);
447
448
449 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] =
450 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v;
451 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] =
452 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h;
453
454 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] =
455 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2];
456 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] =
457 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2];
458
459 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] =
460 scale_cfg->phase_step_x[DPU_SSPP_COMP_0];
461 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] =
462 scale_cfg->phase_step_y[DPU_SSPP_COMP_0];
463
464 for (i = 0; i < DPU_MAX_PLANES; i++) {
465 scale_cfg->src_width[i] = src_w;
466 scale_cfg->src_height[i] = src_h;
467 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) {
468 scale_cfg->src_width[i] /= chroma_subsmpl_h;
469 scale_cfg->src_height[i] /= chroma_subsmpl_v;
470 }
471
472 if (pipe_hw->cap->sblk->scaler_blk.version >= 0x3000) {
473 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
474 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
475 } else {
476 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H;
477 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
478 }
479 }
480 if (!(MSM_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
481 && (src_w == dst_w))
482 return;
483
484 scale_cfg->dst_width = dst_w;
485 scale_cfg->dst_height = dst_h;
486 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL;
487 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL;
488 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL;
489 scale_cfg->lut_flag = 0;
490 scale_cfg->blend_cfg = 1;
491 scale_cfg->enable = 1;
492 }
493
_dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg * scale_cfg,struct dpu_hw_pixel_ext * pixel_ext,uint32_t src_w,uint32_t src_h,uint32_t chroma_subsmpl_h,uint32_t chroma_subsmpl_v)494 static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg,
495 struct dpu_hw_pixel_ext *pixel_ext,
496 uint32_t src_w, uint32_t src_h,
497 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
498 {
499 int i;
500
501 for (i = 0; i < DPU_MAX_PLANES; i++) {
502 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) {
503 src_w /= chroma_subsmpl_h;
504 src_h /= chroma_subsmpl_v;
505 }
506
507 pixel_ext->num_ext_pxls_top[i] = src_h;
508 pixel_ext->num_ext_pxls_left[i] = src_w;
509 }
510 }
511
_dpu_plane_get_csc(struct dpu_sw_pipe * pipe,const struct msm_format * fmt)512 static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe,
513 const struct msm_format *fmt)
514 {
515 const struct dpu_csc_cfg *csc_ptr;
516
517 if (!MSM_FORMAT_IS_YUV(fmt))
518 return NULL;
519
520 if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features)
521 csc_ptr = &dpu_csc10_YUV2RGB_601L;
522 else
523 csc_ptr = &dpu_csc_YUV2RGB_601L;
524
525 return csc_ptr;
526 }
527
_dpu_plane_setup_scaler(struct dpu_sw_pipe * pipe,const struct msm_format * fmt,bool color_fill,struct dpu_sw_pipe_cfg * pipe_cfg,unsigned int rotation)528 static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
529 const struct msm_format *fmt, bool color_fill,
530 struct dpu_sw_pipe_cfg *pipe_cfg,
531 unsigned int rotation)
532 {
533 struct dpu_hw_sspp *pipe_hw = pipe->sspp;
534 const struct drm_format_info *info = drm_format_info(fmt->pixel_format);
535 struct dpu_hw_scaler3_cfg scaler3_cfg;
536 struct dpu_hw_pixel_ext pixel_ext;
537 u32 src_width = drm_rect_width(&pipe_cfg->src_rect);
538 u32 src_height = drm_rect_height(&pipe_cfg->src_rect);
539 u32 dst_width = drm_rect_width(&pipe_cfg->dst_rect);
540 u32 dst_height = drm_rect_height(&pipe_cfg->dst_rect);
541
542 memset(&scaler3_cfg, 0, sizeof(scaler3_cfg));
543 memset(&pixel_ext, 0, sizeof(pixel_ext));
544
545 /* don't chroma subsample if decimating */
546 /* update scaler. calculate default config for QSEED3 */
547 _dpu_plane_setup_scaler3(pipe_hw,
548 src_width,
549 src_height,
550 dst_width,
551 dst_height,
552 &scaler3_cfg, fmt,
553 info->hsub, info->vsub,
554 rotation);
555
556 /* configure pixel extension based on scalar config */
557 _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext,
558 src_width, src_height, info->hsub, info->vsub);
559
560 if (pipe_hw->ops.setup_pe)
561 pipe_hw->ops.setup_pe(pipe_hw,
562 &pixel_ext);
563
564 /**
565 * when programmed in multirect mode, scalar block will be
566 * bypassed. Still we need to update alpha and bitwidth
567 * ONLY for RECT0
568 */
569 if (pipe_hw->ops.setup_scaler &&
570 pipe->multirect_index != DPU_SSPP_RECT_1)
571 pipe_hw->ops.setup_scaler(pipe_hw,
572 &scaler3_cfg,
573 fmt);
574 }
575
_dpu_plane_color_fill_pipe(struct dpu_plane_state * pstate,struct dpu_sw_pipe * pipe,struct drm_rect * dst_rect,u32 fill_color,const struct msm_format * fmt)576 static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
577 struct dpu_sw_pipe *pipe,
578 struct drm_rect *dst_rect,
579 u32 fill_color,
580 const struct msm_format *fmt)
581 {
582 struct dpu_sw_pipe_cfg pipe_cfg;
583
584 /* update sspp */
585 if (!pipe->sspp->ops.setup_solidfill)
586 return;
587
588 pipe->sspp->ops.setup_solidfill(pipe, fill_color);
589
590 /* override scaler/decimation if solid fill */
591 pipe_cfg.dst_rect = *dst_rect;
592
593 pipe_cfg.src_rect.x1 = 0;
594 pipe_cfg.src_rect.y1 = 0;
595 pipe_cfg.src_rect.x2 =
596 drm_rect_width(&pipe_cfg.dst_rect);
597 pipe_cfg.src_rect.y2 =
598 drm_rect_height(&pipe_cfg.dst_rect);
599
600 if (pipe->sspp->ops.setup_format)
601 pipe->sspp->ops.setup_format(pipe, fmt, DPU_SSPP_SOLID_FILL);
602
603 if (pipe->sspp->ops.setup_rects)
604 pipe->sspp->ops.setup_rects(pipe, &pipe_cfg);
605
606 _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation);
607 }
608
609 /**
610 * _dpu_plane_color_fill - enables color fill on plane
611 * @pdpu: Pointer to DPU plane object
612 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
613 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
614 */
_dpu_plane_color_fill(struct dpu_plane * pdpu,uint32_t color,uint32_t alpha)615 static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
616 uint32_t color, uint32_t alpha)
617 {
618 const struct msm_format *fmt;
619 const struct drm_plane *plane = &pdpu->base;
620 struct msm_drm_private *priv = plane->dev->dev_private;
621 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
622 u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24);
623
624 DPU_DEBUG_PLANE(pdpu, "\n");
625
626 /*
627 * select fill format to match user property expectation,
628 * h/w only supports RGB variants
629 */
630 fmt = mdp_get_format(priv->kms, DRM_FORMAT_ABGR8888, 0);
631 /* should not happen ever */
632 if (!fmt)
633 return;
634
635 /* update sspp */
636 _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect,
637 fill_color, fmt);
638
639 if (pstate->r_pipe.sspp)
640 _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect,
641 fill_color, fmt);
642 }
643
dpu_plane_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)644 static int dpu_plane_prepare_fb(struct drm_plane *plane,
645 struct drm_plane_state *new_state)
646 {
647 struct drm_framebuffer *fb = new_state->fb;
648 struct dpu_plane *pdpu = to_dpu_plane(plane);
649 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state);
650 struct dpu_hw_fmt_layout layout;
651 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
652 int ret;
653
654 if (!new_state->fb)
655 return 0;
656
657 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id);
658
659 /* cache aspace */
660 pstate->aspace = kms->base.aspace;
661
662 /*
663 * TODO: Need to sort out the msm_framebuffer_prepare() call below so
664 * we can use msm_atomic_prepare_fb() instead of doing the
665 * implicit fence and fb prepare by hand here.
666 */
667 drm_gem_plane_helper_prepare_fb(plane, new_state);
668
669 if (pstate->aspace) {
670 ret = msm_framebuffer_prepare(new_state->fb,
671 pstate->aspace, pstate->needs_dirtyfb);
672 if (ret) {
673 DPU_ERROR("failed to prepare framebuffer\n");
674 return ret;
675 }
676 }
677
678 /* validate framebuffer layout before commit */
679 ret = dpu_format_populate_layout(pstate->aspace,
680 new_state->fb, &layout);
681 if (ret) {
682 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
683 return ret;
684 }
685
686 return 0;
687 }
688
dpu_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * old_state)689 static void dpu_plane_cleanup_fb(struct drm_plane *plane,
690 struct drm_plane_state *old_state)
691 {
692 struct dpu_plane *pdpu = to_dpu_plane(plane);
693 struct dpu_plane_state *old_pstate;
694
695 if (!old_state || !old_state->fb)
696 return;
697
698 old_pstate = to_dpu_plane_state(old_state);
699
700 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id);
701
702 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace,
703 old_pstate->needs_dirtyfb);
704 }
705
dpu_plane_check_inline_rotation(struct dpu_plane * pdpu,const struct dpu_sspp_sub_blks * sblk,struct drm_rect src,const struct msm_format * fmt)706 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
707 const struct dpu_sspp_sub_blks *sblk,
708 struct drm_rect src, const struct msm_format *fmt)
709 {
710 size_t num_formats;
711 const u32 *supported_formats;
712
713 if (!sblk->rotation_cfg) {
714 DPU_ERROR("invalid rotation cfg\n");
715 return -EINVAL;
716 }
717
718 if (drm_rect_width(&src) > sblk->rotation_cfg->rot_maxheight) {
719 DPU_DEBUG_PLANE(pdpu, "invalid height for inline rot:%d max:%d\n",
720 src.y2, sblk->rotation_cfg->rot_maxheight);
721 return -EINVAL;
722 }
723
724 supported_formats = sblk->rotation_cfg->rot_format_list;
725 num_formats = sblk->rotation_cfg->rot_num_formats;
726
727 if (!MSM_FORMAT_IS_UBWC(fmt) ||
728 !dpu_find_format(fmt->pixel_format, supported_formats, num_formats))
729 return -EINVAL;
730
731 return 0;
732 }
733
dpu_plane_atomic_check_pipe(struct dpu_plane * pdpu,struct dpu_sw_pipe * pipe,struct dpu_sw_pipe_cfg * pipe_cfg,const struct msm_format * fmt,const struct drm_display_mode * mode)734 static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
735 struct dpu_sw_pipe *pipe,
736 struct dpu_sw_pipe_cfg *pipe_cfg,
737 const struct msm_format *fmt,
738 const struct drm_display_mode *mode)
739 {
740 uint32_t min_src_size;
741 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
742
743 min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1;
744
745 if (MSM_FORMAT_IS_YUV(fmt) &&
746 (!pipe->sspp->cap->sblk->scaler_blk.len ||
747 !pipe->sspp->cap->sblk->csc_blk.len)) {
748 DPU_DEBUG_PLANE(pdpu,
749 "plane doesn't have scaler/csc for yuv\n");
750 return -EINVAL;
751 }
752
753 /* check src bounds */
754 if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size ||
755 drm_rect_height(&pipe_cfg->src_rect) < min_src_size) {
756 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
757 DRM_RECT_ARG(&pipe_cfg->src_rect));
758 return -E2BIG;
759 }
760
761 /* valid yuv image */
762 if (MSM_FORMAT_IS_YUV(fmt) &&
763 (pipe_cfg->src_rect.x1 & 0x1 ||
764 pipe_cfg->src_rect.y1 & 0x1 ||
765 drm_rect_width(&pipe_cfg->src_rect) & 0x1 ||
766 drm_rect_height(&pipe_cfg->src_rect) & 0x1)) {
767 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
768 DRM_RECT_ARG(&pipe_cfg->src_rect));
769 return -EINVAL;
770 }
771
772 /* min dst support */
773 if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 ||
774 drm_rect_height(&pipe_cfg->dst_rect) < 0x1) {
775 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
776 DRM_RECT_ARG(&pipe_cfg->dst_rect));
777 return -EINVAL;
778 }
779
780 /* max clk check */
781 if (_dpu_plane_calc_clk(mode, pipe_cfg) > kms->perf.max_core_clk_rate) {
782 DPU_DEBUG_PLANE(pdpu, "plane exceeds max mdp core clk limits\n");
783 return -E2BIG;
784 }
785
786 return 0;
787 }
788
dpu_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)789 static int dpu_plane_atomic_check(struct drm_plane *plane,
790 struct drm_atomic_state *state)
791 {
792 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
793 plane);
794 int ret = 0, min_scale;
795 struct dpu_plane *pdpu = to_dpu_plane(plane);
796 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
797 u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate;
798 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
799 struct dpu_sw_pipe *pipe = &pstate->pipe;
800 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
801 const struct drm_crtc_state *crtc_state = NULL;
802 const struct msm_format *fmt;
803 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
804 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
805 struct drm_rect fb_rect = { 0 };
806 uint32_t max_linewidth;
807 unsigned int rotation;
808 uint32_t supported_rotations;
809 const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap;
810 const struct dpu_sspp_sub_blks *sblk = pstate->pipe.sspp->cap->sblk;
811
812 if (new_plane_state->crtc)
813 crtc_state = drm_atomic_get_new_crtc_state(state,
814 new_plane_state->crtc);
815
816 min_scale = FRAC_16_16(1, sblk->maxupscale);
817 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
818 min_scale,
819 sblk->maxdwnscale << 16,
820 true, true);
821 if (ret) {
822 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
823 return ret;
824 }
825 if (!new_plane_state->visible)
826 return 0;
827
828 pipe->multirect_index = DPU_SSPP_RECT_SOLO;
829 pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
830 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
831 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
832 r_pipe->sspp = NULL;
833
834 pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos;
835 if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) {
836 DPU_ERROR("> %d plane stages assigned\n",
837 pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0);
838 return -EINVAL;
839 }
840
841 pipe_cfg->src_rect = new_plane_state->src;
842
843 /* state->src is 16.16, src_rect is not */
844 pipe_cfg->src_rect.x1 >>= 16;
845 pipe_cfg->src_rect.x2 >>= 16;
846 pipe_cfg->src_rect.y1 >>= 16;
847 pipe_cfg->src_rect.y2 >>= 16;
848
849 pipe_cfg->dst_rect = new_plane_state->dst;
850
851 fb_rect.x2 = new_plane_state->fb->width;
852 fb_rect.y2 = new_plane_state->fb->height;
853
854 /* Ensure fb size is supported */
855 if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH ||
856 drm_rect_height(&fb_rect) > MAX_IMG_HEIGHT) {
857 DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n",
858 DRM_RECT_ARG(&fb_rect));
859 return -E2BIG;
860 }
861
862 fmt = msm_framebuffer_format(new_plane_state->fb);
863
864 max_linewidth = pdpu->catalog->caps->max_linewidth;
865
866 if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) ||
867 _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) {
868 /*
869 * In parallel multirect case only the half of the usual width
870 * is supported for tiled formats. If we are here, we know that
871 * full width is more than max_linewidth, thus each rect is
872 * wider than allowed.
873 */
874 if (MSM_FORMAT_IS_UBWC(fmt) &&
875 drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
876 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n",
877 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
878 return -E2BIG;
879 }
880
881 if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) {
882 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
883 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
884 return -E2BIG;
885 }
886
887 if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) ||
888 drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) ||
889 (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) &&
890 !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) ||
891 MSM_FORMAT_IS_YUV(fmt)) {
892 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n",
893 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
894 return -E2BIG;
895 }
896
897 /*
898 * Use multirect for wide plane. We do not support dynamic
899 * assignment of SSPPs, so we know the configuration.
900 */
901 pipe->multirect_index = DPU_SSPP_RECT_0;
902 pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
903
904 r_pipe->sspp = pipe->sspp;
905 r_pipe->multirect_index = DPU_SSPP_RECT_1;
906 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
907
908 *r_pipe_cfg = *pipe_cfg;
909 pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1;
910 pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1;
911 r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2;
912 r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2;
913 }
914
915 ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode);
916 if (ret)
917 return ret;
918
919 if (r_pipe->sspp) {
920 ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt,
921 &crtc_state->adjusted_mode);
922 if (ret)
923 return ret;
924 }
925
926 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0;
927
928 if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION))
929 supported_rotations |= DRM_MODE_ROTATE_90;
930
931 rotation = drm_rotation_simplify(new_plane_state->rotation,
932 supported_rotations);
933
934 if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) &&
935 (rotation & DRM_MODE_ROTATE_90)) {
936 ret = dpu_plane_check_inline_rotation(pdpu, sblk, pipe_cfg->src_rect, fmt);
937 if (ret)
938 return ret;
939 }
940
941 pstate->rotation = rotation;
942 pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state);
943
944 return 0;
945 }
946
dpu_plane_flush_csc(struct dpu_plane * pdpu,struct dpu_sw_pipe * pipe)947 static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe)
948 {
949 const struct msm_format *format =
950 msm_framebuffer_format(pdpu->base.state->fb);
951 const struct dpu_csc_cfg *csc_ptr;
952
953 if (!pipe->sspp || !pipe->sspp->ops.setup_csc)
954 return;
955
956 csc_ptr = _dpu_plane_get_csc(pipe, format);
957 if (!csc_ptr)
958 return;
959
960 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
961 csc_ptr->csc_mv[0],
962 csc_ptr->csc_mv[1],
963 csc_ptr->csc_mv[2]);
964
965 pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr);
966
967 }
968
dpu_plane_flush(struct drm_plane * plane)969 void dpu_plane_flush(struct drm_plane *plane)
970 {
971 struct dpu_plane *pdpu;
972 struct dpu_plane_state *pstate;
973
974 if (!plane || !plane->state) {
975 DPU_ERROR("invalid plane\n");
976 return;
977 }
978
979 pdpu = to_dpu_plane(plane);
980 pstate = to_dpu_plane_state(plane->state);
981
982 /*
983 * These updates have to be done immediately before the plane flush
984 * timing, and may not be moved to the atomic_update/mode_set functions.
985 */
986 if (pdpu->is_error)
987 /* force white frame with 100% alpha pipe output on error */
988 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF);
989 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
990 /* force 100% alpha */
991 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
992 else {
993 dpu_plane_flush_csc(pdpu, &pstate->pipe);
994 dpu_plane_flush_csc(pdpu, &pstate->r_pipe);
995 }
996
997 /* flag h/w flush complete */
998 if (plane->state)
999 pstate->pending = false;
1000 }
1001
1002 /**
1003 * dpu_plane_set_error: enable/disable error condition
1004 * @plane: pointer to drm_plane structure
1005 * @error: error value to set
1006 */
dpu_plane_set_error(struct drm_plane * plane,bool error)1007 void dpu_plane_set_error(struct drm_plane *plane, bool error)
1008 {
1009 struct dpu_plane *pdpu;
1010
1011 if (!plane)
1012 return;
1013
1014 pdpu = to_dpu_plane(plane);
1015 pdpu->is_error = error;
1016 }
1017
dpu_plane_sspp_update_pipe(struct drm_plane * plane,struct dpu_sw_pipe * pipe,struct dpu_sw_pipe_cfg * pipe_cfg,const struct msm_format * fmt,int frame_rate,struct dpu_hw_fmt_layout * layout)1018 static void dpu_plane_sspp_update_pipe(struct drm_plane *plane,
1019 struct dpu_sw_pipe *pipe,
1020 struct dpu_sw_pipe_cfg *pipe_cfg,
1021 const struct msm_format *fmt,
1022 int frame_rate,
1023 struct dpu_hw_fmt_layout *layout)
1024 {
1025 uint32_t src_flags;
1026 struct dpu_plane *pdpu = to_dpu_plane(plane);
1027 struct drm_plane_state *state = plane->state;
1028 struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1029
1030 if (layout && pipe->sspp->ops.setup_sourceaddress) {
1031 trace_dpu_plane_set_scanout(pipe, layout);
1032 pipe->sspp->ops.setup_sourceaddress(pipe, layout);
1033 }
1034
1035 /* override for color fill */
1036 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
1037 _dpu_plane_set_qos_ctrl(plane, pipe, false);
1038
1039 /* skip remaining processing on color fill */
1040 return;
1041 }
1042
1043 if (pipe->sspp->ops.setup_rects) {
1044 pipe->sspp->ops.setup_rects(pipe,
1045 pipe_cfg);
1046 }
1047
1048 _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation);
1049
1050 if (pipe->sspp->ops.setup_multirect)
1051 pipe->sspp->ops.setup_multirect(
1052 pipe);
1053
1054 if (pipe->sspp->ops.setup_format) {
1055 unsigned int rotation = pstate->rotation;
1056
1057 src_flags = 0x0;
1058
1059 if (rotation & DRM_MODE_REFLECT_X)
1060 src_flags |= DPU_SSPP_FLIP_LR;
1061
1062 if (rotation & DRM_MODE_REFLECT_Y)
1063 src_flags |= DPU_SSPP_FLIP_UD;
1064
1065 if (rotation & DRM_MODE_ROTATE_90)
1066 src_flags |= DPU_SSPP_ROT_90;
1067
1068 /* update format */
1069 pipe->sspp->ops.setup_format(pipe, fmt, src_flags);
1070
1071 if (pipe->sspp->ops.setup_cdp) {
1072 const struct dpu_perf_cfg *perf = pdpu->catalog->perf;
1073
1074 pipe->sspp->ops.setup_cdp(pipe, fmt,
1075 perf->cdp_cfg[DPU_PERF_CDP_USAGE_RT].rd_enable);
1076 }
1077 }
1078
1079 _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg);
1080
1081 if (pipe->sspp->idx != SSPP_CURSOR0 &&
1082 pipe->sspp->idx != SSPP_CURSOR1)
1083 _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate);
1084
1085 if (pstate->needs_qos_remap)
1086 _dpu_plane_set_qos_remap(plane, pipe);
1087 }
1088
dpu_plane_sspp_atomic_update(struct drm_plane * plane)1089 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
1090 {
1091 struct dpu_plane *pdpu = to_dpu_plane(plane);
1092 struct drm_plane_state *state = plane->state;
1093 struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1094 struct dpu_sw_pipe *pipe = &pstate->pipe;
1095 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1096 struct drm_crtc *crtc = state->crtc;
1097 struct drm_framebuffer *fb = state->fb;
1098 bool is_rt_pipe;
1099 const struct msm_format *fmt =
1100 msm_framebuffer_format(fb);
1101 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
1102 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
1103 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
1104 struct msm_gem_address_space *aspace = kms->base.aspace;
1105 struct dpu_hw_fmt_layout layout;
1106 bool layout_valid = false;
1107 int ret;
1108
1109 ret = dpu_format_populate_layout(aspace, fb, &layout);
1110 if (ret)
1111 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
1112 else
1113 layout_valid = true;
1114
1115 pstate->pending = true;
1116
1117 is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
1118 pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
1119 pdpu->is_rt_pipe = is_rt_pipe;
1120
1121 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
1122 ", %p4cc ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
1123 crtc->base.id, DRM_RECT_ARG(&state->dst),
1124 &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt));
1125
1126 dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt,
1127 drm_mode_vrefresh(&crtc->mode),
1128 layout_valid ? &layout : NULL);
1129
1130 if (r_pipe->sspp) {
1131 dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt,
1132 drm_mode_vrefresh(&crtc->mode),
1133 layout_valid ? &layout : NULL);
1134 }
1135
1136 if (pstate->needs_qos_remap)
1137 pstate->needs_qos_remap = false;
1138
1139 pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt,
1140 &crtc->mode, pipe_cfg);
1141
1142 pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg);
1143
1144 if (r_pipe->sspp) {
1145 pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg);
1146
1147 pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg));
1148 }
1149 }
1150
_dpu_plane_atomic_disable(struct drm_plane * plane)1151 static void _dpu_plane_atomic_disable(struct drm_plane *plane)
1152 {
1153 struct drm_plane_state *state = plane->state;
1154 struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1155 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1156
1157 trace_dpu_plane_disable(DRMID(plane), false,
1158 pstate->pipe.multirect_mode);
1159
1160 if (r_pipe->sspp) {
1161 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
1162 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1163
1164 if (r_pipe->sspp->ops.setup_multirect)
1165 r_pipe->sspp->ops.setup_multirect(r_pipe);
1166 }
1167
1168 pstate->pending = true;
1169 }
1170
dpu_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)1171 static void dpu_plane_atomic_update(struct drm_plane *plane,
1172 struct drm_atomic_state *state)
1173 {
1174 struct dpu_plane *pdpu = to_dpu_plane(plane);
1175 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
1176 plane);
1177
1178 pdpu->is_error = false;
1179
1180 DPU_DEBUG_PLANE(pdpu, "\n");
1181
1182 if (!new_state->visible) {
1183 _dpu_plane_atomic_disable(plane);
1184 } else {
1185 dpu_plane_sspp_atomic_update(plane);
1186 }
1187 }
1188
dpu_plane_destroy_state(struct drm_plane * plane,struct drm_plane_state * state)1189 static void dpu_plane_destroy_state(struct drm_plane *plane,
1190 struct drm_plane_state *state)
1191 {
1192 __drm_atomic_helper_plane_destroy_state(state);
1193 kfree(to_dpu_plane_state(state));
1194 }
1195
1196 static struct drm_plane_state *
dpu_plane_duplicate_state(struct drm_plane * plane)1197 dpu_plane_duplicate_state(struct drm_plane *plane)
1198 {
1199 struct dpu_plane *pdpu;
1200 struct dpu_plane_state *pstate;
1201 struct dpu_plane_state *old_state;
1202
1203 if (!plane) {
1204 DPU_ERROR("invalid plane\n");
1205 return NULL;
1206 } else if (!plane->state) {
1207 DPU_ERROR("invalid plane state\n");
1208 return NULL;
1209 }
1210
1211 old_state = to_dpu_plane_state(plane->state);
1212 pdpu = to_dpu_plane(plane);
1213 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1214 if (!pstate) {
1215 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1216 return NULL;
1217 }
1218
1219 DPU_DEBUG_PLANE(pdpu, "\n");
1220
1221 pstate->pending = false;
1222
1223 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
1224
1225 return &pstate->base;
1226 }
1227
1228 static const char * const multirect_mode_name[] = {
1229 [DPU_SSPP_MULTIRECT_NONE] = "none",
1230 [DPU_SSPP_MULTIRECT_PARALLEL] = "parallel",
1231 [DPU_SSPP_MULTIRECT_TIME_MX] = "time_mx",
1232 };
1233
1234 static const char * const multirect_index_name[] = {
1235 [DPU_SSPP_RECT_SOLO] = "solo",
1236 [DPU_SSPP_RECT_0] = "rect_0",
1237 [DPU_SSPP_RECT_1] = "rect_1",
1238 };
1239
dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode)1240 static const char *dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode)
1241 {
1242 if (WARN_ON(mode >= ARRAY_SIZE(multirect_mode_name)))
1243 return "unknown";
1244
1245 return multirect_mode_name[mode];
1246 }
1247
dpu_get_multirect_index(enum dpu_sspp_multirect_index index)1248 static const char *dpu_get_multirect_index(enum dpu_sspp_multirect_index index)
1249 {
1250 if (WARN_ON(index >= ARRAY_SIZE(multirect_index_name)))
1251 return "unknown";
1252
1253 return multirect_index_name[index];
1254 }
1255
dpu_plane_atomic_print_state(struct drm_printer * p,const struct drm_plane_state * state)1256 static void dpu_plane_atomic_print_state(struct drm_printer *p,
1257 const struct drm_plane_state *state)
1258 {
1259 const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1260 const struct dpu_sw_pipe *pipe = &pstate->pipe;
1261 const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
1262 const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1263 const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
1264
1265 drm_printf(p, "\tstage=%d\n", pstate->stage);
1266
1267 drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name);
1268 drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode));
1269 drm_printf(p, "\tmultirect_index[0]=%s\n",
1270 dpu_get_multirect_index(pipe->multirect_index));
1271 drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect));
1272 drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect));
1273
1274 if (r_pipe->sspp) {
1275 drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name);
1276 drm_printf(p, "\tmultirect_mode[1]=%s\n",
1277 dpu_get_multirect_mode(r_pipe->multirect_mode));
1278 drm_printf(p, "\tmultirect_index[1]=%s\n",
1279 dpu_get_multirect_index(r_pipe->multirect_index));
1280 drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect));
1281 drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect));
1282 }
1283 }
1284
dpu_plane_reset(struct drm_plane * plane)1285 static void dpu_plane_reset(struct drm_plane *plane)
1286 {
1287 struct dpu_plane *pdpu;
1288 struct dpu_plane_state *pstate;
1289 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1290
1291 if (!plane) {
1292 DPU_ERROR("invalid plane\n");
1293 return;
1294 }
1295
1296 pdpu = to_dpu_plane(plane);
1297 DPU_DEBUG_PLANE(pdpu, "\n");
1298
1299 /* remove previous state, if present */
1300 if (plane->state) {
1301 dpu_plane_destroy_state(plane, plane->state);
1302 plane->state = NULL;
1303 }
1304
1305 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
1306 if (!pstate) {
1307 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1308 return;
1309 }
1310
1311 /*
1312 * Set the SSPP here until we have proper virtualized DPU planes.
1313 * This is the place where the state is allocated, so fill it fully.
1314 */
1315 pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
1316 pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO;
1317 pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1318
1319 pstate->r_pipe.sspp = NULL;
1320
1321 __drm_atomic_helper_plane_reset(plane, &pstate->base);
1322 }
1323
1324 #ifdef CONFIG_DEBUG_FS
dpu_plane_danger_signal_ctrl(struct drm_plane * plane,bool enable)1325 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
1326 {
1327 struct dpu_plane *pdpu = to_dpu_plane(plane);
1328 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
1329 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1330
1331 if (!pdpu->is_rt_pipe)
1332 return;
1333
1334 pm_runtime_get_sync(&dpu_kms->pdev->dev);
1335 _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable);
1336 if (pstate->r_pipe.sspp)
1337 _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable);
1338 pm_runtime_put_sync(&dpu_kms->pdev->dev);
1339 }
1340 #endif
1341
dpu_plane_format_mod_supported(struct drm_plane * plane,uint32_t format,uint64_t modifier)1342 static bool dpu_plane_format_mod_supported(struct drm_plane *plane,
1343 uint32_t format, uint64_t modifier)
1344 {
1345 if (modifier == DRM_FORMAT_MOD_LINEAR)
1346 return true;
1347
1348 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED)
1349 return dpu_find_format(format, qcom_compressed_supported_formats,
1350 ARRAY_SIZE(qcom_compressed_supported_formats));
1351
1352 return false;
1353 }
1354
1355 static const struct drm_plane_funcs dpu_plane_funcs = {
1356 .update_plane = drm_atomic_helper_update_plane,
1357 .disable_plane = drm_atomic_helper_disable_plane,
1358 .reset = dpu_plane_reset,
1359 .atomic_duplicate_state = dpu_plane_duplicate_state,
1360 .atomic_destroy_state = dpu_plane_destroy_state,
1361 .atomic_print_state = dpu_plane_atomic_print_state,
1362 .format_mod_supported = dpu_plane_format_mod_supported,
1363 };
1364
1365 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = {
1366 .prepare_fb = dpu_plane_prepare_fb,
1367 .cleanup_fb = dpu_plane_cleanup_fb,
1368 .atomic_check = dpu_plane_atomic_check,
1369 .atomic_update = dpu_plane_atomic_update,
1370 };
1371
1372 /* initialize plane */
dpu_plane_init(struct drm_device * dev,uint32_t pipe,enum drm_plane_type type,unsigned long possible_crtcs)1373 struct drm_plane *dpu_plane_init(struct drm_device *dev,
1374 uint32_t pipe, enum drm_plane_type type,
1375 unsigned long possible_crtcs)
1376 {
1377 struct drm_plane *plane = NULL;
1378 const uint32_t *format_list;
1379 struct dpu_plane *pdpu;
1380 struct msm_drm_private *priv = dev->dev_private;
1381 struct dpu_kms *kms = to_dpu_kms(priv->kms);
1382 struct dpu_hw_sspp *pipe_hw;
1383 uint32_t num_formats;
1384 uint32_t supported_rotations;
1385 int ret;
1386
1387 /* initialize underlying h/w driver */
1388 pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
1389 if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) {
1390 DPU_ERROR("[%u]SSPP is invalid\n", pipe);
1391 return ERR_PTR(-EINVAL);
1392 }
1393
1394 format_list = pipe_hw->cap->sblk->format_list;
1395 num_formats = pipe_hw->cap->sblk->num_formats;
1396
1397 pdpu = drmm_universal_plane_alloc(dev, struct dpu_plane, base,
1398 0xff, &dpu_plane_funcs,
1399 format_list, num_formats,
1400 supported_format_modifiers, type, NULL);
1401 if (IS_ERR(pdpu))
1402 return ERR_CAST(pdpu);
1403
1404 /* cache local stuff for later */
1405 plane = &pdpu->base;
1406 pdpu->pipe = pipe;
1407
1408 pdpu->catalog = kms->catalog;
1409
1410 ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX);
1411 if (ret)
1412 DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
1413
1414 drm_plane_create_alpha_property(plane);
1415 drm_plane_create_blend_mode_property(plane,
1416 BIT(DRM_MODE_BLEND_PIXEL_NONE) |
1417 BIT(DRM_MODE_BLEND_PREMULTI) |
1418 BIT(DRM_MODE_BLEND_COVERAGE));
1419
1420 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1421
1422 if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION))
1423 supported_rotations |= DRM_MODE_ROTATE_MASK;
1424
1425 drm_plane_create_rotation_property(plane,
1426 DRM_MODE_ROTATE_0, supported_rotations);
1427
1428 drm_plane_enable_fb_damage_clips(plane);
1429
1430 /* success! finalize initialization */
1431 drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
1432
1433 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name,
1434 pipe, plane->base.id);
1435 return plane;
1436 }
1437