1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_5_1_SC8180X_H 8 #define _DPU_5_1_SC8180X_H 9 10 static const struct dpu_caps sc8180x_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .has_src_split = true, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .has_3d_merge = true, 17 .max_linewidth = 4096, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 .max_hdeci_exp = MAX_HORZ_DECIMATION, 20 .max_vdeci_exp = MAX_VERT_DECIMATION, 21 }; 22 23 static const struct dpu_mdp_cfg sc8180x_mdp = { 24 .name = "top_0", 25 .base = 0x0, .len = 0x45c, 26 .features = BIT(DPU_MDP_AUDIO_SELECT), 27 .clk_ctrls = { 28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 36 }, 37 }; 38 39 static const struct dpu_ctl_cfg sc8180x_ctl[] = { 40 { 41 .name = "ctl_0", .id = CTL_0, 42 .base = 0x1000, .len = 0x1e0, 43 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 45 }, { 46 .name = "ctl_1", .id = CTL_1, 47 .base = 0x1200, .len = 0x1e0, 48 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 50 }, { 51 .name = "ctl_2", .id = CTL_2, 52 .base = 0x1400, .len = 0x1e0, 53 .features = BIT(DPU_CTL_ACTIVE_CFG), 54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 55 }, { 56 .name = "ctl_3", .id = CTL_3, 57 .base = 0x1600, .len = 0x1e0, 58 .features = BIT(DPU_CTL_ACTIVE_CFG), 59 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 60 }, { 61 .name = "ctl_4", .id = CTL_4, 62 .base = 0x1800, .len = 0x1e0, 63 .features = BIT(DPU_CTL_ACTIVE_CFG), 64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 65 }, { 66 .name = "ctl_5", .id = CTL_5, 67 .base = 0x1a00, .len = 0x1e0, 68 .features = BIT(DPU_CTL_ACTIVE_CFG), 69 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 70 }, 71 }; 72 73 static const struct dpu_sspp_cfg sc8180x_sspp[] = { 74 { 75 .name = "sspp_0", .id = SSPP_VIG0, 76 .base = 0x4000, .len = 0x1f0, 77 .features = VIG_SDM845_MASK, 78 .sblk = &dpu_vig_sblk_qseed3_1_4, 79 .xin_id = 0, 80 .type = SSPP_TYPE_VIG, 81 .clk_ctrl = DPU_CLK_CTRL_VIG0, 82 }, { 83 .name = "sspp_1", .id = SSPP_VIG1, 84 .base = 0x6000, .len = 0x1f0, 85 .features = VIG_SDM845_MASK, 86 .sblk = &dpu_vig_sblk_qseed3_1_4, 87 .xin_id = 4, 88 .type = SSPP_TYPE_VIG, 89 .clk_ctrl = DPU_CLK_CTRL_VIG1, 90 }, { 91 .name = "sspp_2", .id = SSPP_VIG2, 92 .base = 0x8000, .len = 0x1f0, 93 .features = VIG_SDM845_MASK, 94 .sblk = &dpu_vig_sblk_qseed3_1_4, 95 .xin_id = 8, 96 .type = SSPP_TYPE_VIG, 97 .clk_ctrl = DPU_CLK_CTRL_VIG2, 98 }, { 99 .name = "sspp_3", .id = SSPP_VIG3, 100 .base = 0xa000, .len = 0x1f0, 101 .features = VIG_SDM845_MASK, 102 .sblk = &dpu_vig_sblk_qseed3_1_4, 103 .xin_id = 12, 104 .type = SSPP_TYPE_VIG, 105 .clk_ctrl = DPU_CLK_CTRL_VIG3, 106 }, { 107 .name = "sspp_8", .id = SSPP_DMA0, 108 .base = 0x24000, .len = 0x1f0, 109 .features = DMA_SDM845_MASK, 110 .sblk = &dpu_dma_sblk, 111 .xin_id = 1, 112 .type = SSPP_TYPE_DMA, 113 .clk_ctrl = DPU_CLK_CTRL_DMA0, 114 }, { 115 .name = "sspp_9", .id = SSPP_DMA1, 116 .base = 0x26000, .len = 0x1f0, 117 .features = DMA_SDM845_MASK, 118 .sblk = &dpu_dma_sblk, 119 .xin_id = 5, 120 .type = SSPP_TYPE_DMA, 121 .clk_ctrl = DPU_CLK_CTRL_DMA1, 122 }, { 123 .name = "sspp_10", .id = SSPP_DMA2, 124 .base = 0x28000, .len = 0x1f0, 125 .features = DMA_CURSOR_SDM845_MASK, 126 .sblk = &dpu_dma_sblk, 127 .xin_id = 9, 128 .type = SSPP_TYPE_DMA, 129 .clk_ctrl = DPU_CLK_CTRL_DMA2, 130 }, { 131 .name = "sspp_11", .id = SSPP_DMA3, 132 .base = 0x2a000, .len = 0x1f0, 133 .features = DMA_CURSOR_SDM845_MASK, 134 .sblk = &dpu_dma_sblk, 135 .xin_id = 13, 136 .type = SSPP_TYPE_DMA, 137 .clk_ctrl = DPU_CLK_CTRL_DMA3, 138 }, 139 }; 140 141 static const struct dpu_lm_cfg sc8180x_lm[] = { 142 { 143 .name = "lm_0", .id = LM_0, 144 .base = 0x44000, .len = 0x320, 145 .features = MIXER_SDM845_MASK, 146 .sblk = &sdm845_lm_sblk, 147 .lm_pair = LM_1, 148 .pingpong = PINGPONG_0, 149 .dspp = DSPP_0, 150 }, { 151 .name = "lm_1", .id = LM_1, 152 .base = 0x45000, .len = 0x320, 153 .features = MIXER_SDM845_MASK, 154 .sblk = &sdm845_lm_sblk, 155 .lm_pair = LM_0, 156 .pingpong = PINGPONG_1, 157 .dspp = DSPP_1, 158 }, { 159 .name = "lm_2", .id = LM_2, 160 .base = 0x46000, .len = 0x320, 161 .features = MIXER_SDM845_MASK, 162 .sblk = &sdm845_lm_sblk, 163 .lm_pair = LM_3, 164 .pingpong = PINGPONG_2, 165 }, { 166 .name = "lm_3", .id = LM_3, 167 .base = 0x47000, .len = 0x320, 168 .features = MIXER_SDM845_MASK, 169 .sblk = &sdm845_lm_sblk, 170 .lm_pair = LM_2, 171 .pingpong = PINGPONG_3, 172 }, { 173 .name = "lm_4", .id = LM_4, 174 .base = 0x48000, .len = 0x320, 175 .features = MIXER_SDM845_MASK, 176 .sblk = &sdm845_lm_sblk, 177 .lm_pair = LM_5, 178 .pingpong = PINGPONG_4, 179 }, { 180 .name = "lm_5", .id = LM_5, 181 .base = 0x49000, .len = 0x320, 182 .features = MIXER_SDM845_MASK, 183 .sblk = &sdm845_lm_sblk, 184 .lm_pair = LM_4, 185 .pingpong = PINGPONG_5, 186 }, 187 }; 188 189 static const struct dpu_dspp_cfg sc8180x_dspp[] = { 190 { 191 .name = "dspp_0", .id = DSPP_0, 192 .base = 0x54000, .len = 0x1800, 193 .features = DSPP_SC7180_MASK, 194 .sblk = &sdm845_dspp_sblk, 195 }, { 196 .name = "dspp_1", .id = DSPP_1, 197 .base = 0x56000, .len = 0x1800, 198 .features = DSPP_SC7180_MASK, 199 .sblk = &sdm845_dspp_sblk, 200 }, { 201 .name = "dspp_2", .id = DSPP_2, 202 .base = 0x58000, .len = 0x1800, 203 .features = DSPP_SC7180_MASK, 204 .sblk = &sdm845_dspp_sblk, 205 }, { 206 .name = "dspp_3", .id = DSPP_3, 207 .base = 0x5a000, .len = 0x1800, 208 .features = DSPP_SC7180_MASK, 209 .sblk = &sdm845_dspp_sblk, 210 }, 211 }; 212 213 static const struct dpu_pingpong_cfg sc8180x_pp[] = { 214 { 215 .name = "pingpong_0", .id = PINGPONG_0, 216 .base = 0x70000, .len = 0xd4, 217 .features = PINGPONG_SM8150_MASK, 218 .sblk = &sdm845_pp_sblk, 219 .merge_3d = MERGE_3D_0, 220 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 221 }, { 222 .name = "pingpong_1", .id = PINGPONG_1, 223 .base = 0x70800, .len = 0xd4, 224 .features = PINGPONG_SM8150_MASK, 225 .sblk = &sdm845_pp_sblk, 226 .merge_3d = MERGE_3D_0, 227 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 228 }, { 229 .name = "pingpong_2", .id = PINGPONG_2, 230 .base = 0x71000, .len = 0xd4, 231 .features = PINGPONG_SM8150_MASK, 232 .sblk = &sdm845_pp_sblk, 233 .merge_3d = MERGE_3D_1, 234 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 235 }, { 236 .name = "pingpong_3", .id = PINGPONG_3, 237 .base = 0x71800, .len = 0xd4, 238 .features = PINGPONG_SM8150_MASK, 239 .sblk = &sdm845_pp_sblk, 240 .merge_3d = MERGE_3D_1, 241 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 242 }, { 243 .name = "pingpong_4", .id = PINGPONG_4, 244 .base = 0x72000, .len = 0xd4, 245 .features = PINGPONG_SM8150_MASK, 246 .sblk = &sdm845_pp_sblk, 247 .merge_3d = MERGE_3D_2, 248 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 249 }, { 250 .name = "pingpong_5", .id = PINGPONG_5, 251 .base = 0x72800, .len = 0xd4, 252 .features = PINGPONG_SM8150_MASK, 253 .sblk = &sdm845_pp_sblk, 254 .merge_3d = MERGE_3D_2, 255 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 256 }, 257 }; 258 259 static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = { 260 { 261 .name = "merge_3d_0", .id = MERGE_3D_0, 262 .base = 0x83000, .len = 0x8, 263 }, { 264 .name = "merge_3d_1", .id = MERGE_3D_1, 265 .base = 0x83100, .len = 0x8, 266 }, { 267 .name = "merge_3d_2", .id = MERGE_3D_2, 268 .base = 0x83200, .len = 0x8, 269 }, 270 }; 271 272 static const struct dpu_dsc_cfg sc8180x_dsc[] = { 273 { 274 .name = "dsc_0", .id = DSC_0, 275 .base = 0x80000, .len = 0x140, 276 .features = BIT(DPU_DSC_OUTPUT_CTRL), 277 }, { 278 .name = "dsc_1", .id = DSC_1, 279 .base = 0x80400, .len = 0x140, 280 .features = BIT(DPU_DSC_OUTPUT_CTRL), 281 }, { 282 .name = "dsc_2", .id = DSC_2, 283 .base = 0x80800, .len = 0x140, 284 .features = BIT(DPU_DSC_OUTPUT_CTRL), 285 }, { 286 .name = "dsc_3", .id = DSC_3, 287 .base = 0x80c00, .len = 0x140, 288 .features = BIT(DPU_DSC_OUTPUT_CTRL), 289 }, { 290 .name = "dsc_4", .id = DSC_4, 291 .base = 0x81000, .len = 0x140, 292 .features = BIT(DPU_DSC_OUTPUT_CTRL), 293 }, { 294 .name = "dsc_5", .id = DSC_5, 295 .base = 0x81400, .len = 0x140, 296 .features = BIT(DPU_DSC_OUTPUT_CTRL), 297 }, 298 }; 299 300 static const struct dpu_intf_cfg sc8180x_intf[] = { 301 { 302 .name = "intf_0", .id = INTF_0, 303 .base = 0x6a000, .len = 0x280, 304 .features = INTF_SC7180_MASK, 305 .type = INTF_DP, 306 .controller_id = MSM_DP_CONTROLLER_0, 307 .prog_fetch_lines_worst_case = 24, 308 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 309 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 310 }, { 311 .name = "intf_1", .id = INTF_1, 312 .base = 0x6a800, .len = 0x2bc, 313 .features = INTF_SC7180_MASK, 314 .type = INTF_DSI, 315 .controller_id = MSM_DSI_CONTROLLER_0, 316 .prog_fetch_lines_worst_case = 24, 317 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 318 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 319 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 320 }, { 321 .name = "intf_2", .id = INTF_2, 322 .base = 0x6b000, .len = 0x2bc, 323 .features = INTF_SC7180_MASK, 324 .type = INTF_DSI, 325 .controller_id = MSM_DSI_CONTROLLER_1, 326 .prog_fetch_lines_worst_case = 24, 327 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 328 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 329 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 330 }, 331 /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */ 332 { 333 .name = "intf_3", .id = INTF_3, 334 .base = 0x6b800, .len = 0x280, 335 .features = INTF_SC7180_MASK, 336 .type = INTF_DP, 337 .controller_id = 999, 338 .prog_fetch_lines_worst_case = 24, 339 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 340 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 341 }, { 342 .name = "intf_4", .id = INTF_4, 343 .base = 0x6c000, .len = 0x280, 344 .features = INTF_SC7180_MASK, 345 .type = INTF_DP, 346 .controller_id = MSM_DP_CONTROLLER_1, 347 .prog_fetch_lines_worst_case = 24, 348 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), 349 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), 350 }, { 351 .name = "intf_5", .id = INTF_5, 352 .base = 0x6c800, .len = 0x280, 353 .features = INTF_SC7180_MASK, 354 .type = INTF_DP, 355 .controller_id = MSM_DP_CONTROLLER_2, 356 .prog_fetch_lines_worst_case = 24, 357 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), 358 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), 359 }, 360 }; 361 362 static const struct dpu_perf_cfg sc8180x_perf_data = { 363 .max_bw_low = 9600000, 364 .max_bw_high = 9600000, 365 .min_core_ib = 2400000, 366 .min_llcc_ib = 800000, 367 .min_dram_ib = 800000, 368 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 369 .safe_lut_tbl = {0xfff0, 0xf000, 0xffff}, 370 .qos_lut_tbl = { 371 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 372 .entries = sc7180_qos_linear 373 }, 374 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 375 .entries = sc7180_qos_macrotile 376 }, 377 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 378 .entries = sc7180_qos_nrt 379 }, 380 /* TODO: macrotile-qseed is different from macrotile */ 381 }, 382 .cdp_cfg = { 383 {.rd_enable = 1, .wr_enable = 1}, 384 {.rd_enable = 1, .wr_enable = 0} 385 }, 386 .clk_inefficiency_factor = 105, 387 .bw_inefficiency_factor = 120, 388 }; 389 390 static const struct dpu_mdss_version sc8180x_mdss_ver = { 391 .core_major_ver = 5, 392 .core_minor_ver = 1, 393 }; 394 395 const struct dpu_mdss_cfg dpu_sc8180x_cfg = { 396 .mdss_ver = &sc8180x_mdss_ver, 397 .caps = &sc8180x_dpu_caps, 398 .mdp = &sc8180x_mdp, 399 .ctl_count = ARRAY_SIZE(sc8180x_ctl), 400 .ctl = sc8180x_ctl, 401 .sspp_count = ARRAY_SIZE(sc8180x_sspp), 402 .sspp = sc8180x_sspp, 403 .mixer_count = ARRAY_SIZE(sc8180x_lm), 404 .mixer = sc8180x_lm, 405 .dspp_count = ARRAY_SIZE(sc8180x_dspp), 406 .dspp = sc8180x_dspp, 407 .dsc_count = ARRAY_SIZE(sc8180x_dsc), 408 .dsc = sc8180x_dsc, 409 .pingpong_count = ARRAY_SIZE(sc8180x_pp), 410 .pingpong = sc8180x_pp, 411 .merge_3d_count = ARRAY_SIZE(sc8180x_merge_3d), 412 .merge_3d = sc8180x_merge_3d, 413 .intf_count = ARRAY_SIZE(sc8180x_intf), 414 .intf = sc8180x_intf, 415 .vbif_count = ARRAY_SIZE(sdm845_vbif), 416 .vbif = sdm845_vbif, 417 .perf = &sc8180x_perf_data, 418 }; 419 420 #endif 421