1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2023 Marijn Suijten <marijn.suijten@somainline.org>. All rights reserved. 4 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _DPU_5_4_SM6125_H 9 #define _DPU_5_4_SM6125_H 10 11 static const struct dpu_caps sm6125_dpu_caps = { 12 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 13 .max_mixer_blendstages = 0x6, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .max_linewidth = 2160, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 .max_hdeci_exp = MAX_HORZ_DECIMATION, 19 .max_vdeci_exp = MAX_VERT_DECIMATION, 20 }; 21 22 static const struct dpu_mdp_cfg sm6125_mdp = { 23 .name = "top_0", 24 .base = 0x0, .len = 0x45c, 25 .features = 0, 26 .clk_ctrls = { 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 30 }, 31 }; 32 33 static const struct dpu_ctl_cfg sm6125_ctl[] = { 34 { 35 .name = "ctl_0", .id = CTL_0, 36 .base = 0x1000, .len = 0x1e0, 37 .features = BIT(DPU_CTL_ACTIVE_CFG), 38 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 39 }, { 40 .name = "ctl_1", .id = CTL_1, 41 .base = 0x1200, .len = 0x1e0, 42 .features = BIT(DPU_CTL_ACTIVE_CFG), 43 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 44 }, { 45 .name = "ctl_2", .id = CTL_2, 46 .base = 0x1400, .len = 0x1e0, 47 .features = BIT(DPU_CTL_ACTIVE_CFG), 48 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 49 }, { 50 .name = "ctl_3", .id = CTL_3, 51 .base = 0x1600, .len = 0x1e0, 52 .features = BIT(DPU_CTL_ACTIVE_CFG), 53 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 54 }, { 55 .name = "ctl_4", .id = CTL_4, 56 .base = 0x1800, .len = 0x1e0, 57 .features = BIT(DPU_CTL_ACTIVE_CFG), 58 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 59 }, { 60 .name = "ctl_5", .id = CTL_5, 61 .base = 0x1a00, .len = 0x1e0, 62 .features = BIT(DPU_CTL_ACTIVE_CFG), 63 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 64 }, 65 }; 66 67 static const struct dpu_sspp_cfg sm6125_sspp[] = { 68 { 69 .name = "sspp_0", .id = SSPP_VIG0, 70 .base = 0x4000, .len = 0x1f0, 71 .features = VIG_SDM845_MASK, 72 .sblk = &dpu_vig_sblk_qseed3_2_4, 73 .xin_id = 0, 74 .type = SSPP_TYPE_VIG, 75 .clk_ctrl = DPU_CLK_CTRL_VIG0, 76 }, { 77 .name = "sspp_8", .id = SSPP_DMA0, 78 .base = 0x24000, .len = 0x1f0, 79 .features = DMA_SDM845_MASK, 80 .sblk = &dpu_dma_sblk, 81 .xin_id = 1, 82 .type = SSPP_TYPE_DMA, 83 .clk_ctrl = DPU_CLK_CTRL_DMA0, 84 }, { 85 .name = "sspp_9", .id = SSPP_DMA1, 86 .base = 0x26000, .len = 0x1f0, 87 .features = DMA_SDM845_MASK, 88 .sblk = &dpu_dma_sblk, 89 .xin_id = 5, 90 .type = SSPP_TYPE_DMA, 91 .clk_ctrl = DPU_CLK_CTRL_DMA1, 92 }, 93 }; 94 95 static const struct dpu_lm_cfg sm6125_lm[] = { 96 { 97 .name = "lm_0", .id = LM_0, 98 .base = 0x44000, .len = 0x320, 99 .features = MIXER_QCM2290_MASK, 100 .sblk = &sdm845_lm_sblk, 101 .pingpong = PINGPONG_0, 102 .dspp = DSPP_0, 103 .lm_pair = LM_1, 104 }, { 105 .name = "lm_1", .id = LM_1, 106 .base = 0x45000, .len = 0x320, 107 .features = MIXER_QCM2290_MASK, 108 .sblk = &sdm845_lm_sblk, 109 .pingpong = PINGPONG_1, 110 .dspp = 0, 111 .lm_pair = LM_0, 112 }, 113 }; 114 115 static const struct dpu_dspp_cfg sm6125_dspp[] = { 116 { 117 .name = "dspp_0", .id = DSPP_0, 118 .base = 0x54000, .len = 0x1800, 119 .features = DSPP_SC7180_MASK, 120 .sblk = &sdm845_dspp_sblk, 121 }, 122 }; 123 124 static const struct dpu_pingpong_cfg sm6125_pp[] = { 125 { 126 .name = "pingpong_0", .id = PINGPONG_0, 127 .base = 0x70000, .len = 0xd4, 128 .features = PINGPONG_SM8150_MASK, 129 .merge_3d = 0, 130 .sblk = &sdm845_pp_sblk, 131 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 132 }, { 133 .name = "pingpong_1", .id = PINGPONG_1, 134 .base = 0x70800, .len = 0xd4, 135 .features = PINGPONG_SM8150_MASK, 136 .merge_3d = 0, 137 .sblk = &sdm845_pp_sblk, 138 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 139 }, 140 }; 141 142 static const struct dpu_intf_cfg sm6125_intf[] = { 143 { 144 .name = "intf_0", .id = INTF_0, 145 .base = 0x6a000, .len = 0x280, 146 .features = INTF_SC7180_MASK, 147 .type = INTF_DP, 148 .controller_id = MSM_DP_CONTROLLER_0, 149 .prog_fetch_lines_worst_case = 24, 150 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 151 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 152 }, { 153 .name = "intf_1", .id = INTF_1, 154 .base = 0x6a800, .len = 0x2c0, 155 .features = INTF_SC7180_MASK, 156 .type = INTF_DSI, 157 .controller_id = 0, 158 .prog_fetch_lines_worst_case = 24, 159 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 160 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 161 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 162 }, 163 }; 164 165 static const struct dpu_perf_cfg sm6125_perf_data = { 166 .max_bw_low = 4100000, 167 .max_bw_high = 4100000, 168 .min_core_ib = 2400000, 169 .min_llcc_ib = 0, /* No LLCC on this SoC */ 170 .min_dram_ib = 800000, 171 .min_prefill_lines = 24, 172 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 173 .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, 174 .qos_lut_tbl = { 175 {.nentry = ARRAY_SIZE(sm8150_qos_linear), 176 .entries = sm8150_qos_linear 177 }, 178 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 179 .entries = sc7180_qos_macrotile 180 }, 181 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 182 .entries = sc7180_qos_nrt 183 }, 184 /* TODO: macrotile-qseed is different from macrotile */ 185 }, 186 .cdp_cfg = { 187 {.rd_enable = 1, .wr_enable = 1}, 188 {.rd_enable = 1, .wr_enable = 0} 189 }, 190 .clk_inefficiency_factor = 105, 191 .bw_inefficiency_factor = 120, 192 }; 193 194 static const struct dpu_mdss_version sm6125_mdss_ver = { 195 .core_major_ver = 5, 196 .core_minor_ver = 4, 197 }; 198 199 const struct dpu_mdss_cfg dpu_sm6125_cfg = { 200 .mdss_ver = &sm6125_mdss_ver, 201 .caps = &sm6125_dpu_caps, 202 .mdp = &sm6125_mdp, 203 .ctl_count = ARRAY_SIZE(sm6125_ctl), 204 .ctl = sm6125_ctl, 205 .sspp_count = ARRAY_SIZE(sm6125_sspp), 206 .sspp = sm6125_sspp, 207 .mixer_count = ARRAY_SIZE(sm6125_lm), 208 .mixer = sm6125_lm, 209 .dspp_count = ARRAY_SIZE(sm6125_dspp), 210 .dspp = sm6125_dspp, 211 .pingpong_count = ARRAY_SIZE(sm6125_pp), 212 .pingpong = sm6125_pp, 213 .intf_count = ARRAY_SIZE(sm6125_intf), 214 .intf = sm6125_intf, 215 .vbif_count = ARRAY_SIZE(sdm845_vbif), 216 .vbif = sdm845_vbif, 217 .perf = &sm6125_perf_data, 218 }; 219 220 #endif 221