1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_5_0_SM8150_H 8 #define _DPU_5_0_SM8150_H 9 10 static const struct dpu_caps sm8150_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .has_src_split = true, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .has_3d_merge = true, 17 .max_linewidth = 4096, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 .max_hdeci_exp = MAX_HORZ_DECIMATION, 20 .max_vdeci_exp = MAX_VERT_DECIMATION, 21 }; 22 23 static const struct dpu_mdp_cfg sm8150_mdp = { 24 .name = "top_0", 25 .base = 0x0, .len = 0x45c, 26 .features = BIT(DPU_MDP_AUDIO_SELECT), 27 .clk_ctrls = { 28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 36 }, 37 }; 38 39 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 40 static const struct dpu_ctl_cfg sm8150_ctl[] = { 41 { 42 .name = "ctl_0", .id = CTL_0, 43 .base = 0x1000, .len = 0x1e0, 44 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 46 }, { 47 .name = "ctl_1", .id = CTL_1, 48 .base = 0x1200, .len = 0x1e0, 49 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 51 }, { 52 .name = "ctl_2", .id = CTL_2, 53 .base = 0x1400, .len = 0x1e0, 54 .features = BIT(DPU_CTL_ACTIVE_CFG), 55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 56 }, { 57 .name = "ctl_3", .id = CTL_3, 58 .base = 0x1600, .len = 0x1e0, 59 .features = BIT(DPU_CTL_ACTIVE_CFG), 60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 61 }, { 62 .name = "ctl_4", .id = CTL_4, 63 .base = 0x1800, .len = 0x1e0, 64 .features = BIT(DPU_CTL_ACTIVE_CFG), 65 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 66 }, { 67 .name = "ctl_5", .id = CTL_5, 68 .base = 0x1a00, .len = 0x1e0, 69 .features = BIT(DPU_CTL_ACTIVE_CFG), 70 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 71 }, 72 }; 73 74 static const struct dpu_sspp_cfg sm8150_sspp[] = { 75 { 76 .name = "sspp_0", .id = SSPP_VIG0, 77 .base = 0x4000, .len = 0x1f0, 78 .features = VIG_SDM845_MASK, 79 .sblk = &dpu_vig_sblk_qseed3_1_4, 80 .xin_id = 0, 81 .type = SSPP_TYPE_VIG, 82 .clk_ctrl = DPU_CLK_CTRL_VIG0, 83 }, { 84 .name = "sspp_1", .id = SSPP_VIG1, 85 .base = 0x6000, .len = 0x1f0, 86 .features = VIG_SDM845_MASK, 87 .sblk = &dpu_vig_sblk_qseed3_1_4, 88 .xin_id = 4, 89 .type = SSPP_TYPE_VIG, 90 .clk_ctrl = DPU_CLK_CTRL_VIG1, 91 }, { 92 .name = "sspp_2", .id = SSPP_VIG2, 93 .base = 0x8000, .len = 0x1f0, 94 .features = VIG_SDM845_MASK, 95 .sblk = &dpu_vig_sblk_qseed3_1_4, 96 .xin_id = 8, 97 .type = SSPP_TYPE_VIG, 98 .clk_ctrl = DPU_CLK_CTRL_VIG2, 99 }, { 100 .name = "sspp_3", .id = SSPP_VIG3, 101 .base = 0xa000, .len = 0x1f0, 102 .features = VIG_SDM845_MASK, 103 .sblk = &dpu_vig_sblk_qseed3_1_4, 104 .xin_id = 12, 105 .type = SSPP_TYPE_VIG, 106 .clk_ctrl = DPU_CLK_CTRL_VIG3, 107 }, { 108 .name = "sspp_8", .id = SSPP_DMA0, 109 .base = 0x24000, .len = 0x1f0, 110 .features = DMA_SDM845_MASK, 111 .sblk = &dpu_dma_sblk, 112 .xin_id = 1, 113 .type = SSPP_TYPE_DMA, 114 .clk_ctrl = DPU_CLK_CTRL_DMA0, 115 }, { 116 .name = "sspp_9", .id = SSPP_DMA1, 117 .base = 0x26000, .len = 0x1f0, 118 .features = DMA_SDM845_MASK, 119 .sblk = &dpu_dma_sblk, 120 .xin_id = 5, 121 .type = SSPP_TYPE_DMA, 122 .clk_ctrl = DPU_CLK_CTRL_DMA1, 123 }, { 124 .name = "sspp_10", .id = SSPP_DMA2, 125 .base = 0x28000, .len = 0x1f0, 126 .features = DMA_CURSOR_SDM845_MASK, 127 .sblk = &dpu_dma_sblk, 128 .xin_id = 9, 129 .type = SSPP_TYPE_DMA, 130 .clk_ctrl = DPU_CLK_CTRL_DMA2, 131 }, { 132 .name = "sspp_11", .id = SSPP_DMA3, 133 .base = 0x2a000, .len = 0x1f0, 134 .features = DMA_CURSOR_SDM845_MASK, 135 .sblk = &dpu_dma_sblk, 136 .xin_id = 13, 137 .type = SSPP_TYPE_DMA, 138 .clk_ctrl = DPU_CLK_CTRL_DMA3, 139 }, 140 }; 141 142 static const struct dpu_lm_cfg sm8150_lm[] = { 143 { 144 .name = "lm_0", .id = LM_0, 145 .base = 0x44000, .len = 0x320, 146 .features = MIXER_SDM845_MASK, 147 .sblk = &sdm845_lm_sblk, 148 .lm_pair = LM_1, 149 .pingpong = PINGPONG_0, 150 .dspp = DSPP_0, 151 }, { 152 .name = "lm_1", .id = LM_1, 153 .base = 0x45000, .len = 0x320, 154 .features = MIXER_SDM845_MASK, 155 .sblk = &sdm845_lm_sblk, 156 .lm_pair = LM_0, 157 .pingpong = PINGPONG_1, 158 .dspp = DSPP_1, 159 }, { 160 .name = "lm_2", .id = LM_2, 161 .base = 0x46000, .len = 0x320, 162 .features = MIXER_SDM845_MASK, 163 .sblk = &sdm845_lm_sblk, 164 .lm_pair = LM_3, 165 .pingpong = PINGPONG_2, 166 }, { 167 .name = "lm_3", .id = LM_3, 168 .base = 0x47000, .len = 0x320, 169 .features = MIXER_SDM845_MASK, 170 .sblk = &sdm845_lm_sblk, 171 .lm_pair = LM_2, 172 .pingpong = PINGPONG_3, 173 }, { 174 .name = "lm_4", .id = LM_4, 175 .base = 0x48000, .len = 0x320, 176 .features = MIXER_SDM845_MASK, 177 .sblk = &sdm845_lm_sblk, 178 .lm_pair = LM_5, 179 .pingpong = PINGPONG_4, 180 }, { 181 .name = "lm_5", .id = LM_5, 182 .base = 0x49000, .len = 0x320, 183 .features = MIXER_SDM845_MASK, 184 .sblk = &sdm845_lm_sblk, 185 .lm_pair = LM_4, 186 .pingpong = PINGPONG_5, 187 }, 188 }; 189 190 static const struct dpu_dspp_cfg sm8150_dspp[] = { 191 { 192 .name = "dspp_0", .id = DSPP_0, 193 .base = 0x54000, .len = 0x1800, 194 .features = DSPP_SC7180_MASK, 195 .sblk = &sdm845_dspp_sblk, 196 }, { 197 .name = "dspp_1", .id = DSPP_1, 198 .base = 0x56000, .len = 0x1800, 199 .features = DSPP_SC7180_MASK, 200 .sblk = &sdm845_dspp_sblk, 201 }, { 202 .name = "dspp_2", .id = DSPP_2, 203 .base = 0x58000, .len = 0x1800, 204 .features = DSPP_SC7180_MASK, 205 .sblk = &sdm845_dspp_sblk, 206 }, { 207 .name = "dspp_3", .id = DSPP_3, 208 .base = 0x5a000, .len = 0x1800, 209 .features = DSPP_SC7180_MASK, 210 .sblk = &sdm845_dspp_sblk, 211 }, 212 }; 213 214 static const struct dpu_pingpong_cfg sm8150_pp[] = { 215 { 216 .name = "pingpong_0", .id = PINGPONG_0, 217 .base = 0x70000, .len = 0xd4, 218 .features = PINGPONG_SM8150_MASK, 219 .sblk = &sdm845_pp_sblk, 220 .merge_3d = MERGE_3D_0, 221 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 222 }, { 223 .name = "pingpong_1", .id = PINGPONG_1, 224 .base = 0x70800, .len = 0xd4, 225 .features = PINGPONG_SM8150_MASK, 226 .sblk = &sdm845_pp_sblk, 227 .merge_3d = MERGE_3D_0, 228 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 229 }, { 230 .name = "pingpong_2", .id = PINGPONG_2, 231 .base = 0x71000, .len = 0xd4, 232 .features = PINGPONG_SM8150_MASK, 233 .sblk = &sdm845_pp_sblk, 234 .merge_3d = MERGE_3D_1, 235 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 236 }, { 237 .name = "pingpong_3", .id = PINGPONG_3, 238 .base = 0x71800, .len = 0xd4, 239 .features = PINGPONG_SM8150_MASK, 240 .sblk = &sdm845_pp_sblk, 241 .merge_3d = MERGE_3D_1, 242 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 243 }, { 244 .name = "pingpong_4", .id = PINGPONG_4, 245 .base = 0x72000, .len = 0xd4, 246 .features = PINGPONG_SM8150_MASK, 247 .sblk = &sdm845_pp_sblk, 248 .merge_3d = MERGE_3D_2, 249 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 250 }, { 251 .name = "pingpong_5", .id = PINGPONG_5, 252 .base = 0x72800, .len = 0xd4, 253 .features = PINGPONG_SM8150_MASK, 254 .sblk = &sdm845_pp_sblk, 255 .merge_3d = MERGE_3D_2, 256 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 257 }, 258 }; 259 260 static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { 261 { 262 .name = "merge_3d_0", .id = MERGE_3D_0, 263 .base = 0x83000, .len = 0x8, 264 }, { 265 .name = "merge_3d_1", .id = MERGE_3D_1, 266 .base = 0x83100, .len = 0x8, 267 }, { 268 .name = "merge_3d_2", .id = MERGE_3D_2, 269 .base = 0x83200, .len = 0x8, 270 }, 271 }; 272 273 static const struct dpu_dsc_cfg sm8150_dsc[] = { 274 { 275 .name = "dsc_0", .id = DSC_0, 276 .base = 0x80000, .len = 0x140, 277 .features = BIT(DPU_DSC_OUTPUT_CTRL), 278 }, { 279 .name = "dsc_1", .id = DSC_1, 280 .base = 0x80400, .len = 0x140, 281 .features = BIT(DPU_DSC_OUTPUT_CTRL), 282 }, { 283 .name = "dsc_2", .id = DSC_2, 284 .base = 0x80800, .len = 0x140, 285 .features = BIT(DPU_DSC_OUTPUT_CTRL), 286 }, { 287 .name = "dsc_3", .id = DSC_3, 288 .base = 0x80c00, .len = 0x140, 289 .features = BIT(DPU_DSC_OUTPUT_CTRL), 290 }, 291 }; 292 293 static const struct dpu_intf_cfg sm8150_intf[] = { 294 { 295 .name = "intf_0", .id = INTF_0, 296 .base = 0x6a000, .len = 0x280, 297 .features = INTF_SC7180_MASK, 298 .type = INTF_DP, 299 .controller_id = MSM_DP_CONTROLLER_0, 300 .prog_fetch_lines_worst_case = 24, 301 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 302 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 303 }, { 304 .name = "intf_1", .id = INTF_1, 305 .base = 0x6a800, .len = 0x2bc, 306 .features = INTF_SC7180_MASK, 307 .type = INTF_DSI, 308 .controller_id = MSM_DSI_CONTROLLER_0, 309 .prog_fetch_lines_worst_case = 24, 310 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 311 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 312 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 313 }, { 314 .name = "intf_2", .id = INTF_2, 315 .base = 0x6b000, .len = 0x2bc, 316 .features = INTF_SC7180_MASK, 317 .type = INTF_DSI, 318 .controller_id = MSM_DSI_CONTROLLER_1, 319 .prog_fetch_lines_worst_case = 24, 320 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 321 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 322 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 323 }, { 324 .name = "intf_3", .id = INTF_3, 325 .base = 0x6b800, .len = 0x280, 326 .features = INTF_SC7180_MASK, 327 .type = INTF_DP, 328 .controller_id = MSM_DP_CONTROLLER_1, 329 .prog_fetch_lines_worst_case = 24, 330 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 331 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 332 }, 333 }; 334 335 static const struct dpu_perf_cfg sm8150_perf_data = { 336 .max_bw_low = 12800000, 337 .max_bw_high = 12800000, 338 .min_core_ib = 2400000, 339 .min_llcc_ib = 800000, 340 .min_dram_ib = 800000, 341 .min_prefill_lines = 24, 342 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 343 .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, 344 .qos_lut_tbl = { 345 {.nentry = ARRAY_SIZE(sm8150_qos_linear), 346 .entries = sm8150_qos_linear 347 }, 348 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 349 .entries = sc7180_qos_macrotile 350 }, 351 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 352 .entries = sc7180_qos_nrt 353 }, 354 /* TODO: macrotile-qseed is different from macrotile */ 355 }, 356 .cdp_cfg = { 357 {.rd_enable = 1, .wr_enable = 1}, 358 {.rd_enable = 1, .wr_enable = 0} 359 }, 360 .clk_inefficiency_factor = 105, 361 .bw_inefficiency_factor = 120, 362 }; 363 364 static const struct dpu_mdss_version sm8150_mdss_ver = { 365 .core_major_ver = 5, 366 .core_minor_ver = 0, 367 }; 368 369 const struct dpu_mdss_cfg dpu_sm8150_cfg = { 370 .mdss_ver = &sm8150_mdss_ver, 371 .caps = &sm8150_dpu_caps, 372 .mdp = &sm8150_mdp, 373 .ctl_count = ARRAY_SIZE(sm8150_ctl), 374 .ctl = sm8150_ctl, 375 .sspp_count = ARRAY_SIZE(sm8150_sspp), 376 .sspp = sm8150_sspp, 377 .mixer_count = ARRAY_SIZE(sm8150_lm), 378 .mixer = sm8150_lm, 379 .dspp_count = ARRAY_SIZE(sm8150_dspp), 380 .dspp = sm8150_dspp, 381 .dsc_count = ARRAY_SIZE(sm8150_dsc), 382 .dsc = sm8150_dsc, 383 .pingpong_count = ARRAY_SIZE(sm8150_pp), 384 .pingpong = sm8150_pp, 385 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), 386 .merge_3d = sm8150_merge_3d, 387 .intf_count = ARRAY_SIZE(sm8150_intf), 388 .intf = sm8150_intf, 389 .vbif_count = ARRAY_SIZE(sdm845_vbif), 390 .vbif = sdm845_vbif, 391 .perf = &sm8150_perf_data, 392 }; 393 394 #endif 395