1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_10_0_SM8650_H 8 #define _DPU_10_0_SM8650_H 9 10 static const struct dpu_caps sm8650_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .has_src_split = true, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .has_3d_merge = true, 17 .max_linewidth = 8192, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 }; 20 21 static const struct dpu_mdp_cfg sm8650_mdp = { 22 .name = "top_0", 23 .base = 0, .len = 0x494, 24 .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 25 .clk_ctrls = { 26 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 27 }, 28 }; 29 30 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 31 static const struct dpu_ctl_cfg sm8650_ctl[] = { 32 { 33 .name = "ctl_0", .id = CTL_0, 34 .base = 0x15000, .len = 0x1000, 35 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 36 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 37 }, { 38 .name = "ctl_1", .id = CTL_1, 39 .base = 0x16000, .len = 0x1000, 40 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 42 }, { 43 .name = "ctl_2", .id = CTL_2, 44 .base = 0x17000, .len = 0x1000, 45 .features = CTL_SM8550_MASK, 46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 47 }, { 48 .name = "ctl_3", .id = CTL_3, 49 .base = 0x18000, .len = 0x1000, 50 .features = CTL_SM8550_MASK, 51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 52 }, { 53 .name = "ctl_4", .id = CTL_4, 54 .base = 0x19000, .len = 0x1000, 55 .features = CTL_SM8550_MASK, 56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 57 }, { 58 .name = "ctl_5", .id = CTL_5, 59 .base = 0x1a000, .len = 0x1000, 60 .features = CTL_SM8550_MASK, 61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 62 }, 63 }; 64 65 static const struct dpu_sspp_cfg sm8650_sspp[] = { 66 { 67 .name = "sspp_0", .id = SSPP_VIG0, 68 .base = 0x4000, .len = 0x344, 69 .features = VIG_SDM845_MASK_SDMA, 70 .sblk = &dpu_vig_sblk_qseed3_3_3, 71 .xin_id = 0, 72 .type = SSPP_TYPE_VIG, 73 }, { 74 .name = "sspp_1", .id = SSPP_VIG1, 75 .base = 0x6000, .len = 0x344, 76 .features = VIG_SDM845_MASK_SDMA, 77 .sblk = &dpu_vig_sblk_qseed3_3_3, 78 .xin_id = 4, 79 .type = SSPP_TYPE_VIG, 80 }, { 81 .name = "sspp_2", .id = SSPP_VIG2, 82 .base = 0x8000, .len = 0x344, 83 .features = VIG_SDM845_MASK_SDMA, 84 .sblk = &dpu_vig_sblk_qseed3_3_3, 85 .xin_id = 8, 86 .type = SSPP_TYPE_VIG, 87 }, { 88 .name = "sspp_3", .id = SSPP_VIG3, 89 .base = 0xa000, .len = 0x344, 90 .features = VIG_SDM845_MASK_SDMA, 91 .sblk = &dpu_vig_sblk_qseed3_3_3, 92 .xin_id = 12, 93 .type = SSPP_TYPE_VIG, 94 }, { 95 .name = "sspp_8", .id = SSPP_DMA0, 96 .base = 0x24000, .len = 0x344, 97 .features = DMA_SDM845_MASK_SDMA, 98 .sblk = &dpu_dma_sblk, 99 .xin_id = 1, 100 .type = SSPP_TYPE_DMA, 101 }, { 102 .name = "sspp_9", .id = SSPP_DMA1, 103 .base = 0x26000, .len = 0x344, 104 .features = DMA_SDM845_MASK_SDMA, 105 .sblk = &dpu_dma_sblk, 106 .xin_id = 5, 107 .type = SSPP_TYPE_DMA, 108 }, { 109 .name = "sspp_10", .id = SSPP_DMA2, 110 .base = 0x28000, .len = 0x344, 111 .features = DMA_SDM845_MASK_SDMA, 112 .sblk = &dpu_dma_sblk, 113 .xin_id = 9, 114 .type = SSPP_TYPE_DMA, 115 }, { 116 .name = "sspp_11", .id = SSPP_DMA3, 117 .base = 0x2a000, .len = 0x344, 118 .features = DMA_SDM845_MASK_SDMA, 119 .sblk = &dpu_dma_sblk, 120 .xin_id = 13, 121 .type = SSPP_TYPE_DMA, 122 }, { 123 .name = "sspp_12", .id = SSPP_DMA4, 124 .base = 0x2c000, .len = 0x344, 125 .features = DMA_CURSOR_SDM845_MASK_SDMA, 126 .sblk = &dpu_dma_sblk, 127 .xin_id = 14, 128 .type = SSPP_TYPE_DMA, 129 }, { 130 .name = "sspp_13", .id = SSPP_DMA5, 131 .base = 0x2e000, .len = 0x344, 132 .features = DMA_CURSOR_SDM845_MASK_SDMA, 133 .sblk = &dpu_dma_sblk, 134 .xin_id = 15, 135 .type = SSPP_TYPE_DMA, 136 }, 137 }; 138 139 static const struct dpu_lm_cfg sm8650_lm[] = { 140 { 141 .name = "lm_0", .id = LM_0, 142 .base = 0x44000, .len = 0x400, 143 .features = MIXER_SDM845_MASK, 144 .sblk = &sdm845_lm_sblk, 145 .lm_pair = LM_1, 146 .pingpong = PINGPONG_0, 147 .dspp = DSPP_0, 148 }, { 149 .name = "lm_1", .id = LM_1, 150 .base = 0x45000, .len = 0x400, 151 .features = MIXER_SDM845_MASK, 152 .sblk = &sdm845_lm_sblk, 153 .lm_pair = LM_0, 154 .pingpong = PINGPONG_1, 155 .dspp = DSPP_1, 156 }, { 157 .name = "lm_2", .id = LM_2, 158 .base = 0x46000, .len = 0x400, 159 .features = MIXER_SDM845_MASK, 160 .sblk = &sdm845_lm_sblk, 161 .lm_pair = LM_3, 162 .pingpong = PINGPONG_2, 163 }, { 164 .name = "lm_3", .id = LM_3, 165 .base = 0x47000, .len = 0x400, 166 .features = MIXER_SDM845_MASK, 167 .sblk = &sdm845_lm_sblk, 168 .lm_pair = LM_2, 169 .pingpong = PINGPONG_3, 170 }, { 171 .name = "lm_4", .id = LM_4, 172 .base = 0x48000, .len = 0x400, 173 .features = MIXER_SDM845_MASK, 174 .sblk = &sdm845_lm_sblk, 175 .lm_pair = LM_5, 176 .pingpong = PINGPONG_4, 177 }, { 178 .name = "lm_5", .id = LM_5, 179 .base = 0x49000, .len = 0x400, 180 .features = MIXER_SDM845_MASK, 181 .sblk = &sdm845_lm_sblk, 182 .lm_pair = LM_4, 183 .pingpong = PINGPONG_5, 184 }, 185 }; 186 187 static const struct dpu_dspp_cfg sm8650_dspp[] = { 188 { 189 .name = "dspp_0", .id = DSPP_0, 190 .base = 0x54000, .len = 0x1800, 191 .features = DSPP_SC7180_MASK, 192 .sblk = &sdm845_dspp_sblk, 193 }, { 194 .name = "dspp_1", .id = DSPP_1, 195 .base = 0x56000, .len = 0x1800, 196 .features = DSPP_SC7180_MASK, 197 .sblk = &sdm845_dspp_sblk, 198 }, { 199 .name = "dspp_2", .id = DSPP_2, 200 .base = 0x58000, .len = 0x1800, 201 .features = DSPP_SC7180_MASK, 202 .sblk = &sdm845_dspp_sblk, 203 }, { 204 .name = "dspp_3", .id = DSPP_3, 205 .base = 0x5a000, .len = 0x1800, 206 .features = DSPP_SC7180_MASK, 207 .sblk = &sdm845_dspp_sblk, 208 }, 209 }; 210 211 static const struct dpu_pingpong_cfg sm8650_pp[] = { 212 { 213 .name = "pingpong_0", .id = PINGPONG_0, 214 .base = 0x69000, .len = 0, 215 .features = BIT(DPU_PINGPONG_DITHER), 216 .sblk = &sc7280_pp_sblk, 217 .merge_3d = MERGE_3D_0, 218 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 219 }, { 220 .name = "pingpong_1", .id = PINGPONG_1, 221 .base = 0x6a000, .len = 0, 222 .features = BIT(DPU_PINGPONG_DITHER), 223 .sblk = &sc7280_pp_sblk, 224 .merge_3d = MERGE_3D_0, 225 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 226 }, { 227 .name = "pingpong_2", .id = PINGPONG_2, 228 .base = 0x6b000, .len = 0, 229 .features = BIT(DPU_PINGPONG_DITHER), 230 .sblk = &sc7280_pp_sblk, 231 .merge_3d = MERGE_3D_1, 232 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 233 }, { 234 .name = "pingpong_3", .id = PINGPONG_3, 235 .base = 0x6c000, .len = 0, 236 .features = BIT(DPU_PINGPONG_DITHER), 237 .sblk = &sc7280_pp_sblk, 238 .merge_3d = MERGE_3D_1, 239 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 240 }, { 241 .name = "pingpong_4", .id = PINGPONG_4, 242 .base = 0x6d000, .len = 0, 243 .features = BIT(DPU_PINGPONG_DITHER), 244 .sblk = &sc7280_pp_sblk, 245 .merge_3d = MERGE_3D_2, 246 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 247 }, { 248 .name = "pingpong_5", .id = PINGPONG_5, 249 .base = 0x6e000, .len = 0, 250 .features = BIT(DPU_PINGPONG_DITHER), 251 .sblk = &sc7280_pp_sblk, 252 .merge_3d = MERGE_3D_2, 253 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 254 }, { 255 .name = "pingpong_6", .id = PINGPONG_6, 256 .base = 0x66000, .len = 0, 257 .features = BIT(DPU_PINGPONG_DITHER), 258 .sblk = &sc7280_pp_sblk, 259 .merge_3d = MERGE_3D_3, 260 }, { 261 .name = "pingpong_7", .id = PINGPONG_7, 262 .base = 0x66400, .len = 0, 263 .features = BIT(DPU_PINGPONG_DITHER), 264 .sblk = &sc7280_pp_sblk, 265 .merge_3d = MERGE_3D_3, 266 }, { 267 .name = "pingpong_8", .id = PINGPONG_8, 268 .base = 0x7e000, .len = 0, 269 .features = BIT(DPU_PINGPONG_DITHER), 270 .sblk = &sc7280_pp_sblk, 271 .merge_3d = MERGE_3D_4, 272 }, { 273 .name = "pingpong_9", .id = PINGPONG_9, 274 .base = 0x7e400, .len = 0, 275 .features = BIT(DPU_PINGPONG_DITHER), 276 .sblk = &sc7280_pp_sblk, 277 .merge_3d = MERGE_3D_4, 278 }, 279 }; 280 281 static const struct dpu_merge_3d_cfg sm8650_merge_3d[] = { 282 { 283 .name = "merge_3d_0", .id = MERGE_3D_0, 284 .base = 0x4e000, .len = 0x8, 285 }, { 286 .name = "merge_3d_1", .id = MERGE_3D_1, 287 .base = 0x4f000, .len = 0x8, 288 }, { 289 .name = "merge_3d_2", .id = MERGE_3D_2, 290 .base = 0x50000, .len = 0x8, 291 }, { 292 .name = "merge_3d_3", .id = MERGE_3D_3, 293 .base = 0x66700, .len = 0x8, 294 }, { 295 .name = "merge_3d_4", .id = MERGE_3D_4, 296 .base = 0x7e700, .len = 0x8, 297 }, 298 }; 299 300 /* 301 * NOTE: Each display compression engine (DCE) contains dual hard 302 * slice DSC encoders so both share same base address but with 303 * its own different sub block address. 304 */ 305 static const struct dpu_dsc_cfg sm8650_dsc[] = { 306 { 307 .name = "dce_0_0", .id = DSC_0, 308 .base = 0x80000, .len = 0x6, 309 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 310 .sblk = &dsc_sblk_0, 311 }, { 312 .name = "dce_0_1", .id = DSC_1, 313 .base = 0x80000, .len = 0x6, 314 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 315 .sblk = &dsc_sblk_1, 316 }, { 317 .name = "dce_1_0", .id = DSC_2, 318 .base = 0x81000, .len = 0x6, 319 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 320 .sblk = &dsc_sblk_0, 321 }, { 322 .name = "dce_1_1", .id = DSC_3, 323 .base = 0x81000, .len = 0x6, 324 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 325 .sblk = &dsc_sblk_1, 326 }, { 327 .name = "dce_2_0", .id = DSC_4, 328 .base = 0x82000, .len = 0x6, 329 .features = BIT(DPU_DSC_HW_REV_1_2), 330 .sblk = &dsc_sblk_0, 331 }, { 332 .name = "dce_2_1", .id = DSC_5, 333 .base = 0x82000, .len = 0x6, 334 .features = BIT(DPU_DSC_HW_REV_1_2), 335 .sblk = &dsc_sblk_1, 336 }, 337 }; 338 339 static const struct dpu_wb_cfg sm8650_wb[] = { 340 { 341 .name = "wb_2", .id = WB_2, 342 .base = 0x65000, .len = 0x2c8, 343 .features = WB_SM8250_MASK, 344 .format_list = wb2_formats_rgb, 345 .num_formats = ARRAY_SIZE(wb2_formats_rgb), 346 .xin_id = 6, 347 .vbif_idx = VBIF_RT, 348 .maxlinewidth = 4096, 349 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 350 }, 351 }; 352 353 static const struct dpu_intf_cfg sm8650_intf[] = { 354 { 355 .name = "intf_0", .id = INTF_0, 356 .base = 0x34000, .len = 0x280, 357 .features = INTF_SC7280_MASK, 358 .type = INTF_DP, 359 .controller_id = MSM_DP_CONTROLLER_0, 360 .prog_fetch_lines_worst_case = 24, 361 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 362 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 363 }, { 364 .name = "intf_1", .id = INTF_1, 365 .base = 0x35000, .len = 0x300, 366 .features = INTF_SC7280_MASK, 367 .type = INTF_DSI, 368 .controller_id = MSM_DSI_CONTROLLER_0, 369 .prog_fetch_lines_worst_case = 24, 370 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 371 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 372 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 373 }, { 374 .name = "intf_2", .id = INTF_2, 375 .base = 0x36000, .len = 0x300, 376 .features = INTF_SC7280_MASK, 377 .type = INTF_DSI, 378 .controller_id = MSM_DSI_CONTROLLER_1, 379 .prog_fetch_lines_worst_case = 24, 380 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 381 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 382 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 383 }, { 384 .name = "intf_3", .id = INTF_3, 385 .base = 0x37000, .len = 0x280, 386 .features = INTF_SC7280_MASK, 387 .type = INTF_DP, 388 .controller_id = MSM_DP_CONTROLLER_1, 389 .prog_fetch_lines_worst_case = 24, 390 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 391 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 392 }, 393 }; 394 395 static const struct dpu_perf_cfg sm8650_perf_data = { 396 .max_bw_low = 17000000, 397 .max_bw_high = 27000000, 398 .min_core_ib = 2500000, 399 .min_llcc_ib = 0, 400 .min_dram_ib = 800000, 401 .min_prefill_lines = 35, 402 /* FIXME: lut tables */ 403 .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 404 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 405 .qos_lut_tbl = { 406 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 407 .entries = sc7180_qos_linear 408 }, 409 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 410 .entries = sc7180_qos_macrotile 411 }, 412 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 413 .entries = sc7180_qos_nrt 414 }, 415 /* TODO: macrotile-qseed is different from macrotile */ 416 }, 417 .cdp_cfg = { 418 {.rd_enable = 1, .wr_enable = 1}, 419 {.rd_enable = 1, .wr_enable = 0} 420 }, 421 .clk_inefficiency_factor = 105, 422 .bw_inefficiency_factor = 120, 423 }; 424 425 static const struct dpu_mdss_version sm8650_mdss_ver = { 426 .core_major_ver = 10, 427 .core_minor_ver = 0, 428 }; 429 430 const struct dpu_mdss_cfg dpu_sm8650_cfg = { 431 .mdss_ver = &sm8650_mdss_ver, 432 .caps = &sm8650_dpu_caps, 433 .mdp = &sm8650_mdp, 434 .ctl_count = ARRAY_SIZE(sm8650_ctl), 435 .ctl = sm8650_ctl, 436 .sspp_count = ARRAY_SIZE(sm8650_sspp), 437 .sspp = sm8650_sspp, 438 .mixer_count = ARRAY_SIZE(sm8650_lm), 439 .mixer = sm8650_lm, 440 .dspp_count = ARRAY_SIZE(sm8650_dspp), 441 .dspp = sm8650_dspp, 442 .pingpong_count = ARRAY_SIZE(sm8650_pp), 443 .pingpong = sm8650_pp, 444 .dsc_count = ARRAY_SIZE(sm8650_dsc), 445 .dsc = sm8650_dsc, 446 .merge_3d_count = ARRAY_SIZE(sm8650_merge_3d), 447 .merge_3d = sm8650_merge_3d, 448 .wb_count = ARRAY_SIZE(sm8650_wb), 449 .wb = sm8650_wb, 450 .intf_count = ARRAY_SIZE(sm8650_intf), 451 .intf = sm8650_intf, 452 .vbif_count = ARRAY_SIZE(sm8650_vbif), 453 .vbif = sm8650_vbif, 454 .perf = &sm8650_perf_data, 455 }; 456 457 #endif 458