1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/circ_buf.h>
26 #include <trace/events/dma_fence.h>
27
28 #include "i915_guc_submission.h"
29 #include "i915_drv.h"
30
31 /**
32 * DOC: GuC-based command submission
33 *
34 * GuC client:
35 * A i915_guc_client refers to a submission path through GuC. Currently, there
36 * is only one of these (the execbuf_client) and this one is charged with all
37 * submissions to the GuC. This struct is the owner of a doorbell, a process
38 * descriptor and a workqueue (all of them inside a single gem object that
39 * contains all required pages for these elements).
40 *
41 * GuC stage descriptor:
42 * During initialization, the driver allocates a static pool of 1024 such
43 * descriptors, and shares them with the GuC.
44 * Currently, there exists a 1:1 mapping between a i915_guc_client and a
45 * guc_stage_desc (via the client's stage_id), so effectively only one
46 * gets used. This stage descriptor lets the GuC know about the doorbell,
47 * workqueue and process descriptor. Theoretically, it also lets the GuC
48 * know about our HW contexts (context ID, etc...), but we actually
49 * employ a kind of submission where the GuC uses the LRCA sent via the work
50 * item instead (the single guc_stage_desc associated to execbuf client
51 * contains information about the default kernel context only, but this is
52 * essentially unused). This is called a "proxy" submission.
53 *
54 * The Scratch registers:
55 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
56 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
57 * triggers an interrupt on the GuC via another register write (0xC4C8).
58 * Firmware writes a success/fail code back to the action register after
59 * processes the request. The kernel driver polls waiting for this update and
60 * then proceeds.
61 * See intel_guc_send()
62 *
63 * Doorbells:
64 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
65 * mapped into process space.
66 *
67 * Work Items:
68 * There are several types of work items that the host may place into a
69 * workqueue, each with its own requirements and limitations. Currently only
70 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
71 * represents in-order queue. The kernel driver packs ring tail pointer and an
72 * ELSP context descriptor dword into Work Item.
73 * See guc_wq_item_append()
74 *
75 * ADS:
76 * The Additional Data Struct (ADS) has pointers for different buffers used by
77 * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
78 * scheduling policies (guc_policies), a structure describing a collection of
79 * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
80 * its internal state for sleep.
81 *
82 */
83
is_high_priority(struct i915_guc_client * client)84 static inline bool is_high_priority(struct i915_guc_client* client)
85 {
86 return client->priority <= GUC_CLIENT_PRIORITY_HIGH;
87 }
88
__reserve_doorbell(struct i915_guc_client * client)89 static int __reserve_doorbell(struct i915_guc_client *client)
90 {
91 unsigned long offset;
92 unsigned long end;
93 u16 id;
94
95 GEM_BUG_ON(client->doorbell_id != GUC_DOORBELL_INVALID);
96
97 /*
98 * The bitmap tracks which doorbell registers are currently in use.
99 * It is split into two halves; the first half is used for normal
100 * priority contexts, the second half for high-priority ones.
101 */
102 offset = 0;
103 end = GUC_NUM_DOORBELLS/2;
104 if (is_high_priority(client)) {
105 offset = end;
106 end += offset;
107 }
108
109 id = find_next_zero_bit(client->guc->doorbell_bitmap, end, offset);
110 if (id == end)
111 return -ENOSPC;
112
113 __set_bit(id, client->guc->doorbell_bitmap);
114 client->doorbell_id = id;
115 DRM_DEBUG_DRIVER("client %u (high prio=%s) reserved doorbell: %d\n",
116 client->stage_id, yesno(is_high_priority(client)),
117 id);
118 return 0;
119 }
120
__unreserve_doorbell(struct i915_guc_client * client)121 static void __unreserve_doorbell(struct i915_guc_client *client)
122 {
123 GEM_BUG_ON(client->doorbell_id == GUC_DOORBELL_INVALID);
124
125 __clear_bit(client->doorbell_id, client->guc->doorbell_bitmap);
126 client->doorbell_id = GUC_DOORBELL_INVALID;
127 }
128
129 /*
130 * Tell the GuC to allocate or deallocate a specific doorbell
131 */
132
__guc_allocate_doorbell(struct intel_guc * guc,u32 stage_id)133 static int __guc_allocate_doorbell(struct intel_guc *guc, u32 stage_id)
134 {
135 u32 action[] = {
136 INTEL_GUC_ACTION_ALLOCATE_DOORBELL,
137 stage_id
138 };
139
140 return intel_guc_send(guc, action, ARRAY_SIZE(action));
141 }
142
__guc_deallocate_doorbell(struct intel_guc * guc,u32 stage_id)143 static int __guc_deallocate_doorbell(struct intel_guc *guc, u32 stage_id)
144 {
145 u32 action[] = {
146 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL,
147 stage_id
148 };
149
150 return intel_guc_send(guc, action, ARRAY_SIZE(action));
151 }
152
__get_stage_desc(struct i915_guc_client * client)153 static struct guc_stage_desc *__get_stage_desc(struct i915_guc_client *client)
154 {
155 struct guc_stage_desc *base = client->guc->stage_desc_pool_vaddr;
156
157 return &base[client->stage_id];
158 }
159
160 /*
161 * Initialise, update, or clear doorbell data shared with the GuC
162 *
163 * These functions modify shared data and so need access to the mapped
164 * client object which contains the page being used for the doorbell
165 */
166
__update_doorbell_desc(struct i915_guc_client * client,u16 new_id)167 static void __update_doorbell_desc(struct i915_guc_client *client, u16 new_id)
168 {
169 struct guc_stage_desc *desc;
170
171 /* Update the GuC's idea of the doorbell ID */
172 desc = __get_stage_desc(client);
173 desc->db_id = new_id;
174 }
175
__get_doorbell(struct i915_guc_client * client)176 static struct guc_doorbell_info *__get_doorbell(struct i915_guc_client *client)
177 {
178 return client->vaddr + client->doorbell_offset;
179 }
180
has_doorbell(struct i915_guc_client * client)181 static bool has_doorbell(struct i915_guc_client *client)
182 {
183 if (client->doorbell_id == GUC_DOORBELL_INVALID)
184 return false;
185
186 return test_bit(client->doorbell_id, client->guc->doorbell_bitmap);
187 }
188
__create_doorbell(struct i915_guc_client * client)189 static int __create_doorbell(struct i915_guc_client *client)
190 {
191 struct guc_doorbell_info *doorbell;
192 int err;
193
194 doorbell = __get_doorbell(client);
195 doorbell->db_status = GUC_DOORBELL_ENABLED;
196 doorbell->cookie = 0;
197
198 err = __guc_allocate_doorbell(client->guc, client->stage_id);
199 if (err)
200 doorbell->db_status = GUC_DOORBELL_DISABLED;
201
202 return err;
203 }
204
__destroy_doorbell(struct i915_guc_client * client)205 static int __destroy_doorbell(struct i915_guc_client *client)
206 {
207 struct drm_i915_private *dev_priv = guc_to_i915(client->guc);
208 struct guc_doorbell_info *doorbell;
209 u16 db_id = client->doorbell_id;
210
211 GEM_BUG_ON(db_id >= GUC_DOORBELL_INVALID);
212
213 doorbell = __get_doorbell(client);
214 doorbell->db_status = GUC_DOORBELL_DISABLED;
215 doorbell->cookie = 0;
216
217 /* Doorbell release flow requires that we wait for GEN8_DRB_VALID bit
218 * to go to zero after updating db_status before we call the GuC to
219 * release the doorbell */
220 if (wait_for_us(!(I915_READ(GEN8_DRBREGL(db_id)) & GEN8_DRB_VALID), 10))
221 WARN_ONCE(true, "Doorbell never became invalid after disable\n");
222
223 return __guc_deallocate_doorbell(client->guc, client->stage_id);
224 }
225
create_doorbell(struct i915_guc_client * client)226 static int create_doorbell(struct i915_guc_client *client)
227 {
228 int ret;
229
230 ret = __reserve_doorbell(client);
231 if (ret)
232 return ret;
233
234 __update_doorbell_desc(client, client->doorbell_id);
235
236 ret = __create_doorbell(client);
237 if (ret)
238 goto err;
239
240 return 0;
241
242 err:
243 __update_doorbell_desc(client, GUC_DOORBELL_INVALID);
244 __unreserve_doorbell(client);
245 return ret;
246 }
247
destroy_doorbell(struct i915_guc_client * client)248 static int destroy_doorbell(struct i915_guc_client *client)
249 {
250 int err;
251
252 GEM_BUG_ON(!has_doorbell(client));
253
254 /* XXX: wait for any interrupts */
255 /* XXX: wait for workqueue to drain */
256
257 err = __destroy_doorbell(client);
258 if (err)
259 return err;
260
261 __update_doorbell_desc(client, GUC_DOORBELL_INVALID);
262
263 __unreserve_doorbell(client);
264
265 return 0;
266 }
267
__select_cacheline(struct intel_guc * guc)268 static unsigned long __select_cacheline(struct intel_guc* guc)
269 {
270 unsigned long offset;
271
272 /* Doorbell uses a single cache line within a page */
273 offset = offset_in_page(guc->db_cacheline);
274
275 /* Moving to next cache line to reduce contention */
276 guc->db_cacheline += cache_line_size();
277
278 DRM_DEBUG_DRIVER("reserved cacheline 0x%lx, next 0x%x, linesize %u\n",
279 offset, guc->db_cacheline, cache_line_size());
280 return offset;
281 }
282
283 static inline struct guc_process_desc *
__get_process_desc(struct i915_guc_client * client)284 __get_process_desc(struct i915_guc_client *client)
285 {
286 return client->vaddr + client->proc_desc_offset;
287 }
288
289 /*
290 * Initialise the process descriptor shared with the GuC firmware.
291 */
guc_proc_desc_init(struct intel_guc * guc,struct i915_guc_client * client)292 static void guc_proc_desc_init(struct intel_guc *guc,
293 struct i915_guc_client *client)
294 {
295 struct guc_process_desc *desc;
296
297 desc = memset(__get_process_desc(client), 0, sizeof(*desc));
298
299 /*
300 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
301 * space for ring3 clients (set them as in mmap_ioctl) or kernel
302 * space for kernel clients (map on demand instead? May make debug
303 * easier to have it mapped).
304 */
305 desc->wq_base_addr = 0;
306 desc->db_base_addr = 0;
307
308 desc->stage_id = client->stage_id;
309 desc->wq_size_bytes = GUC_WQ_SIZE;
310 desc->wq_status = WQ_STATUS_ACTIVE;
311 desc->priority = client->priority;
312 }
313
314 /*
315 * Initialise/clear the stage descriptor shared with the GuC firmware.
316 *
317 * This descriptor tells the GuC where (in GGTT space) to find the important
318 * data structures relating to this client (doorbell, process descriptor,
319 * write queue, etc).
320 */
guc_stage_desc_init(struct intel_guc * guc,struct i915_guc_client * client)321 static void guc_stage_desc_init(struct intel_guc *guc,
322 struct i915_guc_client *client)
323 {
324 struct drm_i915_private *dev_priv = guc_to_i915(guc);
325 struct intel_engine_cs *engine;
326 struct i915_gem_context *ctx = client->owner;
327 struct guc_stage_desc *desc;
328 unsigned int tmp;
329 u32 gfx_addr;
330
331 desc = __get_stage_desc(client);
332 memset(desc, 0, sizeof(*desc));
333
334 desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE | GUC_STAGE_DESC_ATTR_KERNEL;
335 desc->stage_id = client->stage_id;
336 desc->priority = client->priority;
337 desc->db_id = client->doorbell_id;
338
339 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
340 struct intel_context *ce = &ctx->engine[engine->id];
341 u32 guc_engine_id = engine->guc_id;
342 struct guc_execlist_context *lrc = &desc->lrc[guc_engine_id];
343
344 /* TODO: We have a design issue to be solved here. Only when we
345 * receive the first batch, we know which engine is used by the
346 * user. But here GuC expects the lrc and ring to be pinned. It
347 * is not an issue for default context, which is the only one
348 * for now who owns a GuC client. But for future owner of GuC
349 * client, need to make sure lrc is pinned prior to enter here.
350 */
351 if (!ce->state)
352 break; /* XXX: continue? */
353
354 /*
355 * XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy
356 * submission or, in other words, not using a direct submission
357 * model) the KMD's LRCA is not used for any work submission.
358 * Instead, the GuC uses the LRCA of the user mode context (see
359 * guc_wq_item_append below).
360 */
361 lrc->context_desc = lower_32_bits(ce->lrc_desc);
362
363 /* The state page is after PPHWSP */
364 lrc->ring_lrca =
365 guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
366
367 /* XXX: In direct submission, the GuC wants the HW context id
368 * here. In proxy submission, it wants the stage id */
369 lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
370 (guc_engine_id << GUC_ELC_ENGINE_OFFSET);
371
372 lrc->ring_begin = guc_ggtt_offset(ce->ring->vma);
373 lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
374 lrc->ring_next_free_location = lrc->ring_begin;
375 lrc->ring_current_tail_pointer_value = 0;
376
377 desc->engines_used |= (1 << guc_engine_id);
378 }
379
380 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
381 client->engines, desc->engines_used);
382 WARN_ON(desc->engines_used == 0);
383
384 /*
385 * The doorbell, process descriptor, and workqueue are all parts
386 * of the client object, which the GuC will reference via the GGTT
387 */
388 gfx_addr = guc_ggtt_offset(client->vma);
389 desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
390 client->doorbell_offset;
391 desc->db_trigger_cpu = ptr_to_u64(__get_doorbell(client));
392 desc->db_trigger_uk = gfx_addr + client->doorbell_offset;
393 desc->process_desc = gfx_addr + client->proc_desc_offset;
394 desc->wq_addr = gfx_addr + GUC_DB_SIZE;
395 desc->wq_size = GUC_WQ_SIZE;
396
397 desc->desc_private = ptr_to_u64(client);
398 }
399
guc_stage_desc_fini(struct intel_guc * guc,struct i915_guc_client * client)400 static void guc_stage_desc_fini(struct intel_guc *guc,
401 struct i915_guc_client *client)
402 {
403 struct guc_stage_desc *desc;
404
405 desc = __get_stage_desc(client);
406 memset(desc, 0, sizeof(*desc));
407 }
408
409 /* Construct a Work Item and append it to the GuC's Work Queue */
guc_wq_item_append(struct i915_guc_client * client,struct drm_i915_gem_request * rq)410 static void guc_wq_item_append(struct i915_guc_client *client,
411 struct drm_i915_gem_request *rq)
412 {
413 /* wqi_len is in DWords, and does not include the one-word header */
414 const size_t wqi_size = sizeof(struct guc_wq_item);
415 const u32 wqi_len = wqi_size / sizeof(u32) - 1;
416 struct intel_engine_cs *engine = rq->engine;
417 struct i915_gem_context *ctx = rq->ctx;
418 struct guc_process_desc *desc = __get_process_desc(client);
419 struct guc_wq_item *wqi;
420 u32 ring_tail, wq_off;
421
422 lockdep_assert_held(&client->wq_lock);
423
424 ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);
425 GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
426
427 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
428 * should not have the case where structure wqi is across page, neither
429 * wrapped to the beginning. This simplifies the implementation below.
430 *
431 * XXX: if not the case, we need save data to a temp wqi and copy it to
432 * workqueue buffer dw by dw.
433 */
434 BUILD_BUG_ON(wqi_size != 16);
435
436 /* Free space is guaranteed. */
437 wq_off = READ_ONCE(desc->tail);
438 GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
439 GUC_WQ_SIZE) < wqi_size);
440 GEM_BUG_ON(wq_off & (wqi_size - 1));
441
442 /* WQ starts from the page after doorbell / process_desc */
443 wqi = client->vaddr + wq_off + GUC_DB_SIZE;
444
445 /* Now fill in the 4-word work queue item */
446 wqi->header = WQ_TYPE_INORDER |
447 (wqi_len << WQ_LEN_SHIFT) |
448 (engine->guc_id << WQ_TARGET_SHIFT) |
449 WQ_NO_WCFLUSH_WAIT;
450
451 wqi->context_desc = lower_32_bits(intel_lr_context_descriptor(ctx, engine));
452
453 wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
454 wqi->fence_id = rq->global_seqno;
455
456 /* Postincrement WQ tail for next time. */
457 WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
458 }
459
guc_reset_wq(struct i915_guc_client * client)460 static void guc_reset_wq(struct i915_guc_client *client)
461 {
462 struct guc_process_desc *desc = __get_process_desc(client);
463
464 desc->head = 0;
465 desc->tail = 0;
466 }
467
guc_ring_doorbell(struct i915_guc_client * client)468 static void guc_ring_doorbell(struct i915_guc_client *client)
469 {
470 struct guc_doorbell_info *db;
471 u32 cookie;
472
473 lockdep_assert_held(&client->wq_lock);
474
475 /* pointer of current doorbell cacheline */
476 db = __get_doorbell(client);
477
478 /* we're not expecting the doorbell cookie to change behind our back */
479 cookie = READ_ONCE(db->cookie);
480 WARN_ON_ONCE(xchg(&db->cookie, cookie + 1) != cookie);
481
482 /* XXX: doorbell was lost and need to acquire it again */
483 GEM_BUG_ON(db->db_status != GUC_DOORBELL_ENABLED);
484 }
485
486 /**
487 * i915_guc_submit() - Submit commands through GuC
488 * @engine: engine associated with the commands
489 *
490 * The only error here arises if the doorbell hardware isn't functioning
491 * as expected, which really shouln't happen.
492 */
i915_guc_submit(struct intel_engine_cs * engine)493 static void i915_guc_submit(struct intel_engine_cs *engine)
494 {
495 struct drm_i915_private *dev_priv = engine->i915;
496 struct intel_guc *guc = &dev_priv->guc;
497 struct i915_guc_client *client = guc->execbuf_client;
498 struct intel_engine_execlists * const execlists = &engine->execlists;
499 struct execlist_port *port = execlists->port;
500 const unsigned int engine_id = engine->id;
501 unsigned int n;
502
503 for (n = 0; n < execlists_num_ports(execlists); n++) {
504 struct drm_i915_gem_request *rq;
505 unsigned int count;
506
507 rq = port_unpack(&port[n], &count);
508 if (rq && count == 0) {
509 port_set(&port[n], port_pack(rq, ++count));
510
511 if (i915_vma_is_map_and_fenceable(rq->ring->vma))
512 POSTING_READ_FW(GUC_STATUS);
513
514 lockmgr(&client->wq_lock, LK_EXCLUSIVE);
515
516 guc_wq_item_append(client, rq);
517 guc_ring_doorbell(client);
518
519 client->submissions[engine_id] += 1;
520
521 lockmgr(&client->wq_lock, LK_RELEASE);
522 }
523 }
524 }
525
nested_enable_signaling(struct drm_i915_gem_request * rq)526 static void nested_enable_signaling(struct drm_i915_gem_request *rq)
527 {
528 /* If we use dma_fence_enable_sw_signaling() directly, lockdep
529 * detects an ordering issue between the fence lockclass and the
530 * global_timeline. This circular dependency can only occur via 2
531 * different fences (but same fence lockclass), so we use the nesting
532 * annotation here to prevent the warn, equivalent to the nesting
533 * inside i915_gem_request_submit() for when we also enable the
534 * signaler.
535 */
536
537 if (test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
538 &rq->fence.flags))
539 return;
540
541 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags));
542 trace_dma_fence_enable_signal(&rq->fence);
543
544 lockmgr(&rq->lock, LK_EXCLUSIVE);
545 intel_engine_enable_signaling(rq, true);
546 lockmgr(&rq->lock, LK_RELEASE);
547 }
548
port_assign(struct execlist_port * port,struct drm_i915_gem_request * rq)549 static void port_assign(struct execlist_port *port,
550 struct drm_i915_gem_request *rq)
551 {
552 GEM_BUG_ON(rq == port_request(port));
553
554 if (port_isset(port))
555 i915_gem_request_put(port_request(port));
556
557 port_set(port, port_pack(i915_gem_request_get(rq), port_count(port)));
558 nested_enable_signaling(rq);
559 }
560
i915_guc_dequeue(struct intel_engine_cs * engine)561 static void i915_guc_dequeue(struct intel_engine_cs *engine)
562 {
563 struct intel_engine_execlists * const execlists = &engine->execlists;
564 struct execlist_port *port = execlists->port;
565 struct drm_i915_gem_request *last = NULL;
566 const struct execlist_port * const last_port =
567 &execlists->port[execlists->port_mask];
568 bool submit = false;
569 struct rb_node *rb;
570
571 if (port_isset(port))
572 port++;
573
574 spin_lock_irq(&engine->timeline->lock);
575 rb = execlists->first;
576 GEM_BUG_ON(rb_first(&execlists->queue) != rb);
577 while (rb) {
578 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
579 struct drm_i915_gem_request *rq, *rn;
580
581 list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
582 if (last && rq->ctx != last->ctx) {
583 if (port == last_port) {
584 __list_del_many(&p->requests,
585 &rq->priotree.link);
586 goto done;
587 }
588
589 if (submit)
590 port_assign(port, last);
591 port++;
592 }
593
594 INIT_LIST_HEAD(&rq->priotree.link);
595 rq->priotree.priority = INT_MAX;
596
597 __i915_gem_request_submit(rq);
598 trace_i915_gem_request_in(rq, port_index(port, execlists));
599 last = rq;
600 submit = true;
601 }
602
603 rb = rb_next(rb);
604 rb_erase(&p->node, &execlists->queue);
605 INIT_LIST_HEAD(&p->requests);
606 if (p->priority != I915_PRIORITY_NORMAL)
607 kmem_cache_free(engine->i915->priorities, p);
608 }
609 done:
610 execlists->first = rb;
611 if (submit) {
612 port_assign(port, last);
613 execlists_set_active(execlists, EXECLISTS_ACTIVE_USER);
614 i915_guc_submit(engine);
615 }
616 spin_unlock_irq(&engine->timeline->lock);
617 }
618
i915_guc_irq_handler(unsigned long data)619 static void i915_guc_irq_handler(unsigned long data)
620 {
621 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
622 struct intel_engine_execlists * const execlists = &engine->execlists;
623 struct execlist_port *port = execlists->port;
624 const struct execlist_port * const last_port =
625 &execlists->port[execlists->port_mask];
626 struct drm_i915_gem_request *rq;
627
628 rq = port_request(&port[0]);
629 while (rq && i915_gem_request_completed(rq)) {
630 trace_i915_gem_request_out(rq);
631 i915_gem_request_put(rq);
632
633 execlists_port_complete(execlists, port);
634
635 rq = port_request(&port[0]);
636 }
637 if (!rq)
638 execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
639
640 if (!port_isset(last_port))
641 i915_guc_dequeue(engine);
642 }
643
644 /*
645 * Everything below here is concerned with setup & teardown, and is
646 * therefore not part of the somewhat time-critical batch-submission
647 * path of i915_guc_submit() above.
648 */
649
650 /* Check that a doorbell register is in the expected state */
doorbell_ok(struct intel_guc * guc,u16 db_id)651 static bool doorbell_ok(struct intel_guc *guc, u16 db_id)
652 {
653 struct drm_i915_private *dev_priv = guc_to_i915(guc);
654 u32 drbregl;
655 bool valid;
656
657 GEM_BUG_ON(db_id >= GUC_DOORBELL_INVALID);
658
659 drbregl = I915_READ(GEN8_DRBREGL(db_id));
660 valid = drbregl & GEN8_DRB_VALID;
661
662 if (test_bit(db_id, guc->doorbell_bitmap) == valid)
663 return true;
664
665 DRM_DEBUG_DRIVER("Doorbell %d has unexpected state (0x%x): valid=%s\n",
666 db_id, drbregl, yesno(valid));
667
668 return false;
669 }
670
671 /*
672 * If the GuC thinks that the doorbell is unassigned (e.g. because we reset and
673 * reloaded the GuC FW) we can use this function to tell the GuC to reassign the
674 * doorbell to the rightful owner.
675 */
__reset_doorbell(struct i915_guc_client * client,u16 db_id)676 static int __reset_doorbell(struct i915_guc_client* client, u16 db_id)
677 {
678 int err;
679
680 __update_doorbell_desc(client, db_id);
681 err = __create_doorbell(client);
682 if (!err)
683 err = __destroy_doorbell(client);
684
685 return err;
686 }
687
688 /*
689 * Set up & tear down each unused doorbell in turn, to ensure that all doorbell
690 * HW is (re)initialised. For that end, we might have to borrow the first
691 * client. Also, tell GuC about all the doorbells in use by all clients.
692 * We do this because the KMD, the GuC and the doorbell HW can easily go out of
693 * sync (e.g. we can reset the GuC, but not the doorbel HW).
694 */
guc_init_doorbell_hw(struct intel_guc * guc)695 static int guc_init_doorbell_hw(struct intel_guc *guc)
696 {
697 struct i915_guc_client *client = guc->execbuf_client;
698 bool recreate_first_client = false;
699 u16 db_id;
700 int ret;
701
702 /* For unused doorbells, make sure they are disabled */
703 for_each_clear_bit(db_id, guc->doorbell_bitmap, GUC_NUM_DOORBELLS) {
704 if (doorbell_ok(guc, db_id))
705 continue;
706
707 if (has_doorbell(client)) {
708 /* Borrow execbuf_client (we will recreate it later) */
709 destroy_doorbell(client);
710 recreate_first_client = true;
711 }
712
713 ret = __reset_doorbell(client, db_id);
714 WARN(ret, "Doorbell %u reset failed, err %d\n", db_id, ret);
715 }
716
717 if (recreate_first_client) {
718 ret = __reserve_doorbell(client);
719 if (unlikely(ret)) {
720 DRM_ERROR("Couldn't re-reserve first client db: %d\n", ret);
721 return ret;
722 }
723
724 __update_doorbell_desc(client, client->doorbell_id);
725 }
726
727 /* Now for every client (and not only execbuf_client) make sure their
728 * doorbells are known by the GuC */
729 //for (client = client_list; client != NULL; client = client->next)
730 {
731 ret = __create_doorbell(client);
732 if (ret) {
733 DRM_ERROR("Couldn't recreate client %u doorbell: %d\n",
734 client->stage_id, ret);
735 return ret;
736 }
737 }
738
739 /* Read back & verify all (used & unused) doorbell registers */
740 for (db_id = 0; db_id < GUC_NUM_DOORBELLS; ++db_id)
741 WARN_ON(!doorbell_ok(guc, db_id));
742
743 return 0;
744 }
745
746 /**
747 * guc_client_alloc() - Allocate an i915_guc_client
748 * @dev_priv: driver private data structure
749 * @engines: The set of engines to enable for this client
750 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
751 * The kernel client to replace ExecList submission is created with
752 * NORMAL priority. Priority of a client for scheduler can be HIGH,
753 * while a preemption context can use CRITICAL.
754 * @ctx: the context that owns the client (we use the default render
755 * context)
756 *
757 * Return: An i915_guc_client object if success, else NULL.
758 */
759 static struct i915_guc_client *
guc_client_alloc(struct drm_i915_private * dev_priv,u32 engines,u32 priority,struct i915_gem_context * ctx)760 guc_client_alloc(struct drm_i915_private *dev_priv,
761 u32 engines,
762 u32 priority,
763 struct i915_gem_context *ctx)
764 {
765 struct i915_guc_client *client;
766 struct intel_guc *guc = &dev_priv->guc;
767 struct i915_vma *vma;
768 void *vaddr;
769 int ret;
770
771 client = kzalloc(sizeof(*client), GFP_KERNEL);
772 if (!client)
773 return ERR_PTR(-ENOMEM);
774
775 client->guc = guc;
776 client->owner = ctx;
777 client->engines = engines;
778 client->priority = priority;
779 client->doorbell_id = GUC_DOORBELL_INVALID;
780 lockinit(&client->wq_lock, "i9gcwql", 0, 0);
781
782 ret = ida_simple_get(&guc->stage_ids, 0, GUC_MAX_STAGE_DESCRIPTORS,
783 GFP_KERNEL);
784 if (ret < 0)
785 goto err_client;
786
787 client->stage_id = ret;
788
789 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
790 vma = intel_guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
791 if (IS_ERR(vma)) {
792 ret = PTR_ERR(vma);
793 goto err_id;
794 }
795
796 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
797 client->vma = vma;
798
799 vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
800 if (IS_ERR(vaddr)) {
801 ret = PTR_ERR(vaddr);
802 goto err_vma;
803 }
804 client->vaddr = vaddr;
805
806 client->doorbell_offset = __select_cacheline(guc);
807
808 /*
809 * Since the doorbell only requires a single cacheline, we can save
810 * space by putting the application process descriptor in the same
811 * page. Use the half of the page that doesn't include the doorbell.
812 */
813 if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
814 client->proc_desc_offset = 0;
815 else
816 client->proc_desc_offset = (GUC_DB_SIZE / 2);
817
818 guc_proc_desc_init(guc, client);
819 guc_stage_desc_init(guc, client);
820
821 ret = create_doorbell(client);
822 if (ret)
823 goto err_vaddr;
824
825 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: stage_id %u\n",
826 priority, client, client->engines, client->stage_id);
827 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%lx\n",
828 client->doorbell_id, client->doorbell_offset);
829
830 return client;
831
832 err_vaddr:
833 i915_gem_object_unpin_map(client->vma->obj);
834 err_vma:
835 i915_vma_unpin_and_release(&client->vma);
836 err_id:
837 ida_simple_remove(&guc->stage_ids, client->stage_id);
838 err_client:
839 kfree(client);
840 return ERR_PTR(ret);
841 }
842
guc_client_free(struct i915_guc_client * client)843 static void guc_client_free(struct i915_guc_client *client)
844 {
845 /*
846 * XXX: wait for any outstanding submissions before freeing memory.
847 * Be sure to drop any locks
848 */
849
850 /* FIXME: in many cases, by the time we get here the GuC has been
851 * reset, so we cannot destroy the doorbell properly. Ignore the
852 * error message for now */
853 destroy_doorbell(client);
854 guc_stage_desc_fini(client->guc, client);
855 i915_gem_object_unpin_map(client->vma->obj);
856 i915_vma_unpin_and_release(&client->vma);
857 ida_simple_remove(&client->guc->stage_ids, client->stage_id);
858 kfree(client);
859 }
860
guc_policy_init(struct guc_policy * policy)861 static void guc_policy_init(struct guc_policy *policy)
862 {
863 policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;
864 policy->preemption_time = POLICY_DEFAULT_PREEMPTION_TIME_US;
865 policy->fault_time = POLICY_DEFAULT_FAULT_TIME_US;
866 policy->policy_flags = 0;
867 }
868
guc_policies_init(struct guc_policies * policies)869 static void guc_policies_init(struct guc_policies *policies)
870 {
871 struct guc_policy *policy;
872 u32 p, i;
873
874 policies->dpc_promote_time = POLICY_DEFAULT_DPC_PROMOTE_TIME_US;
875 policies->max_num_work_items = POLICY_MAX_NUM_WI;
876
877 for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {
878 for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
879 policy = &policies->policy[p][i];
880
881 guc_policy_init(policy);
882 }
883 }
884
885 policies->is_valid = 1;
886 }
887
888 /*
889 * The first 80 dwords of the register state context, containing the
890 * execlists and ppgtt registers.
891 */
892 #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
893
guc_ads_create(struct intel_guc * guc)894 static int guc_ads_create(struct intel_guc *guc)
895 {
896 struct drm_i915_private *dev_priv = guc_to_i915(guc);
897 struct i915_vma *vma;
898 struct page *page;
899 /* The ads obj includes the struct itself and buffers passed to GuC */
900 struct {
901 struct guc_ads ads;
902 struct guc_policies policies;
903 struct guc_mmio_reg_state reg_state;
904 u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
905 } __packed *blob;
906 struct intel_engine_cs *engine;
907 enum intel_engine_id id;
908 const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
909 const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
910 u32 base;
911
912 GEM_BUG_ON(guc->ads_vma);
913
914 vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
915 if (IS_ERR(vma))
916 return PTR_ERR(vma);
917
918 guc->ads_vma = vma;
919
920 page = i915_vma_first_page(vma);
921 blob = kmap(page);
922
923 /* GuC scheduling policies */
924 guc_policies_init(&blob->policies);
925
926 /* MMIO reg state */
927 for_each_engine(engine, dev_priv, id) {
928 blob->reg_state.white_list[engine->guc_id].mmio_start =
929 engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
930
931 /* Nothing to be saved or restored for now. */
932 blob->reg_state.white_list[engine->guc_id].count = 0;
933 }
934
935 /*
936 * The GuC requires a "Golden Context" when it reinitialises
937 * engines after a reset. Here we use the Render ring default
938 * context, which must already exist and be pinned in the GGTT,
939 * so its address won't change after we've told the GuC where
940 * to find it. Note that we have to skip our header (1 page),
941 * because our GuC shared data is there.
942 */
943 blob->ads.golden_context_lrca =
944 guc_ggtt_offset(dev_priv->kernel_context->engine[RCS].state) + skipped_offset;
945
946 /*
947 * The GuC expects us to exclude the portion of the context image that
948 * it skips from the size it is to read. It starts reading from after
949 * the execlist context (so skipping the first page [PPHWSP] and 80
950 * dwords). Weird guc is weird.
951 */
952 for_each_engine(engine, dev_priv, id)
953 blob->ads.eng_state_size[engine->guc_id] = engine->context_size - skipped_size;
954
955 base = guc_ggtt_offset(vma);
956 blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
957 blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
958 blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
959
960 kunmap(page);
961
962 return 0;
963 }
964
guc_ads_destroy(struct intel_guc * guc)965 static void guc_ads_destroy(struct intel_guc *guc)
966 {
967 i915_vma_unpin_and_release(&guc->ads_vma);
968 }
969
970 /*
971 * Set up the memory resources to be shared with the GuC (via the GGTT)
972 * at firmware loading time.
973 */
i915_guc_submission_init(struct drm_i915_private * dev_priv)974 int i915_guc_submission_init(struct drm_i915_private *dev_priv)
975 {
976 struct intel_guc *guc = &dev_priv->guc;
977 struct i915_vma *vma;
978 void *vaddr;
979 int ret;
980
981 if (guc->stage_desc_pool)
982 return 0;
983
984 vma = intel_guc_allocate_vma(guc,
985 PAGE_ALIGN(sizeof(struct guc_stage_desc) *
986 GUC_MAX_STAGE_DESCRIPTORS));
987 if (IS_ERR(vma))
988 return PTR_ERR(vma);
989
990 guc->stage_desc_pool = vma;
991
992 vaddr = i915_gem_object_pin_map(guc->stage_desc_pool->obj, I915_MAP_WB);
993 if (IS_ERR(vaddr)) {
994 ret = PTR_ERR(vaddr);
995 goto err_vma;
996 }
997
998 guc->stage_desc_pool_vaddr = vaddr;
999
1000 ret = intel_guc_log_create(guc);
1001 if (ret < 0)
1002 goto err_vaddr;
1003
1004 ret = guc_ads_create(guc);
1005 if (ret < 0)
1006 goto err_log;
1007
1008 ida_init(&guc->stage_ids);
1009
1010 return 0;
1011
1012 err_log:
1013 intel_guc_log_destroy(guc);
1014 err_vaddr:
1015 i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
1016 err_vma:
1017 i915_vma_unpin_and_release(&guc->stage_desc_pool);
1018 return ret;
1019 }
1020
i915_guc_submission_fini(struct drm_i915_private * dev_priv)1021 void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
1022 {
1023 struct intel_guc *guc = &dev_priv->guc;
1024
1025 ida_destroy(&guc->stage_ids);
1026 guc_ads_destroy(guc);
1027 intel_guc_log_destroy(guc);
1028 i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
1029 i915_vma_unpin_and_release(&guc->stage_desc_pool);
1030 }
1031
guc_interrupts_capture(struct drm_i915_private * dev_priv)1032 static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
1033 {
1034 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1035 struct intel_engine_cs *engine;
1036 enum intel_engine_id id;
1037 int irqs;
1038
1039 /* tell all command streamers to forward interrupts (but not vblank) to GuC */
1040 irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
1041 for_each_engine(engine, dev_priv, id)
1042 I915_WRITE(RING_MODE_GEN7(engine), irqs);
1043
1044 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
1045 irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
1046 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1047 /* These three registers have the same bit definitions */
1048 I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
1049 I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
1050 I915_WRITE(GUC_WD_VECS_IER, ~irqs);
1051
1052 /*
1053 * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
1054 * (unmasked) PM interrupts to the GuC. All other bits of this
1055 * register *disable* generation of a specific interrupt.
1056 *
1057 * 'pm_intrmsk_mbz' indicates bits that are NOT to be set when
1058 * writing to the PM interrupt mask register, i.e. interrupts
1059 * that must not be disabled.
1060 *
1061 * If the GuC is handling these interrupts, then we must not let
1062 * the PM code disable ANY interrupt that the GuC is expecting.
1063 * So for each ENABLED (0) bit in this register, we must SET the
1064 * bit in pm_intrmsk_mbz so that it's left enabled for the GuC.
1065 * GuC needs ARAT expired interrupt unmasked hence it is set in
1066 * pm_intrmsk_mbz.
1067 *
1068 * Here we CLEAR REDIRECT_TO_GUC bit in pm_intrmsk_mbz, which will
1069 * result in the register bit being left SET!
1070 */
1071 rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
1072 rps->pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
1073 }
1074
guc_interrupts_release(struct drm_i915_private * dev_priv)1075 static void guc_interrupts_release(struct drm_i915_private *dev_priv)
1076 {
1077 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1078 struct intel_engine_cs *engine;
1079 enum intel_engine_id id;
1080 int irqs;
1081
1082 /*
1083 * tell all command streamers NOT to forward interrupts or vblank
1084 * to GuC.
1085 */
1086 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
1087 irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
1088 for_each_engine(engine, dev_priv, id)
1089 I915_WRITE(RING_MODE_GEN7(engine), irqs);
1090
1091 /* route all GT interrupts to the host */
1092 I915_WRITE(GUC_BCS_RCS_IER, 0);
1093 I915_WRITE(GUC_VCS2_VCS1_IER, 0);
1094 I915_WRITE(GUC_WD_VECS_IER, 0);
1095
1096 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
1097 rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
1098 }
1099
i915_guc_submission_enable(struct drm_i915_private * dev_priv)1100 int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
1101 {
1102 struct intel_guc *guc = &dev_priv->guc;
1103 struct i915_guc_client *client = guc->execbuf_client;
1104 struct intel_engine_cs *engine;
1105 enum intel_engine_id id;
1106 int err;
1107
1108 /*
1109 * We're using GuC work items for submitting work through GuC. Since
1110 * we're coalescing multiple requests from a single context into a
1111 * single work item prior to assigning it to execlist_port, we can
1112 * never have more work items than the total number of ports (for all
1113 * engines). The GuC firmware is controlling the HEAD of work queue,
1114 * and it is guaranteed that it will remove the work item from the
1115 * queue before our request is completed.
1116 */
1117 BUILD_BUG_ON(ARRAY_SIZE(engine->execlists.port) *
1118 sizeof(struct guc_wq_item) *
1119 I915_NUM_ENGINES > GUC_WQ_SIZE);
1120
1121 if (!client) {
1122 client = guc_client_alloc(dev_priv,
1123 INTEL_INFO(dev_priv)->ring_mask,
1124 GUC_CLIENT_PRIORITY_KMD_NORMAL,
1125 dev_priv->kernel_context);
1126 if (IS_ERR(client)) {
1127 DRM_ERROR("Failed to create GuC client for execbuf!\n");
1128 return PTR_ERR(client);
1129 }
1130
1131 guc->execbuf_client = client;
1132 }
1133
1134 err = intel_guc_sample_forcewake(guc);
1135 if (err)
1136 goto err_execbuf_client;
1137
1138 guc_reset_wq(client);
1139
1140 err = guc_init_doorbell_hw(guc);
1141 if (err)
1142 goto err_execbuf_client;
1143
1144 /* Take over from manual control of ELSP (execlists) */
1145 guc_interrupts_capture(dev_priv);
1146
1147 for_each_engine(engine, dev_priv, id) {
1148 struct intel_engine_execlists * const execlists = &engine->execlists;
1149 /* The tasklet was initialised by execlists, and may be in
1150 * a state of flux (across a reset) and so we just want to
1151 * take over the callback without changing any other state
1152 * in the tasklet.
1153 */
1154 execlists->irq_tasklet.func = i915_guc_irq_handler;
1155 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1156 tasklet_schedule(&execlists->irq_tasklet);
1157 }
1158
1159 return 0;
1160
1161 err_execbuf_client:
1162 guc_client_free(guc->execbuf_client);
1163 guc->execbuf_client = NULL;
1164 return err;
1165 }
1166
i915_guc_submission_disable(struct drm_i915_private * dev_priv)1167 void i915_guc_submission_disable(struct drm_i915_private *dev_priv)
1168 {
1169 struct intel_guc *guc = &dev_priv->guc;
1170
1171 guc_interrupts_release(dev_priv);
1172
1173 /* Revert back to manual ELSP submission */
1174 intel_engines_reset_default_submission(dev_priv);
1175
1176 guc_client_free(guc->execbuf_client);
1177 guc->execbuf_client = NULL;
1178 }
1179