1 /* $NetBSD: drm_dsc.c,v 1.3 2021/12/19 09:45:49 riastradh Exp $ */
2
3 // SPDX-License-Identifier: MIT
4 /*
5 * Copyright © 2018 Intel Corp
6 *
7 * Author:
8 * Manasi Navare <manasi.d.navare@intel.com>
9 */
10
11 #include <sys/cdefs.h>
12 __KERNEL_RCSID(0, "$NetBSD: drm_dsc.c,v 1.3 2021/12/19 09:45:49 riastradh Exp $");
13
14 #include <linux/bug.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/errno.h>
19 #include <linux/byteorder/generic.h>
20 #include <drm/drm_print.h>
21 #include <drm/drm_dp_helper.h>
22 #include <drm/drm_dsc.h>
23
24 /**
25 * DOC: dsc helpers
26 *
27 * VESA specification for DP 1.4 adds a new feature called Display Stream
28 * Compression (DSC) used to compress the pixel bits before sending it on
29 * DP/eDP/MIPI DSI interface. DSC is required to be enabled so that the existing
30 * display interfaces can support high resolutions at higher frames rates uisng
31 * the maximum available link capacity of these interfaces.
32 *
33 * These functions contain some common logic and helpers to deal with VESA
34 * Display Stream Compression standard required for DSC on Display Port/eDP or
35 * MIPI display interfaces.
36 */
37
38 /**
39 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
40 * for DisplayPort as per the DP 1.4 spec.
41 * @pps_header: Secondary data packet header for DSC Picture
42 * Parameter Set as defined in &struct dp_sdp_header
43 *
44 * DP 1.4 spec defines the secondary data packet for sending the
45 * picture parameter infoframes from the source to the sink.
46 * This function populates the SDP header defined in
47 * &struct dp_sdp_header.
48 */
drm_dsc_dp_pps_header_init(struct dp_sdp_header * pps_header)49 void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header)
50 {
51 memset(pps_header, 0, sizeof(*pps_header));
52
53 pps_header->HB1 = DP_SDP_PPS;
54 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
55 }
56 EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
57
58 /**
59 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
60 *
61 * @pps_payload:
62 * Bitwise struct for DSC Picture Parameter Set. This is defined
63 * by &struct drm_dsc_picture_parameter_set
64 * @dsc_cfg:
65 * DSC Configuration data filled by driver as defined by
66 * &struct drm_dsc_config
67 *
68 * DSC source device sends a picture parameter set (PPS) containing the
69 * information required by the sink to decode the compressed frame. Driver
70 * populates the DSC PPS struct using the DSC configuration parameters in
71 * the order expected by the DSC Display Sink device. For the DSC, the sink
72 * device expects the PPS payload in big endian format for fields
73 * that span more than 1 byte.
74 */
drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set * pps_payload,const struct drm_dsc_config * dsc_cfg)75 void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
76 const struct drm_dsc_config *dsc_cfg)
77 {
78 int i;
79
80 /* Protect against someone accidently changing struct size */
81 BUILD_BUG_ON(sizeof(*pps_payload) !=
82 DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
83
84 memset(pps_payload, 0, sizeof(*pps_payload));
85
86 /* PPS 0 */
87 pps_payload->dsc_version =
88 dsc_cfg->dsc_version_minor |
89 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
90
91 /* PPS 1, 2 is 0 */
92
93 /* PPS 3 */
94 pps_payload->pps_3 =
95 dsc_cfg->line_buf_depth |
96 dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
97
98 /* PPS 4 */
99 pps_payload->pps_4 =
100 ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
101 DSC_PPS_MSB_SHIFT) |
102 dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
103 dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
104 dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
105 dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
106
107 /* PPS 5 */
108 pps_payload->bits_per_pixel_low =
109 (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
110
111 /*
112 * The DSC panel expects the PPS packet to have big endian format
113 * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
114 * to big endian format. If format is little endian, it will swap
115 * bytes to convert to Big endian else keep it unchanged.
116 */
117
118 /* PPS 6, 7 */
119 pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
120
121 /* PPS 8, 9 */
122 pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
123
124 /* PPS 10, 11 */
125 pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
126
127 /* PPS 12, 13 */
128 pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
129
130 /* PPS 14, 15 */
131 pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
132
133 /* PPS 16 */
134 pps_payload->initial_xmit_delay_high =
135 ((dsc_cfg->initial_xmit_delay &
136 DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
137 DSC_PPS_MSB_SHIFT);
138
139 /* PPS 17 */
140 pps_payload->initial_xmit_delay_low =
141 (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
142
143 /* PPS 18, 19 */
144 pps_payload->initial_dec_delay =
145 cpu_to_be16(dsc_cfg->initial_dec_delay);
146
147 /* PPS 20 is 0 */
148
149 /* PPS 21 */
150 pps_payload->initial_scale_value =
151 dsc_cfg->initial_scale_value;
152
153 /* PPS 22, 23 */
154 pps_payload->scale_increment_interval =
155 cpu_to_be16(dsc_cfg->scale_increment_interval);
156
157 /* PPS 24 */
158 pps_payload->scale_decrement_interval_high =
159 ((dsc_cfg->scale_decrement_interval &
160 DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
161 DSC_PPS_MSB_SHIFT);
162
163 /* PPS 25 */
164 pps_payload->scale_decrement_interval_low =
165 (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
166
167 /* PPS 26[7:0], PPS 27[7:5] RESERVED */
168
169 /* PPS 27 */
170 pps_payload->first_line_bpg_offset =
171 dsc_cfg->first_line_bpg_offset;
172
173 /* PPS 28, 29 */
174 pps_payload->nfl_bpg_offset =
175 cpu_to_be16(dsc_cfg->nfl_bpg_offset);
176
177 /* PPS 30, 31 */
178 pps_payload->slice_bpg_offset =
179 cpu_to_be16(dsc_cfg->slice_bpg_offset);
180
181 /* PPS 32, 33 */
182 pps_payload->initial_offset =
183 cpu_to_be16(dsc_cfg->initial_offset);
184
185 /* PPS 34, 35 */
186 pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
187
188 /* PPS 36 */
189 pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
190
191 /* PPS 37 */
192 pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
193
194 /* PPS 38, 39 */
195 pps_payload->rc_model_size =
196 cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);
197
198 /* PPS 40 */
199 pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
200
201 /* PPS 41 */
202 pps_payload->rc_quant_incr_limit0 =
203 dsc_cfg->rc_quant_incr_limit0;
204
205 /* PPS 42 */
206 pps_payload->rc_quant_incr_limit1 =
207 dsc_cfg->rc_quant_incr_limit1;
208
209 /* PPS 43 */
210 pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
211 DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
212
213 /* PPS 44 - 57 */
214 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
215 pps_payload->rc_buf_thresh[i] =
216 dsc_cfg->rc_buf_thresh[i];
217
218 /* PPS 58 - 87 */
219 /*
220 * For DSC sink programming the RC Range parameter fields
221 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
222 */
223 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
224 pps_payload->rc_range_parameters[i] =
225 cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp <<
226 DSC_PPS_RC_RANGE_MINQP_SHIFT) |
227 (dsc_cfg->rc_range_params[i].range_max_qp <<
228 DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
229 (dsc_cfg->rc_range_params[i].range_bpg_offset));
230 }
231
232 /* PPS 88 */
233 pps_payload->native_422_420 = dsc_cfg->native_422 |
234 dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
235
236 /* PPS 89 */
237 pps_payload->second_line_bpg_offset =
238 dsc_cfg->second_line_bpg_offset;
239
240 /* PPS 90, 91 */
241 pps_payload->nsl_bpg_offset =
242 cpu_to_be16(dsc_cfg->nsl_bpg_offset);
243
244 /* PPS 92, 93 */
245 pps_payload->second_line_offset_adj =
246 cpu_to_be16(dsc_cfg->second_line_offset_adj);
247
248 /* PPS 94 - 127 are O */
249 }
250 EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
251
252 /**
253 * drm_dsc_compute_rc_parameters() - Write rate control
254 * parameters to the dsc configuration defined in
255 * &struct drm_dsc_config in accordance with the DSC 1.2
256 * specification. Some configuration fields must be present
257 * beforehand.
258 *
259 * @vdsc_cfg:
260 * DSC Configuration data partially filled by driver
261 */
drm_dsc_compute_rc_parameters(struct drm_dsc_config * vdsc_cfg)262 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
263 {
264 unsigned long groups_per_line = 0;
265 unsigned long groups_total = 0;
266 unsigned long num_extra_mux_bits = 0;
267 unsigned long slice_bits = 0;
268 unsigned long hrd_delay = 0;
269 unsigned long final_scale = 0;
270 unsigned long rbs_min = 0;
271
272 if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
273 /* Number of groups used to code each line of a slice */
274 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
275 DSC_RC_PIXELS_PER_GROUP);
276
277 /* chunksize in Bytes */
278 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
279 vdsc_cfg->bits_per_pixel,
280 (8 * 16));
281 } else {
282 /* Number of groups used to code each line of a slice */
283 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
284 DSC_RC_PIXELS_PER_GROUP);
285
286 /* chunksize in Bytes */
287 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
288 vdsc_cfg->bits_per_pixel,
289 (8 * 16));
290 }
291
292 if (vdsc_cfg->convert_rgb)
293 num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
294 (4 * vdsc_cfg->bits_per_component + 4)
295 - 2);
296 else if (vdsc_cfg->native_422)
297 num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
298 (4 * vdsc_cfg->bits_per_component + 4) +
299 3 * (4 * vdsc_cfg->bits_per_component) - 2;
300 else
301 num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
302 (4 * vdsc_cfg->bits_per_component + 4) +
303 2 * (4 * vdsc_cfg->bits_per_component) - 2;
304 /* Number of bits in one Slice */
305 slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
306
307 while ((num_extra_mux_bits > 0) &&
308 ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
309 num_extra_mux_bits--;
310
311 if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
312 vdsc_cfg->initial_scale_value = groups_per_line + 8;
313
314 /* scale_decrement_interval calculation according to DSC spec 1.11 */
315 if (vdsc_cfg->initial_scale_value > 8)
316 vdsc_cfg->scale_decrement_interval = groups_per_line /
317 (vdsc_cfg->initial_scale_value - 8);
318 else
319 vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
320
321 vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
322 (vdsc_cfg->initial_xmit_delay *
323 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
324
325 if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
326 DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
327 return -ERANGE;
328 }
329
330 final_scale = (vdsc_cfg->rc_model_size * 8) /
331 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
332 if (vdsc_cfg->slice_height > 1)
333 /*
334 * NflBpgOffset is 16 bit value with 11 fractional bits
335 * hence we multiply by 2^11 for preserving the
336 * fractional part
337 */
338 vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
339 (vdsc_cfg->slice_height - 1));
340 else
341 vdsc_cfg->nfl_bpg_offset = 0;
342
343 /* Number of groups used to code the entire slice */
344 groups_total = groups_per_line * vdsc_cfg->slice_height;
345
346 /* slice_bpg_offset is 16 bit value with 11 fractional bits */
347 vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
348 vdsc_cfg->initial_offset +
349 num_extra_mux_bits) << 11),
350 groups_total);
351
352 if (final_scale > 9) {
353 /*
354 * ScaleIncrementInterval =
355 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
356 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
357 * we need divide by 2^11 from pstDscCfg values
358 */
359 vdsc_cfg->scale_increment_interval =
360 (vdsc_cfg->final_offset * (1 << 11)) /
361 ((vdsc_cfg->nfl_bpg_offset +
362 vdsc_cfg->slice_bpg_offset) *
363 (final_scale - 9));
364 } else {
365 /*
366 * If finalScaleValue is less than or equal to 9, a value of 0 should
367 * be used to disable the scale increment at the end of the slice
368 */
369 vdsc_cfg->scale_increment_interval = 0;
370 }
371
372 /*
373 * DSC spec mentions that bits_per_pixel specifies the target
374 * bits/pixel (bpp) rate that is used by the encoder,
375 * in steps of 1/16 of a bit per pixel
376 */
377 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
378 DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
379 vdsc_cfg->bits_per_pixel, 16) +
380 groups_per_line * vdsc_cfg->first_line_bpg_offset;
381
382 hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
383 vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
384 vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
385
386 return 0;
387 }
388 EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);
389