1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30
31 #include <linux/bitfield.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/slab.h>
38 #include <linux/vga_switcheroo.h>
39
40 #include <drm/drm_displayid.h>
41 #include <drm/drm_drv.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_encoder.h>
44 #include <drm/drm_print.h>
45
46 #include "drm_crtc_internal.h"
47
oui(u8 first,u8 second,u8 third)48 static int oui(u8 first, u8 second, u8 third)
49 {
50 return (first << 16) | (second << 8) | third;
51 }
52
53 #define EDID_EST_TIMINGS 16
54 #define EDID_STD_TIMINGS 8
55 #define EDID_DETAILED_TIMINGS 4
56
57 /*
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
62 */
63
64 /* First detailed mode wrong, use largest 60Hz mode */
65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66 /* Reported 135MHz pixel clock is too high, needs adjustment */
67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68 /* Prefer the largest mode at 75 Hz */
69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70 /* Detail timing is in cm not mm */
71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72 /* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
74 */
75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
76 /* use +hsync +vsync for detailed mode */
77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
78 /* Force reduced-blanking timings for detailed modes */
79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
80 /* Force 8bpc */
81 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
82 /* Force 12bpc */
83 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
84 /* Force 6bpc */
85 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
86 /* Force 10bpc */
87 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
88 /* Non desktop display (i.e. HMD) */
89 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
90 /* Cap the DSC target bitrate to 15bpp */
91 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
92
93 #define MICROSOFT_IEEE_OUI 0xca125c
94
95 struct detailed_mode_closure {
96 struct drm_connector *connector;
97 const struct drm_edid *drm_edid;
98 bool preferred;
99 int modes;
100 };
101
102 #define LEVEL_DMT 0
103 #define LEVEL_GTF 1
104 #define LEVEL_GTF2 2
105 #define LEVEL_CVT 3
106
107 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
108 { \
109 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
110 product_id), \
111 .quirks = _quirks \
112 }
113
114 static const struct edid_quirk {
115 u32 panel_id;
116 u32 quirks;
117 } edid_quirk_list[] = {
118 /* Acer AL1706 */
119 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
120 /* Acer F51 */
121 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
122
123 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
124 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
125
126 /* BenQ GW2765 */
127 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
128
129 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
130 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
131
132 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
133 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
134
135 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
136 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
137
138 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
139 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
140
141 /* Belinea 10 15 55 */
142 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
143 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
144
145 /* Envision Peripherals, Inc. EN-7100e */
146 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
147 /* Envision EN2028 */
148 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
149
150 /* Funai Electronics PM36B */
151 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
152 EDID_QUIRK_DETAILED_IN_CM),
153
154 /* LG 27GP950 */
155 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
156
157 /* LG 27GN950 */
158 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
159
160 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
161 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
162
163 /* LG Philips LCD LP154W01-A5 */
164 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
165 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
166
167 /* Samsung SyncMaster 205BW. Note: irony */
168 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
169 /* Samsung SyncMaster 22[5-6]BW */
170 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
171 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
172
173 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
174 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
175
176 /* ViewSonic VA2026w */
177 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
178
179 /* Medion MD 30217 PG */
180 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
181
182 /* Lenovo G50 */
183 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
184
185 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
186 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
187
188 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
189 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
190
191 /* Valve Index Headset */
192 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
209
210 /* HTC Vive and Vive Pro VR Headsets */
211 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
213
214 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
215 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
217 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
218 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
219
220 /* Windows Mixed Reality Headsets */
221 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
222 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
223 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
224 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
225 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
226 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
227
228 /* Sony PlayStation VR Headset */
229 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
230
231 /* Sensics VR Headsets */
232 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
233
234 /* OSVR HDK and HDK2 VR Headsets */
235 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
236 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
237 };
238
239 /*
240 * Autogenerated from the DMT spec.
241 * This table is copied from xfree86/modes/xf86EdidModes.c.
242 */
243 static const struct drm_display_mode drm_dmt_modes[] = {
244 /* 0x01 - 640x350@85Hz */
245 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
246 736, 832, 0, 350, 382, 385, 445, 0,
247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
248 /* 0x02 - 640x400@85Hz */
249 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
250 736, 832, 0, 400, 401, 404, 445, 0,
251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
252 /* 0x03 - 720x400@85Hz */
253 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
254 828, 936, 0, 400, 401, 404, 446, 0,
255 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
256 /* 0x04 - 640x480@60Hz */
257 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
258 752, 800, 0, 480, 490, 492, 525, 0,
259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
260 /* 0x05 - 640x480@72Hz */
261 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
262 704, 832, 0, 480, 489, 492, 520, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
264 /* 0x06 - 640x480@75Hz */
265 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
266 720, 840, 0, 480, 481, 484, 500, 0,
267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
268 /* 0x07 - 640x480@85Hz */
269 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
270 752, 832, 0, 480, 481, 484, 509, 0,
271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
272 /* 0x08 - 800x600@56Hz */
273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
274 896, 1024, 0, 600, 601, 603, 625, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
276 /* 0x09 - 800x600@60Hz */
277 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
278 968, 1056, 0, 600, 601, 605, 628, 0,
279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
280 /* 0x0a - 800x600@72Hz */
281 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
282 976, 1040, 0, 600, 637, 643, 666, 0,
283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
284 /* 0x0b - 800x600@75Hz */
285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
286 896, 1056, 0, 600, 601, 604, 625, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
288 /* 0x0c - 800x600@85Hz */
289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
290 896, 1048, 0, 600, 601, 604, 631, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
292 /* 0x0d - 800x600@120Hz RB */
293 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
294 880, 960, 0, 600, 603, 607, 636, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
296 /* 0x0e - 848x480@60Hz */
297 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
298 976, 1088, 0, 480, 486, 494, 517, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
300 /* 0x0f - 1024x768@43Hz, interlace */
301 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
302 1208, 1264, 0, 768, 768, 776, 817, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
304 DRM_MODE_FLAG_INTERLACE) },
305 /* 0x10 - 1024x768@60Hz */
306 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
307 1184, 1344, 0, 768, 771, 777, 806, 0,
308 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
309 /* 0x11 - 1024x768@70Hz */
310 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
311 1184, 1328, 0, 768, 771, 777, 806, 0,
312 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
313 /* 0x12 - 1024x768@75Hz */
314 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
315 1136, 1312, 0, 768, 769, 772, 800, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
317 /* 0x13 - 1024x768@85Hz */
318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
319 1168, 1376, 0, 768, 769, 772, 808, 0,
320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
321 /* 0x14 - 1024x768@120Hz RB */
322 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
323 1104, 1184, 0, 768, 771, 775, 813, 0,
324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
325 /* 0x15 - 1152x864@75Hz */
326 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
327 1344, 1600, 0, 864, 865, 868, 900, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
329 /* 0x55 - 1280x720@60Hz */
330 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
331 1430, 1650, 0, 720, 725, 730, 750, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
333 /* 0x16 - 1280x768@60Hz RB */
334 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
335 1360, 1440, 0, 768, 771, 778, 790, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
337 /* 0x17 - 1280x768@60Hz */
338 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
339 1472, 1664, 0, 768, 771, 778, 798, 0,
340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x18 - 1280x768@75Hz */
342 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
343 1488, 1696, 0, 768, 771, 778, 805, 0,
344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
345 /* 0x19 - 1280x768@85Hz */
346 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
347 1496, 1712, 0, 768, 771, 778, 809, 0,
348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
349 /* 0x1a - 1280x768@120Hz RB */
350 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
351 1360, 1440, 0, 768, 771, 778, 813, 0,
352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
353 /* 0x1b - 1280x800@60Hz RB */
354 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
355 1360, 1440, 0, 800, 803, 809, 823, 0,
356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
357 /* 0x1c - 1280x800@60Hz */
358 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
359 1480, 1680, 0, 800, 803, 809, 831, 0,
360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x1d - 1280x800@75Hz */
362 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
363 1488, 1696, 0, 800, 803, 809, 838, 0,
364 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
365 /* 0x1e - 1280x800@85Hz */
366 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
367 1496, 1712, 0, 800, 803, 809, 843, 0,
368 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
369 /* 0x1f - 1280x800@120Hz RB */
370 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
371 1360, 1440, 0, 800, 803, 809, 847, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
373 /* 0x20 - 1280x960@60Hz */
374 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
375 1488, 1800, 0, 960, 961, 964, 1000, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
377 /* 0x21 - 1280x960@85Hz */
378 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
379 1504, 1728, 0, 960, 961, 964, 1011, 0,
380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
381 /* 0x22 - 1280x960@120Hz RB */
382 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
383 1360, 1440, 0, 960, 963, 967, 1017, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
385 /* 0x23 - 1280x1024@60Hz */
386 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
387 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
389 /* 0x24 - 1280x1024@75Hz */
390 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
391 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 0x25 - 1280x1024@85Hz */
394 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
395 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
397 /* 0x26 - 1280x1024@120Hz RB */
398 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
399 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
401 /* 0x27 - 1360x768@60Hz */
402 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
403 1536, 1792, 0, 768, 771, 777, 795, 0,
404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 0x28 - 1360x768@120Hz RB */
406 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
407 1440, 1520, 0, 768, 771, 776, 813, 0,
408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
409 /* 0x51 - 1366x768@60Hz */
410 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
411 1579, 1792, 0, 768, 771, 774, 798, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
413 /* 0x56 - 1366x768@60Hz */
414 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
415 1436, 1500, 0, 768, 769, 772, 800, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
417 /* 0x29 - 1400x1050@60Hz RB */
418 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
419 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
421 /* 0x2a - 1400x1050@60Hz */
422 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
423 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 0x2b - 1400x1050@75Hz */
426 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
427 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 0x2c - 1400x1050@85Hz */
430 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
431 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
433 /* 0x2d - 1400x1050@120Hz RB */
434 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
435 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
437 /* 0x2e - 1440x900@60Hz RB */
438 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
439 1520, 1600, 0, 900, 903, 909, 926, 0,
440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
441 /* 0x2f - 1440x900@60Hz */
442 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
443 1672, 1904, 0, 900, 903, 909, 934, 0,
444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
445 /* 0x30 - 1440x900@75Hz */
446 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
447 1688, 1936, 0, 900, 903, 909, 942, 0,
448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
449 /* 0x31 - 1440x900@85Hz */
450 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
451 1696, 1952, 0, 900, 903, 909, 948, 0,
452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
453 /* 0x32 - 1440x900@120Hz RB */
454 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
455 1520, 1600, 0, 900, 903, 909, 953, 0,
456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
457 /* 0x53 - 1600x900@60Hz */
458 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
459 1704, 1800, 0, 900, 901, 904, 1000, 0,
460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 0x33 - 1600x1200@60Hz */
462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
463 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
465 /* 0x34 - 1600x1200@65Hz */
466 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
467 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
469 /* 0x35 - 1600x1200@70Hz */
470 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
471 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
473 /* 0x36 - 1600x1200@75Hz */
474 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
475 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 0x37 - 1600x1200@85Hz */
478 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
479 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
481 /* 0x38 - 1600x1200@120Hz RB */
482 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
483 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
485 /* 0x39 - 1680x1050@60Hz RB */
486 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
487 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
489 /* 0x3a - 1680x1050@60Hz */
490 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
491 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
493 /* 0x3b - 1680x1050@75Hz */
494 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
495 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
497 /* 0x3c - 1680x1050@85Hz */
498 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
499 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
501 /* 0x3d - 1680x1050@120Hz RB */
502 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
503 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
505 /* 0x3e - 1792x1344@60Hz */
506 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
507 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
509 /* 0x3f - 1792x1344@75Hz */
510 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
511 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
513 /* 0x40 - 1792x1344@120Hz RB */
514 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
515 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
517 /* 0x41 - 1856x1392@60Hz */
518 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
519 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
521 /* 0x42 - 1856x1392@75Hz */
522 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
523 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
525 /* 0x43 - 1856x1392@120Hz RB */
526 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
527 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
529 /* 0x52 - 1920x1080@60Hz */
530 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
531 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
533 /* 0x44 - 1920x1200@60Hz RB */
534 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
535 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
537 /* 0x45 - 1920x1200@60Hz */
538 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
539 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
541 /* 0x46 - 1920x1200@75Hz */
542 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
543 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
545 /* 0x47 - 1920x1200@85Hz */
546 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
547 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
549 /* 0x48 - 1920x1200@120Hz RB */
550 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
551 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
553 /* 0x49 - 1920x1440@60Hz */
554 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
555 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
557 /* 0x4a - 1920x1440@75Hz */
558 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
559 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
561 /* 0x4b - 1920x1440@120Hz RB */
562 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
563 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
565 /* 0x54 - 2048x1152@60Hz */
566 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
567 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
569 /* 0x4c - 2560x1600@60Hz RB */
570 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
571 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
573 /* 0x4d - 2560x1600@60Hz */
574 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
575 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
576 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
577 /* 0x4e - 2560x1600@75Hz */
578 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
579 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
580 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
581 /* 0x4f - 2560x1600@85Hz */
582 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
583 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
584 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
585 /* 0x50 - 2560x1600@120Hz RB */
586 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
587 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
589 /* 0x57 - 4096x2160@60Hz RB */
590 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
591 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
593 /* 0x58 - 4096x2160@59.94Hz RB */
594 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
595 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
597 };
598
599 /*
600 * These more or less come from the DMT spec. The 720x400 modes are
601 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
602 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
603 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
604 * mode.
605 *
606 * The DMT modes have been fact-checked; the rest are mild guesses.
607 */
608 static const struct drm_display_mode edid_est_modes[] = {
609 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
610 968, 1056, 0, 600, 601, 605, 628, 0,
611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
612 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
613 896, 1024, 0, 600, 601, 603, 625, 0,
614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
616 720, 840, 0, 480, 481, 484, 500, 0,
617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
619 704, 832, 0, 480, 489, 492, 520, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
622 768, 864, 0, 480, 483, 486, 525, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
624 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
625 752, 800, 0, 480, 490, 492, 525, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
627 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
628 846, 900, 0, 400, 421, 423, 449, 0,
629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
630 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
631 846, 900, 0, 400, 412, 414, 449, 0,
632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
633 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
634 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
637 1136, 1312, 0, 768, 769, 772, 800, 0,
638 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
640 1184, 1328, 0, 768, 771, 777, 806, 0,
641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
642 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
643 1184, 1344, 0, 768, 771, 777, 806, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
645 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
646 1208, 1264, 0, 768, 768, 776, 817, 0,
647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
648 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
649 928, 1152, 0, 624, 625, 628, 667, 0,
650 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
651 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
652 896, 1056, 0, 600, 601, 604, 625, 0,
653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
654 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
655 976, 1040, 0, 600, 637, 643, 666, 0,
656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
657 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
658 1344, 1600, 0, 864, 865, 868, 900, 0,
659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
660 };
661
662 struct minimode {
663 short w;
664 short h;
665 short r;
666 short rb;
667 };
668
669 static const struct minimode est3_modes[] = {
670 /* byte 6 */
671 { 640, 350, 85, 0 },
672 { 640, 400, 85, 0 },
673 { 720, 400, 85, 0 },
674 { 640, 480, 85, 0 },
675 { 848, 480, 60, 0 },
676 { 800, 600, 85, 0 },
677 { 1024, 768, 85, 0 },
678 { 1152, 864, 75, 0 },
679 /* byte 7 */
680 { 1280, 768, 60, 1 },
681 { 1280, 768, 60, 0 },
682 { 1280, 768, 75, 0 },
683 { 1280, 768, 85, 0 },
684 { 1280, 960, 60, 0 },
685 { 1280, 960, 85, 0 },
686 { 1280, 1024, 60, 0 },
687 { 1280, 1024, 85, 0 },
688 /* byte 8 */
689 { 1360, 768, 60, 0 },
690 { 1440, 900, 60, 1 },
691 { 1440, 900, 60, 0 },
692 { 1440, 900, 75, 0 },
693 { 1440, 900, 85, 0 },
694 { 1400, 1050, 60, 1 },
695 { 1400, 1050, 60, 0 },
696 { 1400, 1050, 75, 0 },
697 /* byte 9 */
698 { 1400, 1050, 85, 0 },
699 { 1680, 1050, 60, 1 },
700 { 1680, 1050, 60, 0 },
701 { 1680, 1050, 75, 0 },
702 { 1680, 1050, 85, 0 },
703 { 1600, 1200, 60, 0 },
704 { 1600, 1200, 65, 0 },
705 { 1600, 1200, 70, 0 },
706 /* byte 10 */
707 { 1600, 1200, 75, 0 },
708 { 1600, 1200, 85, 0 },
709 { 1792, 1344, 60, 0 },
710 { 1792, 1344, 75, 0 },
711 { 1856, 1392, 60, 0 },
712 { 1856, 1392, 75, 0 },
713 { 1920, 1200, 60, 1 },
714 { 1920, 1200, 60, 0 },
715 /* byte 11 */
716 { 1920, 1200, 75, 0 },
717 { 1920, 1200, 85, 0 },
718 { 1920, 1440, 60, 0 },
719 { 1920, 1440, 75, 0 },
720 };
721
722 static const struct minimode extra_modes[] = {
723 { 1024, 576, 60, 0 },
724 { 1366, 768, 60, 0 },
725 { 1600, 900, 60, 0 },
726 { 1680, 945, 60, 0 },
727 { 1920, 1080, 60, 0 },
728 { 2048, 1152, 60, 0 },
729 { 2048, 1536, 60, 0 },
730 };
731
732 /*
733 * From CEA/CTA-861 spec.
734 *
735 * Do not access directly, instead always use cea_mode_for_vic().
736 */
737 static const struct drm_display_mode edid_cea_modes_1[] = {
738 /* 1 - 640x480@60Hz 4:3 */
739 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
740 752, 800, 0, 480, 490, 492, 525, 0,
741 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
742 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
743 /* 2 - 720x480@60Hz 4:3 */
744 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
745 798, 858, 0, 480, 489, 495, 525, 0,
746 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
747 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
748 /* 3 - 720x480@60Hz 16:9 */
749 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
750 798, 858, 0, 480, 489, 495, 525, 0,
751 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
752 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
753 /* 4 - 1280x720@60Hz 16:9 */
754 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
755 1430, 1650, 0, 720, 725, 730, 750, 0,
756 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
758 /* 5 - 1920x1080i@60Hz 16:9 */
759 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
760 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
761 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
762 DRM_MODE_FLAG_INTERLACE),
763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
764 /* 6 - 720(1440)x480i@60Hz 4:3 */
765 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
766 801, 858, 0, 480, 488, 494, 525, 0,
767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
768 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
770 /* 7 - 720(1440)x480i@60Hz 16:9 */
771 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
772 801, 858, 0, 480, 488, 494, 525, 0,
773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
774 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
776 /* 8 - 720(1440)x240@60Hz 4:3 */
777 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
778 801, 858, 0, 240, 244, 247, 262, 0,
779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
780 DRM_MODE_FLAG_DBLCLK),
781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
782 /* 9 - 720(1440)x240@60Hz 16:9 */
783 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
784 801, 858, 0, 240, 244, 247, 262, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
786 DRM_MODE_FLAG_DBLCLK),
787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
788 /* 10 - 2880x480i@60Hz 4:3 */
789 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
790 3204, 3432, 0, 480, 488, 494, 525, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
792 DRM_MODE_FLAG_INTERLACE),
793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
794 /* 11 - 2880x480i@60Hz 16:9 */
795 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
796 3204, 3432, 0, 480, 488, 494, 525, 0,
797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
798 DRM_MODE_FLAG_INTERLACE),
799 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
800 /* 12 - 2880x240@60Hz 4:3 */
801 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
802 3204, 3432, 0, 240, 244, 247, 262, 0,
803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
804 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
805 /* 13 - 2880x240@60Hz 16:9 */
806 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
807 3204, 3432, 0, 240, 244, 247, 262, 0,
808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
809 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
810 /* 14 - 1440x480@60Hz 4:3 */
811 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
812 1596, 1716, 0, 480, 489, 495, 525, 0,
813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
814 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
815 /* 15 - 1440x480@60Hz 16:9 */
816 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
817 1596, 1716, 0, 480, 489, 495, 525, 0,
818 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
819 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
820 /* 16 - 1920x1080@60Hz 16:9 */
821 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
822 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
824 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
825 /* 17 - 720x576@50Hz 4:3 */
826 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
827 796, 864, 0, 576, 581, 586, 625, 0,
828 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
829 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
830 /* 18 - 720x576@50Hz 16:9 */
831 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
832 796, 864, 0, 576, 581, 586, 625, 0,
833 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
834 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
835 /* 19 - 1280x720@50Hz 16:9 */
836 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
837 1760, 1980, 0, 720, 725, 730, 750, 0,
838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
840 /* 20 - 1920x1080i@50Hz 16:9 */
841 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
842 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
843 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
844 DRM_MODE_FLAG_INTERLACE),
845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
846 /* 21 - 720(1440)x576i@50Hz 4:3 */
847 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
848 795, 864, 0, 576, 580, 586, 625, 0,
849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
850 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
852 /* 22 - 720(1440)x576i@50Hz 16:9 */
853 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
854 795, 864, 0, 576, 580, 586, 625, 0,
855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
856 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
858 /* 23 - 720(1440)x288@50Hz 4:3 */
859 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
860 795, 864, 0, 288, 290, 293, 312, 0,
861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
862 DRM_MODE_FLAG_DBLCLK),
863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
864 /* 24 - 720(1440)x288@50Hz 16:9 */
865 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
866 795, 864, 0, 288, 290, 293, 312, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
868 DRM_MODE_FLAG_DBLCLK),
869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
870 /* 25 - 2880x576i@50Hz 4:3 */
871 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
872 3180, 3456, 0, 576, 580, 586, 625, 0,
873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
874 DRM_MODE_FLAG_INTERLACE),
875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
876 /* 26 - 2880x576i@50Hz 16:9 */
877 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
878 3180, 3456, 0, 576, 580, 586, 625, 0,
879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
880 DRM_MODE_FLAG_INTERLACE),
881 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
882 /* 27 - 2880x288@50Hz 4:3 */
883 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
884 3180, 3456, 0, 288, 290, 293, 312, 0,
885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
886 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
887 /* 28 - 2880x288@50Hz 16:9 */
888 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
889 3180, 3456, 0, 288, 290, 293, 312, 0,
890 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
891 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
892 /* 29 - 1440x576@50Hz 4:3 */
893 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
894 1592, 1728, 0, 576, 581, 586, 625, 0,
895 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
896 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
897 /* 30 - 1440x576@50Hz 16:9 */
898 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
899 1592, 1728, 0, 576, 581, 586, 625, 0,
900 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
901 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
902 /* 31 - 1920x1080@50Hz 16:9 */
903 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
904 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
905 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
906 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
907 /* 32 - 1920x1080@24Hz 16:9 */
908 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
909 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
911 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
912 /* 33 - 1920x1080@25Hz 16:9 */
913 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
914 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
915 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
916 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
917 /* 34 - 1920x1080@30Hz 16:9 */
918 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
919 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
920 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
921 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
922 /* 35 - 2880x480@60Hz 4:3 */
923 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
924 3192, 3432, 0, 480, 489, 495, 525, 0,
925 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
926 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
927 /* 36 - 2880x480@60Hz 16:9 */
928 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
929 3192, 3432, 0, 480, 489, 495, 525, 0,
930 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
931 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
932 /* 37 - 2880x576@50Hz 4:3 */
933 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
934 3184, 3456, 0, 576, 581, 586, 625, 0,
935 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
936 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
937 /* 38 - 2880x576@50Hz 16:9 */
938 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
939 3184, 3456, 0, 576, 581, 586, 625, 0,
940 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
941 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
942 /* 39 - 1920x1080i@50Hz 16:9 */
943 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
944 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
945 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
946 DRM_MODE_FLAG_INTERLACE),
947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
948 /* 40 - 1920x1080i@100Hz 16:9 */
949 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
950 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
951 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
952 DRM_MODE_FLAG_INTERLACE),
953 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
954 /* 41 - 1280x720@100Hz 16:9 */
955 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
956 1760, 1980, 0, 720, 725, 730, 750, 0,
957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
958 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
959 /* 42 - 720x576@100Hz 4:3 */
960 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
961 796, 864, 0, 576, 581, 586, 625, 0,
962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
963 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
964 /* 43 - 720x576@100Hz 16:9 */
965 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
966 796, 864, 0, 576, 581, 586, 625, 0,
967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
969 /* 44 - 720(1440)x576i@100Hz 4:3 */
970 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
971 795, 864, 0, 576, 580, 586, 625, 0,
972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
974 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
975 /* 45 - 720(1440)x576i@100Hz 16:9 */
976 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
977 795, 864, 0, 576, 580, 586, 625, 0,
978 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
979 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
981 /* 46 - 1920x1080i@120Hz 16:9 */
982 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
983 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
985 DRM_MODE_FLAG_INTERLACE),
986 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
987 /* 47 - 1280x720@120Hz 16:9 */
988 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
989 1430, 1650, 0, 720, 725, 730, 750, 0,
990 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
991 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
992 /* 48 - 720x480@120Hz 4:3 */
993 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
994 798, 858, 0, 480, 489, 495, 525, 0,
995 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
997 /* 49 - 720x480@120Hz 16:9 */
998 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
999 798, 858, 0, 480, 489, 495, 525, 0,
1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1001 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1002 /* 50 - 720(1440)x480i@120Hz 4:3 */
1003 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1004 801, 858, 0, 480, 488, 494, 525, 0,
1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1006 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1008 /* 51 - 720(1440)x480i@120Hz 16:9 */
1009 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1010 801, 858, 0, 480, 488, 494, 525, 0,
1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1012 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1013 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1014 /* 52 - 720x576@200Hz 4:3 */
1015 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1016 796, 864, 0, 576, 581, 586, 625, 0,
1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1018 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1019 /* 53 - 720x576@200Hz 16:9 */
1020 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1021 796, 864, 0, 576, 581, 586, 625, 0,
1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1023 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1024 /* 54 - 720(1440)x576i@200Hz 4:3 */
1025 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1026 795, 864, 0, 576, 580, 586, 625, 0,
1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1028 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1030 /* 55 - 720(1440)x576i@200Hz 16:9 */
1031 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1032 795, 864, 0, 576, 580, 586, 625, 0,
1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1034 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1035 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1036 /* 56 - 720x480@240Hz 4:3 */
1037 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1038 798, 858, 0, 480, 489, 495, 525, 0,
1039 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1041 /* 57 - 720x480@240Hz 16:9 */
1042 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1043 798, 858, 0, 480, 489, 495, 525, 0,
1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1045 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1046 /* 58 - 720(1440)x480i@240Hz 4:3 */
1047 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1048 801, 858, 0, 480, 488, 494, 525, 0,
1049 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1050 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1052 /* 59 - 720(1440)x480i@240Hz 16:9 */
1053 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1054 801, 858, 0, 480, 488, 494, 525, 0,
1055 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1056 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1057 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1058 /* 60 - 1280x720@24Hz 16:9 */
1059 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1060 3080, 3300, 0, 720, 725, 730, 750, 0,
1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1062 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1063 /* 61 - 1280x720@25Hz 16:9 */
1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1065 3740, 3960, 0, 720, 725, 730, 750, 0,
1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1067 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1068 /* 62 - 1280x720@30Hz 16:9 */
1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1070 3080, 3300, 0, 720, 725, 730, 750, 0,
1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1072 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1073 /* 63 - 1920x1080@120Hz 16:9 */
1074 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1075 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1077 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1078 /* 64 - 1920x1080@100Hz 16:9 */
1079 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1080 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1082 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1083 /* 65 - 1280x720@24Hz 64:27 */
1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1085 3080, 3300, 0, 720, 725, 730, 750, 0,
1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1087 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1088 /* 66 - 1280x720@25Hz 64:27 */
1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1090 3740, 3960, 0, 720, 725, 730, 750, 0,
1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1092 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1093 /* 67 - 1280x720@30Hz 64:27 */
1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1095 3080, 3300, 0, 720, 725, 730, 750, 0,
1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1097 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1098 /* 68 - 1280x720@50Hz 64:27 */
1099 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1100 1760, 1980, 0, 720, 725, 730, 750, 0,
1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1102 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1103 /* 69 - 1280x720@60Hz 64:27 */
1104 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1105 1430, 1650, 0, 720, 725, 730, 750, 0,
1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1107 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1108 /* 70 - 1280x720@100Hz 64:27 */
1109 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1110 1760, 1980, 0, 720, 725, 730, 750, 0,
1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1112 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1113 /* 71 - 1280x720@120Hz 64:27 */
1114 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1115 1430, 1650, 0, 720, 725, 730, 750, 0,
1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1117 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1118 /* 72 - 1920x1080@24Hz 64:27 */
1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1120 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1122 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1123 /* 73 - 1920x1080@25Hz 64:27 */
1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1127 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1128 /* 74 - 1920x1080@30Hz 64:27 */
1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1132 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1133 /* 75 - 1920x1080@50Hz 64:27 */
1134 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1135 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1137 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1138 /* 76 - 1920x1080@60Hz 64:27 */
1139 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1140 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1142 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1143 /* 77 - 1920x1080@100Hz 64:27 */
1144 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1145 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1147 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1148 /* 78 - 1920x1080@120Hz 64:27 */
1149 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1150 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1152 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1153 /* 79 - 1680x720@24Hz 64:27 */
1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1155 3080, 3300, 0, 720, 725, 730, 750, 0,
1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1157 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1158 /* 80 - 1680x720@25Hz 64:27 */
1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1160 2948, 3168, 0, 720, 725, 730, 750, 0,
1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1162 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1163 /* 81 - 1680x720@30Hz 64:27 */
1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1165 2420, 2640, 0, 720, 725, 730, 750, 0,
1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1167 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1168 /* 82 - 1680x720@50Hz 64:27 */
1169 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1170 1980, 2200, 0, 720, 725, 730, 750, 0,
1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1172 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1173 /* 83 - 1680x720@60Hz 64:27 */
1174 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1175 1980, 2200, 0, 720, 725, 730, 750, 0,
1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1177 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1178 /* 84 - 1680x720@100Hz 64:27 */
1179 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1180 1780, 2000, 0, 720, 725, 730, 825, 0,
1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1182 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1183 /* 85 - 1680x720@120Hz 64:27 */
1184 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1185 1780, 2000, 0, 720, 725, 730, 825, 0,
1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1187 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1188 /* 86 - 2560x1080@24Hz 64:27 */
1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1190 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1192 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1193 /* 87 - 2560x1080@25Hz 64:27 */
1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1195 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1197 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1198 /* 88 - 2560x1080@30Hz 64:27 */
1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1200 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1202 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1203 /* 89 - 2560x1080@50Hz 64:27 */
1204 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1205 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1207 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1208 /* 90 - 2560x1080@60Hz 64:27 */
1209 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1210 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1212 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1213 /* 91 - 2560x1080@100Hz 64:27 */
1214 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1215 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1217 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1218 /* 92 - 2560x1080@120Hz 64:27 */
1219 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1220 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1222 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1223 /* 93 - 3840x2160@24Hz 16:9 */
1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1225 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1227 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1228 /* 94 - 3840x2160@25Hz 16:9 */
1229 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1230 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1232 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1233 /* 95 - 3840x2160@30Hz 16:9 */
1234 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1235 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1237 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1238 /* 96 - 3840x2160@50Hz 16:9 */
1239 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1240 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1242 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1243 /* 97 - 3840x2160@60Hz 16:9 */
1244 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1245 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1247 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1248 /* 98 - 4096x2160@24Hz 256:135 */
1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1250 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1252 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1253 /* 99 - 4096x2160@25Hz 256:135 */
1254 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1255 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1257 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1258 /* 100 - 4096x2160@30Hz 256:135 */
1259 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1260 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1262 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1263 /* 101 - 4096x2160@50Hz 256:135 */
1264 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1265 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1267 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1268 /* 102 - 4096x2160@60Hz 256:135 */
1269 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1270 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1272 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1273 /* 103 - 3840x2160@24Hz 64:27 */
1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1275 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1277 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1278 /* 104 - 3840x2160@25Hz 64:27 */
1279 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1280 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1282 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1283 /* 105 - 3840x2160@30Hz 64:27 */
1284 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1285 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1287 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1288 /* 106 - 3840x2160@50Hz 64:27 */
1289 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1290 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1292 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1293 /* 107 - 3840x2160@60Hz 64:27 */
1294 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1295 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1297 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1298 /* 108 - 1280x720@48Hz 16:9 */
1299 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1300 2280, 2500, 0, 720, 725, 730, 750, 0,
1301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1302 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1303 /* 109 - 1280x720@48Hz 64:27 */
1304 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1305 2280, 2500, 0, 720, 725, 730, 750, 0,
1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1307 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1308 /* 110 - 1680x720@48Hz 64:27 */
1309 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1310 2530, 2750, 0, 720, 725, 730, 750, 0,
1311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1312 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1313 /* 111 - 1920x1080@48Hz 16:9 */
1314 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1315 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1317 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1318 /* 112 - 1920x1080@48Hz 64:27 */
1319 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1320 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1322 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1323 /* 113 - 2560x1080@48Hz 64:27 */
1324 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1325 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1327 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1328 /* 114 - 3840x2160@48Hz 16:9 */
1329 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1330 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1332 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1333 /* 115 - 4096x2160@48Hz 256:135 */
1334 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1335 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1337 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1338 /* 116 - 3840x2160@48Hz 64:27 */
1339 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1340 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1342 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1343 /* 117 - 3840x2160@100Hz 16:9 */
1344 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1345 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1347 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1348 /* 118 - 3840x2160@120Hz 16:9 */
1349 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1350 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1352 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1353 /* 119 - 3840x2160@100Hz 64:27 */
1354 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1355 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1357 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1358 /* 120 - 3840x2160@120Hz 64:27 */
1359 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1360 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1362 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1363 /* 121 - 5120x2160@24Hz 64:27 */
1364 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1365 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1367 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1368 /* 122 - 5120x2160@25Hz 64:27 */
1369 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1370 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1372 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1373 /* 123 - 5120x2160@30Hz 64:27 */
1374 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1375 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1377 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1378 /* 124 - 5120x2160@48Hz 64:27 */
1379 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1380 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1382 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1383 /* 125 - 5120x2160@50Hz 64:27 */
1384 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1385 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1387 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1388 /* 126 - 5120x2160@60Hz 64:27 */
1389 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1390 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1392 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1393 /* 127 - 5120x2160@100Hz 64:27 */
1394 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1395 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1397 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1398 };
1399
1400 /*
1401 * From CEA/CTA-861 spec.
1402 *
1403 * Do not access directly, instead always use cea_mode_for_vic().
1404 */
1405 static const struct drm_display_mode edid_cea_modes_193[] = {
1406 /* 193 - 5120x2160@120Hz 64:27 */
1407 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1408 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1410 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1411 /* 194 - 7680x4320@24Hz 16:9 */
1412 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1413 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1415 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1416 /* 195 - 7680x4320@25Hz 16:9 */
1417 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1418 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1420 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1421 /* 196 - 7680x4320@30Hz 16:9 */
1422 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1423 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1425 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1426 /* 197 - 7680x4320@48Hz 16:9 */
1427 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1428 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1430 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1431 /* 198 - 7680x4320@50Hz 16:9 */
1432 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1433 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1435 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1436 /* 199 - 7680x4320@60Hz 16:9 */
1437 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1438 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1440 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1441 /* 200 - 7680x4320@100Hz 16:9 */
1442 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1443 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1445 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1446 /* 201 - 7680x4320@120Hz 16:9 */
1447 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1448 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1450 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1451 /* 202 - 7680x4320@24Hz 64:27 */
1452 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1453 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1455 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1456 /* 203 - 7680x4320@25Hz 64:27 */
1457 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1458 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1460 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1461 /* 204 - 7680x4320@30Hz 64:27 */
1462 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1463 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1465 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1466 /* 205 - 7680x4320@48Hz 64:27 */
1467 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1468 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1470 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1471 /* 206 - 7680x4320@50Hz 64:27 */
1472 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1473 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1475 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1476 /* 207 - 7680x4320@60Hz 64:27 */
1477 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1478 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1480 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1481 /* 208 - 7680x4320@100Hz 64:27 */
1482 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1483 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1485 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1486 /* 209 - 7680x4320@120Hz 64:27 */
1487 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1488 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1490 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1491 /* 210 - 10240x4320@24Hz 64:27 */
1492 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1493 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1495 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1496 /* 211 - 10240x4320@25Hz 64:27 */
1497 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1498 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1500 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1501 /* 212 - 10240x4320@30Hz 64:27 */
1502 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1503 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1505 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1506 /* 213 - 10240x4320@48Hz 64:27 */
1507 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1508 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1510 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1511 /* 214 - 10240x4320@50Hz 64:27 */
1512 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1513 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1515 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1516 /* 215 - 10240x4320@60Hz 64:27 */
1517 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1518 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1520 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1521 /* 216 - 10240x4320@100Hz 64:27 */
1522 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1523 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1525 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1526 /* 217 - 10240x4320@120Hz 64:27 */
1527 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1528 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1530 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1531 /* 218 - 4096x2160@100Hz 256:135 */
1532 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1533 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1535 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1536 /* 219 - 4096x2160@120Hz 256:135 */
1537 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1538 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1540 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1541 };
1542
1543 /*
1544 * HDMI 1.4 4k modes. Index using the VIC.
1545 */
1546 static const struct drm_display_mode edid_4k_modes[] = {
1547 /* 0 - dummy, VICs start at 1 */
1548 { },
1549 /* 1 - 3840x2160@30Hz */
1550 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1551 3840, 4016, 4104, 4400, 0,
1552 2160, 2168, 2178, 2250, 0,
1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1555 /* 2 - 3840x2160@25Hz */
1556 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1557 3840, 4896, 4984, 5280, 0,
1558 2160, 2168, 2178, 2250, 0,
1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1560 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1561 /* 3 - 3840x2160@24Hz */
1562 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1563 3840, 5116, 5204, 5500, 0,
1564 2160, 2168, 2178, 2250, 0,
1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1567 /* 4 - 4096x2160@24Hz (SMPTE) */
1568 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1569 4096, 5116, 5204, 5500, 0,
1570 2160, 2168, 2178, 2250, 0,
1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1572 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1573 };
1574
1575 /*** DDC fetch and block validation ***/
1576
1577 /*
1578 * The opaque EDID type, internal to drm_edid.c.
1579 */
1580 struct drm_edid {
1581 /* Size allocated for edid */
1582 size_t size;
1583 const struct edid *edid;
1584 };
1585
1586 static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1587
edid_hfeeodb_block_count(const struct edid * edid)1588 static int edid_hfeeodb_block_count(const struct edid *edid)
1589 {
1590 int eeodb = edid_hfeeodb_extension_block_count(edid);
1591
1592 return eeodb ? eeodb + 1 : 0;
1593 }
1594
edid_extension_block_count(const struct edid * edid)1595 static int edid_extension_block_count(const struct edid *edid)
1596 {
1597 return edid->extensions;
1598 }
1599
edid_block_count(const struct edid * edid)1600 static int edid_block_count(const struct edid *edid)
1601 {
1602 return edid_extension_block_count(edid) + 1;
1603 }
1604
edid_size_by_blocks(int num_blocks)1605 static int edid_size_by_blocks(int num_blocks)
1606 {
1607 return num_blocks * EDID_LENGTH;
1608 }
1609
edid_size(const struct edid * edid)1610 static int edid_size(const struct edid *edid)
1611 {
1612 return edid_size_by_blocks(edid_block_count(edid));
1613 }
1614
edid_block_data(const struct edid * edid,int index)1615 static const void *edid_block_data(const struct edid *edid, int index)
1616 {
1617 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1618
1619 return edid + index;
1620 }
1621
edid_extension_block_data(const struct edid * edid,int index)1622 static const void *edid_extension_block_data(const struct edid *edid, int index)
1623 {
1624 return edid_block_data(edid, index + 1);
1625 }
1626
1627 /* EDID block count indicated in EDID, may exceed allocated size */
__drm_edid_block_count(const struct drm_edid * drm_edid)1628 static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1629 {
1630 int num_blocks;
1631
1632 /* Starting point */
1633 num_blocks = edid_block_count(drm_edid->edid);
1634
1635 /* HF-EEODB override */
1636 if (drm_edid->size >= edid_size_by_blocks(2)) {
1637 int eeodb;
1638
1639 /*
1640 * Note: HF-EEODB may specify a smaller extension count than the
1641 * regular one. Unlike in buffer allocation, here we can use it.
1642 */
1643 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1644 if (eeodb)
1645 num_blocks = eeodb;
1646 }
1647
1648 return num_blocks;
1649 }
1650
1651 /* EDID block count, limited by allocated size */
drm_edid_block_count(const struct drm_edid * drm_edid)1652 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1653 {
1654 /* Limit by allocated size */
1655 return min(__drm_edid_block_count(drm_edid),
1656 (int)drm_edid->size / EDID_LENGTH);
1657 }
1658
1659 /* EDID extension block count, limited by allocated size */
drm_edid_extension_block_count(const struct drm_edid * drm_edid)1660 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1661 {
1662 return drm_edid_block_count(drm_edid) - 1;
1663 }
1664
drm_edid_block_data(const struct drm_edid * drm_edid,int index)1665 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1666 {
1667 return edid_block_data(drm_edid->edid, index);
1668 }
1669
drm_edid_extension_block_data(const struct drm_edid * drm_edid,int index)1670 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1671 int index)
1672 {
1673 return edid_extension_block_data(drm_edid->edid, index);
1674 }
1675
1676 /*
1677 * Initializer helper for legacy interfaces, where we have no choice but to
1678 * trust edid size. Not for general purpose use.
1679 */
drm_edid_legacy_init(struct drm_edid * drm_edid,const struct edid * edid)1680 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1681 const struct edid *edid)
1682 {
1683 if (!edid)
1684 return NULL;
1685
1686 memset(drm_edid, 0, sizeof(*drm_edid));
1687
1688 drm_edid->edid = edid;
1689 drm_edid->size = edid_size(edid);
1690
1691 return drm_edid;
1692 }
1693
1694 /*
1695 * EDID base and extension block iterator.
1696 *
1697 * struct drm_edid_iter iter;
1698 * const u8 *block;
1699 *
1700 * drm_edid_iter_begin(drm_edid, &iter);
1701 * drm_edid_iter_for_each(block, &iter) {
1702 * // do stuff with block
1703 * }
1704 * drm_edid_iter_end(&iter);
1705 */
1706 struct drm_edid_iter {
1707 const struct drm_edid *drm_edid;
1708
1709 /* Current block index. */
1710 int index;
1711 };
1712
drm_edid_iter_begin(const struct drm_edid * drm_edid,struct drm_edid_iter * iter)1713 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1714 struct drm_edid_iter *iter)
1715 {
1716 memset(iter, 0, sizeof(*iter));
1717
1718 iter->drm_edid = drm_edid;
1719 }
1720
__drm_edid_iter_next(struct drm_edid_iter * iter)1721 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1722 {
1723 const void *block = NULL;
1724
1725 if (!iter->drm_edid)
1726 return NULL;
1727
1728 if (iter->index < drm_edid_block_count(iter->drm_edid))
1729 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1730
1731 return block;
1732 }
1733
1734 #define drm_edid_iter_for_each(__block, __iter) \
1735 while (((__block) = __drm_edid_iter_next(__iter)))
1736
drm_edid_iter_end(struct drm_edid_iter * iter)1737 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1738 {
1739 memset(iter, 0, sizeof(*iter));
1740 }
1741
1742 static const u8 edid_header[] = {
1743 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1744 };
1745
edid_header_fix(void * edid)1746 static void edid_header_fix(void *edid)
1747 {
1748 memcpy(edid, edid_header, sizeof(edid_header));
1749 }
1750
1751 /**
1752 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1753 * @_edid: pointer to raw base EDID block
1754 *
1755 * Sanity check the header of the base EDID block.
1756 *
1757 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1758 */
drm_edid_header_is_valid(const void * _edid)1759 int drm_edid_header_is_valid(const void *_edid)
1760 {
1761 const struct edid *edid = _edid;
1762 int i, score = 0;
1763
1764 for (i = 0; i < sizeof(edid_header); i++) {
1765 if (edid->header[i] == edid_header[i])
1766 score++;
1767 }
1768
1769 return score;
1770 }
1771 EXPORT_SYMBOL(drm_edid_header_is_valid);
1772
1773 static int edid_fixup __read_mostly = 6;
1774 module_param_named(edid_fixup, edid_fixup, int, 0400);
1775 MODULE_PARM_DESC(edid_fixup,
1776 "Minimum number of valid EDID header bytes (0-8, default 6)");
1777
edid_block_compute_checksum(const void * _block)1778 static int edid_block_compute_checksum(const void *_block)
1779 {
1780 const u8 *block = _block;
1781 int i;
1782 u8 csum = 0, crc = 0;
1783
1784 for (i = 0; i < EDID_LENGTH - 1; i++)
1785 csum += block[i];
1786
1787 crc = 0x100 - csum;
1788
1789 return crc;
1790 }
1791
edid_block_get_checksum(const void * _block)1792 static int edid_block_get_checksum(const void *_block)
1793 {
1794 const struct edid *block = _block;
1795
1796 return block->checksum;
1797 }
1798
edid_block_tag(const void * _block)1799 static int edid_block_tag(const void *_block)
1800 {
1801 const u8 *block = _block;
1802
1803 return block[0];
1804 }
1805
edid_block_is_zero(const void * edid)1806 static bool edid_block_is_zero(const void *edid)
1807 {
1808 return !memchr_inv(edid, 0, EDID_LENGTH);
1809 }
1810
1811 /**
1812 * drm_edid_are_equal - compare two edid blobs.
1813 * @edid1: pointer to first blob
1814 * @edid2: pointer to second blob
1815 * This helper can be used during probing to determine if
1816 * edid had changed.
1817 */
drm_edid_are_equal(const struct edid * edid1,const struct edid * edid2)1818 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1819 {
1820 int edid1_len, edid2_len;
1821 bool edid1_present = edid1 != NULL;
1822 bool edid2_present = edid2 != NULL;
1823
1824 if (edid1_present != edid2_present)
1825 return false;
1826
1827 if (edid1) {
1828 edid1_len = edid_size(edid1);
1829 edid2_len = edid_size(edid2);
1830
1831 if (edid1_len != edid2_len)
1832 return false;
1833
1834 if (memcmp(edid1, edid2, edid1_len))
1835 return false;
1836 }
1837
1838 return true;
1839 }
1840 EXPORT_SYMBOL(drm_edid_are_equal);
1841
1842 enum edid_block_status {
1843 EDID_BLOCK_OK = 0,
1844 EDID_BLOCK_READ_FAIL,
1845 EDID_BLOCK_NULL,
1846 EDID_BLOCK_ZERO,
1847 EDID_BLOCK_HEADER_CORRUPT,
1848 EDID_BLOCK_HEADER_REPAIR,
1849 EDID_BLOCK_HEADER_FIXED,
1850 EDID_BLOCK_CHECKSUM,
1851 EDID_BLOCK_VERSION,
1852 };
1853
edid_block_check(const void * _block,bool is_base_block)1854 static enum edid_block_status edid_block_check(const void *_block,
1855 bool is_base_block)
1856 {
1857 const struct edid *block = _block;
1858
1859 if (!block)
1860 return EDID_BLOCK_NULL;
1861
1862 if (is_base_block) {
1863 int score = drm_edid_header_is_valid(block);
1864
1865 if (score < clamp(edid_fixup, 0, 8)) {
1866 if (edid_block_is_zero(block))
1867 return EDID_BLOCK_ZERO;
1868 else
1869 return EDID_BLOCK_HEADER_CORRUPT;
1870 }
1871
1872 if (score < 8)
1873 return EDID_BLOCK_HEADER_REPAIR;
1874 }
1875
1876 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1877 if (edid_block_is_zero(block))
1878 return EDID_BLOCK_ZERO;
1879 else
1880 return EDID_BLOCK_CHECKSUM;
1881 }
1882
1883 if (is_base_block) {
1884 if (block->version != 1)
1885 return EDID_BLOCK_VERSION;
1886 }
1887
1888 return EDID_BLOCK_OK;
1889 }
1890
edid_block_status_valid(enum edid_block_status status,int tag)1891 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1892 {
1893 return status == EDID_BLOCK_OK ||
1894 status == EDID_BLOCK_HEADER_FIXED ||
1895 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1896 }
1897
edid_block_valid(const void * block,bool base)1898 static bool edid_block_valid(const void *block, bool base)
1899 {
1900 return edid_block_status_valid(edid_block_check(block, base),
1901 edid_block_tag(block));
1902 }
1903
edid_block_status_print(enum edid_block_status status,const struct edid * block,int block_num)1904 static void edid_block_status_print(enum edid_block_status status,
1905 const struct edid *block,
1906 int block_num)
1907 {
1908 switch (status) {
1909 case EDID_BLOCK_OK:
1910 break;
1911 case EDID_BLOCK_READ_FAIL:
1912 pr_debug("EDID block %d read failed\n", block_num);
1913 break;
1914 case EDID_BLOCK_NULL:
1915 pr_debug("EDID block %d pointer is NULL\n", block_num);
1916 break;
1917 case EDID_BLOCK_ZERO:
1918 pr_notice("EDID block %d is all zeroes\n", block_num);
1919 break;
1920 case EDID_BLOCK_HEADER_CORRUPT:
1921 pr_notice("EDID has corrupt header\n");
1922 break;
1923 case EDID_BLOCK_HEADER_REPAIR:
1924 pr_debug("EDID corrupt header needs repair\n");
1925 break;
1926 case EDID_BLOCK_HEADER_FIXED:
1927 pr_debug("EDID corrupt header fixed\n");
1928 break;
1929 case EDID_BLOCK_CHECKSUM:
1930 if (edid_block_status_valid(status, edid_block_tag(block))) {
1931 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1932 block_num, edid_block_tag(block),
1933 edid_block_compute_checksum(block));
1934 } else {
1935 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1936 block_num, edid_block_tag(block),
1937 edid_block_compute_checksum(block));
1938 }
1939 break;
1940 case EDID_BLOCK_VERSION:
1941 pr_notice("EDID has major version %d, instead of 1\n",
1942 block->version);
1943 break;
1944 default:
1945 WARN(1, "EDID block %d unknown edid block status code %d\n",
1946 block_num, status);
1947 break;
1948 }
1949 }
1950
edid_block_dump(const char * level,const void * block,int block_num)1951 static void edid_block_dump(const char *level, const void *block, int block_num)
1952 {
1953 enum edid_block_status status;
1954 char prefix[20];
1955
1956 status = edid_block_check(block, block_num == 0);
1957 if (status == EDID_BLOCK_ZERO)
1958 snprintf(prefix, sizeof(prefix), "\t[%02x] ZERO ", block_num);
1959 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1960 snprintf(prefix, sizeof(prefix), "\t[%02x] BAD ", block_num);
1961 else
1962 snprintf(prefix, sizeof(prefix), "\t[%02x] GOOD ", block_num);
1963
1964 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1965 block, EDID_LENGTH, false);
1966 }
1967
1968 /**
1969 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1970 * @_block: pointer to raw EDID block
1971 * @block_num: type of block to validate (0 for base, extension otherwise)
1972 * @print_bad_edid: if true, dump bad EDID blocks to the console
1973 * @edid_corrupt: if true, the header or checksum is invalid
1974 *
1975 * Validate a base or extension EDID block and optionally dump bad blocks to
1976 * the console.
1977 *
1978 * Return: True if the block is valid, false otherwise.
1979 */
drm_edid_block_valid(u8 * _block,int block_num,bool print_bad_edid,bool * edid_corrupt)1980 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1981 bool *edid_corrupt)
1982 {
1983 struct edid *block = (struct edid *)_block;
1984 enum edid_block_status status;
1985 bool is_base_block = block_num == 0;
1986 bool valid;
1987
1988 if (WARN_ON(!block))
1989 return false;
1990
1991 status = edid_block_check(block, is_base_block);
1992 if (status == EDID_BLOCK_HEADER_REPAIR) {
1993 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1994 edid_header_fix(block);
1995
1996 /* Retry with fixed header, update status if that worked. */
1997 status = edid_block_check(block, is_base_block);
1998 if (status == EDID_BLOCK_OK)
1999 status = EDID_BLOCK_HEADER_FIXED;
2000 }
2001
2002 if (edid_corrupt) {
2003 /*
2004 * Unknown major version isn't corrupt but we can't use it. Only
2005 * the base block can reset edid_corrupt to false.
2006 */
2007 if (is_base_block &&
2008 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2009 *edid_corrupt = false;
2010 else if (status != EDID_BLOCK_OK)
2011 *edid_corrupt = true;
2012 }
2013
2014 edid_block_status_print(status, block, block_num);
2015
2016 /* Determine whether we can use this block with this status. */
2017 valid = edid_block_status_valid(status, edid_block_tag(block));
2018
2019 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2020 pr_notice("Raw EDID:\n");
2021 edid_block_dump(KERN_NOTICE, block, block_num);
2022 }
2023
2024 return valid;
2025 }
2026 EXPORT_SYMBOL(drm_edid_block_valid);
2027
2028 /**
2029 * drm_edid_is_valid - sanity check EDID data
2030 * @edid: EDID data
2031 *
2032 * Sanity-check an entire EDID record (including extensions)
2033 *
2034 * Return: True if the EDID data is valid, false otherwise.
2035 */
drm_edid_is_valid(struct edid * edid)2036 bool drm_edid_is_valid(struct edid *edid)
2037 {
2038 int i;
2039
2040 if (!edid)
2041 return false;
2042
2043 for (i = 0; i < edid_block_count(edid); i++) {
2044 void *block = (void *)edid_block_data(edid, i);
2045
2046 if (!drm_edid_block_valid(block, i, true, NULL))
2047 return false;
2048 }
2049
2050 return true;
2051 }
2052 EXPORT_SYMBOL(drm_edid_is_valid);
2053
2054 /**
2055 * drm_edid_valid - sanity check EDID data
2056 * @drm_edid: EDID data
2057 *
2058 * Sanity check an EDID. Cross check block count against allocated size and
2059 * checksum the blocks.
2060 *
2061 * Return: True if the EDID data is valid, false otherwise.
2062 */
drm_edid_valid(const struct drm_edid * drm_edid)2063 bool drm_edid_valid(const struct drm_edid *drm_edid)
2064 {
2065 int i;
2066
2067 if (!drm_edid)
2068 return false;
2069
2070 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2071 return false;
2072
2073 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2074 const void *block = drm_edid_block_data(drm_edid, i);
2075
2076 if (!edid_block_valid(block, i == 0))
2077 return false;
2078 }
2079
2080 return true;
2081 }
2082 EXPORT_SYMBOL(drm_edid_valid);
2083
edid_filter_invalid_blocks(struct edid * edid,size_t * alloc_size)2084 static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2085 size_t *alloc_size)
2086 {
2087 struct edid *new;
2088 int i, valid_blocks = 0;
2089
2090 /*
2091 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2092 * back to regular extension count here. We don't want to start
2093 * modifying the HF-EEODB extension too.
2094 */
2095 for (i = 0; i < edid_block_count(edid); i++) {
2096 const void *src_block = edid_block_data(edid, i);
2097
2098 if (edid_block_valid(src_block, i == 0)) {
2099 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2100
2101 memmove(dst_block, src_block, EDID_LENGTH);
2102 valid_blocks++;
2103 }
2104 }
2105
2106 /* We already trusted the base block to be valid here... */
2107 if (WARN_ON(!valid_blocks)) {
2108 kfree(edid);
2109 return NULL;
2110 }
2111
2112 edid->extensions = valid_blocks - 1;
2113 edid->checksum = edid_block_compute_checksum(edid);
2114
2115 *alloc_size = edid_size_by_blocks(valid_blocks);
2116
2117 #ifdef __linux__
2118 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2119 if (!new)
2120 kfree(edid);
2121 #else
2122 new = kmalloc(*alloc_size, GFP_KERNEL);
2123 if (!new) {
2124 kfree(edid);
2125 return NULL;
2126 }
2127 memcpy(new, edid, EDID_LENGTH);
2128 kfree(edid);
2129 #endif
2130
2131 return new;
2132 }
2133
2134 #define DDC_SEGMENT_ADDR 0x30
2135 /**
2136 * drm_do_probe_ddc_edid() - get EDID information via I2C
2137 * @data: I2C device adapter
2138 * @buf: EDID data buffer to be filled
2139 * @block: 128 byte EDID block to start fetching from
2140 * @len: EDID data buffer length to fetch
2141 *
2142 * Try to fetch EDID information by calling I2C driver functions.
2143 *
2144 * Return: 0 on success or -1 on failure.
2145 */
2146 static int
drm_do_probe_ddc_edid(void * data,u8 * buf,unsigned int block,size_t len)2147 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2148 {
2149 struct i2c_adapter *adapter = data;
2150 unsigned char start = block * EDID_LENGTH;
2151 unsigned char segment = block >> 1;
2152 unsigned char xfers = segment ? 3 : 2;
2153 int ret, retries = 5;
2154
2155 /*
2156 * The core I2C driver will automatically retry the transfer if the
2157 * adapter reports EAGAIN. However, we find that bit-banging transfers
2158 * are susceptible to errors under a heavily loaded machine and
2159 * generate spurious NAKs and timeouts. Retrying the transfer
2160 * of the individual block a few times seems to overcome this.
2161 */
2162 do {
2163 struct i2c_msg msgs[] = {
2164 {
2165 .addr = DDC_SEGMENT_ADDR,
2166 .flags = 0,
2167 .len = 1,
2168 .buf = &segment,
2169 }, {
2170 .addr = DDC_ADDR,
2171 .flags = 0,
2172 .len = 1,
2173 .buf = &start,
2174 }, {
2175 .addr = DDC_ADDR,
2176 .flags = I2C_M_RD,
2177 .len = len,
2178 .buf = buf,
2179 }
2180 };
2181
2182 /*
2183 * Avoid sending the segment addr to not upset non-compliant
2184 * DDC monitors.
2185 */
2186 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2187
2188 if (ret == -ENXIO) {
2189 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2190 adapter->name);
2191 break;
2192 }
2193 } while (ret != xfers && --retries);
2194
2195 return ret == xfers ? 0 : -1;
2196 }
2197
connector_bad_edid(struct drm_connector * connector,const struct edid * edid,int num_blocks)2198 static void connector_bad_edid(struct drm_connector *connector,
2199 const struct edid *edid, int num_blocks)
2200 {
2201 int i;
2202 u8 last_block;
2203
2204 /*
2205 * 0x7e in the EDID is the number of extension blocks. The EDID
2206 * is 1 (base block) + num_ext_blocks big. That means we can think
2207 * of 0x7e in the EDID of the _index_ of the last block in the
2208 * combined chunk of memory.
2209 */
2210 last_block = edid->extensions;
2211
2212 /* Calculate real checksum for the last edid extension block data */
2213 if (last_block < num_blocks)
2214 connector->real_edid_checksum =
2215 edid_block_compute_checksum(edid + last_block);
2216
2217 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2218 return;
2219
2220 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2221 connector->base.id, connector->name);
2222 for (i = 0; i < num_blocks; i++)
2223 edid_block_dump(KERN_DEBUG, edid + i, i);
2224 }
2225
2226 /* Get override or firmware EDID */
drm_edid_override_get(struct drm_connector * connector)2227 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2228 {
2229 const struct drm_edid *override = NULL;
2230
2231 mutex_lock(&connector->edid_override_mutex);
2232
2233 if (connector->edid_override)
2234 override = drm_edid_dup(connector->edid_override);
2235
2236 mutex_unlock(&connector->edid_override_mutex);
2237
2238 if (!override)
2239 override = drm_edid_load_firmware(connector);
2240
2241 return IS_ERR(override) ? NULL : override;
2242 }
2243
2244 /* For debugfs edid_override implementation */
drm_edid_override_show(struct drm_connector * connector,struct seq_file * m)2245 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2246 {
2247 const struct drm_edid *drm_edid;
2248
2249 mutex_lock(&connector->edid_override_mutex);
2250
2251 drm_edid = connector->edid_override;
2252 if (drm_edid)
2253 seq_write(m, drm_edid->edid, drm_edid->size);
2254
2255 mutex_unlock(&connector->edid_override_mutex);
2256
2257 return 0;
2258 }
2259
2260 /* For debugfs edid_override implementation */
drm_edid_override_set(struct drm_connector * connector,const void * edid,size_t size)2261 int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2262 size_t size)
2263 {
2264 const struct drm_edid *drm_edid;
2265
2266 drm_edid = drm_edid_alloc(edid, size);
2267 if (!drm_edid_valid(drm_edid)) {
2268 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2269 connector->base.id, connector->name);
2270 drm_edid_free(drm_edid);
2271 return -EINVAL;
2272 }
2273
2274 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2275 connector->base.id, connector->name);
2276
2277 mutex_lock(&connector->edid_override_mutex);
2278
2279 drm_edid_free(connector->edid_override);
2280 connector->edid_override = drm_edid;
2281
2282 mutex_unlock(&connector->edid_override_mutex);
2283
2284 return 0;
2285 }
2286
2287 /* For debugfs edid_override implementation */
drm_edid_override_reset(struct drm_connector * connector)2288 int drm_edid_override_reset(struct drm_connector *connector)
2289 {
2290 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2291 connector->base.id, connector->name);
2292
2293 mutex_lock(&connector->edid_override_mutex);
2294
2295 drm_edid_free(connector->edid_override);
2296 connector->edid_override = NULL;
2297
2298 mutex_unlock(&connector->edid_override_mutex);
2299
2300 return 0;
2301 }
2302
2303 /**
2304 * drm_edid_override_connector_update - add modes from override/firmware EDID
2305 * @connector: connector we're probing
2306 *
2307 * Add modes from the override/firmware EDID, if available. Only to be used from
2308 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2309 * failed during drm_get_edid() and caused the override/firmware EDID to be
2310 * skipped.
2311 *
2312 * Return: The number of modes added or 0 if we couldn't find any.
2313 */
drm_edid_override_connector_update(struct drm_connector * connector)2314 int drm_edid_override_connector_update(struct drm_connector *connector)
2315 {
2316 const struct drm_edid *override;
2317 int num_modes = 0;
2318
2319 override = drm_edid_override_get(connector);
2320 if (override) {
2321 if (drm_edid_connector_update(connector, override) == 0)
2322 num_modes = drm_edid_connector_add_modes(connector);
2323
2324 drm_edid_free(override);
2325
2326 drm_dbg_kms(connector->dev,
2327 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2328 connector->base.id, connector->name, num_modes);
2329 }
2330
2331 return num_modes;
2332 }
2333 EXPORT_SYMBOL(drm_edid_override_connector_update);
2334
2335 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2336
edid_block_read(void * block,unsigned int block_num,read_block_fn read_block,void * context)2337 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2338 read_block_fn read_block,
2339 void *context)
2340 {
2341 enum edid_block_status status;
2342 bool is_base_block = block_num == 0;
2343 int try;
2344
2345 for (try = 0; try < 4; try++) {
2346 if (read_block(context, block, block_num, EDID_LENGTH))
2347 return EDID_BLOCK_READ_FAIL;
2348
2349 status = edid_block_check(block, is_base_block);
2350 if (status == EDID_BLOCK_HEADER_REPAIR) {
2351 edid_header_fix(block);
2352
2353 /* Retry with fixed header, update status if that worked. */
2354 status = edid_block_check(block, is_base_block);
2355 if (status == EDID_BLOCK_OK)
2356 status = EDID_BLOCK_HEADER_FIXED;
2357 }
2358
2359 if (edid_block_status_valid(status, edid_block_tag(block)))
2360 break;
2361
2362 /* Fail early for unrepairable base block all zeros. */
2363 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2364 break;
2365 }
2366
2367 return status;
2368 }
2369
_drm_do_get_edid(struct drm_connector * connector,read_block_fn read_block,void * context,size_t * size)2370 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2371 read_block_fn read_block, void *context,
2372 size_t *size)
2373 {
2374 enum edid_block_status status;
2375 int i, num_blocks, invalid_blocks = 0;
2376 const struct drm_edid *override;
2377 struct edid *edid, *new;
2378 size_t alloc_size = EDID_LENGTH;
2379
2380 override = drm_edid_override_get(connector);
2381 if (override) {
2382 alloc_size = override->size;
2383 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2384 drm_edid_free(override);
2385 if (!edid)
2386 return NULL;
2387 goto ok;
2388 }
2389
2390 edid = kmalloc(alloc_size, GFP_KERNEL);
2391 if (!edid)
2392 return NULL;
2393
2394 status = edid_block_read(edid, 0, read_block, context);
2395
2396 edid_block_status_print(status, edid, 0);
2397
2398 if (status == EDID_BLOCK_READ_FAIL)
2399 goto fail;
2400
2401 /* FIXME: Clarify what a corrupt EDID actually means. */
2402 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2403 connector->edid_corrupt = false;
2404 else
2405 connector->edid_corrupt = true;
2406
2407 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2408 if (status == EDID_BLOCK_ZERO)
2409 connector->null_edid_counter++;
2410
2411 connector_bad_edid(connector, edid, 1);
2412 goto fail;
2413 }
2414
2415 if (!edid_extension_block_count(edid))
2416 goto ok;
2417
2418 alloc_size = edid_size(edid);
2419 #ifdef __linux__
2420 new = krealloc(edid, alloc_size, GFP_KERNEL);
2421 if (!new)
2422 goto fail;
2423 #else
2424 new = kmalloc(alloc_size, GFP_KERNEL);
2425 if (!new)
2426 goto fail;
2427 memcpy(new, edid, EDID_LENGTH);
2428 kfree(edid);
2429 #endif
2430 edid = new;
2431
2432 num_blocks = edid_block_count(edid);
2433 for (i = 1; i < num_blocks; i++) {
2434 void *block = (void *)edid_block_data(edid, i);
2435
2436 status = edid_block_read(block, i, read_block, context);
2437
2438 edid_block_status_print(status, block, i);
2439
2440 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2441 if (status == EDID_BLOCK_READ_FAIL)
2442 goto fail;
2443 invalid_blocks++;
2444 } else if (i == 1) {
2445 /*
2446 * If the first EDID extension is a CTA extension, and
2447 * the first Data Block is HF-EEODB, override the
2448 * extension block count.
2449 *
2450 * Note: HF-EEODB could specify a smaller extension
2451 * count too, but we can't risk allocating a smaller
2452 * amount.
2453 */
2454 int eeodb = edid_hfeeodb_block_count(edid);
2455
2456 if (eeodb > num_blocks) {
2457 num_blocks = eeodb;
2458 alloc_size = edid_size_by_blocks(num_blocks);
2459 #ifdef __linux__
2460 new = krealloc(edid, alloc_size, GFP_KERNEL);
2461 if (!new)
2462 goto fail;
2463 #else
2464 new = kmalloc(alloc_size, GFP_KERNEL);
2465 if (!new)
2466 goto fail;
2467 memcpy(new, edid, EDID_LENGTH);
2468 kfree(edid);
2469 #endif
2470 edid = new;
2471 }
2472 }
2473 }
2474
2475 if (invalid_blocks) {
2476 connector_bad_edid(connector, edid, num_blocks);
2477
2478 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2479 }
2480
2481 ok:
2482 if (size)
2483 *size = alloc_size;
2484
2485 return edid;
2486
2487 fail:
2488 kfree(edid);
2489 return NULL;
2490 }
2491
2492 /**
2493 * drm_do_get_edid - get EDID data using a custom EDID block read function
2494 * @connector: connector we're probing
2495 * @read_block: EDID block read function
2496 * @context: private data passed to the block read function
2497 *
2498 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2499 * exposes a different interface to read EDID blocks this function can be used
2500 * to get EDID data using a custom block read function.
2501 *
2502 * As in the general case the DDC bus is accessible by the kernel at the I2C
2503 * level, drivers must make all reasonable efforts to expose it as an I2C
2504 * adapter and use drm_get_edid() instead of abusing this function.
2505 *
2506 * The EDID may be overridden using debugfs override_edid or firmware EDID
2507 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2508 * order. Having either of them bypasses actual EDID reads.
2509 *
2510 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2511 */
drm_do_get_edid(struct drm_connector * connector,read_block_fn read_block,void * context)2512 struct edid *drm_do_get_edid(struct drm_connector *connector,
2513 read_block_fn read_block,
2514 void *context)
2515 {
2516 return _drm_do_get_edid(connector, read_block, context, NULL);
2517 }
2518 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2519
2520 /**
2521 * drm_edid_raw - Get a pointer to the raw EDID data.
2522 * @drm_edid: drm_edid container
2523 *
2524 * Get a pointer to the raw EDID data.
2525 *
2526 * This is for transition only. Avoid using this like the plague.
2527 *
2528 * Return: Pointer to raw EDID data.
2529 */
drm_edid_raw(const struct drm_edid * drm_edid)2530 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2531 {
2532 if (!drm_edid || !drm_edid->size)
2533 return NULL;
2534
2535 /*
2536 * Do not return pointers where relying on EDID extension count would
2537 * lead to buffer overflow.
2538 */
2539 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2540 return NULL;
2541
2542 return drm_edid->edid;
2543 }
2544 EXPORT_SYMBOL(drm_edid_raw);
2545
2546 /* Allocate struct drm_edid container *without* duplicating the edid data */
_drm_edid_alloc(const void * edid,size_t size)2547 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2548 {
2549 struct drm_edid *drm_edid;
2550
2551 if (!edid || !size || size < EDID_LENGTH)
2552 return NULL;
2553
2554 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2555 if (drm_edid) {
2556 drm_edid->edid = edid;
2557 drm_edid->size = size;
2558 }
2559
2560 return drm_edid;
2561 }
2562
2563 /**
2564 * drm_edid_alloc - Allocate a new drm_edid container
2565 * @edid: Pointer to raw EDID data
2566 * @size: Size of memory allocated for EDID
2567 *
2568 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2569 * the actual size that has been allocated for the data. There is no validation
2570 * of the raw EDID data against the size, but at least the EDID base block must
2571 * fit in the buffer.
2572 *
2573 * The returned pointer must be freed using drm_edid_free().
2574 *
2575 * Return: drm_edid container, or NULL on errors
2576 */
drm_edid_alloc(const void * edid,size_t size)2577 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2578 {
2579 const struct drm_edid *drm_edid;
2580
2581 if (!edid || !size || size < EDID_LENGTH)
2582 return NULL;
2583
2584 edid = kmemdup(edid, size, GFP_KERNEL);
2585 if (!edid)
2586 return NULL;
2587
2588 drm_edid = _drm_edid_alloc(edid, size);
2589 if (!drm_edid)
2590 kfree(edid);
2591
2592 return drm_edid;
2593 }
2594 EXPORT_SYMBOL(drm_edid_alloc);
2595
2596 /**
2597 * drm_edid_dup - Duplicate a drm_edid container
2598 * @drm_edid: EDID to duplicate
2599 *
2600 * The returned pointer must be freed using drm_edid_free().
2601 *
2602 * Returns: drm_edid container copy, or NULL on errors
2603 */
drm_edid_dup(const struct drm_edid * drm_edid)2604 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2605 {
2606 if (!drm_edid)
2607 return NULL;
2608
2609 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2610 }
2611 EXPORT_SYMBOL(drm_edid_dup);
2612
2613 /**
2614 * drm_edid_free - Free the drm_edid container
2615 * @drm_edid: EDID to free
2616 */
drm_edid_free(const struct drm_edid * drm_edid)2617 void drm_edid_free(const struct drm_edid *drm_edid)
2618 {
2619 if (!drm_edid)
2620 return;
2621
2622 kfree(drm_edid->edid);
2623 kfree(drm_edid);
2624 }
2625 EXPORT_SYMBOL(drm_edid_free);
2626
2627 /**
2628 * drm_probe_ddc() - probe DDC presence
2629 * @adapter: I2C adapter to probe
2630 *
2631 * Return: True on success, false on failure.
2632 */
2633 bool
drm_probe_ddc(struct i2c_adapter * adapter)2634 drm_probe_ddc(struct i2c_adapter *adapter)
2635 {
2636 unsigned char out;
2637
2638 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2639 }
2640 EXPORT_SYMBOL(drm_probe_ddc);
2641
2642 /**
2643 * drm_get_edid - get EDID data, if available
2644 * @connector: connector we're probing
2645 * @adapter: I2C adapter to use for DDC
2646 *
2647 * Poke the given I2C channel to grab EDID data if possible. If found,
2648 * attach it to the connector.
2649 *
2650 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2651 */
drm_get_edid(struct drm_connector * connector,struct i2c_adapter * adapter)2652 struct edid *drm_get_edid(struct drm_connector *connector,
2653 struct i2c_adapter *adapter)
2654 {
2655 struct edid *edid;
2656
2657 if (connector->force == DRM_FORCE_OFF)
2658 return NULL;
2659
2660 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2661 return NULL;
2662
2663 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2664 drm_connector_update_edid_property(connector, edid);
2665 return edid;
2666 }
2667 EXPORT_SYMBOL(drm_get_edid);
2668
2669 /**
2670 * drm_edid_read_custom - Read EDID data using given EDID block read function
2671 * @connector: Connector to use
2672 * @read_block: EDID block read function
2673 * @context: Private data passed to the block read function
2674 *
2675 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2676 * exposes a different interface to read EDID blocks this function can be used
2677 * to get EDID data using a custom block read function.
2678 *
2679 * As in the general case the DDC bus is accessible by the kernel at the I2C
2680 * level, drivers must make all reasonable efforts to expose it as an I2C
2681 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2682 * this function.
2683 *
2684 * The EDID may be overridden using debugfs override_edid or firmware EDID
2685 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2686 * order. Having either of them bypasses actual EDID reads.
2687 *
2688 * The returned pointer must be freed using drm_edid_free().
2689 *
2690 * Return: Pointer to EDID, or NULL if probe/read failed.
2691 */
drm_edid_read_custom(struct drm_connector * connector,read_block_fn read_block,void * context)2692 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2693 read_block_fn read_block,
2694 void *context)
2695 {
2696 const struct drm_edid *drm_edid;
2697 struct edid *edid;
2698 size_t size = 0;
2699
2700 edid = _drm_do_get_edid(connector, read_block, context, &size);
2701 if (!edid)
2702 return NULL;
2703
2704 /* Sanity check for now */
2705 drm_WARN_ON(connector->dev, !size);
2706
2707 drm_edid = _drm_edid_alloc(edid, size);
2708 if (!drm_edid)
2709 kfree(edid);
2710
2711 return drm_edid;
2712 }
2713 EXPORT_SYMBOL(drm_edid_read_custom);
2714
2715 /**
2716 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2717 * @connector: Connector to use
2718 * @adapter: I2C adapter to use for DDC
2719 *
2720 * Read EDID using the given I2C adapter.
2721 *
2722 * The EDID may be overridden using debugfs override_edid or firmware EDID
2723 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2724 * order. Having either of them bypasses actual EDID reads.
2725 *
2726 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2727 * using drm_edid_read() instead of this function.
2728 *
2729 * The returned pointer must be freed using drm_edid_free().
2730 *
2731 * Return: Pointer to EDID, or NULL if probe/read failed.
2732 */
drm_edid_read_ddc(struct drm_connector * connector,struct i2c_adapter * adapter)2733 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2734 struct i2c_adapter *adapter)
2735 {
2736 const struct drm_edid *drm_edid;
2737
2738 if (connector->force == DRM_FORCE_OFF)
2739 return NULL;
2740
2741 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2742 return NULL;
2743
2744 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2745
2746 /* Note: Do *not* call connector updates here. */
2747
2748 return drm_edid;
2749 }
2750 EXPORT_SYMBOL(drm_edid_read_ddc);
2751
2752 /**
2753 * drm_edid_read - Read EDID data using connector's I2C adapter
2754 * @connector: Connector to use
2755 *
2756 * Read EDID using the connector's I2C adapter.
2757 *
2758 * The EDID may be overridden using debugfs override_edid or firmware EDID
2759 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2760 * order. Having either of them bypasses actual EDID reads.
2761 *
2762 * The returned pointer must be freed using drm_edid_free().
2763 *
2764 * Return: Pointer to EDID, or NULL if probe/read failed.
2765 */
drm_edid_read(struct drm_connector * connector)2766 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2767 {
2768 if (drm_WARN_ON(connector->dev, !connector->ddc))
2769 return NULL;
2770
2771 return drm_edid_read_ddc(connector, connector->ddc);
2772 }
2773 EXPORT_SYMBOL(drm_edid_read);
2774
edid_extract_panel_id(const struct edid * edid)2775 static u32 edid_extract_panel_id(const struct edid *edid)
2776 {
2777 /*
2778 * We represent the ID as a 32-bit number so it can easily be compared
2779 * with "==".
2780 *
2781 * NOTE that we deal with endianness differently for the top half
2782 * of this ID than for the bottom half. The bottom half (the product
2783 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2784 * that's how everyone seems to interpret it. The top half (the mfg_id)
2785 * gets stored as big endian because that makes
2786 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2787 * to write (it's easier to extract the ASCII). It doesn't really
2788 * matter, though, as long as the number here is unique.
2789 */
2790 return (u32)edid->mfg_id[0] << 24 |
2791 (u32)edid->mfg_id[1] << 16 |
2792 (u32)EDID_PRODUCT_ID(edid);
2793 }
2794
2795 /**
2796 * drm_edid_get_panel_id - Get a panel's ID through DDC
2797 * @adapter: I2C adapter to use for DDC
2798 *
2799 * This function reads the first block of the EDID of a panel and (assuming
2800 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2801 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2802 * supposed to be different for each different modem of panel.
2803 *
2804 * This function is intended to be used during early probing on devices where
2805 * more than one panel might be present. Because of its intended use it must
2806 * assume that the EDID of the panel is correct, at least as far as the ID
2807 * is concerned (in other words, we don't process any overrides here).
2808 *
2809 * NOTE: it's expected that this function and drm_do_get_edid() will both
2810 * be read the EDID, but there is no caching between them. Since we're only
2811 * reading the first block, hopefully this extra overhead won't be too big.
2812 *
2813 * Return: A 32-bit ID that should be different for each make/model of panel.
2814 * See the functions drm_edid_encode_panel_id() and
2815 * drm_edid_decode_panel_id() for some details on the structure of this
2816 * ID.
2817 */
2818
drm_edid_get_panel_id(struct i2c_adapter * adapter)2819 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2820 {
2821 enum edid_block_status status;
2822 void *base_block;
2823 u32 panel_id = 0;
2824
2825 /*
2826 * There are no manufacturer IDs of 0, so if there is a problem reading
2827 * the EDID then we'll just return 0.
2828 */
2829
2830 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2831 if (!base_block)
2832 return 0;
2833
2834 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2835
2836 edid_block_status_print(status, base_block, 0);
2837
2838 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2839 panel_id = edid_extract_panel_id(base_block);
2840 else
2841 edid_block_dump(KERN_NOTICE, base_block, 0);
2842
2843 kfree(base_block);
2844
2845 return panel_id;
2846 }
2847 EXPORT_SYMBOL(drm_edid_get_panel_id);
2848
2849 /**
2850 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2851 * @connector: connector we're probing
2852 * @adapter: I2C adapter to use for DDC
2853 *
2854 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2855 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2856 * switch DDC to the GPU which is retrieving EDID.
2857 *
2858 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2859 */
drm_get_edid_switcheroo(struct drm_connector * connector,struct i2c_adapter * adapter)2860 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2861 struct i2c_adapter *adapter)
2862 {
2863 STUB();
2864 return NULL;
2865 #ifdef notyet
2866 struct drm_device *dev = connector->dev;
2867 struct pci_dev *pdev = to_pci_dev(dev->dev);
2868 struct edid *edid;
2869
2870 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2871 return NULL;
2872
2873 vga_switcheroo_lock_ddc(pdev);
2874 edid = drm_get_edid(connector, adapter);
2875 vga_switcheroo_unlock_ddc(pdev);
2876
2877 return edid;
2878 #endif
2879 }
2880 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2881
2882 /**
2883 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2884 * @connector: connector we're probing
2885 * @adapter: I2C adapter to use for DDC
2886 *
2887 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2888 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2889 * temporarily switch DDC to the GPU which is retrieving EDID.
2890 *
2891 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2892 */
drm_edid_read_switcheroo(struct drm_connector * connector,struct i2c_adapter * adapter)2893 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2894 struct i2c_adapter *adapter)
2895 {
2896 STUB();
2897 return NULL;
2898 #ifdef notyet
2899 struct drm_device *dev = connector->dev;
2900 struct pci_dev *pdev = to_pci_dev(dev->dev);
2901 const struct drm_edid *drm_edid;
2902
2903 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2904 return NULL;
2905
2906 vga_switcheroo_lock_ddc(pdev);
2907 drm_edid = drm_edid_read_ddc(connector, adapter);
2908 vga_switcheroo_unlock_ddc(pdev);
2909
2910 return drm_edid;
2911 #endif
2912 }
2913 EXPORT_SYMBOL(drm_edid_read_switcheroo);
2914
2915 /**
2916 * drm_edid_duplicate - duplicate an EDID and the extensions
2917 * @edid: EDID to duplicate
2918 *
2919 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2920 */
drm_edid_duplicate(const struct edid * edid)2921 struct edid *drm_edid_duplicate(const struct edid *edid)
2922 {
2923 if (!edid)
2924 return NULL;
2925
2926 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2927 }
2928 EXPORT_SYMBOL(drm_edid_duplicate);
2929
2930 /*** EDID parsing ***/
2931
2932 /**
2933 * edid_get_quirks - return quirk flags for a given EDID
2934 * @drm_edid: EDID to process
2935 *
2936 * This tells subsequent routines what fixes they need to apply.
2937 */
edid_get_quirks(const struct drm_edid * drm_edid)2938 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2939 {
2940 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2941 const struct edid_quirk *quirk;
2942 int i;
2943
2944 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2945 quirk = &edid_quirk_list[i];
2946 if (quirk->panel_id == panel_id)
2947 return quirk->quirks;
2948 }
2949
2950 return 0;
2951 }
2952
2953 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2954 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2955
2956 /*
2957 * Walk the mode list for connector, clearing the preferred status on existing
2958 * modes and setting it anew for the right mode ala quirks.
2959 */
edid_fixup_preferred(struct drm_connector * connector)2960 static void edid_fixup_preferred(struct drm_connector *connector)
2961 {
2962 const struct drm_display_info *info = &connector->display_info;
2963 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2964 int target_refresh = 0;
2965 int cur_vrefresh, preferred_vrefresh;
2966
2967 if (list_empty(&connector->probed_modes))
2968 return;
2969
2970 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
2971 target_refresh = 60;
2972 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
2973 target_refresh = 75;
2974
2975 preferred_mode = list_first_entry(&connector->probed_modes,
2976 struct drm_display_mode, head);
2977
2978 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2979 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2980
2981 if (cur_mode == preferred_mode)
2982 continue;
2983
2984 /* Largest mode is preferred */
2985 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2986 preferred_mode = cur_mode;
2987
2988 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2989 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2990 /* At a given size, try to get closest to target refresh */
2991 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2992 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2993 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2994 preferred_mode = cur_mode;
2995 }
2996 }
2997
2998 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2999 }
3000
3001 static bool
mode_is_rb(const struct drm_display_mode * mode)3002 mode_is_rb(const struct drm_display_mode *mode)
3003 {
3004 return (mode->htotal - mode->hdisplay == 160) &&
3005 (mode->hsync_end - mode->hdisplay == 80) &&
3006 (mode->hsync_end - mode->hsync_start == 32) &&
3007 (mode->vsync_start - mode->vdisplay == 3);
3008 }
3009
3010 /*
3011 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
3012 * @dev: Device to duplicate against
3013 * @hsize: Mode width
3014 * @vsize: Mode height
3015 * @fresh: Mode refresh rate
3016 * @rb: Mode reduced-blanking-ness
3017 *
3018 * Walk the DMT mode list looking for a match for the given parameters.
3019 *
3020 * Return: A newly allocated copy of the mode, or NULL if not found.
3021 */
drm_mode_find_dmt(struct drm_device * dev,int hsize,int vsize,int fresh,bool rb)3022 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
3023 int hsize, int vsize, int fresh,
3024 bool rb)
3025 {
3026 int i;
3027
3028 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3029 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
3030
3031 if (hsize != ptr->hdisplay)
3032 continue;
3033 if (vsize != ptr->vdisplay)
3034 continue;
3035 if (fresh != drm_mode_vrefresh(ptr))
3036 continue;
3037 if (rb != mode_is_rb(ptr))
3038 continue;
3039
3040 return drm_mode_duplicate(dev, ptr);
3041 }
3042
3043 return NULL;
3044 }
3045 EXPORT_SYMBOL(drm_mode_find_dmt);
3046
is_display_descriptor(const struct detailed_timing * descriptor,u8 type)3047 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
3048 {
3049 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3050 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3051 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3052
3053 return descriptor->pixel_clock == 0 &&
3054 descriptor->data.other_data.pad1 == 0 &&
3055 descriptor->data.other_data.type == type;
3056 }
3057
is_detailed_timing_descriptor(const struct detailed_timing * descriptor)3058 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
3059 {
3060 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3061
3062 return descriptor->pixel_clock != 0;
3063 }
3064
3065 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
3066
3067 static void
cea_for_each_detailed_block(const u8 * ext,detailed_cb * cb,void * closure)3068 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3069 {
3070 int i, n;
3071 u8 d = ext[0x02];
3072 const u8 *det_base = ext + d;
3073
3074 if (d < 4 || d > 127)
3075 return;
3076
3077 n = (127 - d) / 18;
3078 for (i = 0; i < n; i++)
3079 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3080 }
3081
3082 static void
vtb_for_each_detailed_block(const u8 * ext,detailed_cb * cb,void * closure)3083 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3084 {
3085 unsigned int i, n = min((int)ext[0x02], 6);
3086 const u8 *det_base = ext + 5;
3087
3088 if (ext[0x01] != 1)
3089 return; /* unknown version */
3090
3091 for (i = 0; i < n; i++)
3092 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3093 }
3094
drm_for_each_detailed_block(const struct drm_edid * drm_edid,detailed_cb * cb,void * closure)3095 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3096 detailed_cb *cb, void *closure)
3097 {
3098 struct drm_edid_iter edid_iter;
3099 const u8 *ext;
3100 int i;
3101
3102 if (!drm_edid)
3103 return;
3104
3105 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3106 cb(&drm_edid->edid->detailed_timings[i], closure);
3107
3108 drm_edid_iter_begin(drm_edid, &edid_iter);
3109 drm_edid_iter_for_each(ext, &edid_iter) {
3110 switch (*ext) {
3111 case CEA_EXT:
3112 cea_for_each_detailed_block(ext, cb, closure);
3113 break;
3114 case VTB_EXT:
3115 vtb_for_each_detailed_block(ext, cb, closure);
3116 break;
3117 default:
3118 break;
3119 }
3120 }
3121 drm_edid_iter_end(&edid_iter);
3122 }
3123
3124 static void
is_rb(const struct detailed_timing * descriptor,void * data)3125 is_rb(const struct detailed_timing *descriptor, void *data)
3126 {
3127 bool *res = data;
3128
3129 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3130 return;
3131
3132 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3133 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3134
3135 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3136 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3137 *res = true;
3138 }
3139
3140 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3141 static bool
drm_monitor_supports_rb(const struct drm_edid * drm_edid)3142 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3143 {
3144 if (drm_edid->edid->revision >= 4) {
3145 bool ret = false;
3146
3147 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3148 return ret;
3149 }
3150
3151 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
3152 }
3153
3154 static void
find_gtf2(const struct detailed_timing * descriptor,void * data)3155 find_gtf2(const struct detailed_timing *descriptor, void *data)
3156 {
3157 const struct detailed_timing **res = data;
3158
3159 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3160 return;
3161
3162 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3163
3164 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3165 *res = descriptor;
3166 }
3167
3168 /* Secondary GTF curve kicks in above some break frequency */
3169 static int
drm_gtf2_hbreak(const struct drm_edid * drm_edid)3170 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3171 {
3172 const struct detailed_timing *descriptor = NULL;
3173
3174 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3175
3176 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3177
3178 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3179 }
3180
3181 static int
drm_gtf2_2c(const struct drm_edid * drm_edid)3182 drm_gtf2_2c(const struct drm_edid *drm_edid)
3183 {
3184 const struct detailed_timing *descriptor = NULL;
3185
3186 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3187
3188 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3189
3190 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3191 }
3192
3193 static int
drm_gtf2_m(const struct drm_edid * drm_edid)3194 drm_gtf2_m(const struct drm_edid *drm_edid)
3195 {
3196 const struct detailed_timing *descriptor = NULL;
3197
3198 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3199
3200 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3201
3202 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3203 }
3204
3205 static int
drm_gtf2_k(const struct drm_edid * drm_edid)3206 drm_gtf2_k(const struct drm_edid *drm_edid)
3207 {
3208 const struct detailed_timing *descriptor = NULL;
3209
3210 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3211
3212 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3213
3214 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3215 }
3216
3217 static int
drm_gtf2_2j(const struct drm_edid * drm_edid)3218 drm_gtf2_2j(const struct drm_edid *drm_edid)
3219 {
3220 const struct detailed_timing *descriptor = NULL;
3221
3222 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3223
3224 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3225
3226 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3227 }
3228
3229 static void
get_timing_level(const struct detailed_timing * descriptor,void * data)3230 get_timing_level(const struct detailed_timing *descriptor, void *data)
3231 {
3232 int *res = data;
3233
3234 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3235 return;
3236
3237 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3238
3239 switch (descriptor->data.other_data.data.range.flags) {
3240 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3241 *res = LEVEL_GTF;
3242 break;
3243 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3244 *res = LEVEL_GTF2;
3245 break;
3246 case DRM_EDID_CVT_SUPPORT_FLAG:
3247 *res = LEVEL_CVT;
3248 break;
3249 default:
3250 break;
3251 }
3252 }
3253
3254 /* Get standard timing level (CVT/GTF/DMT). */
standard_timing_level(const struct drm_edid * drm_edid)3255 static int standard_timing_level(const struct drm_edid *drm_edid)
3256 {
3257 const struct edid *edid = drm_edid->edid;
3258
3259 if (edid->revision >= 4) {
3260 /*
3261 * If the range descriptor doesn't
3262 * indicate otherwise default to CVT
3263 */
3264 int ret = LEVEL_CVT;
3265
3266 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3267
3268 return ret;
3269 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3270 return LEVEL_GTF2;
3271 } else if (edid->revision >= 2) {
3272 return LEVEL_GTF;
3273 } else {
3274 return LEVEL_DMT;
3275 }
3276 }
3277
3278 /*
3279 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3280 * monitors fill with ascii space (0x20) instead.
3281 */
3282 static int
bad_std_timing(u8 a,u8 b)3283 bad_std_timing(u8 a, u8 b)
3284 {
3285 return (a == 0x00 && b == 0x00) ||
3286 (a == 0x01 && b == 0x01) ||
3287 (a == 0x20 && b == 0x20);
3288 }
3289
drm_mode_hsync(const struct drm_display_mode * mode)3290 static int drm_mode_hsync(const struct drm_display_mode *mode)
3291 {
3292 if (mode->htotal <= 0)
3293 return 0;
3294
3295 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3296 }
3297
3298 static struct drm_display_mode *
drm_gtf2_mode(struct drm_device * dev,const struct drm_edid * drm_edid,int hsize,int vsize,int vrefresh_rate)3299 drm_gtf2_mode(struct drm_device *dev,
3300 const struct drm_edid *drm_edid,
3301 int hsize, int vsize, int vrefresh_rate)
3302 {
3303 struct drm_display_mode *mode;
3304
3305 /*
3306 * This is potentially wrong if there's ever a monitor with
3307 * more than one ranges section, each claiming a different
3308 * secondary GTF curve. Please don't do that.
3309 */
3310 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3311 if (!mode)
3312 return NULL;
3313
3314 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3315 drm_mode_destroy(dev, mode);
3316 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3317 vrefresh_rate, 0, 0,
3318 drm_gtf2_m(drm_edid),
3319 drm_gtf2_2c(drm_edid),
3320 drm_gtf2_k(drm_edid),
3321 drm_gtf2_2j(drm_edid));
3322 }
3323
3324 return mode;
3325 }
3326
3327 /*
3328 * Take the standard timing params (in this case width, aspect, and refresh)
3329 * and convert them into a real mode using CVT/GTF/DMT.
3330 */
drm_mode_std(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct std_timing * t)3331 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3332 const struct drm_edid *drm_edid,
3333 const struct std_timing *t)
3334 {
3335 struct drm_device *dev = connector->dev;
3336 struct drm_display_mode *m, *mode = NULL;
3337 int hsize, vsize;
3338 int vrefresh_rate;
3339 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3340 >> EDID_TIMING_ASPECT_SHIFT;
3341 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3342 >> EDID_TIMING_VFREQ_SHIFT;
3343 int timing_level = standard_timing_level(drm_edid);
3344
3345 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3346 return NULL;
3347
3348 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3349 hsize = t->hsize * 8 + 248;
3350 /* vrefresh_rate = vfreq + 60 */
3351 vrefresh_rate = vfreq + 60;
3352 /* the vdisplay is calculated based on the aspect ratio */
3353 if (aspect_ratio == 0) {
3354 if (drm_edid->edid->revision < 3)
3355 vsize = hsize;
3356 else
3357 vsize = (hsize * 10) / 16;
3358 } else if (aspect_ratio == 1)
3359 vsize = (hsize * 3) / 4;
3360 else if (aspect_ratio == 2)
3361 vsize = (hsize * 4) / 5;
3362 else
3363 vsize = (hsize * 9) / 16;
3364
3365 /* HDTV hack, part 1 */
3366 if (vrefresh_rate == 60 &&
3367 ((hsize == 1360 && vsize == 765) ||
3368 (hsize == 1368 && vsize == 769))) {
3369 hsize = 1366;
3370 vsize = 768;
3371 }
3372
3373 /*
3374 * If this connector already has a mode for this size and refresh
3375 * rate (because it came from detailed or CVT info), use that
3376 * instead. This way we don't have to guess at interlace or
3377 * reduced blanking.
3378 */
3379 list_for_each_entry(m, &connector->probed_modes, head)
3380 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3381 drm_mode_vrefresh(m) == vrefresh_rate)
3382 return NULL;
3383
3384 /* HDTV hack, part 2 */
3385 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3386 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3387 false);
3388 if (!mode)
3389 return NULL;
3390 mode->hdisplay = 1366;
3391 mode->hsync_start = mode->hsync_start - 1;
3392 mode->hsync_end = mode->hsync_end - 1;
3393 return mode;
3394 }
3395
3396 /* check whether it can be found in default mode table */
3397 if (drm_monitor_supports_rb(drm_edid)) {
3398 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3399 true);
3400 if (mode)
3401 return mode;
3402 }
3403 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3404 if (mode)
3405 return mode;
3406
3407 /* okay, generate it */
3408 switch (timing_level) {
3409 case LEVEL_DMT:
3410 break;
3411 case LEVEL_GTF:
3412 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3413 break;
3414 case LEVEL_GTF2:
3415 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3416 break;
3417 case LEVEL_CVT:
3418 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3419 false);
3420 break;
3421 }
3422 return mode;
3423 }
3424
3425 /*
3426 * EDID is delightfully ambiguous about how interlaced modes are to be
3427 * encoded. Our internal representation is of frame height, but some
3428 * HDTV detailed timings are encoded as field height.
3429 *
3430 * The format list here is from CEA, in frame size. Technically we
3431 * should be checking refresh rate too. Whatever.
3432 */
3433 static void
drm_mode_do_interlace_quirk(struct drm_display_mode * mode,const struct detailed_pixel_timing * pt)3434 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3435 const struct detailed_pixel_timing *pt)
3436 {
3437 int i;
3438 static const struct {
3439 int w, h;
3440 } cea_interlaced[] = {
3441 { 1920, 1080 },
3442 { 720, 480 },
3443 { 1440, 480 },
3444 { 2880, 480 },
3445 { 720, 576 },
3446 { 1440, 576 },
3447 { 2880, 576 },
3448 };
3449
3450 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3451 return;
3452
3453 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3454 if ((mode->hdisplay == cea_interlaced[i].w) &&
3455 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3456 mode->vdisplay *= 2;
3457 mode->vsync_start *= 2;
3458 mode->vsync_end *= 2;
3459 mode->vtotal *= 2;
3460 mode->vtotal |= 1;
3461 }
3462 }
3463
3464 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3465 }
3466
3467 /*
3468 * Create a new mode from an EDID detailed timing section. An EDID detailed
3469 * timing block contains enough info for us to create and return a new struct
3470 * drm_display_mode.
3471 */
drm_mode_detailed(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3472 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3473 const struct drm_edid *drm_edid,
3474 const struct detailed_timing *timing)
3475 {
3476 const struct drm_display_info *info = &connector->display_info;
3477 struct drm_device *dev = connector->dev;
3478 struct drm_display_mode *mode;
3479 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3480 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3481 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3482 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3483 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3484 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3485 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3486 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3487 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3488
3489 /* ignore tiny modes */
3490 if (hactive < 64 || vactive < 64)
3491 return NULL;
3492
3493 if (pt->misc & DRM_EDID_PT_STEREO) {
3494 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3495 connector->base.id, connector->name);
3496 return NULL;
3497 }
3498 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3499 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3500 connector->base.id, connector->name);
3501 }
3502
3503 /* it is incorrect if hsync/vsync width is zero */
3504 if (!hsync_pulse_width || !vsync_pulse_width) {
3505 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3506 connector->base.id, connector->name);
3507 return NULL;
3508 }
3509
3510 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3511 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3512 if (!mode)
3513 return NULL;
3514
3515 goto set_size;
3516 }
3517
3518 mode = drm_mode_create(dev);
3519 if (!mode)
3520 return NULL;
3521
3522 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3523 mode->clock = 1088 * 10;
3524 else
3525 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3526
3527 mode->hdisplay = hactive;
3528 mode->hsync_start = mode->hdisplay + hsync_offset;
3529 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3530 mode->htotal = mode->hdisplay + hblank;
3531
3532 mode->vdisplay = vactive;
3533 mode->vsync_start = mode->vdisplay + vsync_offset;
3534 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3535 mode->vtotal = mode->vdisplay + vblank;
3536
3537 /* Some EDIDs have bogus h/vsync_end values */
3538 if (mode->hsync_end > mode->htotal) {
3539 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n",
3540 connector->base.id, connector->name,
3541 mode->hsync_end, mode->htotal);
3542 mode->hsync_end = mode->htotal;
3543 }
3544 if (mode->vsync_end > mode->vtotal) {
3545 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n",
3546 connector->base.id, connector->name,
3547 mode->vsync_end, mode->vtotal);
3548 mode->vsync_end = mode->vtotal;
3549 }
3550
3551 drm_mode_do_interlace_quirk(mode, pt);
3552
3553 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3554 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3555 } else {
3556 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3557 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3558 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3559 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3560 }
3561
3562 set_size:
3563 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3564 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3565
3566 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
3567 mode->width_mm *= 10;
3568 mode->height_mm *= 10;
3569 }
3570
3571 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3572 mode->width_mm = drm_edid->edid->width_cm * 10;
3573 mode->height_mm = drm_edid->edid->height_cm * 10;
3574 }
3575
3576 mode->type = DRM_MODE_TYPE_DRIVER;
3577 drm_mode_set_name(mode);
3578
3579 return mode;
3580 }
3581
3582 static bool
mode_in_hsync_range(const struct drm_display_mode * mode,const struct edid * edid,const u8 * t)3583 mode_in_hsync_range(const struct drm_display_mode *mode,
3584 const struct edid *edid, const u8 *t)
3585 {
3586 int hsync, hmin, hmax;
3587
3588 hmin = t[7];
3589 if (edid->revision >= 4)
3590 hmin += ((t[4] & 0x04) ? 255 : 0);
3591 hmax = t[8];
3592 if (edid->revision >= 4)
3593 hmax += ((t[4] & 0x08) ? 255 : 0);
3594 hsync = drm_mode_hsync(mode);
3595
3596 return (hsync <= hmax && hsync >= hmin);
3597 }
3598
3599 static bool
mode_in_vsync_range(const struct drm_display_mode * mode,const struct edid * edid,const u8 * t)3600 mode_in_vsync_range(const struct drm_display_mode *mode,
3601 const struct edid *edid, const u8 *t)
3602 {
3603 int vsync, vmin, vmax;
3604
3605 vmin = t[5];
3606 if (edid->revision >= 4)
3607 vmin += ((t[4] & 0x01) ? 255 : 0);
3608 vmax = t[6];
3609 if (edid->revision >= 4)
3610 vmax += ((t[4] & 0x02) ? 255 : 0);
3611 vsync = drm_mode_vrefresh(mode);
3612
3613 return (vsync <= vmax && vsync >= vmin);
3614 }
3615
3616 static u32
range_pixel_clock(const struct edid * edid,const u8 * t)3617 range_pixel_clock(const struct edid *edid, const u8 *t)
3618 {
3619 /* unspecified */
3620 if (t[9] == 0 || t[9] == 255)
3621 return 0;
3622
3623 /* 1.4 with CVT support gives us real precision, yay */
3624 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3625 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3626
3627 /* 1.3 is pathetic, so fuzz up a bit */
3628 return t[9] * 10000 + 5001;
3629 }
3630
mode_in_range(const struct drm_display_mode * mode,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3631 static bool mode_in_range(const struct drm_display_mode *mode,
3632 const struct drm_edid *drm_edid,
3633 const struct detailed_timing *timing)
3634 {
3635 const struct edid *edid = drm_edid->edid;
3636 u32 max_clock;
3637 const u8 *t = (const u8 *)timing;
3638
3639 if (!mode_in_hsync_range(mode, edid, t))
3640 return false;
3641
3642 if (!mode_in_vsync_range(mode, edid, t))
3643 return false;
3644
3645 if ((max_clock = range_pixel_clock(edid, t)))
3646 if (mode->clock > max_clock)
3647 return false;
3648
3649 /* 1.4 max horizontal check */
3650 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3651 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3652 return false;
3653
3654 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3655 return false;
3656
3657 return true;
3658 }
3659
valid_inferred_mode(const struct drm_connector * connector,const struct drm_display_mode * mode)3660 static bool valid_inferred_mode(const struct drm_connector *connector,
3661 const struct drm_display_mode *mode)
3662 {
3663 const struct drm_display_mode *m;
3664 bool ok = false;
3665
3666 list_for_each_entry(m, &connector->probed_modes, head) {
3667 if (mode->hdisplay == m->hdisplay &&
3668 mode->vdisplay == m->vdisplay &&
3669 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3670 return false; /* duplicated */
3671 if (mode->hdisplay <= m->hdisplay &&
3672 mode->vdisplay <= m->vdisplay)
3673 ok = true;
3674 }
3675 return ok;
3676 }
3677
drm_dmt_modes_for_range(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3678 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3679 const struct drm_edid *drm_edid,
3680 const struct detailed_timing *timing)
3681 {
3682 int i, modes = 0;
3683 struct drm_display_mode *newmode;
3684 struct drm_device *dev = connector->dev;
3685
3686 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3687 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3688 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3689 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3690 if (newmode) {
3691 drm_mode_probed_add(connector, newmode);
3692 modes++;
3693 }
3694 }
3695 }
3696
3697 return modes;
3698 }
3699
3700 /* fix up 1366x768 mode from 1368x768;
3701 * GFT/CVT can't express 1366 width which isn't dividable by 8
3702 */
drm_mode_fixup_1366x768(struct drm_display_mode * mode)3703 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3704 {
3705 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3706 mode->hdisplay = 1366;
3707 mode->hsync_start--;
3708 mode->hsync_end--;
3709 drm_mode_set_name(mode);
3710 }
3711 }
3712
drm_gtf_modes_for_range(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3713 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3714 const struct drm_edid *drm_edid,
3715 const struct detailed_timing *timing)
3716 {
3717 int i, modes = 0;
3718 struct drm_display_mode *newmode;
3719 struct drm_device *dev = connector->dev;
3720
3721 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3722 const struct minimode *m = &extra_modes[i];
3723
3724 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3725 if (!newmode)
3726 return modes;
3727
3728 drm_mode_fixup_1366x768(newmode);
3729 if (!mode_in_range(newmode, drm_edid, timing) ||
3730 !valid_inferred_mode(connector, newmode)) {
3731 drm_mode_destroy(dev, newmode);
3732 continue;
3733 }
3734
3735 drm_mode_probed_add(connector, newmode);
3736 modes++;
3737 }
3738
3739 return modes;
3740 }
3741
drm_gtf2_modes_for_range(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3742 static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3743 const struct drm_edid *drm_edid,
3744 const struct detailed_timing *timing)
3745 {
3746 int i, modes = 0;
3747 struct drm_display_mode *newmode;
3748 struct drm_device *dev = connector->dev;
3749
3750 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3751 const struct minimode *m = &extra_modes[i];
3752
3753 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3754 if (!newmode)
3755 return modes;
3756
3757 drm_mode_fixup_1366x768(newmode);
3758 if (!mode_in_range(newmode, drm_edid, timing) ||
3759 !valid_inferred_mode(connector, newmode)) {
3760 drm_mode_destroy(dev, newmode);
3761 continue;
3762 }
3763
3764 drm_mode_probed_add(connector, newmode);
3765 modes++;
3766 }
3767
3768 return modes;
3769 }
3770
drm_cvt_modes_for_range(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3771 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3772 const struct drm_edid *drm_edid,
3773 const struct detailed_timing *timing)
3774 {
3775 int i, modes = 0;
3776 struct drm_display_mode *newmode;
3777 struct drm_device *dev = connector->dev;
3778 bool rb = drm_monitor_supports_rb(drm_edid);
3779
3780 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3781 const struct minimode *m = &extra_modes[i];
3782
3783 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3784 if (!newmode)
3785 return modes;
3786
3787 drm_mode_fixup_1366x768(newmode);
3788 if (!mode_in_range(newmode, drm_edid, timing) ||
3789 !valid_inferred_mode(connector, newmode)) {
3790 drm_mode_destroy(dev, newmode);
3791 continue;
3792 }
3793
3794 drm_mode_probed_add(connector, newmode);
3795 modes++;
3796 }
3797
3798 return modes;
3799 }
3800
3801 static void
do_inferred_modes(const struct detailed_timing * timing,void * c)3802 do_inferred_modes(const struct detailed_timing *timing, void *c)
3803 {
3804 struct detailed_mode_closure *closure = c;
3805 const struct detailed_non_pixel *data = &timing->data.other_data;
3806 const struct detailed_data_monitor_range *range = &data->data.range;
3807
3808 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3809 return;
3810
3811 closure->modes += drm_dmt_modes_for_range(closure->connector,
3812 closure->drm_edid,
3813 timing);
3814
3815 if (closure->drm_edid->edid->revision < 2)
3816 return; /* GTF not defined yet */
3817
3818 switch (range->flags) {
3819 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3820 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3821 closure->drm_edid,
3822 timing);
3823 break;
3824 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3825 closure->modes += drm_gtf_modes_for_range(closure->connector,
3826 closure->drm_edid,
3827 timing);
3828 break;
3829 case DRM_EDID_CVT_SUPPORT_FLAG:
3830 if (closure->drm_edid->edid->revision < 4)
3831 break;
3832
3833 closure->modes += drm_cvt_modes_for_range(closure->connector,
3834 closure->drm_edid,
3835 timing);
3836 break;
3837 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3838 default:
3839 break;
3840 }
3841 }
3842
add_inferred_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)3843 static int add_inferred_modes(struct drm_connector *connector,
3844 const struct drm_edid *drm_edid)
3845 {
3846 struct detailed_mode_closure closure = {
3847 .connector = connector,
3848 .drm_edid = drm_edid,
3849 };
3850
3851 if (drm_edid->edid->revision >= 1)
3852 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3853
3854 return closure.modes;
3855 }
3856
3857 static int
drm_est3_modes(struct drm_connector * connector,const struct detailed_timing * timing)3858 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3859 {
3860 int i, j, m, modes = 0;
3861 struct drm_display_mode *mode;
3862 const u8 *est = ((const u8 *)timing) + 6;
3863
3864 for (i = 0; i < 6; i++) {
3865 for (j = 7; j >= 0; j--) {
3866 m = (i * 8) + (7 - j);
3867 if (m >= ARRAY_SIZE(est3_modes))
3868 break;
3869 if (est[i] & (1 << j)) {
3870 mode = drm_mode_find_dmt(connector->dev,
3871 est3_modes[m].w,
3872 est3_modes[m].h,
3873 est3_modes[m].r,
3874 est3_modes[m].rb);
3875 if (mode) {
3876 drm_mode_probed_add(connector, mode);
3877 modes++;
3878 }
3879 }
3880 }
3881 }
3882
3883 return modes;
3884 }
3885
3886 static void
do_established_modes(const struct detailed_timing * timing,void * c)3887 do_established_modes(const struct detailed_timing *timing, void *c)
3888 {
3889 struct detailed_mode_closure *closure = c;
3890
3891 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3892 return;
3893
3894 closure->modes += drm_est3_modes(closure->connector, timing);
3895 }
3896
3897 /*
3898 * Get established modes from EDID and add them. Each EDID block contains a
3899 * bitmap of the supported "established modes" list (defined above). Tease them
3900 * out and add them to the global modes list.
3901 */
add_established_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)3902 static int add_established_modes(struct drm_connector *connector,
3903 const struct drm_edid *drm_edid)
3904 {
3905 struct drm_device *dev = connector->dev;
3906 const struct edid *edid = drm_edid->edid;
3907 unsigned long est_bits = edid->established_timings.t1 |
3908 (edid->established_timings.t2 << 8) |
3909 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3910 int i, modes = 0;
3911 struct detailed_mode_closure closure = {
3912 .connector = connector,
3913 .drm_edid = drm_edid,
3914 };
3915
3916 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3917 if (est_bits & (1<<i)) {
3918 struct drm_display_mode *newmode;
3919
3920 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3921 if (newmode) {
3922 drm_mode_probed_add(connector, newmode);
3923 modes++;
3924 }
3925 }
3926 }
3927
3928 if (edid->revision >= 1)
3929 drm_for_each_detailed_block(drm_edid, do_established_modes,
3930 &closure);
3931
3932 return modes + closure.modes;
3933 }
3934
3935 static void
do_standard_modes(const struct detailed_timing * timing,void * c)3936 do_standard_modes(const struct detailed_timing *timing, void *c)
3937 {
3938 struct detailed_mode_closure *closure = c;
3939 const struct detailed_non_pixel *data = &timing->data.other_data;
3940 struct drm_connector *connector = closure->connector;
3941 int i;
3942
3943 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3944 return;
3945
3946 for (i = 0; i < 6; i++) {
3947 const struct std_timing *std = &data->data.timings[i];
3948 struct drm_display_mode *newmode;
3949
3950 newmode = drm_mode_std(connector, closure->drm_edid, std);
3951 if (newmode) {
3952 drm_mode_probed_add(connector, newmode);
3953 closure->modes++;
3954 }
3955 }
3956 }
3957
3958 /*
3959 * Get standard modes from EDID and add them. Standard modes can be calculated
3960 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3961 * add them to the list.
3962 */
add_standard_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)3963 static int add_standard_modes(struct drm_connector *connector,
3964 const struct drm_edid *drm_edid)
3965 {
3966 int i, modes = 0;
3967 struct detailed_mode_closure closure = {
3968 .connector = connector,
3969 .drm_edid = drm_edid,
3970 };
3971
3972 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3973 struct drm_display_mode *newmode;
3974
3975 newmode = drm_mode_std(connector, drm_edid,
3976 &drm_edid->edid->standard_timings[i]);
3977 if (newmode) {
3978 drm_mode_probed_add(connector, newmode);
3979 modes++;
3980 }
3981 }
3982
3983 if (drm_edid->edid->revision >= 1)
3984 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3985 &closure);
3986
3987 /* XXX should also look for standard codes in VTB blocks */
3988
3989 return modes + closure.modes;
3990 }
3991
drm_cvt_modes(struct drm_connector * connector,const struct detailed_timing * timing)3992 static int drm_cvt_modes(struct drm_connector *connector,
3993 const struct detailed_timing *timing)
3994 {
3995 int i, j, modes = 0;
3996 struct drm_display_mode *newmode;
3997 struct drm_device *dev = connector->dev;
3998 const struct cvt_timing *cvt;
3999 static const int rates[] = { 60, 85, 75, 60, 50 };
4000 const u8 empty[3] = { 0, 0, 0 };
4001
4002 for (i = 0; i < 4; i++) {
4003 int width, height;
4004
4005 cvt = &(timing->data.other_data.data.cvt[i]);
4006
4007 if (!memcmp(cvt->code, empty, 3))
4008 continue;
4009
4010 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
4011 switch (cvt->code[1] & 0x0c) {
4012 /* default - because compiler doesn't see that we've enumerated all cases */
4013 default:
4014 case 0x00:
4015 width = height * 4 / 3;
4016 break;
4017 case 0x04:
4018 width = height * 16 / 9;
4019 break;
4020 case 0x08:
4021 width = height * 16 / 10;
4022 break;
4023 case 0x0c:
4024 width = height * 15 / 9;
4025 break;
4026 }
4027
4028 for (j = 1; j < 5; j++) {
4029 if (cvt->code[2] & (1 << j)) {
4030 newmode = drm_cvt_mode(dev, width, height,
4031 rates[j], j == 0,
4032 false, false);
4033 if (newmode) {
4034 drm_mode_probed_add(connector, newmode);
4035 modes++;
4036 }
4037 }
4038 }
4039 }
4040
4041 return modes;
4042 }
4043
4044 static void
do_cvt_mode(const struct detailed_timing * timing,void * c)4045 do_cvt_mode(const struct detailed_timing *timing, void *c)
4046 {
4047 struct detailed_mode_closure *closure = c;
4048
4049 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
4050 return;
4051
4052 closure->modes += drm_cvt_modes(closure->connector, timing);
4053 }
4054
4055 static int
add_cvt_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)4056 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4057 {
4058 struct detailed_mode_closure closure = {
4059 .connector = connector,
4060 .drm_edid = drm_edid,
4061 };
4062
4063 if (drm_edid->edid->revision >= 3)
4064 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
4065
4066 /* XXX should also look for CVT codes in VTB blocks */
4067
4068 return closure.modes;
4069 }
4070
4071 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4072 struct drm_display_mode *mode);
4073
4074 static void
do_detailed_mode(const struct detailed_timing * timing,void * c)4075 do_detailed_mode(const struct detailed_timing *timing, void *c)
4076 {
4077 struct detailed_mode_closure *closure = c;
4078 struct drm_display_mode *newmode;
4079
4080 if (!is_detailed_timing_descriptor(timing))
4081 return;
4082
4083 newmode = drm_mode_detailed(closure->connector,
4084 closure->drm_edid, timing);
4085 if (!newmode)
4086 return;
4087
4088 if (closure->preferred)
4089 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4090
4091 /*
4092 * Detailed modes are limited to 10kHz pixel clock resolution,
4093 * so fix up anything that looks like CEA/HDMI mode, but the clock
4094 * is just slightly off.
4095 */
4096 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4097
4098 drm_mode_probed_add(closure->connector, newmode);
4099 closure->modes++;
4100 closure->preferred = false;
4101 }
4102
4103 /*
4104 * add_detailed_modes - Add modes from detailed timings
4105 * @connector: attached connector
4106 * @drm_edid: EDID block to scan
4107 */
add_detailed_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)4108 static int add_detailed_modes(struct drm_connector *connector,
4109 const struct drm_edid *drm_edid)
4110 {
4111 struct detailed_mode_closure closure = {
4112 .connector = connector,
4113 .drm_edid = drm_edid,
4114 };
4115
4116 if (drm_edid->edid->revision >= 4)
4117 closure.preferred = true; /* first detailed timing is always preferred */
4118 else
4119 closure.preferred =
4120 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4121
4122 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4123
4124 return closure.modes;
4125 }
4126
4127 /* CTA-861-H Table 60 - CTA Tag Codes */
4128 #define CTA_DB_AUDIO 1
4129 #define CTA_DB_VIDEO 2
4130 #define CTA_DB_VENDOR 3
4131 #define CTA_DB_SPEAKER 4
4132 #define CTA_DB_EXTENDED_TAG 7
4133
4134 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
4135 #define CTA_EXT_DB_VIDEO_CAP 0
4136 #define CTA_EXT_DB_VENDOR 1
4137 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
4138 #define CTA_EXT_DB_420_VIDEO_DATA 14
4139 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4140 #define CTA_EXT_DB_HF_EEODB 0x78
4141 #define CTA_EXT_DB_HF_SCDB 0x79
4142
4143 #define EDID_BASIC_AUDIO (1 << 6)
4144 #define EDID_CEA_YCRCB444 (1 << 5)
4145 #define EDID_CEA_YCRCB422 (1 << 4)
4146 #define EDID_CEA_VCDB_QS (1 << 6)
4147
4148 /*
4149 * Search EDID for CEA extension block.
4150 *
4151 * FIXME: Prefer not returning pointers to raw EDID data.
4152 */
drm_find_edid_extension(const struct drm_edid * drm_edid,int ext_id,int * ext_index)4153 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4154 int ext_id, int *ext_index)
4155 {
4156 const u8 *edid_ext = NULL;
4157 int i;
4158
4159 /* No EDID or EDID extensions */
4160 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4161 return NULL;
4162
4163 /* Find CEA extension */
4164 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4165 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4166 if (edid_block_tag(edid_ext) == ext_id)
4167 break;
4168 }
4169
4170 if (i >= drm_edid_extension_block_count(drm_edid))
4171 return NULL;
4172
4173 *ext_index = i + 1;
4174
4175 return edid_ext;
4176 }
4177
4178 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
drm_edid_has_cta_extension(const struct drm_edid * drm_edid)4179 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4180 {
4181 const struct displayid_block *block;
4182 struct displayid_iter iter;
4183 int ext_index = 0;
4184 bool found = false;
4185
4186 /* Look for a top level CEA extension block */
4187 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
4188 return true;
4189
4190 /* CEA blocks can also be found embedded in a DisplayID block */
4191 displayid_iter_edid_begin(drm_edid, &iter);
4192 displayid_iter_for_each(block, &iter) {
4193 if (block->tag == DATA_BLOCK_CTA) {
4194 found = true;
4195 break;
4196 }
4197 }
4198 displayid_iter_end(&iter);
4199
4200 return found;
4201 }
4202
cea_mode_for_vic(u8 vic)4203 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4204 {
4205 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4206 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4207
4208 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4209 return &edid_cea_modes_1[vic - 1];
4210 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4211 return &edid_cea_modes_193[vic - 193];
4212 return NULL;
4213 }
4214
cea_num_vics(void)4215 static u8 cea_num_vics(void)
4216 {
4217 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4218 }
4219
cea_next_vic(u8 vic)4220 static u8 cea_next_vic(u8 vic)
4221 {
4222 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4223 vic = 193;
4224 return vic;
4225 }
4226
4227 /*
4228 * Calculate the alternate clock for the CEA mode
4229 * (60Hz vs. 59.94Hz etc.)
4230 */
4231 static unsigned int
cea_mode_alternate_clock(const struct drm_display_mode * cea_mode)4232 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4233 {
4234 unsigned int clock = cea_mode->clock;
4235
4236 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4237 return clock;
4238
4239 /*
4240 * edid_cea_modes contains the 59.94Hz
4241 * variant for 240 and 480 line modes,
4242 * and the 60Hz variant otherwise.
4243 */
4244 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4245 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4246 else
4247 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4248
4249 return clock;
4250 }
4251
4252 static bool
cea_mode_alternate_timings(u8 vic,struct drm_display_mode * mode)4253 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4254 {
4255 /*
4256 * For certain VICs the spec allows the vertical
4257 * front porch to vary by one or two lines.
4258 *
4259 * cea_modes[] stores the variant with the shortest
4260 * vertical front porch. We can adjust the mode to
4261 * get the other variants by simply increasing the
4262 * vertical front porch length.
4263 */
4264 #ifdef notyet
4265 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4266 cea_mode_for_vic(9)->vtotal != 262 ||
4267 cea_mode_for_vic(12)->vtotal != 262 ||
4268 cea_mode_for_vic(13)->vtotal != 262 ||
4269 cea_mode_for_vic(23)->vtotal != 312 ||
4270 cea_mode_for_vic(24)->vtotal != 312 ||
4271 cea_mode_for_vic(27)->vtotal != 312 ||
4272 cea_mode_for_vic(28)->vtotal != 312);
4273 #endif
4274
4275 if (((vic == 8 || vic == 9 ||
4276 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4277 ((vic == 23 || vic == 24 ||
4278 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4279 mode->vsync_start++;
4280 mode->vsync_end++;
4281 mode->vtotal++;
4282
4283 return true;
4284 }
4285
4286 return false;
4287 }
4288
drm_match_cea_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)4289 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4290 unsigned int clock_tolerance)
4291 {
4292 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4293 u8 vic;
4294
4295 if (!to_match->clock)
4296 return 0;
4297
4298 if (to_match->picture_aspect_ratio)
4299 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4300
4301 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4302 struct drm_display_mode cea_mode;
4303 unsigned int clock1, clock2;
4304
4305 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4306
4307 /* Check both 60Hz and 59.94Hz */
4308 clock1 = cea_mode.clock;
4309 clock2 = cea_mode_alternate_clock(&cea_mode);
4310
4311 if (abs(to_match->clock - clock1) > clock_tolerance &&
4312 abs(to_match->clock - clock2) > clock_tolerance)
4313 continue;
4314
4315 do {
4316 if (drm_mode_match(to_match, &cea_mode, match_flags))
4317 return vic;
4318 } while (cea_mode_alternate_timings(vic, &cea_mode));
4319 }
4320
4321 return 0;
4322 }
4323
4324 /**
4325 * drm_match_cea_mode - look for a CEA mode matching given mode
4326 * @to_match: display mode
4327 *
4328 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4329 * mode.
4330 */
drm_match_cea_mode(const struct drm_display_mode * to_match)4331 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4332 {
4333 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4334 u8 vic;
4335
4336 if (!to_match->clock)
4337 return 0;
4338
4339 if (to_match->picture_aspect_ratio)
4340 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4341
4342 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4343 struct drm_display_mode cea_mode;
4344 unsigned int clock1, clock2;
4345
4346 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4347
4348 /* Check both 60Hz and 59.94Hz */
4349 clock1 = cea_mode.clock;
4350 clock2 = cea_mode_alternate_clock(&cea_mode);
4351
4352 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4353 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4354 continue;
4355
4356 do {
4357 if (drm_mode_match(to_match, &cea_mode, match_flags))
4358 return vic;
4359 } while (cea_mode_alternate_timings(vic, &cea_mode));
4360 }
4361
4362 return 0;
4363 }
4364 EXPORT_SYMBOL(drm_match_cea_mode);
4365
drm_valid_cea_vic(u8 vic)4366 static bool drm_valid_cea_vic(u8 vic)
4367 {
4368 return cea_mode_for_vic(vic) != NULL;
4369 }
4370
drm_get_cea_aspect_ratio(const u8 video_code)4371 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4372 {
4373 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4374
4375 if (mode)
4376 return mode->picture_aspect_ratio;
4377
4378 return HDMI_PICTURE_ASPECT_NONE;
4379 }
4380
drm_get_hdmi_aspect_ratio(const u8 video_code)4381 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4382 {
4383 return edid_4k_modes[video_code].picture_aspect_ratio;
4384 }
4385
4386 /*
4387 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4388 * specific block).
4389 */
4390 static unsigned int
hdmi_mode_alternate_clock(const struct drm_display_mode * hdmi_mode)4391 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4392 {
4393 return cea_mode_alternate_clock(hdmi_mode);
4394 }
4395
drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)4396 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4397 unsigned int clock_tolerance)
4398 {
4399 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4400 u8 vic;
4401
4402 if (!to_match->clock)
4403 return 0;
4404
4405 if (to_match->picture_aspect_ratio)
4406 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4407
4408 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4409 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4410 unsigned int clock1, clock2;
4411
4412 /* Make sure to also match alternate clocks */
4413 clock1 = hdmi_mode->clock;
4414 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4415
4416 if (abs(to_match->clock - clock1) > clock_tolerance &&
4417 abs(to_match->clock - clock2) > clock_tolerance)
4418 continue;
4419
4420 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4421 return vic;
4422 }
4423
4424 return 0;
4425 }
4426
4427 /*
4428 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4429 * @to_match: display mode
4430 *
4431 * An HDMI mode is one defined in the HDMI vendor specific block.
4432 *
4433 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4434 */
drm_match_hdmi_mode(const struct drm_display_mode * to_match)4435 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4436 {
4437 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4438 u8 vic;
4439
4440 if (!to_match->clock)
4441 return 0;
4442
4443 if (to_match->picture_aspect_ratio)
4444 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4445
4446 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4447 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4448 unsigned int clock1, clock2;
4449
4450 /* Make sure to also match alternate clocks */
4451 clock1 = hdmi_mode->clock;
4452 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4453
4454 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4455 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4456 drm_mode_match(to_match, hdmi_mode, match_flags))
4457 return vic;
4458 }
4459 return 0;
4460 }
4461
drm_valid_hdmi_vic(u8 vic)4462 static bool drm_valid_hdmi_vic(u8 vic)
4463 {
4464 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4465 }
4466
add_alternate_cea_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)4467 static int add_alternate_cea_modes(struct drm_connector *connector,
4468 const struct drm_edid *drm_edid)
4469 {
4470 struct drm_device *dev = connector->dev;
4471 struct drm_display_mode *mode, *tmp;
4472 DRM_LIST_HEAD(list);
4473 int modes = 0;
4474
4475 /* Don't add CTA modes if the CTA extension block is missing */
4476 if (!drm_edid_has_cta_extension(drm_edid))
4477 return 0;
4478
4479 /*
4480 * Go through all probed modes and create a new mode
4481 * with the alternate clock for certain CEA modes.
4482 */
4483 list_for_each_entry(mode, &connector->probed_modes, head) {
4484 const struct drm_display_mode *cea_mode = NULL;
4485 struct drm_display_mode *newmode;
4486 u8 vic = drm_match_cea_mode(mode);
4487 unsigned int clock1, clock2;
4488
4489 if (drm_valid_cea_vic(vic)) {
4490 cea_mode = cea_mode_for_vic(vic);
4491 clock2 = cea_mode_alternate_clock(cea_mode);
4492 } else {
4493 vic = drm_match_hdmi_mode(mode);
4494 if (drm_valid_hdmi_vic(vic)) {
4495 cea_mode = &edid_4k_modes[vic];
4496 clock2 = hdmi_mode_alternate_clock(cea_mode);
4497 }
4498 }
4499
4500 if (!cea_mode)
4501 continue;
4502
4503 clock1 = cea_mode->clock;
4504
4505 if (clock1 == clock2)
4506 continue;
4507
4508 if (mode->clock != clock1 && mode->clock != clock2)
4509 continue;
4510
4511 newmode = drm_mode_duplicate(dev, cea_mode);
4512 if (!newmode)
4513 continue;
4514
4515 /* Carry over the stereo flags */
4516 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4517
4518 /*
4519 * The current mode could be either variant. Make
4520 * sure to pick the "other" clock for the new mode.
4521 */
4522 if (mode->clock != clock1)
4523 newmode->clock = clock1;
4524 else
4525 newmode->clock = clock2;
4526
4527 list_add_tail(&newmode->head, &list);
4528 }
4529
4530 list_for_each_entry_safe(mode, tmp, &list, head) {
4531 list_del(&mode->head);
4532 drm_mode_probed_add(connector, mode);
4533 modes++;
4534 }
4535
4536 return modes;
4537 }
4538
svd_to_vic(u8 svd)4539 static u8 svd_to_vic(u8 svd)
4540 {
4541 /* 0-6 bit vic, 7th bit native mode indicator */
4542 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4543 return svd & 127;
4544
4545 return svd;
4546 }
4547
4548 /*
4549 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4550 * the EDID, or NULL on errors.
4551 */
4552 static struct drm_display_mode *
drm_display_mode_from_vic_index(struct drm_connector * connector,int vic_index)4553 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4554 {
4555 const struct drm_display_info *info = &connector->display_info;
4556 struct drm_device *dev = connector->dev;
4557
4558 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4559 return NULL;
4560
4561 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4562 }
4563
4564 /*
4565 * do_y420vdb_modes - Parse YCBCR 420 only modes
4566 * @connector: connector corresponding to the HDMI sink
4567 * @svds: start of the data block of CEA YCBCR 420 VDB
4568 * @len: length of the CEA YCBCR 420 VDB
4569 *
4570 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4571 * which contains modes which can be supported in YCBCR 420
4572 * output format only.
4573 */
do_y420vdb_modes(struct drm_connector * connector,const u8 * svds,u8 svds_len)4574 static int do_y420vdb_modes(struct drm_connector *connector,
4575 const u8 *svds, u8 svds_len)
4576 {
4577 struct drm_device *dev = connector->dev;
4578 int modes = 0, i;
4579
4580 for (i = 0; i < svds_len; i++) {
4581 u8 vic = svd_to_vic(svds[i]);
4582 struct drm_display_mode *newmode;
4583
4584 if (!drm_valid_cea_vic(vic))
4585 continue;
4586
4587 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4588 if (!newmode)
4589 break;
4590 drm_mode_probed_add(connector, newmode);
4591 modes++;
4592 }
4593
4594 return modes;
4595 }
4596
4597 /**
4598 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4599 * @dev: DRM device
4600 * @video_code: CEA VIC of the mode
4601 *
4602 * Creates a new mode matching the specified CEA VIC.
4603 *
4604 * Returns: A new drm_display_mode on success or NULL on failure
4605 */
4606 struct drm_display_mode *
drm_display_mode_from_cea_vic(struct drm_device * dev,u8 video_code)4607 drm_display_mode_from_cea_vic(struct drm_device *dev,
4608 u8 video_code)
4609 {
4610 const struct drm_display_mode *cea_mode;
4611 struct drm_display_mode *newmode;
4612
4613 cea_mode = cea_mode_for_vic(video_code);
4614 if (!cea_mode)
4615 return NULL;
4616
4617 newmode = drm_mode_duplicate(dev, cea_mode);
4618 if (!newmode)
4619 return NULL;
4620
4621 return newmode;
4622 }
4623 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4624
4625 /* Add modes based on VICs parsed in parse_cta_vdb() */
add_cta_vdb_modes(struct drm_connector * connector)4626 static int add_cta_vdb_modes(struct drm_connector *connector)
4627 {
4628 const struct drm_display_info *info = &connector->display_info;
4629 int i, modes = 0;
4630
4631 if (!info->vics)
4632 return 0;
4633
4634 for (i = 0; i < info->vics_len; i++) {
4635 struct drm_display_mode *mode;
4636
4637 mode = drm_display_mode_from_vic_index(connector, i);
4638 if (mode) {
4639 drm_mode_probed_add(connector, mode);
4640 modes++;
4641 }
4642 }
4643
4644 return modes;
4645 }
4646
4647 struct stereo_mandatory_mode {
4648 int width, height, vrefresh;
4649 unsigned int flags;
4650 };
4651
4652 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4653 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4654 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4655 { 1920, 1080, 50,
4656 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4657 { 1920, 1080, 60,
4658 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4659 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4660 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4661 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4662 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4663 };
4664
4665 static bool
stereo_match_mandatory(const struct drm_display_mode * mode,const struct stereo_mandatory_mode * stereo_mode)4666 stereo_match_mandatory(const struct drm_display_mode *mode,
4667 const struct stereo_mandatory_mode *stereo_mode)
4668 {
4669 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4670
4671 return mode->hdisplay == stereo_mode->width &&
4672 mode->vdisplay == stereo_mode->height &&
4673 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4674 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4675 }
4676
add_hdmi_mandatory_stereo_modes(struct drm_connector * connector)4677 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4678 {
4679 struct drm_device *dev = connector->dev;
4680 const struct drm_display_mode *mode;
4681 struct list_head stereo_modes;
4682 int modes = 0, i;
4683
4684 INIT_LIST_HEAD(&stereo_modes);
4685
4686 list_for_each_entry(mode, &connector->probed_modes, head) {
4687 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4688 const struct stereo_mandatory_mode *mandatory;
4689 struct drm_display_mode *new_mode;
4690
4691 if (!stereo_match_mandatory(mode,
4692 &stereo_mandatory_modes[i]))
4693 continue;
4694
4695 mandatory = &stereo_mandatory_modes[i];
4696 new_mode = drm_mode_duplicate(dev, mode);
4697 if (!new_mode)
4698 continue;
4699
4700 new_mode->flags |= mandatory->flags;
4701 list_add_tail(&new_mode->head, &stereo_modes);
4702 modes++;
4703 }
4704 }
4705
4706 list_splice_tail(&stereo_modes, &connector->probed_modes);
4707
4708 return modes;
4709 }
4710
add_hdmi_mode(struct drm_connector * connector,u8 vic)4711 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4712 {
4713 struct drm_device *dev = connector->dev;
4714 struct drm_display_mode *newmode;
4715
4716 if (!drm_valid_hdmi_vic(vic)) {
4717 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4718 connector->base.id, connector->name, vic);
4719 return 0;
4720 }
4721
4722 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4723 if (!newmode)
4724 return 0;
4725
4726 drm_mode_probed_add(connector, newmode);
4727
4728 return 1;
4729 }
4730
add_3d_struct_modes(struct drm_connector * connector,u16 structure,int vic_index)4731 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4732 int vic_index)
4733 {
4734 struct drm_display_mode *newmode;
4735 int modes = 0;
4736
4737 if (structure & (1 << 0)) {
4738 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4739 if (newmode) {
4740 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4741 drm_mode_probed_add(connector, newmode);
4742 modes++;
4743 }
4744 }
4745 if (structure & (1 << 6)) {
4746 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4747 if (newmode) {
4748 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4749 drm_mode_probed_add(connector, newmode);
4750 modes++;
4751 }
4752 }
4753 if (structure & (1 << 8)) {
4754 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4755 if (newmode) {
4756 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4757 drm_mode_probed_add(connector, newmode);
4758 modes++;
4759 }
4760 }
4761
4762 return modes;
4763 }
4764
hdmi_vsdb_latency_present(const u8 * db)4765 static bool hdmi_vsdb_latency_present(const u8 *db)
4766 {
4767 return db[8] & BIT(7);
4768 }
4769
hdmi_vsdb_i_latency_present(const u8 * db)4770 static bool hdmi_vsdb_i_latency_present(const u8 *db)
4771 {
4772 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4773 }
4774
hdmi_vsdb_latency_length(const u8 * db)4775 static int hdmi_vsdb_latency_length(const u8 *db)
4776 {
4777 if (hdmi_vsdb_i_latency_present(db))
4778 return 4;
4779 else if (hdmi_vsdb_latency_present(db))
4780 return 2;
4781 else
4782 return 0;
4783 }
4784
4785 /*
4786 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4787 * @connector: connector corresponding to the HDMI sink
4788 * @db: start of the CEA vendor specific block
4789 * @len: length of the CEA block payload, ie. one can access up to db[len]
4790 *
4791 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4792 * also adds the stereo 3d modes when applicable.
4793 */
4794 static int
do_hdmi_vsdb_modes(struct drm_connector * connector,const u8 * db,u8 len)4795 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4796 {
4797 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4798 u8 vic_len, hdmi_3d_len = 0;
4799 u16 mask;
4800 u16 structure_all;
4801
4802 if (len < 8)
4803 goto out;
4804
4805 /* no HDMI_Video_Present */
4806 if (!(db[8] & (1 << 5)))
4807 goto out;
4808
4809 offset += hdmi_vsdb_latency_length(db);
4810
4811 /* the declared length is not long enough for the 2 first bytes
4812 * of additional video format capabilities */
4813 if (len < (8 + offset + 2))
4814 goto out;
4815
4816 /* 3D_Present */
4817 offset++;
4818 if (db[8 + offset] & (1 << 7)) {
4819 modes += add_hdmi_mandatory_stereo_modes(connector);
4820
4821 /* 3D_Multi_present */
4822 multi_present = (db[8 + offset] & 0x60) >> 5;
4823 }
4824
4825 offset++;
4826 vic_len = db[8 + offset] >> 5;
4827 hdmi_3d_len = db[8 + offset] & 0x1f;
4828
4829 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4830 u8 vic;
4831
4832 vic = db[9 + offset + i];
4833 modes += add_hdmi_mode(connector, vic);
4834 }
4835 offset += 1 + vic_len;
4836
4837 if (multi_present == 1)
4838 multi_len = 2;
4839 else if (multi_present == 2)
4840 multi_len = 4;
4841 else
4842 multi_len = 0;
4843
4844 if (len < (8 + offset + hdmi_3d_len - 1))
4845 goto out;
4846
4847 if (hdmi_3d_len < multi_len)
4848 goto out;
4849
4850 if (multi_present == 1 || multi_present == 2) {
4851 /* 3D_Structure_ALL */
4852 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4853
4854 /* check if 3D_MASK is present */
4855 if (multi_present == 2)
4856 mask = (db[10 + offset] << 8) | db[11 + offset];
4857 else
4858 mask = 0xffff;
4859
4860 for (i = 0; i < 16; i++) {
4861 if (mask & (1 << i))
4862 modes += add_3d_struct_modes(connector,
4863 structure_all, i);
4864 }
4865 }
4866
4867 offset += multi_len;
4868
4869 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4870 int vic_index;
4871 struct drm_display_mode *newmode = NULL;
4872 unsigned int newflag = 0;
4873 bool detail_present;
4874
4875 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4876
4877 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4878 break;
4879
4880 /* 2D_VIC_order_X */
4881 vic_index = db[8 + offset + i] >> 4;
4882
4883 /* 3D_Structure_X */
4884 switch (db[8 + offset + i] & 0x0f) {
4885 case 0:
4886 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4887 break;
4888 case 6:
4889 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4890 break;
4891 case 8:
4892 /* 3D_Detail_X */
4893 if ((db[9 + offset + i] >> 4) == 1)
4894 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4895 break;
4896 }
4897
4898 if (newflag != 0) {
4899 newmode = drm_display_mode_from_vic_index(connector,
4900 vic_index);
4901
4902 if (newmode) {
4903 newmode->flags |= newflag;
4904 drm_mode_probed_add(connector, newmode);
4905 modes++;
4906 }
4907 }
4908
4909 if (detail_present)
4910 i++;
4911 }
4912
4913 out:
4914 return modes;
4915 }
4916
4917 static int
cea_revision(const u8 * cea)4918 cea_revision(const u8 *cea)
4919 {
4920 /*
4921 * FIXME is this correct for the DispID variant?
4922 * The DispID spec doesn't really specify whether
4923 * this is the revision of the CEA extension or
4924 * the DispID CEA data block. And the only value
4925 * given as an example is 0.
4926 */
4927 return cea[1];
4928 }
4929
4930 /*
4931 * CTA Data Block iterator.
4932 *
4933 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4934 * CTA Data Blocks.
4935 *
4936 * struct cea_db *db:
4937 * struct cea_db_iter iter;
4938 *
4939 * cea_db_iter_edid_begin(edid, &iter);
4940 * cea_db_iter_for_each(db, &iter) {
4941 * // do stuff with db
4942 * }
4943 * cea_db_iter_end(&iter);
4944 */
4945 struct cea_db_iter {
4946 struct drm_edid_iter edid_iter;
4947 struct displayid_iter displayid_iter;
4948
4949 /* Current Data Block Collection. */
4950 const u8 *collection;
4951
4952 /* Current Data Block index in current collection. */
4953 int index;
4954
4955 /* End index in current collection. */
4956 int end;
4957 };
4958
4959 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4960 struct cea_db {
4961 u8 tag_length;
4962 u8 data[];
4963 } __packed;
4964
cea_db_tag(const struct cea_db * db)4965 static int cea_db_tag(const struct cea_db *db)
4966 {
4967 return db->tag_length >> 5;
4968 }
4969
cea_db_payload_len(const void * _db)4970 static int cea_db_payload_len(const void *_db)
4971 {
4972 /* FIXME: Transition to passing struct cea_db * everywhere. */
4973 const struct cea_db *db = _db;
4974
4975 return db->tag_length & 0x1f;
4976 }
4977
cea_db_data(const struct cea_db * db)4978 static const void *cea_db_data(const struct cea_db *db)
4979 {
4980 return db->data;
4981 }
4982
cea_db_is_extended_tag(const struct cea_db * db,int tag)4983 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4984 {
4985 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4986 cea_db_payload_len(db) >= 1 &&
4987 db->data[0] == tag;
4988 }
4989
cea_db_is_vendor(const struct cea_db * db,int vendor_oui)4990 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4991 {
4992 const u8 *data = cea_db_data(db);
4993
4994 return cea_db_tag(db) == CTA_DB_VENDOR &&
4995 cea_db_payload_len(db) >= 3 &&
4996 oui(data[2], data[1], data[0]) == vendor_oui;
4997 }
4998
cea_db_iter_edid_begin(const struct drm_edid * drm_edid,struct cea_db_iter * iter)4999 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
5000 struct cea_db_iter *iter)
5001 {
5002 memset(iter, 0, sizeof(*iter));
5003
5004 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
5005 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
5006 }
5007
5008 static const struct cea_db *
__cea_db_iter_current_block(const struct cea_db_iter * iter)5009 __cea_db_iter_current_block(const struct cea_db_iter *iter)
5010 {
5011 const struct cea_db *db;
5012
5013 if (!iter->collection)
5014 return NULL;
5015
5016 db = (const struct cea_db *)&iter->collection[iter->index];
5017
5018 if (iter->index + sizeof(*db) <= iter->end &&
5019 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
5020 return db;
5021
5022 return NULL;
5023 }
5024
5025 /*
5026 * References:
5027 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5028 */
cea_db_collection_size(const u8 * cta)5029 static int cea_db_collection_size(const u8 *cta)
5030 {
5031 u8 d = cta[2];
5032
5033 if (d < 4 || d > 127)
5034 return 0;
5035
5036 return d - 4;
5037 }
5038
5039 /*
5040 * References:
5041 * - VESA E-EDID v1.4
5042 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5043 */
__cea_db_iter_edid_next(struct cea_db_iter * iter)5044 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5045 {
5046 const u8 *ext;
5047
5048 drm_edid_iter_for_each(ext, &iter->edid_iter) {
5049 int size;
5050
5051 /* Only support CTA Extension revision 3+ */
5052 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5053 continue;
5054
5055 size = cea_db_collection_size(ext);
5056 if (!size)
5057 continue;
5058
5059 iter->index = 4;
5060 iter->end = iter->index + size;
5061
5062 return ext;
5063 }
5064
5065 return NULL;
5066 }
5067
5068 /*
5069 * References:
5070 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5071 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5072 *
5073 * Note that the above do not specify any connection between DisplayID Data
5074 * Block revision and CTA Extension versions.
5075 */
__cea_db_iter_displayid_next(struct cea_db_iter * iter)5076 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5077 {
5078 const struct displayid_block *block;
5079
5080 displayid_iter_for_each(block, &iter->displayid_iter) {
5081 if (block->tag != DATA_BLOCK_CTA)
5082 continue;
5083
5084 /*
5085 * The displayid iterator has already verified the block bounds
5086 * in displayid_iter_block().
5087 */
5088 iter->index = sizeof(*block);
5089 iter->end = iter->index + block->num_bytes;
5090
5091 return block;
5092 }
5093
5094 return NULL;
5095 }
5096
__cea_db_iter_next(struct cea_db_iter * iter)5097 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5098 {
5099 const struct cea_db *db;
5100
5101 if (iter->collection) {
5102 /* Current collection should always be valid. */
5103 db = __cea_db_iter_current_block(iter);
5104 if (WARN_ON(!db)) {
5105 iter->collection = NULL;
5106 return NULL;
5107 }
5108
5109 /* Next block in CTA Data Block Collection */
5110 iter->index += sizeof(*db) + cea_db_payload_len(db);
5111
5112 db = __cea_db_iter_current_block(iter);
5113 if (db)
5114 return db;
5115 }
5116
5117 for (;;) {
5118 /*
5119 * Find the next CTA Data Block Collection. First iterate all
5120 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5121 *
5122 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5123 * Extension, it's recommended that DisplayID extensions are
5124 * exposed after all of the CTA Extensions.
5125 */
5126 iter->collection = __cea_db_iter_edid_next(iter);
5127 if (!iter->collection)
5128 iter->collection = __cea_db_iter_displayid_next(iter);
5129
5130 if (!iter->collection)
5131 return NULL;
5132
5133 db = __cea_db_iter_current_block(iter);
5134 if (db)
5135 return db;
5136 }
5137 }
5138
5139 #define cea_db_iter_for_each(__db, __iter) \
5140 while (((__db) = __cea_db_iter_next(__iter)))
5141
cea_db_iter_end(struct cea_db_iter * iter)5142 static void cea_db_iter_end(struct cea_db_iter *iter)
5143 {
5144 displayid_iter_end(&iter->displayid_iter);
5145 drm_edid_iter_end(&iter->edid_iter);
5146
5147 memset(iter, 0, sizeof(*iter));
5148 }
5149
cea_db_is_hdmi_vsdb(const struct cea_db * db)5150 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5151 {
5152 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5153 cea_db_payload_len(db) >= 5;
5154 }
5155
cea_db_is_hdmi_forum_vsdb(const struct cea_db * db)5156 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5157 {
5158 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5159 cea_db_payload_len(db) >= 7;
5160 }
5161
cea_db_is_hdmi_forum_eeodb(const void * db)5162 static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5163 {
5164 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5165 cea_db_payload_len(db) >= 2;
5166 }
5167
cea_db_is_microsoft_vsdb(const struct cea_db * db)5168 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5169 {
5170 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5171 cea_db_payload_len(db) == 21;
5172 }
5173
cea_db_is_vcdb(const struct cea_db * db)5174 static bool cea_db_is_vcdb(const struct cea_db *db)
5175 {
5176 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5177 cea_db_payload_len(db) == 2;
5178 }
5179
cea_db_is_hdmi_forum_scdb(const struct cea_db * db)5180 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5181 {
5182 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5183 cea_db_payload_len(db) >= 7;
5184 }
5185
cea_db_is_y420cmdb(const struct cea_db * db)5186 static bool cea_db_is_y420cmdb(const struct cea_db *db)
5187 {
5188 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5189 }
5190
cea_db_is_y420vdb(const struct cea_db * db)5191 static bool cea_db_is_y420vdb(const struct cea_db *db)
5192 {
5193 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5194 }
5195
cea_db_is_hdmi_hdr_metadata_block(const struct cea_db * db)5196 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5197 {
5198 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5199 cea_db_payload_len(db) >= 3;
5200 }
5201
5202 /*
5203 * Get the HF-EEODB override extension block count from EDID.
5204 *
5205 * The passed in EDID may be partially read, as long as it has at least two
5206 * blocks (base block and one extension block) if EDID extension count is > 0.
5207 *
5208 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5209 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5210 * iterators instead.
5211 *
5212 * References:
5213 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5214 */
edid_hfeeodb_extension_block_count(const struct edid * edid)5215 static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5216 {
5217 const u8 *cta;
5218
5219 /* No extensions according to base block, no HF-EEODB. */
5220 if (!edid_extension_block_count(edid))
5221 return 0;
5222
5223 /* HF-EEODB is always in the first EDID extension block only */
5224 cta = edid_extension_block_data(edid, 0);
5225 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5226 return 0;
5227
5228 /* Need to have the data block collection, and at least 3 bytes. */
5229 if (cea_db_collection_size(cta) < 3)
5230 return 0;
5231
5232 /*
5233 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5234 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5235 * through 6 of Block 1 of the E-EDID.
5236 */
5237 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5238 return 0;
5239
5240 return cta[4 + 2];
5241 }
5242
5243 /*
5244 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5245 *
5246 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5247 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5248 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5249 * support YCBCR420 output too.
5250 */
parse_cta_y420cmdb(struct drm_connector * connector,const struct cea_db * db,u64 * y420cmdb_map)5251 static void parse_cta_y420cmdb(struct drm_connector *connector,
5252 const struct cea_db *db, u64 *y420cmdb_map)
5253 {
5254 struct drm_display_info *info = &connector->display_info;
5255 int i, map_len = cea_db_payload_len(db) - 1;
5256 const u8 *data = cea_db_data(db) + 1;
5257 u64 map = 0;
5258
5259 if (map_len == 0) {
5260 /* All CEA modes support ycbcr420 sampling also.*/
5261 map = U64_MAX;
5262 goto out;
5263 }
5264
5265 /*
5266 * This map indicates which of the existing CEA block modes
5267 * from VDB can support YCBCR420 output too. So if bit=0 is
5268 * set, first mode from VDB can support YCBCR420 output too.
5269 * We will parse and keep this map, before parsing VDB itself
5270 * to avoid going through the same block again and again.
5271 *
5272 * Spec is not clear about max possible size of this block.
5273 * Clamping max bitmap block size at 8 bytes. Every byte can
5274 * address 8 CEA modes, in this way this map can address
5275 * 8*8 = first 64 SVDs.
5276 */
5277 if (WARN_ON_ONCE(map_len > 8))
5278 map_len = 8;
5279
5280 for (i = 0; i < map_len; i++)
5281 map |= (u64)data[i] << (8 * i);
5282
5283 out:
5284 if (map)
5285 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5286
5287 *y420cmdb_map = map;
5288 }
5289
add_cea_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)5290 static int add_cea_modes(struct drm_connector *connector,
5291 const struct drm_edid *drm_edid)
5292 {
5293 const struct cea_db *db;
5294 struct cea_db_iter iter;
5295 int modes;
5296
5297 /* CTA VDB block VICs parsed earlier */
5298 modes = add_cta_vdb_modes(connector);
5299
5300 cea_db_iter_edid_begin(drm_edid, &iter);
5301 cea_db_iter_for_each(db, &iter) {
5302 if (cea_db_is_hdmi_vsdb(db)) {
5303 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5304 cea_db_payload_len(db));
5305 } else if (cea_db_is_y420vdb(db)) {
5306 const u8 *vdb420 = cea_db_data(db) + 1;
5307
5308 /* Add 4:2:0(only) modes present in EDID */
5309 modes += do_y420vdb_modes(connector, vdb420,
5310 cea_db_payload_len(db) - 1);
5311 }
5312 }
5313 cea_db_iter_end(&iter);
5314
5315 return modes;
5316 }
5317
fixup_detailed_cea_mode_clock(struct drm_connector * connector,struct drm_display_mode * mode)5318 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5319 struct drm_display_mode *mode)
5320 {
5321 const struct drm_display_mode *cea_mode;
5322 int clock1, clock2, clock;
5323 u8 vic;
5324 const char *type;
5325
5326 /*
5327 * allow 5kHz clock difference either way to account for
5328 * the 10kHz clock resolution limit of detailed timings.
5329 */
5330 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5331 if (drm_valid_cea_vic(vic)) {
5332 type = "CEA";
5333 cea_mode = cea_mode_for_vic(vic);
5334 clock1 = cea_mode->clock;
5335 clock2 = cea_mode_alternate_clock(cea_mode);
5336 } else {
5337 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5338 if (drm_valid_hdmi_vic(vic)) {
5339 type = "HDMI";
5340 cea_mode = &edid_4k_modes[vic];
5341 clock1 = cea_mode->clock;
5342 clock2 = hdmi_mode_alternate_clock(cea_mode);
5343 } else {
5344 return;
5345 }
5346 }
5347
5348 /* pick whichever is closest */
5349 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5350 clock = clock1;
5351 else
5352 clock = clock2;
5353
5354 if (mode->clock == clock)
5355 return;
5356
5357 drm_dbg_kms(connector->dev,
5358 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5359 connector->base.id, connector->name,
5360 type, vic, mode->clock, clock);
5361 mode->clock = clock;
5362 }
5363
drm_calculate_luminance_range(struct drm_connector * connector)5364 static void drm_calculate_luminance_range(struct drm_connector *connector)
5365 {
5366 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5367 struct drm_luminance_range_info *luminance_range =
5368 &connector->display_info.luminance_range;
5369 static const u8 pre_computed_values[] = {
5370 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5371 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5372 };
5373 u32 max_avg, min_cll, max, min, q, r;
5374
5375 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5376 return;
5377
5378 max_avg = hdr_metadata->max_fall;
5379 min_cll = hdr_metadata->min_cll;
5380
5381 /*
5382 * From the specification (CTA-861-G), for calculating the maximum
5383 * luminance we need to use:
5384 * Luminance = 50*2**(CV/32)
5385 * Where CV is a one-byte value.
5386 * For calculating this expression we may need float point precision;
5387 * to avoid this complexity level, we take advantage that CV is divided
5388 * by a constant. From the Euclids division algorithm, we know that CV
5389 * can be written as: CV = 32*q + r. Next, we replace CV in the
5390 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5391 * need to pre-compute the value of r/32. For pre-computing the values
5392 * We just used the following Ruby line:
5393 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5394 * The results of the above expressions can be verified at
5395 * pre_computed_values.
5396 */
5397 q = max_avg >> 5;
5398 r = max_avg % 32;
5399 max = (1 << q) * pre_computed_values[r];
5400
5401 /* min luminance: maxLum * (CV/255)^2 / 100 */
5402 q = DIV_ROUND_CLOSEST(min_cll, 255);
5403 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5404
5405 luminance_range->min_luminance = min;
5406 luminance_range->max_luminance = max;
5407 }
5408
eotf_supported(const u8 * edid_ext)5409 static uint8_t eotf_supported(const u8 *edid_ext)
5410 {
5411 return edid_ext[2] &
5412 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5413 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5414 BIT(HDMI_EOTF_SMPTE_ST2084) |
5415 BIT(HDMI_EOTF_BT_2100_HLG));
5416 }
5417
hdr_metadata_type(const u8 * edid_ext)5418 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5419 {
5420 return edid_ext[3] &
5421 BIT(HDMI_STATIC_METADATA_TYPE1);
5422 }
5423
5424 static void
drm_parse_hdr_metadata_block(struct drm_connector * connector,const u8 * db)5425 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5426 {
5427 u16 len;
5428
5429 len = cea_db_payload_len(db);
5430
5431 connector->hdr_sink_metadata.hdmi_type1.eotf =
5432 eotf_supported(db);
5433 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5434 hdr_metadata_type(db);
5435
5436 if (len >= 4)
5437 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5438 if (len >= 5)
5439 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5440 if (len >= 6) {
5441 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5442
5443 /* Calculate only when all values are available */
5444 drm_calculate_luminance_range(connector);
5445 }
5446 }
5447
5448 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5449 static void
drm_parse_hdmi_vsdb_audio(struct drm_connector * connector,const u8 * db)5450 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5451 {
5452 u8 len = cea_db_payload_len(db);
5453
5454 if (len >= 6 && (db[6] & (1 << 7)))
5455 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5456
5457 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5458 connector->latency_present[0] = true;
5459 connector->video_latency[0] = db[9];
5460 connector->audio_latency[0] = db[10];
5461 }
5462
5463 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5464 connector->latency_present[1] = true;
5465 connector->video_latency[1] = db[11];
5466 connector->audio_latency[1] = db[12];
5467 }
5468
5469 drm_dbg_kms(connector->dev,
5470 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5471 connector->base.id, connector->name,
5472 connector->latency_present[0], connector->latency_present[1],
5473 connector->video_latency[0], connector->video_latency[1],
5474 connector->audio_latency[0], connector->audio_latency[1]);
5475 }
5476
5477 static void
monitor_name(const struct detailed_timing * timing,void * data)5478 monitor_name(const struct detailed_timing *timing, void *data)
5479 {
5480 const char **res = data;
5481
5482 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5483 return;
5484
5485 *res = timing->data.other_data.data.str.str;
5486 }
5487
get_monitor_name(const struct drm_edid * drm_edid,char name[13])5488 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5489 {
5490 const char *edid_name = NULL;
5491 int mnl;
5492
5493 if (!drm_edid || !name)
5494 return 0;
5495
5496 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5497 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5498 if (edid_name[mnl] == 0x0a)
5499 break;
5500
5501 name[mnl] = edid_name[mnl];
5502 }
5503
5504 return mnl;
5505 }
5506
5507 /**
5508 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5509 * @edid: monitor EDID information
5510 * @name: pointer to a character array to hold the name of the monitor
5511 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5512 *
5513 */
drm_edid_get_monitor_name(const struct edid * edid,char * name,int bufsize)5514 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5515 {
5516 int name_length = 0;
5517
5518 if (bufsize <= 0)
5519 return;
5520
5521 if (edid) {
5522 char buf[13];
5523 struct drm_edid drm_edid = {
5524 .edid = edid,
5525 .size = edid_size(edid),
5526 };
5527
5528 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5529 memcpy(name, buf, name_length);
5530 }
5531
5532 name[name_length] = '\0';
5533 }
5534 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5535
clear_eld(struct drm_connector * connector)5536 static void clear_eld(struct drm_connector *connector)
5537 {
5538 memset(connector->eld, 0, sizeof(connector->eld));
5539
5540 connector->latency_present[0] = false;
5541 connector->latency_present[1] = false;
5542 connector->video_latency[0] = 0;
5543 connector->audio_latency[0] = 0;
5544 connector->video_latency[1] = 0;
5545 connector->audio_latency[1] = 0;
5546 }
5547
5548 /*
5549 * drm_edid_to_eld - build ELD from EDID
5550 * @connector: connector corresponding to the HDMI/DP sink
5551 * @drm_edid: EDID to parse
5552 *
5553 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5554 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5555 */
drm_edid_to_eld(struct drm_connector * connector,const struct drm_edid * drm_edid)5556 static void drm_edid_to_eld(struct drm_connector *connector,
5557 const struct drm_edid *drm_edid)
5558 {
5559 const struct drm_display_info *info = &connector->display_info;
5560 const struct cea_db *db;
5561 struct cea_db_iter iter;
5562 uint8_t *eld = connector->eld;
5563 int total_sad_count = 0;
5564 int mnl;
5565
5566 if (!drm_edid)
5567 return;
5568
5569 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5570 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5571 connector->base.id, connector->name,
5572 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5573
5574 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5575 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5576
5577 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5578
5579 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5580 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5581 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5582 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5583
5584 cea_db_iter_edid_begin(drm_edid, &iter);
5585 cea_db_iter_for_each(db, &iter) {
5586 const u8 *data = cea_db_data(db);
5587 int len = cea_db_payload_len(db);
5588 int sad_count;
5589
5590 switch (cea_db_tag(db)) {
5591 case CTA_DB_AUDIO:
5592 /* Audio Data Block, contains SADs */
5593 sad_count = min(len / 3, 15 - total_sad_count);
5594 if (sad_count >= 1)
5595 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5596 data, sad_count * 3);
5597 total_sad_count += sad_count;
5598 break;
5599 case CTA_DB_SPEAKER:
5600 /* Speaker Allocation Data Block */
5601 if (len >= 1)
5602 eld[DRM_ELD_SPEAKER] = data[0];
5603 break;
5604 case CTA_DB_VENDOR:
5605 /* HDMI Vendor-Specific Data Block */
5606 if (cea_db_is_hdmi_vsdb(db))
5607 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5608 break;
5609 default:
5610 break;
5611 }
5612 }
5613 cea_db_iter_end(&iter);
5614
5615 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5616
5617 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5618 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5619 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5620 else
5621 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5622
5623 eld[DRM_ELD_BASELINE_ELD_LEN] =
5624 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5625
5626 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5627 connector->base.id, connector->name,
5628 drm_eld_size(eld), total_sad_count);
5629 }
5630
_drm_edid_to_sad(const struct drm_edid * drm_edid,struct cea_sad ** sads)5631 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5632 struct cea_sad **sads)
5633 {
5634 const struct cea_db *db;
5635 struct cea_db_iter iter;
5636 int count = 0;
5637
5638 cea_db_iter_edid_begin(drm_edid, &iter);
5639 cea_db_iter_for_each(db, &iter) {
5640 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5641 int j;
5642
5643 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5644 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5645 if (!*sads)
5646 return -ENOMEM;
5647 for (j = 0; j < count; j++) {
5648 const u8 *sad = &db->data[j * 3];
5649
5650 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5651 (*sads)[j].channels = sad[0] & 0x7;
5652 (*sads)[j].freq = sad[1] & 0x7F;
5653 (*sads)[j].byte2 = sad[2];
5654 }
5655 break;
5656 }
5657 }
5658 cea_db_iter_end(&iter);
5659
5660 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5661
5662 return count;
5663 }
5664
5665 /**
5666 * drm_edid_to_sad - extracts SADs from EDID
5667 * @edid: EDID to parse
5668 * @sads: pointer that will be set to the extracted SADs
5669 *
5670 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5671 *
5672 * Note: The returned pointer needs to be freed using kfree().
5673 *
5674 * Return: The number of found SADs or negative number on error.
5675 */
drm_edid_to_sad(const struct edid * edid,struct cea_sad ** sads)5676 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5677 {
5678 struct drm_edid drm_edid;
5679
5680 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5681 }
5682 EXPORT_SYMBOL(drm_edid_to_sad);
5683
_drm_edid_to_speaker_allocation(const struct drm_edid * drm_edid,u8 ** sadb)5684 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5685 u8 **sadb)
5686 {
5687 const struct cea_db *db;
5688 struct cea_db_iter iter;
5689 int count = 0;
5690
5691 cea_db_iter_edid_begin(drm_edid, &iter);
5692 cea_db_iter_for_each(db, &iter) {
5693 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5694 cea_db_payload_len(db) == 3) {
5695 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5696 GFP_KERNEL);
5697 if (!*sadb)
5698 return -ENOMEM;
5699 count = cea_db_payload_len(db);
5700 break;
5701 }
5702 }
5703 cea_db_iter_end(&iter);
5704
5705 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5706
5707 return count;
5708 }
5709
5710 /**
5711 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5712 * @edid: EDID to parse
5713 * @sadb: pointer to the speaker block
5714 *
5715 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5716 *
5717 * Note: The returned pointer needs to be freed using kfree().
5718 *
5719 * Return: The number of found Speaker Allocation Blocks or negative number on
5720 * error.
5721 */
drm_edid_to_speaker_allocation(const struct edid * edid,u8 ** sadb)5722 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5723 {
5724 struct drm_edid drm_edid;
5725
5726 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5727 sadb);
5728 }
5729 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5730
5731 /**
5732 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5733 * @connector: connector associated with the HDMI/DP sink
5734 * @mode: the display mode
5735 *
5736 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5737 * the sink doesn't support audio or video.
5738 */
drm_av_sync_delay(struct drm_connector * connector,const struct drm_display_mode * mode)5739 int drm_av_sync_delay(struct drm_connector *connector,
5740 const struct drm_display_mode *mode)
5741 {
5742 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5743 int a, v;
5744
5745 if (!connector->latency_present[0])
5746 return 0;
5747 if (!connector->latency_present[1])
5748 i = 0;
5749
5750 a = connector->audio_latency[i];
5751 v = connector->video_latency[i];
5752
5753 /*
5754 * HDMI/DP sink doesn't support audio or video?
5755 */
5756 if (a == 255 || v == 255)
5757 return 0;
5758
5759 /*
5760 * Convert raw EDID values to millisecond.
5761 * Treat unknown latency as 0ms.
5762 */
5763 if (a)
5764 a = min(2 * (a - 1), 500);
5765 if (v)
5766 v = min(2 * (v - 1), 500);
5767
5768 return max(v - a, 0);
5769 }
5770 EXPORT_SYMBOL(drm_av_sync_delay);
5771
_drm_detect_hdmi_monitor(const struct drm_edid * drm_edid)5772 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5773 {
5774 const struct cea_db *db;
5775 struct cea_db_iter iter;
5776 bool hdmi = false;
5777
5778 /*
5779 * Because HDMI identifier is in Vendor Specific Block,
5780 * search it from all data blocks of CEA extension.
5781 */
5782 cea_db_iter_edid_begin(drm_edid, &iter);
5783 cea_db_iter_for_each(db, &iter) {
5784 if (cea_db_is_hdmi_vsdb(db)) {
5785 hdmi = true;
5786 break;
5787 }
5788 }
5789 cea_db_iter_end(&iter);
5790
5791 return hdmi;
5792 }
5793
5794 /**
5795 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5796 * @edid: monitor EDID information
5797 *
5798 * Parse the CEA extension according to CEA-861-B.
5799 *
5800 * Drivers that have added the modes parsed from EDID to drm_display_info
5801 * should use &drm_display_info.is_hdmi instead of calling this function.
5802 *
5803 * Return: True if the monitor is HDMI, false if not or unknown.
5804 */
drm_detect_hdmi_monitor(const struct edid * edid)5805 bool drm_detect_hdmi_monitor(const struct edid *edid)
5806 {
5807 struct drm_edid drm_edid;
5808
5809 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5810 }
5811 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5812
_drm_detect_monitor_audio(const struct drm_edid * drm_edid)5813 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5814 {
5815 struct drm_edid_iter edid_iter;
5816 const struct cea_db *db;
5817 struct cea_db_iter iter;
5818 const u8 *edid_ext;
5819 bool has_audio = false;
5820
5821 drm_edid_iter_begin(drm_edid, &edid_iter);
5822 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5823 if (edid_ext[0] == CEA_EXT) {
5824 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5825 if (has_audio)
5826 break;
5827 }
5828 }
5829 drm_edid_iter_end(&edid_iter);
5830
5831 if (has_audio) {
5832 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5833 goto end;
5834 }
5835
5836 cea_db_iter_edid_begin(drm_edid, &iter);
5837 cea_db_iter_for_each(db, &iter) {
5838 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5839 const u8 *data = cea_db_data(db);
5840 int i;
5841
5842 for (i = 0; i < cea_db_payload_len(db); i += 3)
5843 DRM_DEBUG_KMS("CEA audio format %d\n",
5844 (data[i] >> 3) & 0xf);
5845 has_audio = true;
5846 break;
5847 }
5848 }
5849 cea_db_iter_end(&iter);
5850
5851 end:
5852 return has_audio;
5853 }
5854
5855 /**
5856 * drm_detect_monitor_audio - check monitor audio capability
5857 * @edid: EDID block to scan
5858 *
5859 * Monitor should have CEA extension block.
5860 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5861 * audio' only. If there is any audio extension block and supported
5862 * audio format, assume at least 'basic audio' support, even if 'basic
5863 * audio' is not defined in EDID.
5864 *
5865 * Return: True if the monitor supports audio, false otherwise.
5866 */
drm_detect_monitor_audio(const struct edid * edid)5867 bool drm_detect_monitor_audio(const struct edid *edid)
5868 {
5869 struct drm_edid drm_edid;
5870
5871 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5872 }
5873 EXPORT_SYMBOL(drm_detect_monitor_audio);
5874
5875
5876 /**
5877 * drm_default_rgb_quant_range - default RGB quantization range
5878 * @mode: display mode
5879 *
5880 * Determine the default RGB quantization range for the mode,
5881 * as specified in CEA-861.
5882 *
5883 * Return: The default RGB quantization range for the mode
5884 */
5885 enum hdmi_quantization_range
drm_default_rgb_quant_range(const struct drm_display_mode * mode)5886 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5887 {
5888 /* All CEA modes other than VIC 1 use limited quantization range. */
5889 return drm_match_cea_mode(mode) > 1 ?
5890 HDMI_QUANTIZATION_RANGE_LIMITED :
5891 HDMI_QUANTIZATION_RANGE_FULL;
5892 }
5893 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5894
5895 /* CTA-861 Video Data Block (CTA VDB) */
parse_cta_vdb(struct drm_connector * connector,const struct cea_db * db)5896 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5897 {
5898 struct drm_display_info *info = &connector->display_info;
5899 int i, vic_index, len = cea_db_payload_len(db);
5900 const u8 *svds = cea_db_data(db);
5901 u8 *vics;
5902
5903 if (!len)
5904 return;
5905
5906 /* Gracefully handle multiple VDBs, however unlikely that is */
5907 #ifdef __linux__
5908 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
5909 if (!vics)
5910 return;
5911 #else
5912 vics = kmalloc(info->vics_len + len, GFP_KERNEL);
5913 if (!vics)
5914 return;
5915 memcpy(vics, info->vics, info->vics_len);
5916 kfree(info->vics);
5917 #endif
5918
5919 vic_index = info->vics_len;
5920 info->vics_len += len;
5921 info->vics = vics;
5922
5923 for (i = 0; i < len; i++) {
5924 u8 vic = svd_to_vic(svds[i]);
5925
5926 if (!drm_valid_cea_vic(vic))
5927 vic = 0;
5928
5929 info->vics[vic_index++] = vic;
5930 }
5931 }
5932
5933 /*
5934 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
5935 *
5936 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
5937 * using the VICs themselves.
5938 */
update_cta_y420cmdb(struct drm_connector * connector,u64 y420cmdb_map)5939 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
5940 {
5941 struct drm_display_info *info = &connector->display_info;
5942 struct drm_hdmi_info *hdmi = &info->hdmi;
5943 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
5944
5945 for (i = 0; i < len; i++) {
5946 u8 vic = info->vics[i];
5947
5948 if (vic && y420cmdb_map & BIT_ULL(i))
5949 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
5950 }
5951 }
5952
cta_vdb_has_vic(const struct drm_connector * connector,u8 vic)5953 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
5954 {
5955 const struct drm_display_info *info = &connector->display_info;
5956 int i;
5957
5958 if (!vic || !info->vics)
5959 return false;
5960
5961 for (i = 0; i < info->vics_len; i++) {
5962 if (info->vics[i] == vic)
5963 return true;
5964 }
5965
5966 return false;
5967 }
5968
5969 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
parse_cta_y420vdb(struct drm_connector * connector,const struct cea_db * db)5970 static void parse_cta_y420vdb(struct drm_connector *connector,
5971 const struct cea_db *db)
5972 {
5973 struct drm_display_info *info = &connector->display_info;
5974 struct drm_hdmi_info *hdmi = &info->hdmi;
5975 const u8 *svds = cea_db_data(db) + 1;
5976 int i;
5977
5978 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
5979 u8 vic = svd_to_vic(svds[i]);
5980
5981 if (!drm_valid_cea_vic(vic))
5982 continue;
5983
5984 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
5985 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5986 }
5987 }
5988
drm_parse_vcdb(struct drm_connector * connector,const u8 * db)5989 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5990 {
5991 struct drm_display_info *info = &connector->display_info;
5992
5993 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
5994 connector->base.id, connector->name, db[2]);
5995
5996 if (db[2] & EDID_CEA_VCDB_QS)
5997 info->rgb_quant_range_selectable = true;
5998 }
5999
6000 static
drm_get_max_frl_rate(int max_frl_rate,u8 * max_lanes,u8 * max_rate_per_lane)6001 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
6002 {
6003 switch (max_frl_rate) {
6004 case 1:
6005 *max_lanes = 3;
6006 *max_rate_per_lane = 3;
6007 break;
6008 case 2:
6009 *max_lanes = 3;
6010 *max_rate_per_lane = 6;
6011 break;
6012 case 3:
6013 *max_lanes = 4;
6014 *max_rate_per_lane = 6;
6015 break;
6016 case 4:
6017 *max_lanes = 4;
6018 *max_rate_per_lane = 8;
6019 break;
6020 case 5:
6021 *max_lanes = 4;
6022 *max_rate_per_lane = 10;
6023 break;
6024 case 6:
6025 *max_lanes = 4;
6026 *max_rate_per_lane = 12;
6027 break;
6028 case 0:
6029 default:
6030 *max_lanes = 0;
6031 *max_rate_per_lane = 0;
6032 }
6033 }
6034
drm_parse_ycbcr420_deep_color_info(struct drm_connector * connector,const u8 * db)6035 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
6036 const u8 *db)
6037 {
6038 u8 dc_mask;
6039 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
6040
6041 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
6042 hdmi->y420_dc_modes = dc_mask;
6043 }
6044
drm_parse_dsc_info(struct drm_hdmi_dsc_cap * hdmi_dsc,const u8 * hf_scds)6045 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6046 const u8 *hf_scds)
6047 {
6048 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6049
6050 if (!hdmi_dsc->v_1p2)
6051 return;
6052
6053 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6054 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6055
6056 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6057 hdmi_dsc->bpc_supported = 16;
6058 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6059 hdmi_dsc->bpc_supported = 12;
6060 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6061 hdmi_dsc->bpc_supported = 10;
6062 else
6063 /* Supports min 8 BPC if DSC 1.2 is supported*/
6064 hdmi_dsc->bpc_supported = 8;
6065
6066 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6067 u8 dsc_max_slices;
6068 u8 dsc_max_frl_rate;
6069
6070 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6071 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6072 &hdmi_dsc->max_frl_rate_per_lane);
6073
6074 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6075
6076 switch (dsc_max_slices) {
6077 case 1:
6078 hdmi_dsc->max_slices = 1;
6079 hdmi_dsc->clk_per_slice = 340;
6080 break;
6081 case 2:
6082 hdmi_dsc->max_slices = 2;
6083 hdmi_dsc->clk_per_slice = 340;
6084 break;
6085 case 3:
6086 hdmi_dsc->max_slices = 4;
6087 hdmi_dsc->clk_per_slice = 340;
6088 break;
6089 case 4:
6090 hdmi_dsc->max_slices = 8;
6091 hdmi_dsc->clk_per_slice = 340;
6092 break;
6093 case 5:
6094 hdmi_dsc->max_slices = 8;
6095 hdmi_dsc->clk_per_slice = 400;
6096 break;
6097 case 6:
6098 hdmi_dsc->max_slices = 12;
6099 hdmi_dsc->clk_per_slice = 400;
6100 break;
6101 case 7:
6102 hdmi_dsc->max_slices = 16;
6103 hdmi_dsc->clk_per_slice = 400;
6104 break;
6105 case 0:
6106 default:
6107 hdmi_dsc->max_slices = 0;
6108 hdmi_dsc->clk_per_slice = 0;
6109 }
6110 }
6111
6112 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6113 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6114 }
6115
6116 /* Sink Capability Data Structure */
drm_parse_hdmi_forum_scds(struct drm_connector * connector,const u8 * hf_scds)6117 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6118 const u8 *hf_scds)
6119 {
6120 struct drm_display_info *info = &connector->display_info;
6121 struct drm_hdmi_info *hdmi = &info->hdmi;
6122 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6123 int max_tmds_clock = 0;
6124 u8 max_frl_rate = 0;
6125 bool dsc_support = false;
6126
6127 info->has_hdmi_infoframe = true;
6128
6129 if (hf_scds[6] & 0x80) {
6130 hdmi->scdc.supported = true;
6131 if (hf_scds[6] & 0x40)
6132 hdmi->scdc.read_request = true;
6133 }
6134
6135 /*
6136 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6137 * And as per the spec, three factors confirm this:
6138 * * Availability of a HF-VSDB block in EDID (check)
6139 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6140 * * SCDC support available (let's check)
6141 * Lets check it out.
6142 */
6143
6144 if (hf_scds[5]) {
6145 struct drm_scdc *scdc = &hdmi->scdc;
6146
6147 /* max clock is 5000 KHz times block value */
6148 max_tmds_clock = hf_scds[5] * 5000;
6149
6150 if (max_tmds_clock > 340000) {
6151 info->max_tmds_clock = max_tmds_clock;
6152 }
6153
6154 if (scdc->supported) {
6155 scdc->scrambling.supported = true;
6156
6157 /* Few sinks support scrambling for clocks < 340M */
6158 if ((hf_scds[6] & 0x8))
6159 scdc->scrambling.low_rates = true;
6160 }
6161 }
6162
6163 if (hf_scds[7]) {
6164 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6165 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6166 &hdmi->max_frl_rate_per_lane);
6167 }
6168
6169 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6170
6171 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6172 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6173 dsc_support = true;
6174 }
6175
6176 drm_dbg_kms(connector->dev,
6177 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6178 connector->base.id, connector->name,
6179 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6180 }
6181
drm_parse_hdmi_deep_color_info(struct drm_connector * connector,const u8 * hdmi)6182 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6183 const u8 *hdmi)
6184 {
6185 struct drm_display_info *info = &connector->display_info;
6186 unsigned int dc_bpc = 0;
6187
6188 /* HDMI supports at least 8 bpc */
6189 info->bpc = 8;
6190
6191 if (cea_db_payload_len(hdmi) < 6)
6192 return;
6193
6194 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6195 dc_bpc = 10;
6196 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6197 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6198 connector->base.id, connector->name);
6199 }
6200
6201 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6202 dc_bpc = 12;
6203 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6204 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6205 connector->base.id, connector->name);
6206 }
6207
6208 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6209 dc_bpc = 16;
6210 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6211 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6212 connector->base.id, connector->name);
6213 }
6214
6215 if (dc_bpc == 0) {
6216 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6217 connector->base.id, connector->name);
6218 return;
6219 }
6220
6221 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6222 connector->base.id, connector->name, dc_bpc);
6223 info->bpc = dc_bpc;
6224
6225 /* YCRCB444 is optional according to spec. */
6226 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6227 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6228 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6229 connector->base.id, connector->name);
6230 }
6231
6232 /*
6233 * Spec says that if any deep color mode is supported at all,
6234 * then deep color 36 bit must be supported.
6235 */
6236 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6237 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6238 connector->base.id, connector->name);
6239 }
6240 }
6241
6242 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6243 static void
drm_parse_hdmi_vsdb_video(struct drm_connector * connector,const u8 * db)6244 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6245 {
6246 struct drm_display_info *info = &connector->display_info;
6247 u8 len = cea_db_payload_len(db);
6248
6249 info->is_hdmi = true;
6250
6251 if (len >= 6)
6252 info->dvi_dual = db[6] & 1;
6253 if (len >= 7)
6254 info->max_tmds_clock = db[7] * 5000;
6255
6256 /*
6257 * Try to infer whether the sink supports HDMI infoframes.
6258 *
6259 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6260 * supports infoframes if HDMI_Video_present is set.
6261 */
6262 if (len >= 8 && db[8] & BIT(5))
6263 info->has_hdmi_infoframe = true;
6264
6265 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6266 connector->base.id, connector->name,
6267 info->dvi_dual, info->max_tmds_clock);
6268
6269 drm_parse_hdmi_deep_color_info(connector, db);
6270 }
6271
6272 /*
6273 * See EDID extension for head-mounted and specialized monitors, specified at:
6274 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6275 */
drm_parse_microsoft_vsdb(struct drm_connector * connector,const u8 * db)6276 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6277 const u8 *db)
6278 {
6279 struct drm_display_info *info = &connector->display_info;
6280 u8 version = db[4];
6281 bool desktop_usage = db[5] & BIT(6);
6282
6283 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6284 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6285 info->non_desktop = true;
6286
6287 drm_dbg_kms(connector->dev,
6288 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6289 connector->base.id, connector->name, version, db[5]);
6290 }
6291
drm_parse_cea_ext(struct drm_connector * connector,const struct drm_edid * drm_edid)6292 static void drm_parse_cea_ext(struct drm_connector *connector,
6293 const struct drm_edid *drm_edid)
6294 {
6295 struct drm_display_info *info = &connector->display_info;
6296 struct drm_edid_iter edid_iter;
6297 const struct cea_db *db;
6298 struct cea_db_iter iter;
6299 const u8 *edid_ext;
6300 u64 y420cmdb_map = 0;
6301
6302 drm_edid_iter_begin(drm_edid, &edid_iter);
6303 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6304 if (edid_ext[0] != CEA_EXT)
6305 continue;
6306
6307 if (!info->cea_rev)
6308 info->cea_rev = edid_ext[1];
6309
6310 if (info->cea_rev != edid_ext[1])
6311 drm_dbg_kms(connector->dev,
6312 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6313 connector->base.id, connector->name,
6314 info->cea_rev, edid_ext[1]);
6315
6316 /* The existence of a CTA extension should imply RGB support */
6317 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6318 if (edid_ext[3] & EDID_CEA_YCRCB444)
6319 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6320 if (edid_ext[3] & EDID_CEA_YCRCB422)
6321 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6322 if (edid_ext[3] & EDID_BASIC_AUDIO)
6323 info->has_audio = true;
6324
6325 }
6326 drm_edid_iter_end(&edid_iter);
6327
6328 cea_db_iter_edid_begin(drm_edid, &iter);
6329 cea_db_iter_for_each(db, &iter) {
6330 /* FIXME: convert parsers to use struct cea_db */
6331 const u8 *data = (const u8 *)db;
6332
6333 if (cea_db_is_hdmi_vsdb(db))
6334 drm_parse_hdmi_vsdb_video(connector, data);
6335 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6336 cea_db_is_hdmi_forum_scdb(db))
6337 drm_parse_hdmi_forum_scds(connector, data);
6338 else if (cea_db_is_microsoft_vsdb(db))
6339 drm_parse_microsoft_vsdb(connector, data);
6340 else if (cea_db_is_y420cmdb(db))
6341 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6342 else if (cea_db_is_y420vdb(db))
6343 parse_cta_y420vdb(connector, db);
6344 else if (cea_db_is_vcdb(db))
6345 drm_parse_vcdb(connector, data);
6346 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6347 drm_parse_hdr_metadata_block(connector, data);
6348 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6349 parse_cta_vdb(connector, db);
6350 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6351 info->has_audio = true;
6352 }
6353 cea_db_iter_end(&iter);
6354
6355 if (y420cmdb_map)
6356 update_cta_y420cmdb(connector, y420cmdb_map);
6357 }
6358
6359 static
get_monitor_range(const struct detailed_timing * timing,void * c)6360 void get_monitor_range(const struct detailed_timing *timing, void *c)
6361 {
6362 struct detailed_mode_closure *closure = c;
6363 struct drm_display_info *info = &closure->connector->display_info;
6364 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6365 const struct detailed_non_pixel *data = &timing->data.other_data;
6366 const struct detailed_data_monitor_range *range = &data->data.range;
6367 const struct edid *edid = closure->drm_edid->edid;
6368
6369 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6370 return;
6371
6372 /*
6373 * These limits are used to determine the VRR refresh
6374 * rate range. Only the "range limits only" variant
6375 * of the range descriptor seems to guarantee that
6376 * any and all timings are accepted by the sink, as
6377 * opposed to just timings conforming to the indicated
6378 * formula (GTF/GTF2/CVT). Thus other variants of the
6379 * range descriptor are not accepted here.
6380 */
6381 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6382 return;
6383
6384 monitor_range->min_vfreq = range->min_vfreq;
6385 monitor_range->max_vfreq = range->max_vfreq;
6386
6387 if (edid->revision >= 4) {
6388 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6389 monitor_range->min_vfreq += 255;
6390 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6391 monitor_range->max_vfreq += 255;
6392 }
6393 }
6394
drm_get_monitor_range(struct drm_connector * connector,const struct drm_edid * drm_edid)6395 static void drm_get_monitor_range(struct drm_connector *connector,
6396 const struct drm_edid *drm_edid)
6397 {
6398 const struct drm_display_info *info = &connector->display_info;
6399 struct detailed_mode_closure closure = {
6400 .connector = connector,
6401 .drm_edid = drm_edid,
6402 };
6403
6404 if (drm_edid->edid->revision < 4)
6405 return;
6406
6407 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6408 return;
6409
6410 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6411
6412 drm_dbg_kms(connector->dev,
6413 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6414 connector->base.id, connector->name,
6415 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6416 }
6417
drm_parse_vesa_mso_data(struct drm_connector * connector,const struct displayid_block * block)6418 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6419 const struct displayid_block *block)
6420 {
6421 struct displayid_vesa_vendor_specific_block *vesa =
6422 (struct displayid_vesa_vendor_specific_block *)block;
6423 struct drm_display_info *info = &connector->display_info;
6424
6425 if (block->num_bytes < 3) {
6426 drm_dbg_kms(connector->dev,
6427 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6428 connector->base.id, connector->name, block->num_bytes);
6429 return;
6430 }
6431
6432 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6433 return;
6434
6435 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6436 drm_dbg_kms(connector->dev,
6437 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6438 connector->base.id, connector->name);
6439 return;
6440 }
6441
6442 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6443 default:
6444 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6445 connector->base.id, connector->name);
6446 fallthrough;
6447 case 0:
6448 info->mso_stream_count = 0;
6449 break;
6450 case 1:
6451 info->mso_stream_count = 2; /* 2 or 4 links */
6452 break;
6453 case 2:
6454 info->mso_stream_count = 4; /* 4 links */
6455 break;
6456 }
6457
6458 if (!info->mso_stream_count) {
6459 info->mso_pixel_overlap = 0;
6460 return;
6461 }
6462
6463 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6464 if (info->mso_pixel_overlap > 8) {
6465 drm_dbg_kms(connector->dev,
6466 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6467 connector->base.id, connector->name,
6468 info->mso_pixel_overlap);
6469 info->mso_pixel_overlap = 8;
6470 }
6471
6472 drm_dbg_kms(connector->dev,
6473 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6474 connector->base.id, connector->name,
6475 info->mso_stream_count, info->mso_pixel_overlap);
6476 }
6477
drm_update_mso(struct drm_connector * connector,const struct drm_edid * drm_edid)6478 static void drm_update_mso(struct drm_connector *connector,
6479 const struct drm_edid *drm_edid)
6480 {
6481 const struct displayid_block *block;
6482 struct displayid_iter iter;
6483
6484 displayid_iter_edid_begin(drm_edid, &iter);
6485 displayid_iter_for_each(block, &iter) {
6486 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6487 drm_parse_vesa_mso_data(connector, block);
6488 }
6489 displayid_iter_end(&iter);
6490 }
6491
6492 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6493 * all of the values which would have been set from EDID
6494 */
drm_reset_display_info(struct drm_connector * connector)6495 static void drm_reset_display_info(struct drm_connector *connector)
6496 {
6497 struct drm_display_info *info = &connector->display_info;
6498
6499 info->width_mm = 0;
6500 info->height_mm = 0;
6501
6502 info->bpc = 0;
6503 info->color_formats = 0;
6504 info->cea_rev = 0;
6505 info->max_tmds_clock = 0;
6506 info->dvi_dual = false;
6507 info->is_hdmi = false;
6508 info->has_audio = false;
6509 info->has_hdmi_infoframe = false;
6510 info->rgb_quant_range_selectable = false;
6511 memset(&info->hdmi, 0, sizeof(info->hdmi));
6512
6513 info->edid_hdmi_rgb444_dc_modes = 0;
6514 info->edid_hdmi_ycbcr444_dc_modes = 0;
6515
6516 info->non_desktop = 0;
6517 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6518 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6519
6520 info->mso_stream_count = 0;
6521 info->mso_pixel_overlap = 0;
6522 info->max_dsc_bpp = 0;
6523
6524 kfree(info->vics);
6525 info->vics = NULL;
6526 info->vics_len = 0;
6527
6528 info->quirks = 0;
6529 }
6530
update_displayid_info(struct drm_connector * connector,const struct drm_edid * drm_edid)6531 static void update_displayid_info(struct drm_connector *connector,
6532 const struct drm_edid *drm_edid)
6533 {
6534 struct drm_display_info *info = &connector->display_info;
6535 const struct displayid_block *block;
6536 struct displayid_iter iter;
6537
6538 displayid_iter_edid_begin(drm_edid, &iter);
6539 displayid_iter_for_each(block, &iter) {
6540 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6541 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6542 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6543 info->non_desktop = true;
6544
6545 /*
6546 * We're only interested in the base section here, no need to
6547 * iterate further.
6548 */
6549 break;
6550 }
6551 displayid_iter_end(&iter);
6552 }
6553
update_display_info(struct drm_connector * connector,const struct drm_edid * drm_edid)6554 static void update_display_info(struct drm_connector *connector,
6555 const struct drm_edid *drm_edid)
6556 {
6557 struct drm_display_info *info = &connector->display_info;
6558 const struct edid *edid;
6559
6560 drm_reset_display_info(connector);
6561 clear_eld(connector);
6562
6563 if (!drm_edid)
6564 return;
6565
6566 edid = drm_edid->edid;
6567
6568 info->quirks = edid_get_quirks(drm_edid);
6569
6570 info->width_mm = edid->width_cm * 10;
6571 info->height_mm = edid->height_cm * 10;
6572
6573 drm_get_monitor_range(connector, drm_edid);
6574
6575 if (edid->revision < 3)
6576 goto out;
6577
6578 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
6579 goto out;
6580
6581 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6582 drm_parse_cea_ext(connector, drm_edid);
6583
6584 update_displayid_info(connector, drm_edid);
6585
6586 /*
6587 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6588 *
6589 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6590 * tells us to assume 8 bpc color depth if the EDID doesn't have
6591 * extensions which tell otherwise.
6592 */
6593 if (info->bpc == 0 && edid->revision == 3 &&
6594 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6595 info->bpc = 8;
6596 drm_dbg_kms(connector->dev,
6597 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6598 connector->base.id, connector->name, info->bpc);
6599 }
6600
6601 /* Only defined for 1.4 with digital displays */
6602 if (edid->revision < 4)
6603 goto out;
6604
6605 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6606 case DRM_EDID_DIGITAL_DEPTH_6:
6607 info->bpc = 6;
6608 break;
6609 case DRM_EDID_DIGITAL_DEPTH_8:
6610 info->bpc = 8;
6611 break;
6612 case DRM_EDID_DIGITAL_DEPTH_10:
6613 info->bpc = 10;
6614 break;
6615 case DRM_EDID_DIGITAL_DEPTH_12:
6616 info->bpc = 12;
6617 break;
6618 case DRM_EDID_DIGITAL_DEPTH_14:
6619 info->bpc = 14;
6620 break;
6621 case DRM_EDID_DIGITAL_DEPTH_16:
6622 info->bpc = 16;
6623 break;
6624 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6625 default:
6626 info->bpc = 0;
6627 break;
6628 }
6629
6630 drm_dbg_kms(connector->dev,
6631 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6632 connector->base.id, connector->name, info->bpc);
6633
6634 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6635 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6636 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6637 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6638
6639 drm_update_mso(connector, drm_edid);
6640
6641 out:
6642 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
6643 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6644 connector->base.id, connector->name,
6645 info->non_desktop ? " (redundant quirk)" : "");
6646 info->non_desktop = true;
6647 }
6648
6649 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
6650 info->max_dsc_bpp = 15;
6651
6652 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6653 info->bpc = 6;
6654
6655 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6656 info->bpc = 8;
6657
6658 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6659 info->bpc = 10;
6660
6661 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6662 info->bpc = 12;
6663
6664 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6665 drm_edid_to_eld(connector, drm_edid);
6666 }
6667
drm_mode_displayid_detailed(struct drm_device * dev,struct displayid_detailed_timings_1 * timings,bool type_7)6668 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6669 struct displayid_detailed_timings_1 *timings,
6670 bool type_7)
6671 {
6672 struct drm_display_mode *mode;
6673 unsigned pixel_clock = (timings->pixel_clock[0] |
6674 (timings->pixel_clock[1] << 8) |
6675 (timings->pixel_clock[2] << 16)) + 1;
6676 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6677 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6678 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6679 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6680 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6681 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6682 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6683 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6684 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6685 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6686
6687 mode = drm_mode_create(dev);
6688 if (!mode)
6689 return NULL;
6690
6691 /* resolution is kHz for type VII, and 10 kHz for type I */
6692 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6693 mode->hdisplay = hactive;
6694 mode->hsync_start = mode->hdisplay + hsync;
6695 mode->hsync_end = mode->hsync_start + hsync_width;
6696 mode->htotal = mode->hdisplay + hblank;
6697
6698 mode->vdisplay = vactive;
6699 mode->vsync_start = mode->vdisplay + vsync;
6700 mode->vsync_end = mode->vsync_start + vsync_width;
6701 mode->vtotal = mode->vdisplay + vblank;
6702
6703 mode->flags = 0;
6704 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6705 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6706 mode->type = DRM_MODE_TYPE_DRIVER;
6707
6708 if (timings->flags & 0x80)
6709 mode->type |= DRM_MODE_TYPE_PREFERRED;
6710 drm_mode_set_name(mode);
6711
6712 return mode;
6713 }
6714
add_displayid_detailed_1_modes(struct drm_connector * connector,const struct displayid_block * block)6715 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6716 const struct displayid_block *block)
6717 {
6718 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6719 int i;
6720 int num_timings;
6721 struct drm_display_mode *newmode;
6722 int num_modes = 0;
6723 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6724 /* blocks must be multiple of 20 bytes length */
6725 if (block->num_bytes % 20)
6726 return 0;
6727
6728 num_timings = block->num_bytes / 20;
6729 for (i = 0; i < num_timings; i++) {
6730 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6731
6732 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6733 if (!newmode)
6734 continue;
6735
6736 drm_mode_probed_add(connector, newmode);
6737 num_modes++;
6738 }
6739 return num_modes;
6740 }
6741
add_displayid_detailed_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)6742 static int add_displayid_detailed_modes(struct drm_connector *connector,
6743 const struct drm_edid *drm_edid)
6744 {
6745 const struct displayid_block *block;
6746 struct displayid_iter iter;
6747 int num_modes = 0;
6748
6749 displayid_iter_edid_begin(drm_edid, &iter);
6750 displayid_iter_for_each(block, &iter) {
6751 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6752 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6753 num_modes += add_displayid_detailed_1_modes(connector, block);
6754 }
6755 displayid_iter_end(&iter);
6756
6757 return num_modes;
6758 }
6759
_drm_edid_connector_add_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)6760 static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6761 const struct drm_edid *drm_edid)
6762 {
6763 const struct drm_display_info *info = &connector->display_info;
6764 int num_modes = 0;
6765
6766 if (!drm_edid)
6767 return 0;
6768
6769 /*
6770 * EDID spec says modes should be preferred in this order:
6771 * - preferred detailed mode
6772 * - other detailed modes from base block
6773 * - detailed modes from extension blocks
6774 * - CVT 3-byte code modes
6775 * - standard timing codes
6776 * - established timing codes
6777 * - modes inferred from GTF or CVT range information
6778 *
6779 * We get this pretty much right.
6780 *
6781 * XXX order for additional mode types in extension blocks?
6782 */
6783 num_modes += add_detailed_modes(connector, drm_edid);
6784 num_modes += add_cvt_modes(connector, drm_edid);
6785 num_modes += add_standard_modes(connector, drm_edid);
6786 num_modes += add_established_modes(connector, drm_edid);
6787 num_modes += add_cea_modes(connector, drm_edid);
6788 num_modes += add_alternate_cea_modes(connector, drm_edid);
6789 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6790 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6791 num_modes += add_inferred_modes(connector, drm_edid);
6792
6793 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6794 edid_fixup_preferred(connector);
6795
6796 return num_modes;
6797 }
6798
6799 static void _drm_update_tile_info(struct drm_connector *connector,
6800 const struct drm_edid *drm_edid);
6801
_drm_edid_connector_property_update(struct drm_connector * connector,const struct drm_edid * drm_edid)6802 static int _drm_edid_connector_property_update(struct drm_connector *connector,
6803 const struct drm_edid *drm_edid)
6804 {
6805 struct drm_device *dev = connector->dev;
6806 int ret;
6807
6808 if (connector->edid_blob_ptr) {
6809 const struct edid *old_edid = connector->edid_blob_ptr->data;
6810
6811 if (old_edid) {
6812 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6813 connector->epoch_counter++;
6814 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6815 connector->base.id, connector->name,
6816 connector->epoch_counter);
6817 }
6818 }
6819 }
6820
6821 ret = drm_property_replace_global_blob(dev,
6822 &connector->edid_blob_ptr,
6823 drm_edid ? drm_edid->size : 0,
6824 drm_edid ? drm_edid->edid : NULL,
6825 &connector->base,
6826 dev->mode_config.edid_property);
6827 if (ret) {
6828 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6829 connector->base.id, connector->name, ret);
6830 goto out;
6831 }
6832
6833 ret = drm_object_property_set_value(&connector->base,
6834 dev->mode_config.non_desktop_property,
6835 connector->display_info.non_desktop);
6836 if (ret) {
6837 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6838 connector->base.id, connector->name, ret);
6839 goto out;
6840 }
6841
6842 ret = drm_connector_set_tile_property(connector);
6843 if (ret) {
6844 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6845 connector->base.id, connector->name, ret);
6846 goto out;
6847 }
6848
6849 out:
6850 return ret;
6851 }
6852
6853 /**
6854 * drm_edid_connector_update - Update connector information from EDID
6855 * @connector: Connector
6856 * @drm_edid: EDID
6857 *
6858 * Update the connector display info, ELD, HDR metadata, relevant properties,
6859 * etc. from the passed in EDID.
6860 *
6861 * If EDID is NULL, reset the information.
6862 *
6863 * Must be called before calling drm_edid_connector_add_modes().
6864 *
6865 * Return: 0 on success, negative error on errors.
6866 */
drm_edid_connector_update(struct drm_connector * connector,const struct drm_edid * drm_edid)6867 int drm_edid_connector_update(struct drm_connector *connector,
6868 const struct drm_edid *drm_edid)
6869 {
6870 update_display_info(connector, drm_edid);
6871
6872 _drm_update_tile_info(connector, drm_edid);
6873
6874 return _drm_edid_connector_property_update(connector, drm_edid);
6875 }
6876 EXPORT_SYMBOL(drm_edid_connector_update);
6877
6878 /**
6879 * drm_edid_connector_add_modes - Update probed modes from the EDID property
6880 * @connector: Connector
6881 *
6882 * Add the modes from the previously updated EDID property to the connector
6883 * probed modes list.
6884 *
6885 * drm_edid_connector_update() must have been called before this to update the
6886 * EDID property.
6887 *
6888 * Return: The number of modes added, or 0 if we couldn't find any.
6889 */
drm_edid_connector_add_modes(struct drm_connector * connector)6890 int drm_edid_connector_add_modes(struct drm_connector *connector)
6891 {
6892 const struct drm_edid *drm_edid = NULL;
6893 int count;
6894
6895 if (connector->edid_blob_ptr)
6896 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
6897 connector->edid_blob_ptr->length);
6898
6899 count = _drm_edid_connector_add_modes(connector, drm_edid);
6900
6901 drm_edid_free(drm_edid);
6902
6903 return count;
6904 }
6905 EXPORT_SYMBOL(drm_edid_connector_add_modes);
6906
6907 /**
6908 * drm_connector_update_edid_property - update the edid property of a connector
6909 * @connector: drm connector
6910 * @edid: new value of the edid property
6911 *
6912 * This function creates a new blob modeset object and assigns its id to the
6913 * connector's edid property.
6914 * Since we also parse tile information from EDID's displayID block, we also
6915 * set the connector's tile property here. See drm_connector_set_tile_property()
6916 * for more details.
6917 *
6918 * This function is deprecated. Use drm_edid_connector_update() instead.
6919 *
6920 * Returns:
6921 * Zero on success, negative errno on failure.
6922 */
drm_connector_update_edid_property(struct drm_connector * connector,const struct edid * edid)6923 int drm_connector_update_edid_property(struct drm_connector *connector,
6924 const struct edid *edid)
6925 {
6926 struct drm_edid drm_edid;
6927
6928 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
6929 }
6930 EXPORT_SYMBOL(drm_connector_update_edid_property);
6931
6932 /**
6933 * drm_add_edid_modes - add modes from EDID data, if available
6934 * @connector: connector we're probing
6935 * @edid: EDID data
6936 *
6937 * Add the specified modes to the connector's mode list. Also fills out the
6938 * &drm_display_info structure and ELD in @connector with any information which
6939 * can be derived from the edid.
6940 *
6941 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
6942 *
6943 * Return: The number of modes added or 0 if we couldn't find any.
6944 */
drm_add_edid_modes(struct drm_connector * connector,struct edid * edid)6945 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6946 {
6947 struct drm_edid _drm_edid;
6948 const struct drm_edid *drm_edid;
6949
6950 if (edid && !drm_edid_is_valid(edid)) {
6951 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
6952 connector->base.id, connector->name);
6953 edid = NULL;
6954 }
6955
6956 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
6957
6958 update_display_info(connector, drm_edid);
6959
6960 return _drm_edid_connector_add_modes(connector, drm_edid);
6961 }
6962 EXPORT_SYMBOL(drm_add_edid_modes);
6963
6964 /**
6965 * drm_add_modes_noedid - add modes for the connectors without EDID
6966 * @connector: connector we're probing
6967 * @hdisplay: the horizontal display limit
6968 * @vdisplay: the vertical display limit
6969 *
6970 * Add the specified modes to the connector's mode list. Only when the
6971 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6972 *
6973 * Return: The number of modes added or 0 if we couldn't find any.
6974 */
drm_add_modes_noedid(struct drm_connector * connector,int hdisplay,int vdisplay)6975 int drm_add_modes_noedid(struct drm_connector *connector,
6976 int hdisplay, int vdisplay)
6977 {
6978 int i, count, num_modes = 0;
6979 struct drm_display_mode *mode;
6980 struct drm_device *dev = connector->dev;
6981
6982 count = ARRAY_SIZE(drm_dmt_modes);
6983 if (hdisplay < 0)
6984 hdisplay = 0;
6985 if (vdisplay < 0)
6986 vdisplay = 0;
6987
6988 for (i = 0; i < count; i++) {
6989 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6990
6991 if (hdisplay && vdisplay) {
6992 /*
6993 * Only when two are valid, they will be used to check
6994 * whether the mode should be added to the mode list of
6995 * the connector.
6996 */
6997 if (ptr->hdisplay > hdisplay ||
6998 ptr->vdisplay > vdisplay)
6999 continue;
7000 }
7001 if (drm_mode_vrefresh(ptr) > 61)
7002 continue;
7003 mode = drm_mode_duplicate(dev, ptr);
7004 if (mode) {
7005 drm_mode_probed_add(connector, mode);
7006 num_modes++;
7007 }
7008 }
7009 return num_modes;
7010 }
7011 EXPORT_SYMBOL(drm_add_modes_noedid);
7012
7013 /**
7014 * drm_set_preferred_mode - Sets the preferred mode of a connector
7015 * @connector: connector whose mode list should be processed
7016 * @hpref: horizontal resolution of preferred mode
7017 * @vpref: vertical resolution of preferred mode
7018 *
7019 * Marks a mode as preferred if it matches the resolution specified by @hpref
7020 * and @vpref.
7021 */
drm_set_preferred_mode(struct drm_connector * connector,int hpref,int vpref)7022 void drm_set_preferred_mode(struct drm_connector *connector,
7023 int hpref, int vpref)
7024 {
7025 struct drm_display_mode *mode;
7026
7027 list_for_each_entry(mode, &connector->probed_modes, head) {
7028 if (mode->hdisplay == hpref &&
7029 mode->vdisplay == vpref)
7030 mode->type |= DRM_MODE_TYPE_PREFERRED;
7031 }
7032 }
7033 EXPORT_SYMBOL(drm_set_preferred_mode);
7034
is_hdmi2_sink(const struct drm_connector * connector)7035 static bool is_hdmi2_sink(const struct drm_connector *connector)
7036 {
7037 /*
7038 * FIXME: sil-sii8620 doesn't have a connector around when
7039 * we need one, so we have to be prepared for a NULL connector.
7040 */
7041 if (!connector)
7042 return true;
7043
7044 return connector->display_info.hdmi.scdc.supported ||
7045 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
7046 }
7047
drm_mode_hdmi_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)7048 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
7049 const struct drm_display_mode *mode)
7050 {
7051 bool has_hdmi_infoframe = connector ?
7052 connector->display_info.has_hdmi_infoframe : false;
7053
7054 if (!has_hdmi_infoframe)
7055 return 0;
7056
7057 /* No HDMI VIC when signalling 3D video format */
7058 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7059 return 0;
7060
7061 return drm_match_hdmi_mode(mode);
7062 }
7063
drm_mode_cea_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)7064 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
7065 const struct drm_display_mode *mode)
7066 {
7067 /*
7068 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7069 * we should send its VIC in vendor infoframes, else send the
7070 * VIC in AVI infoframes. Lets check if this mode is present in
7071 * HDMI 1.4b 4K modes
7072 */
7073 if (drm_mode_hdmi_vic(connector, mode))
7074 return 0;
7075
7076 return drm_match_cea_mode(mode);
7077 }
7078
7079 /*
7080 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7081 * conform to HDMI 1.4.
7082 *
7083 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7084 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
7085 *
7086 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7087 * version.
7088 */
vic_for_avi_infoframe(const struct drm_connector * connector,u8 vic)7089 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7090 {
7091 if (!is_hdmi2_sink(connector) && vic > 64 &&
7092 !cta_vdb_has_vic(connector, vic))
7093 return 0;
7094
7095 return vic;
7096 }
7097
7098 /**
7099 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7100 * data from a DRM display mode
7101 * @frame: HDMI AVI infoframe
7102 * @connector: the connector
7103 * @mode: DRM display mode
7104 *
7105 * Return: 0 on success or a negative error code on failure.
7106 */
7107 int
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)7108 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
7109 const struct drm_connector *connector,
7110 const struct drm_display_mode *mode)
7111 {
7112 enum hdmi_picture_aspect picture_aspect;
7113 u8 vic, hdmi_vic;
7114
7115 if (!frame || !mode)
7116 return -EINVAL;
7117
7118 hdmi_avi_infoframe_init(frame);
7119
7120 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7121 frame->pixel_repeat = 1;
7122
7123 vic = drm_mode_cea_vic(connector, mode);
7124 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7125
7126 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7127
7128 /*
7129 * As some drivers don't support atomic, we can't use connector state.
7130 * So just initialize the frame with default values, just the same way
7131 * as it's done with other properties here.
7132 */
7133 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7134 frame->itc = 0;
7135
7136 /*
7137 * Populate picture aspect ratio from either
7138 * user input (if specified) or from the CEA/HDMI mode lists.
7139 */
7140 picture_aspect = mode->picture_aspect_ratio;
7141 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7142 if (vic)
7143 picture_aspect = drm_get_cea_aspect_ratio(vic);
7144 else if (hdmi_vic)
7145 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7146 }
7147
7148 /*
7149 * The infoframe can't convey anything but none, 4:3
7150 * and 16:9, so if the user has asked for anything else
7151 * we can only satisfy it by specifying the right VIC.
7152 */
7153 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7154 if (vic) {
7155 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7156 return -EINVAL;
7157 } else if (hdmi_vic) {
7158 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7159 return -EINVAL;
7160 } else {
7161 return -EINVAL;
7162 }
7163
7164 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7165 }
7166
7167 frame->video_code = vic_for_avi_infoframe(connector, vic);
7168 frame->picture_aspect = picture_aspect;
7169 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7170 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7171
7172 return 0;
7173 }
7174 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7175
7176 /**
7177 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7178 * quantization range information
7179 * @frame: HDMI AVI infoframe
7180 * @connector: the connector
7181 * @mode: DRM display mode
7182 * @rgb_quant_range: RGB quantization range (Q)
7183 */
7184 void
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode,enum hdmi_quantization_range rgb_quant_range)7185 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7186 const struct drm_connector *connector,
7187 const struct drm_display_mode *mode,
7188 enum hdmi_quantization_range rgb_quant_range)
7189 {
7190 const struct drm_display_info *info = &connector->display_info;
7191
7192 /*
7193 * CEA-861:
7194 * "A Source shall not send a non-zero Q value that does not correspond
7195 * to the default RGB Quantization Range for the transmitted Picture
7196 * unless the Sink indicates support for the Q bit in a Video
7197 * Capabilities Data Block."
7198 *
7199 * HDMI 2.0 recommends sending non-zero Q when it does match the
7200 * default RGB quantization range for the mode, even when QS=0.
7201 */
7202 if (info->rgb_quant_range_selectable ||
7203 rgb_quant_range == drm_default_rgb_quant_range(mode))
7204 frame->quantization_range = rgb_quant_range;
7205 else
7206 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7207
7208 /*
7209 * CEA-861-F:
7210 * "When transmitting any RGB colorimetry, the Source should set the
7211 * YQ-field to match the RGB Quantization Range being transmitted
7212 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7213 * set YQ=1) and the Sink shall ignore the YQ-field."
7214 *
7215 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7216 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7217 * good way to tell which version of CEA-861 the sink supports, so
7218 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7219 * on CEA-861-F.
7220 */
7221 if (!is_hdmi2_sink(connector) ||
7222 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7223 frame->ycc_quantization_range =
7224 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7225 else
7226 frame->ycc_quantization_range =
7227 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7228 }
7229 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7230
7231 static enum hdmi_3d_structure
s3d_structure_from_display_mode(const struct drm_display_mode * mode)7232 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7233 {
7234 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7235
7236 switch (layout) {
7237 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7238 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7239 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7240 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7241 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7242 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7243 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7244 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7245 case DRM_MODE_FLAG_3D_L_DEPTH:
7246 return HDMI_3D_STRUCTURE_L_DEPTH;
7247 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7248 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7249 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7250 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7251 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7252 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7253 default:
7254 return HDMI_3D_STRUCTURE_INVALID;
7255 }
7256 }
7257
7258 /**
7259 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7260 * data from a DRM display mode
7261 * @frame: HDMI vendor infoframe
7262 * @connector: the connector
7263 * @mode: DRM display mode
7264 *
7265 * Note that there's is a need to send HDMI vendor infoframes only when using a
7266 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7267 * function will return -EINVAL, error that can be safely ignored.
7268 *
7269 * Return: 0 on success or a negative error code on failure.
7270 */
7271 int
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)7272 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7273 const struct drm_connector *connector,
7274 const struct drm_display_mode *mode)
7275 {
7276 /*
7277 * FIXME: sil-sii8620 doesn't have a connector around when
7278 * we need one, so we have to be prepared for a NULL connector.
7279 */
7280 bool has_hdmi_infoframe = connector ?
7281 connector->display_info.has_hdmi_infoframe : false;
7282 int err;
7283
7284 if (!frame || !mode)
7285 return -EINVAL;
7286
7287 if (!has_hdmi_infoframe)
7288 return -EINVAL;
7289
7290 err = hdmi_vendor_infoframe_init(frame);
7291 if (err < 0)
7292 return err;
7293
7294 /*
7295 * Even if it's not absolutely necessary to send the infoframe
7296 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7297 * know that the sink can handle it. This is based on a
7298 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7299 * have trouble realizing that they should switch from 3D to 2D
7300 * mode if the source simply stops sending the infoframe when
7301 * it wants to switch from 3D to 2D.
7302 */
7303 frame->vic = drm_mode_hdmi_vic(connector, mode);
7304 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7305
7306 return 0;
7307 }
7308 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7309
drm_parse_tiled_block(struct drm_connector * connector,const struct displayid_block * block)7310 static void drm_parse_tiled_block(struct drm_connector *connector,
7311 const struct displayid_block *block)
7312 {
7313 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7314 u16 w, h;
7315 u8 tile_v_loc, tile_h_loc;
7316 u8 num_v_tile, num_h_tile;
7317 struct drm_tile_group *tg;
7318
7319 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7320 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7321
7322 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7323 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7324 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7325 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7326
7327 connector->has_tile = true;
7328 if (tile->tile_cap & 0x80)
7329 connector->tile_is_single_monitor = true;
7330
7331 connector->num_h_tile = num_h_tile + 1;
7332 connector->num_v_tile = num_v_tile + 1;
7333 connector->tile_h_loc = tile_h_loc;
7334 connector->tile_v_loc = tile_v_loc;
7335 connector->tile_h_size = w + 1;
7336 connector->tile_v_size = h + 1;
7337
7338 drm_dbg_kms(connector->dev,
7339 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7340 connector->base.id, connector->name,
7341 tile->tile_cap,
7342 connector->tile_h_size, connector->tile_v_size,
7343 connector->num_h_tile, connector->num_v_tile,
7344 connector->tile_h_loc, connector->tile_v_loc,
7345 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7346
7347 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7348 if (!tg)
7349 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7350 if (!tg)
7351 return;
7352
7353 if (connector->tile_group != tg) {
7354 /* if we haven't got a pointer,
7355 take the reference, drop ref to old tile group */
7356 if (connector->tile_group)
7357 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7358 connector->tile_group = tg;
7359 } else {
7360 /* if same tile group, then release the ref we just took. */
7361 drm_mode_put_tile_group(connector->dev, tg);
7362 }
7363 }
7364
displayid_is_tiled_block(const struct displayid_iter * iter,const struct displayid_block * block)7365 static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7366 const struct displayid_block *block)
7367 {
7368 return (displayid_version(iter) < DISPLAY_ID_STRUCTURE_VER_20 &&
7369 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7370 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7371 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7372 }
7373
_drm_update_tile_info(struct drm_connector * connector,const struct drm_edid * drm_edid)7374 static void _drm_update_tile_info(struct drm_connector *connector,
7375 const struct drm_edid *drm_edid)
7376 {
7377 const struct displayid_block *block;
7378 struct displayid_iter iter;
7379
7380 connector->has_tile = false;
7381
7382 displayid_iter_edid_begin(drm_edid, &iter);
7383 displayid_iter_for_each(block, &iter) {
7384 if (displayid_is_tiled_block(&iter, block))
7385 drm_parse_tiled_block(connector, block);
7386 }
7387 displayid_iter_end(&iter);
7388
7389 if (!connector->has_tile && connector->tile_group) {
7390 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7391 connector->tile_group = NULL;
7392 }
7393 }
7394