1 /*
2 * nextpnr -- Next Generation Place and Route
3 *
4 * Copyright (C) 2018 David Shah <david@symbioticeda.com>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "bitstream.h"
21
22 #include <boost/algorithm/string/predicate.hpp>
23 #include <fstream>
24 #include <iomanip>
25 #include <queue>
26 #include <regex>
27 #include <streambuf>
28 #include "config.h"
29 #include "log.h"
30 #include "pio.h"
31 #include "util.h"
32
33 #define fmt_str(x) (static_cast<const std::ostringstream &>(std::ostringstream() << x).str())
34
35 NEXTPNR_NAMESPACE_BEGIN
36
37 namespace BaseConfigs {
38 void config_empty_lfe5u_25f(ChipConfig &cc);
39 void config_empty_lfe5u_45f(ChipConfig &cc);
40 void config_empty_lfe5u_85f(ChipConfig &cc);
41 void config_empty_lfe5um_25f(ChipConfig &cc);
42 void config_empty_lfe5um_45f(ChipConfig &cc);
43 void config_empty_lfe5um_85f(ChipConfig &cc);
44 void config_empty_lfe5um5g_25f(ChipConfig &cc);
45 void config_empty_lfe5um5g_45f(ChipConfig &cc);
46 void config_empty_lfe5um5g_85f(ChipConfig &cc);
47 } // namespace BaseConfigs
48
49 // Convert an absolute wire name to a relative Trellis one
get_trellis_wirename(Context * ctx,Location loc,WireId wire)50 static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
51 {
52 std::string basename = ctx->locInfo(wire)->wire_data[wire.index].name.get();
53 std::string prefix2 = basename.substr(0, 2);
54 if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_")
55 return basename;
56 if (loc == wire.location)
57 return basename;
58 std::string rel_prefix;
59 if (wire.location.y < loc.y)
60 rel_prefix += "N" + std::to_string(loc.y - wire.location.y);
61 if (wire.location.y > loc.y)
62 rel_prefix += "S" + std::to_string(wire.location.y - loc.y);
63 if (wire.location.x > loc.x)
64 rel_prefix += "E" + std::to_string(wire.location.x - loc.x);
65 if (wire.location.x < loc.x)
66 rel_prefix += "W" + std::to_string(loc.x - wire.location.x);
67 return rel_prefix + "_" + basename;
68 }
69
int_to_bitvector(int val,int size)70 static std::vector<bool> int_to_bitvector(int val, int size)
71 {
72 std::vector<bool> bv;
73 for (int i = 0; i < size; i++) {
74 bv.push_back((val & (1 << i)) != 0);
75 }
76 return bv;
77 }
78
str_to_bitvector(std::string str,int size)79 static std::vector<bool> str_to_bitvector(std::string str, int size)
80 {
81 std::vector<bool> bv;
82 bv.resize(size, 0);
83 if (str.substr(0, 2) != "0b")
84 log_error("error parsing value '%s', expected 0b prefix\n", str.c_str());
85 for (int i = 0; i < int(str.size()) - 2; i++) {
86 char c = str.at((str.size() - i) - 1);
87 NPNR_ASSERT(c == '0' || c == '1');
88 bv.at(i) = (c == '1');
89 }
90 return bv;
91 }
92
93 // Tie a wire using the CIB ties
tie_cib_signal(Context * ctx,ChipConfig & cc,WireId wire,bool value)94 static void tie_cib_signal(Context *ctx, ChipConfig &cc, WireId wire, bool value)
95 {
96 static const std::regex cib_re("J([A-D]|CE|LSR|CLK)[0-7]");
97 std::queue<WireId> signals;
98 signals.push(wire);
99 WireId cibsig;
100 std::string basename;
101 while (true) {
102 NPNR_ASSERT(!signals.empty());
103 NPNR_ASSERT(signals.size() < 100);
104 cibsig = signals.front();
105 basename = ctx->getWireBasename(cibsig).str(ctx);
106 signals.pop();
107 if (std::regex_match(basename, cib_re))
108 break;
109 for (auto pip : ctx->getPipsUphill(cibsig))
110 signals.push(ctx->getPipSrcWire(pip));
111 }
112
113 bool out_value = value;
114 if (basename.substr(0, 3) == "JCE")
115 NPNR_ASSERT(value);
116 if (basename.substr(0, 4) == "JCLK" || basename.substr(0, 4) == "JLSR") {
117 NPNR_ASSERT(value);
118 out_value = 0;
119 }
120
121 for (const auto &tile : ctx->getTilesAtLocation(cibsig.location.y, cibsig.location.x)) {
122 if (tile.second.substr(0, 3) == "CIB" || tile.second.substr(0, 4) == "VCIB") {
123
124 cc.tiles[tile.first].add_enum("CIB." + basename + "MUX", out_value ? "1" : "0");
125 return;
126 }
127 }
128 NPNR_ASSERT_FALSE("CIB tile not found at location");
129 }
130
chtohex(char c)131 inline int chtohex(char c)
132 {
133 static const std::string hex = "0123456789ABCDEF";
134 return hex.find(c);
135 }
136
parse_init_str(const Property & p,int length,const char * cellname)137 std::vector<bool> parse_init_str(const Property &p, int length, const char *cellname)
138 {
139 // Parse a string that may be binary or hex
140 std::vector<bool> result;
141 result.resize(length, false);
142 if (p.is_string) {
143 std::string str = p.as_string();
144 NPNR_ASSERT(str.substr(0, 2) == "0x");
145 // Lattice style hex string
146 if (int(str.length()) > (2 + ((length + 3) / 4)))
147 log_error("hex string value too long, expected up to %d chars and found %d.\n", (2 + ((length + 3) / 4)),
148 int(str.length()));
149 for (int i = 0; i < int(str.length()) - 2; i++) {
150 char c = str.at((str.size() - i) - 1);
151 int nibble = chtohex(c);
152 result.at(i * 4) = nibble & 0x1;
153 if (i * 4 + 1 < length)
154 result.at(i * 4 + 1) = nibble & 0x2;
155 if (i * 4 + 2 < length)
156 result.at(i * 4 + 2) = nibble & 0x4;
157 if (i * 4 + 3 < length)
158 result.at(i * 4 + 3) = nibble & 0x8;
159 }
160 } else {
161 result = p.as_bits();
162 result.resize(length, false);
163 }
164 return result;
165 }
166
bit_reverse(uint16_t x,int size)167 inline uint16_t bit_reverse(uint16_t x, int size)
168 {
169 uint16_t y = 0;
170 for (int i = 0; i < size; i++)
171 if (x & (1 << i))
172 y |= (1 << ((size - 1) - i));
173 return y;
174 }
175
176 // Get the PIO tile corresponding to a PIO bel
get_pio_tile(Context * ctx,BelId bel)177 static std::string get_pio_tile(Context *ctx, BelId bel)
178 {
179 static const std::set<std::string> pioabcd_l = {"PICL1", "PICL1_DQS0", "PICL1_DQS3"};
180 static const std::set<std::string> pioabcd_r = {"PICR1", "PICR1_DQS0", "PICR1_DQS3"};
181 static const std::set<std::string> pioa_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0", "SPICB0"};
182 static const std::set<std::string> piob_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"};
183
184 std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get();
185 if (bel.location.y == 0) {
186 if (pio_name == "PIOA") {
187 return ctx->getTileByTypeAndLocation(0, bel.location.x, "PIOT0");
188 } else if (pio_name == "PIOB") {
189 return ctx->getTileByTypeAndLocation(0, bel.location.x + 1, "PIOT1");
190 } else {
191 NPNR_ASSERT_FALSE("bad PIO location");
192 }
193 } else if (bel.location.y == ctx->chip_info->height - 1) {
194 if (pio_name == "PIOA") {
195 return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, pioa_b);
196 } else if (pio_name == "PIOB") {
197 return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x + 1, piob_b);
198 } else {
199 NPNR_ASSERT_FALSE("bad PIO location");
200 }
201 } else if (bel.location.x == 0) {
202 return ctx->getTileByTypeAndLocation(bel.location.y + 1, bel.location.x, pioabcd_l);
203 } else if (bel.location.x == ctx->chip_info->width - 1) {
204 return ctx->getTileByTypeAndLocation(bel.location.y + 1, bel.location.x, pioabcd_r);
205 } else {
206 NPNR_ASSERT_FALSE("bad PIO location");
207 }
208 }
209
210 // Get the PIC tile corresponding to a PIO bel
get_pic_tile(Context * ctx,BelId bel)211 static std::string get_pic_tile(Context *ctx, BelId bel)
212 {
213 static const std::set<std::string> picab_l = {"PICL0", "PICL0_DQS2"};
214 static const std::set<std::string> piccd_l = {"PICL2", "PICL2_DQS1", "MIB_CIB_LR"};
215 static const std::set<std::string> picab_r = {"PICR0", "PICR0_DQS2"};
216 static const std::set<std::string> piccd_r = {"PICR2", "PICR2_DQS1", "MIB_CIB_LR_A"};
217
218 static const std::set<std::string> pica_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0", "SPICB0"};
219 static const std::set<std::string> picb_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"};
220
221 std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get();
222 if (bel.location.y == 0) {
223 if (pio_name == "PIOA") {
224 return ctx->getTileByTypeAndLocation(1, bel.location.x, "PICT0");
225 } else if (pio_name == "PIOB") {
226 return ctx->getTileByTypeAndLocation(1, bel.location.x + 1, "PICT1");
227 } else {
228 NPNR_ASSERT_FALSE("bad PIO location");
229 }
230 } else if (bel.location.y == ctx->chip_info->height - 1) {
231 if (pio_name == "PIOA") {
232 return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, pica_b);
233 } else if (pio_name == "PIOB") {
234 return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x + 1, picb_b);
235 } else {
236 NPNR_ASSERT_FALSE("bad PIO location");
237 }
238 } else if (bel.location.x == 0) {
239 if (pio_name == "PIOA" || pio_name == "PIOB") {
240 return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, picab_l);
241 } else if (pio_name == "PIOC" || pio_name == "PIOD") {
242 return ctx->getTileByTypeAndLocation(bel.location.y + 2, bel.location.x, piccd_l);
243 } else {
244 NPNR_ASSERT_FALSE("bad PIO location");
245 }
246 } else if (bel.location.x == ctx->chip_info->width - 1) {
247 if (pio_name == "PIOA" || pio_name == "PIOB") {
248 return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, picab_r);
249 } else if (pio_name == "PIOC" || pio_name == "PIOD") {
250 return ctx->getTileByTypeAndLocation(bel.location.y + 2, bel.location.x, piccd_r);
251 } else {
252 NPNR_ASSERT_FALSE("bad PIO location");
253 }
254 } else {
255 NPNR_ASSERT_FALSE("bad PIO location");
256 }
257 }
258
259 // Get the complement PIC and PIO tiles for a pseudo differential IO
get_comp_pio_tile(Context * ctx,BelId bel)260 static std::string get_comp_pio_tile(Context *ctx, BelId bel)
261 {
262 NPNR_ASSERT(bel.location.y == 0);
263 return ctx->getTileByTypeAndLocation(0, bel.location.x + 1, "PIOT1");
264 }
get_comp_pic_tile(Context * ctx,BelId bel)265 static std::string get_comp_pic_tile(Context *ctx, BelId bel)
266 {
267 NPNR_ASSERT(bel.location.y == 0);
268 return ctx->getTileByTypeAndLocation(1, bel.location.x + 1, "PICT1");
269 }
270
271 // Get the list of tiles corresponding to a blockram
get_bram_tiles(Context * ctx,BelId bel)272 std::vector<std::string> get_bram_tiles(Context *ctx, BelId bel)
273 {
274 std::vector<std::string> tiles;
275 Loc loc = ctx->getBelLocation(bel);
276
277 static const std::set<std::string> ebr0 = {"MIB_EBR0", "EBR_CMUX_UR", "EBR_CMUX_LR", "EBR_CMUX_LR_25K"};
278 static const std::set<std::string> ebr8 = {"MIB_EBR8", "EBR_SPINE_UL1", "EBR_SPINE_UR1", "EBR_SPINE_LL1",
279 "EBR_CMUX_UL", "EBR_SPINE_LL0", "EBR_CMUX_LL", "EBR_SPINE_LR0",
280 "EBR_SPINE_LR1", "EBR_CMUX_LL_25K", "EBR_SPINE_UL2", "EBR_SPINE_UL0",
281 "EBR_SPINE_UR2", "EBR_SPINE_LL2", "EBR_SPINE_LR2", "EBR_SPINE_UR0"};
282
283 switch (loc.z) {
284 case 0:
285 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, ebr0));
286 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_EBR1"));
287 break;
288 case 1:
289 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_EBR2"));
290 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_EBR3"));
291 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB_EBR4"));
292 break;
293 case 2:
294 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_EBR4"));
295 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_EBR5"));
296 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB_EBR6"));
297 break;
298 case 3:
299 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_EBR6"));
300 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_EBR7"));
301 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, ebr8));
302 break;
303 default:
304 NPNR_ASSERT_FALSE("bad EBR z loc");
305 }
306 return tiles;
307 }
308
309 // Get the list of tiles corresponding to a DSP
get_dsp_tiles(Context * ctx,BelId bel)310 std::vector<std::string> get_dsp_tiles(Context *ctx, BelId bel)
311 {
312 std::vector<std::string> tiles;
313 Loc loc = ctx->getBelLocation(bel);
314
315 static const std::set<std::string> dsp8 = {"MIB_DSP8", "DSP_SPINE_UL0", "DSP_SPINE_UR0", "DSP_SPINE_UR1"};
316 if (ctx->getBelType(bel) == id_MULT18X18D) {
317 switch (loc.z) {
318 case 0:
319 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_DSP0"));
320 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB2_DSP0"));
321 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_DSP1"));
322 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB2_DSP1"));
323 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB_DSP2"));
324 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB2_DSP2"));
325 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, "MIB_DSP3"));
326 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, "MIB2_DSP3"));
327 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 4, "MIB_DSP4"));
328 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 4, "MIB2_DSP4"));
329 break;
330 case 1:
331 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB_DSP0"));
332 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB2_DSP0"));
333 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_DSP1"));
334 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB2_DSP1"));
335 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_DSP2"));
336 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB2_DSP2"));
337 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB_DSP3"));
338 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB2_DSP3"));
339 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, "MIB_DSP4"));
340 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, "MIB2_DSP4"));
341 break;
342 case 4:
343 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_DSP4"));
344 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB2_DSP4"));
345 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_DSP5"));
346 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB2_DSP5"));
347 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB_DSP6"));
348 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB2_DSP6"));
349 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, "MIB_DSP7"));
350 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, "MIB2_DSP7"));
351 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 4, dsp8));
352 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 4, "MIB2_DSP8"));
353 break;
354 case 5:
355 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB_DSP4"));
356 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB2_DSP4"));
357 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_DSP5"));
358 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB2_DSP5"));
359 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_DSP6"));
360 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB2_DSP6"));
361 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB_DSP7"));
362 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 2, "MIB2_DSP7"));
363 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, dsp8));
364 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 3, "MIB2_DSP8"));
365 break;
366 default:
367 NPNR_ASSERT_FALSE("bad MULT z loc");
368 }
369 } else if (ctx->getBelType(bel) == id_ALU54B) {
370 switch (loc.z) {
371 case 3:
372 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 3, "MIB_DSP0"));
373 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 3, "MIB2_DSP0"));
374 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 2, "MIB_DSP1"));
375 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 2, "MIB2_DSP1"));
376 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB_DSP2"));
377 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB2_DSP2"));
378 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_DSP3"));
379 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB2_DSP3"));
380 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB_DSP4"));
381 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB2_DSP4"));
382 break;
383 case 7:
384 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 3, "MIB_DSP4"));
385 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 3, "MIB2_DSP4"));
386 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 2, "MIB_DSP5"));
387 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 2, "MIB2_DSP5"));
388 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB_DSP6"));
389 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "MIB2_DSP6"));
390 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB_DSP7"));
391 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "MIB2_DSP7"));
392 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, dsp8));
393 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "MIB2_DSP8"));
394 break;
395 default:
396 NPNR_ASSERT_FALSE("bad ALU z loc");
397 }
398 }
399 return tiles;
400 }
401
402 // Get the list of tiles corresponding to a DCU
get_dcu_tiles(Context * ctx,BelId bel)403 std::vector<std::string> get_dcu_tiles(Context *ctx, BelId bel)
404 {
405 std::vector<std::string> tiles;
406 Loc loc = ctx->getBelLocation(bel);
407 for (int i = 0; i < 9; i++)
408 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + i, "DCU" + std::to_string(i)));
409 return tiles;
410 }
411
412 // Get the list of tiles corresponding to a PLL
get_pll_tiles(Context * ctx,BelId bel)413 std::vector<std::string> get_pll_tiles(Context *ctx, BelId bel)
414 {
415 std::string name = ctx->locInfo(bel)->bel_data[bel.index].name.get();
416 std::vector<std::string> tiles;
417 Loc loc = ctx->getBelLocation(bel);
418 static const std::set<std::string> pll1_lr = {"PLL1_LR", "BANKREF4"};
419
420 if (name == "EHXPLL_UL") {
421 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "PLL0_UL"));
422 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x - 1, "PLL1_UL"));
423 } else if (name == "EHXPLL_LL") {
424 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x, "PLL0_LL"));
425 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x + 1, "BANKREF8"));
426 } else if (name == "EHXPLL_LR") {
427 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x, "PLL0_LR"));
428 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x - 1, pll1_lr));
429 } else if (name == "EHXPLL_UR") {
430 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "PLL0_UR"));
431 tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x + 1, "PLL1_UR"));
432 } else {
433 NPNR_ASSERT_FALSE_STR("bad PLL loc " + name);
434 }
435 return tiles;
436 }
437
fix_tile_names(Context * ctx,ChipConfig & cc)438 void fix_tile_names(Context *ctx, ChipConfig &cc)
439 {
440 // Remove the V prefix/suffix on certain tiles if device is a SERDES variant
441 if (ctx->args.type == ArchArgs::LFE5U_12F || ctx->args.type == ArchArgs::LFE5U_25F ||
442 ctx->args.type == ArchArgs::LFE5U_45F || ctx->args.type == ArchArgs::LFE5U_85F) {
443 std::map<std::string, std::string> tiletype_xform;
444 for (const auto &tile : cc.tiles) {
445 std::string newname = tile.first;
446 auto cibdcu = tile.first.find("CIB_DCU");
447 if (cibdcu != std::string::npos) {
448 // Add the V
449 if (newname.at(cibdcu - 1) != 'V') {
450 newname.insert(cibdcu, 1, 'V');
451 tiletype_xform[tile.first] = newname;
452 }
453 } else if (boost::ends_with(tile.first, "BMID_0H")) {
454 newname.back() = 'V';
455 tiletype_xform[tile.first] = newname;
456 } else if (boost::ends_with(tile.first, "BMID_2")) {
457 newname.push_back('V');
458 tiletype_xform[tile.first] = newname;
459 }
460 }
461 // Apply the name changes
462 for (auto xform : tiletype_xform) {
463 auto &existing = cc.tiles.at(xform.first);
464 for (const auto &carc : existing.carcs)
465 cc.tiles[xform.second].carcs.push_back(carc);
466 for (const auto &cenum : existing.cenums)
467 cc.tiles[xform.second].cenums.push_back(cenum);
468 for (const auto &cword : existing.cwords)
469 cc.tiles[xform.second].cwords.push_back(cword);
470 for (const auto &cunknown : existing.cunknowns)
471 cc.tiles[xform.second].cunknowns.push_back(cunknown);
472 cc.tiles.erase(xform.first);
473 }
474 }
475 }
476
tieoff_dsp_ports(Context * ctx,ChipConfig & cc,CellInfo * ci)477 void tieoff_dsp_ports(Context *ctx, ChipConfig &cc, CellInfo *ci)
478 {
479 for (auto port : ci->ports) {
480 if (port.second.net == nullptr && port.second.type == PORT_IN) {
481 if (port.first.str(ctx).substr(0, 3) == "CLK" || port.first.str(ctx).substr(0, 2) == "CE" ||
482 port.first.str(ctx).substr(0, 3) == "RST" || port.first.str(ctx).substr(0, 3) == "SRO" ||
483 port.first.str(ctx).substr(0, 3) == "SRI" || port.first.str(ctx).substr(0, 2) == "RO" ||
484 port.first.str(ctx).substr(0, 2) == "MA" || port.first.str(ctx).substr(0, 2) == "MB" ||
485 port.first.str(ctx).substr(0, 3) == "CFB" || port.first.str(ctx).substr(0, 3) == "CIN" ||
486 port.first.str(ctx).substr(0, 6) == "SOURCE" || port.first.str(ctx).substr(0, 6) == "SIGNED" ||
487 port.first.str(ctx).substr(0, 2) == "OP")
488 continue;
489 bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false);
490 tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), value);
491 }
492 }
493 }
494
tieoff_dcu_ports(Context * ctx,ChipConfig & cc,CellInfo * ci)495 void tieoff_dcu_ports(Context *ctx, ChipConfig &cc, CellInfo *ci)
496 {
497 for (auto port : ci->ports) {
498 if (port.second.net == nullptr && port.second.type == PORT_IN) {
499 if (port.first.str(ctx).find("CLK") != std::string::npos ||
500 port.first.str(ctx).find("HDIN") != std::string::npos ||
501 port.first.str(ctx).find("HDOUT") != std::string::npos)
502 continue;
503 bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false);
504 tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), value);
505 }
506 }
507 }
508
set_pip(Context * ctx,ChipConfig & cc,PipId pip)509 static void set_pip(Context *ctx, ChipConfig &cc, PipId pip)
510 {
511 std::string tile = ctx->getPipTilename(pip);
512 std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
513 std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
514 cc.tiles[tile].add_arc(sink, source);
515 }
516
parse_config_str(const Property & p,int length)517 static std::vector<bool> parse_config_str(const Property &p, int length)
518 {
519 std::vector<bool> word;
520 if (p.is_string) {
521 std::string str = p.as_string();
522 // For DCU config which might be bin, hex or dec using prefices accordingly
523 std::string base = str.substr(0, 2);
524 word.resize(length, false);
525 if (base == "0b") {
526 for (int i = 0; i < int(str.length()) - 2; i++) {
527 char c = str.at((str.size() - 1) - i);
528 NPNR_ASSERT(c == '0' || c == '1');
529 word.at(i) = (c == '1');
530 }
531 } else if (base == "0x") {
532 for (int i = 0; i < int(str.length()) - 2; i++) {
533 char c = str.at((str.size() - i) - 1);
534 int nibble = chtohex(c);
535 word.at(i * 4) = nibble & 0x1;
536 if (i * 4 + 1 < length)
537 word.at(i * 4 + 1) = nibble & 0x2;
538 if (i * 4 + 2 < length)
539 word.at(i * 4 + 2) = nibble & 0x4;
540 if (i * 4 + 3 < length)
541 word.at(i * 4 + 3) = nibble & 0x8;
542 }
543 } else if (base == "0d") {
544 NPNR_ASSERT(length < 64);
545 unsigned long long value = std::stoull(str.substr(2));
546 for (int i = 0; i < length; i++)
547 if (value & (1 << i))
548 word.at(i) = true;
549 } else {
550 NPNR_ASSERT(length < 64);
551 unsigned long long value = std::stoull(str);
552 for (int i = 0; i < length; i++)
553 if (value & (1 << i))
554 word.at(i) = true;
555 }
556 } else {
557 word = p.as_bits();
558 word.resize(length, 0);
559 }
560
561 return word;
562 }
563
intstr_or_default(const std::unordered_map<IdString,Property> & ct,const IdString & key,std::string def="0")564 std::string intstr_or_default(const std::unordered_map<IdString, Property> &ct, const IdString &key,
565 std::string def = "0")
566 {
567 auto found = ct.find(key);
568 if (found == ct.end())
569 return def;
570 else {
571 if (found->second.is_string)
572 return found->second.as_string();
573 else
574 return std::to_string(found->second.as_int64());
575 }
576 };
577
write_bitstream(Context * ctx,std::string base_config_file,std::string text_config_file)578 void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file)
579 {
580 ChipConfig cc;
581
582 std::set<std::string> cib_tiles = {"CIB", "CIB_LR", "CIB_LR_S", "CIB_EFB0", "CIB_EFB1"};
583
584 if (!base_config_file.empty()) {
585 std::ifstream config_file(base_config_file);
586 if (!config_file) {
587 log_error("failed to open base config file '%s'\n", base_config_file.c_str());
588 }
589 config_file >> cc;
590 } else {
591 switch (ctx->args.type) {
592 case ArchArgs::LFE5U_12F:
593 BaseConfigs::config_empty_lfe5u_25f(cc);
594 cc.chip_name = "LFE5U-12F";
595 break;
596 case ArchArgs::LFE5U_25F:
597 BaseConfigs::config_empty_lfe5u_25f(cc);
598 break;
599 case ArchArgs::LFE5U_45F:
600 BaseConfigs::config_empty_lfe5u_45f(cc);
601 break;
602 case ArchArgs::LFE5U_85F:
603 BaseConfigs::config_empty_lfe5u_85f(cc);
604 break;
605 case ArchArgs::LFE5UM_25F:
606 BaseConfigs::config_empty_lfe5um_25f(cc);
607 break;
608 case ArchArgs::LFE5UM_45F:
609 BaseConfigs::config_empty_lfe5um_45f(cc);
610 break;
611 case ArchArgs::LFE5UM_85F:
612 BaseConfigs::config_empty_lfe5um_85f(cc);
613 break;
614 case ArchArgs::LFE5UM5G_25F:
615 BaseConfigs::config_empty_lfe5um5g_25f(cc);
616 break;
617 case ArchArgs::LFE5UM5G_45F:
618 BaseConfigs::config_empty_lfe5um5g_45f(cc);
619 break;
620 case ArchArgs::LFE5UM5G_85F:
621 BaseConfigs::config_empty_lfe5um5g_85f(cc);
622 break;
623 default:
624 NPNR_ASSERT_FALSE("Unsupported device type");
625 }
626 }
627
628 cc.metadata.push_back("Part: " + ctx->getFullChipName());
629
630 // Clear out DCU tieoffs in base config if DCU used
631 for (auto &cell : ctx->cells) {
632 CellInfo *ci = cell.second.get();
633 if (ci->type == id_DCUA) {
634 Loc loc = ctx->getBelLocation(ci->bel);
635 for (int i = 0; i < 12; i++) {
636 auto tiles = ctx->getTilesAtLocation(loc.y - 1, loc.x + i);
637 for (const auto &tile : tiles) {
638 auto cc_tile = cc.tiles.find(tile.first);
639 if (cc_tile != cc.tiles.end()) {
640 cc_tile->second.cenums.clear();
641 cc_tile->second.cunknowns.clear();
642 }
643 }
644 }
645 }
646 }
647 // Add all set, configurable pips to the config
648 for (auto pip : ctx->getPips()) {
649 if (ctx->getBoundPipNet(pip) != nullptr) {
650 if (ctx->getPipClass(pip) == 0) { // ignore fixed pips
651 std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
652 if (source.find("CLKI_PLL") != std::string::npos) {
653 // Special case - must set pip in all relevant tiles
654 for (auto equiv_pip : ctx->getPipsUphill(ctx->getPipDstWire(pip))) {
655 if (ctx->getPipSrcWire(equiv_pip) == ctx->getPipSrcWire(pip))
656 set_pip(ctx, cc, equiv_pip);
657 }
658 } else {
659 set_pip(ctx, cc, pip);
660 }
661 }
662 }
663 }
664 // Find bank voltages
665 std::unordered_map<int, IOVoltage> bankVcc;
666 std::unordered_map<int, bool> bankLvds, bankVref, bankDiff;
667
668 for (auto &cell : ctx->cells) {
669 CellInfo *ci = cell.second.get();
670 if (ci->bel != BelId() && ci->type == ctx->id("TRELLIS_IO")) {
671 int bank = ctx->getPioBelBank(ci->bel);
672 std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
673 std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
674
675 if (dir != "INPUT" || is_referenced(ioType_from_str(iotype))) {
676 IOVoltage vcc = get_vccio(ioType_from_str(iotype));
677 if (bankVcc.find(bank) != bankVcc.end()) {
678 // TODO: strong and weak constraints
679 if (bankVcc[bank] != vcc) {
680 log_error("Error processing '%s': incompatible IO voltages %s and %s on bank %d.",
681 cell.first.c_str(ctx), iovoltage_to_str(bankVcc[bank]).c_str(),
682 iovoltage_to_str(vcc).c_str(), bank);
683 }
684 } else {
685 bankVcc[bank] = vcc;
686 }
687 }
688
689 if (iotype == "LVDS")
690 bankLvds[bank] = true;
691 if ((dir == "INPUT" || dir == "BIDIR") && is_differential(ioType_from_str(iotype)))
692 bankDiff[bank] = true;
693 if ((dir == "INPUT" || dir == "BIDIR") && is_referenced(ioType_from_str(iotype)))
694 bankVref[bank] = true;
695 }
696 }
697
698 // Set all bankref tiles to appropriate VccIO
699 for (int y = 0; y < ctx->getGridDimY(); y++) {
700 for (int x = 0; x < ctx->getGridDimX(); x++) {
701 auto tiles = ctx->getTilesAtLocation(y, x);
702 for (auto tile : tiles) {
703 std::string type = tile.second;
704 if (type.find("BANKREF") != std::string::npos) {
705 int bank = std::stoi(type.substr(7));
706 if (bank == 8 && ctx->settings.count(ctx->id("arch.sysconfig.CONFIG_IOVOLTAGE"))) {
707 std::string vcc = str_or_default(ctx->settings, ctx->id("arch.sysconfig.CONFIG_IOVOLTAGE"));
708 vcc.at(1) = 'V';
709 cc.tiles[tile.first].add_enum("BANK.VCCIO", vcc);
710 } else if (bankVcc.find(bank) != bankVcc.end()) {
711 if (bankVcc[bank] == IOVoltage::VCC_1V35)
712 cc.tiles[tile.first].add_enum("BANK.VCCIO", "1V2");
713 else
714 cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank]));
715 }
716 if (bankLvds[bank]) {
717 cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
718 cc.tiles[tile.first].add_enum("BANK.LVDSO", "ON");
719 }
720 if (bankDiff[bank]) {
721 cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
722 }
723 if (bankVref[bank]) {
724 cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
725 cc.tiles[tile.first].add_enum("BANK.VREF", "ON");
726 }
727 }
728 }
729 }
730 }
731
732 // Create dummy outputs used as Vref input buffer for banks where Vref is used
733 for (auto bv : bankVref) {
734 if (!bv.second)
735 continue;
736 BelId vrefIO = ctx->getPioByFunctionName(fmt_str("VREF1_" << bv.first));
737 if (vrefIO == BelId())
738 log_error("unable to find VREF input for bank %d\n", bv.first);
739 if (!ctx->checkBelAvail(vrefIO)) {
740 CellInfo *bound = ctx->getBoundBelCell(vrefIO);
741 if (bound != nullptr)
742 log_error("VREF pin %s of bank %d is occupied by IO '%s'\n", ctx->getBelPackagePin(vrefIO).c_str(),
743 bv.first, bound->name.c_str(ctx));
744 else
745 log_error("VREF pin %s of bank %d is unavailable\n", ctx->getBelPackagePin(vrefIO).c_str(), bv.first);
746 }
747 log_info("Using pin %s as VREF for bank %d\n", ctx->getBelPackagePin(vrefIO).c_str(), bv.first);
748 std::string pio_tile = get_pio_tile(ctx, vrefIO);
749
750 std::string iotype;
751 switch (bankVcc[bv.first]) {
752 case IOVoltage::VCC_1V2:
753 iotype = "HSUL12";
754 break;
755 case IOVoltage::VCC_1V35:
756 iotype = "SSTL18_I";
757 break;
758 case IOVoltage::VCC_1V5:
759 iotype = "SSTL18_I";
760 break;
761 case IOVoltage::VCC_1V8:
762 iotype = "SSTL18_I";
763 break;
764 default:
765 log_error("Referenced inputs are not supported with bank VccIO of %s.\n",
766 iovoltage_to_str(bankVcc[bv.first]).c_str());
767 }
768
769 std::string pio = ctx->locInfo(vrefIO)->bel_data[vrefIO.index].name.get();
770 cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", "OUTPUT_" + iotype);
771 cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
772 }
773
774 // Configure slices
775 for (auto &cell : ctx->cells) {
776 CellInfo *ci = cell.second.get();
777 if (ci->bel == BelId()) {
778 log_warning("found unplaced cell '%s' during bitstream gen\n", ci->name.c_str(ctx));
779 }
780 BelId bel = ci->bel;
781 if (ci->type == ctx->id("TRELLIS_SLICE")) {
782 std::string tname = ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, "PLC2");
783 std::string slice = ctx->locInfo(bel)->bel_data[bel.index].name.get();
784 int lut0_init = int_or_default(ci->params, ctx->id("LUT0_INITVAL"));
785 int lut1_init = int_or_default(ci->params, ctx->id("LUT1_INITVAL"));
786 cc.tiles[tname].add_word(slice + ".K0.INIT", int_to_bitvector(lut0_init, 16));
787 cc.tiles[tname].add_word(slice + ".K1.INIT", int_to_bitvector(lut1_init, 16));
788 cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, ctx->id("MODE"), "LOGIC"));
789 cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
790 cc.tiles[tname].add_enum(slice + ".REG0.SD", intstr_or_default(ci->params, ctx->id("REG0_SD"), "0"));
791 cc.tiles[tname].add_enum(slice + ".REG1.SD", intstr_or_default(ci->params, ctx->id("REG1_SD"), "0"));
792 cc.tiles[tname].add_enum(slice + ".REG0.REGSET",
793 str_or_default(ci->params, ctx->id("REG0_REGSET"), "RESET"));
794 cc.tiles[tname].add_enum(slice + ".REG1.REGSET",
795 str_or_default(ci->params, ctx->id("REG1_REGSET"), "RESET"));
796 cc.tiles[tname].add_enum(slice + ".REG0.LSRMODE",
797 str_or_default(ci->params, ctx->id("REG0_LSRMODE"), "LSR"));
798 cc.tiles[tname].add_enum(slice + ".REG1.LSRMODE",
799 str_or_default(ci->params, ctx->id("REG1_LSRMODE"), "LSR"));
800 cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, ctx->id("CEMUX"), "1"));
801
802 if (ci->sliceInfo.using_dff) {
803 NetInfo *lsrnet = nullptr;
804 if (ci->ports.find(ctx->id("LSR")) != ci->ports.end() && ci->ports.at(ctx->id("LSR")).net != nullptr)
805 lsrnet = ci->ports.at(ctx->id("LSR")).net;
806 if (ctx->getBoundWireNet(ctx->getWireByName(
807 ctx->id(fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/LSR0")))) == lsrnet) {
808 cc.tiles[tname].add_enum("LSR0.SRMODE",
809 str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
810 cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
811 } else if (ctx->getBoundWireNet(ctx->getWireByName(ctx->id(
812 fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/LSR1")))) == lsrnet) {
813 cc.tiles[tname].add_enum("LSR1.SRMODE",
814 str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
815 cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
816 }
817
818 NetInfo *clknet = nullptr;
819 if (ci->ports.find(ctx->id("CLK")) != ci->ports.end() && ci->ports.at(ctx->id("CLK")).net != nullptr)
820 clknet = ci->ports.at(ctx->id("CLK")).net;
821 if (ctx->getBoundWireNet(ctx->getWireByName(
822 ctx->id(fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/CLK0")))) == clknet) {
823 cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, ctx->id("CLKMUX"), "CLK"));
824 } else if (ctx->getBoundWireNet(ctx->getWireByName(ctx->id(
825 fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/CLK1")))) == clknet) {
826 cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, ctx->id("CLKMUX"), "CLK"));
827 }
828 }
829
830 if (str_or_default(ci->params, ctx->id("MODE"), "LOGIC") == "CCU2") {
831 cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_0",
832 str_or_default(ci->params, ctx->id("CCU2_INJECT1_0"), "YES"));
833 cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_1",
834 str_or_default(ci->params, ctx->id("CCU2_INJECT1_1"), "YES"));
835 } else {
836 // Don't interfere with cascade mux wiring
837 cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_0", "_NONE_");
838 cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_1", "_NONE_");
839 }
840
841 if (str_or_default(ci->params, ctx->id("MODE"), "LOGIC") == "DPRAM" && slice == "SLICEA") {
842 cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, ctx->id("WREMUX"), "WRE"));
843
844 std::string wckmux = str_or_default(ci->params, ctx->id("WCKMUX"), "WCK");
845 wckmux = (wckmux == "WCK") ? "CLK" : wckmux;
846 cc.tiles[tname].add_enum("CLK1.CLKMUX", wckmux);
847 }
848
849 // Tie unused inputs high
850 for (auto input : {id_A0, id_B0, id_C0, id_D0, id_A1, id_B1, id_C1, id_D1}) {
851 if (ci->ports.find(input) == ci->ports.end() || ci->ports.at(input).net == nullptr) {
852 cc.tiles[tname].add_enum(slice + "." + input.str(ctx) + "MUX", "1");
853 }
854 }
855
856 // TODO: CLKMUX
857 } else if (ci->type == ctx->id("TRELLIS_IO")) {
858 std::string pio = ctx->locInfo(bel)->bel_data[bel.index].name.get();
859 std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
860 std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
861 std::string pio_tile = get_pio_tile(ctx, bel);
862 std::string pic_tile = get_pic_tile(ctx, bel);
863 cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
864 cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
865 if (is_differential(ioType_from_str(iotype))) {
866 if (bel.location.y == 0) {
867 // Pseudo differential top IO
868 NPNR_ASSERT(dir == "OUTPUT");
869 NPNR_ASSERT(pio == "PIOA");
870 std::string cpio_tile = get_comp_pio_tile(ctx, bel);
871 std::string cpic_tile = get_comp_pic_tile(ctx, bel);
872 cc.tiles[cpio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
873 cc.tiles[cpic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
874 } else {
875 // Explicitly disable other pair
876 std::string other;
877 if (pio == "PIOA")
878 other = "PIOB";
879 else if (pio == "PIOC")
880 other = "PIOD";
881 else
882 log_error("cannot place differential IO at location %s\n", pio.c_str());
883 // cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
884 // cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
885 cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE");
886 cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
887 }
888
889 } else if (is_referenced(ioType_from_str(iotype))) {
890 cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
891 }
892 if (dir != "INPUT" &&
893 (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr) &&
894 (ci->ports.find(ctx->id("IOLTO")) == ci->ports.end() ||
895 ci->ports.at(ctx->id("IOLTO")).net == nullptr)) {
896 // Tie tristate low if unconnected for outputs or bidir
897 std::string jpt = fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/JPADDT" << pio.back());
898 WireId jpt_wire = ctx->getWireByName(ctx->id(jpt));
899 PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin();
900 WireId cib_wire = ctx->getPipSrcWire(jpt_pip);
901 std::string cib_tile =
902 ctx->getTileByTypeAndLocation(cib_wire.location.y, cib_wire.location.x, cib_tiles);
903 std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get();
904 cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0");
905 }
906 if ((dir == "INPUT" || dir == "BIDIR") && !is_differential(ioType_from_str(iotype)) &&
907 !is_referenced(ioType_from_str(iotype))) {
908 cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS",
909 str_or_default(ci->attrs, ctx->id("HYSTERESIS"), "ON"));
910 }
911 if (ci->attrs.count(ctx->id("SLEWRATE")) && !is_referenced(ioType_from_str(iotype)))
912 cc.tiles[pio_tile].add_enum(pio + ".SLEWRATE", str_or_default(ci->attrs, ctx->id("SLEWRATE"), "SLOW"));
913 if (ci->attrs.count(ctx->id("PULLMODE")))
914 cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", str_or_default(ci->attrs, ctx->id("PULLMODE"), "NONE"));
915 if (ci->attrs.count(ctx->id("DIFFRESISTOR")))
916 cc.tiles[pio_tile].add_enum(pio + ".DIFFRESISTOR",
917 str_or_default(ci->attrs, ctx->id("DIFFRESISTOR"), "OFF"));
918 if (ci->attrs.count(ctx->id("DRIVE"))) {
919 static bool drive_3v3_warning_done = false;
920 if (iotype == "LVCMOS33") {
921 cc.tiles[pio_tile].add_enum(pio + ".DRIVE", str_or_default(ci->attrs, ctx->id("DRIVE"), "8"));
922 } else if (iotype == "LVCMOS33D") {
923 if (bel.location.y == 0) {
924 // Pseudo differential top IO
925 NPNR_ASSERT(dir == "OUTPUT");
926 NPNR_ASSERT(pio == "PIOA");
927 std::string cpio_tile = get_comp_pio_tile(ctx, bel);
928 cc.tiles[pio_tile].add_enum("PIOA.DRIVE", str_or_default(ci->attrs, ctx->id("DRIVE"), "12"));
929 cc.tiles[cpio_tile].add_enum("PIOB.DRIVE", str_or_default(ci->attrs, ctx->id("DRIVE"), "12"));
930 } else {
931 std::string other;
932 if (pio == "PIOA")
933 other = "PIOB";
934 else if (pio == "PIOC")
935 other = "PIOD";
936 else
937 log_error("cannot set DRIVE on differential IO at location %s\n", pio.c_str());
938 cc.tiles[pio_tile].add_enum(pio + ".DRIVE", str_or_default(ci->attrs, ctx->id("DRIVE"), "12"));
939 cc.tiles[pio_tile].add_enum(other + ".DRIVE",
940 str_or_default(ci->attrs, ctx->id("DRIVE"), "12"));
941 }
942 } else {
943 if (!drive_3v3_warning_done)
944 log_warning("Trellis limitation: DRIVE can only be set on 3V3 IO pins.\n");
945 drive_3v3_warning_done = true;
946 }
947 }
948 if (ci->attrs.count(ctx->id("TERMINATION"))) {
949 auto vccio = get_vccio(ioType_from_str(iotype));
950 switch (vccio) {
951 case IOVoltage::VCC_1V8:
952 cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V8",
953 str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
954 break;
955 case IOVoltage::VCC_1V5:
956 cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V5",
957 str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
958 break;
959 case IOVoltage::VCC_1V35:
960 cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V35",
961 str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
962 break;
963 default:
964 log_error("TERMINATION is not supported with Vcc = %s (on PIO %s)\n",
965 iovoltage_to_str(vccio).c_str(), ci->name.c_str(ctx));
966 }
967 }
968 if (ci->attrs.count(ctx->id("OPENDRAIN")))
969 cc.tiles[pio_tile].add_enum(pio + ".OPENDRAIN", str_or_default(ci->attrs, ctx->id("OPENDRAIN"), "OFF"));
970 std::string datamux_oddr = str_or_default(ci->params, ctx->id("DATAMUX_ODDR"), "PADDO");
971 if (datamux_oddr != "PADDO")
972 cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_ODDR", datamux_oddr);
973 std::string datamux_oreg = str_or_default(ci->params, ctx->id("DATAMUX_OREG"), "PADDO");
974 if (datamux_oreg != "PADDO")
975 cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_OREG", datamux_oreg);
976 std::string datamux_mddr = str_or_default(ci->params, ctx->id("DATAMUX_MDDR"), "PADDO");
977 if (datamux_mddr != "PADDO")
978 cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_MDDR", datamux_mddr);
979 std::string trimux_tsreg = str_or_default(ci->params, ctx->id("TRIMUX_TSREG"), "PADDT");
980 if (trimux_tsreg != "PADDT")
981 cc.tiles[pic_tile].add_enum(pio + ".TRIMUX_TSREG", trimux_tsreg);
982 } else if (ci->type == ctx->id("DCCA")) {
983 const NetInfo *cen = get_net_or_empty(ci, ctx->id("CE"));
984 if (cen != nullptr) {
985 std::string belname = ctx->locInfo(bel)->bel_data[bel.index].name.get();
986 Loc loc = ctx->getBelLocation(bel);
987 TileGroup tg;
988 switch (belname[0]) {
989 case 'B':
990 tg.tiles.push_back(
991 ctx->getTileByTypeAndLocation(loc.y, loc.x, std::set<std::string>{"BMID_0H", "BMID_0V"}));
992 tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1,
993 std::set<std::string>{"BMID_2", "BMID_2V"}));
994 break;
995 case 'T':
996 tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "TMID_0"));
997 tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "TMID_1"));
998 break;
999 case 'L':
1000 tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "LMID_0"));
1001 break;
1002 case 'R':
1003 tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "RMID_0"));
1004 break;
1005 default:
1006 NPNR_ASSERT_FALSE("bad DCC for gating");
1007 break;
1008 }
1009 tg.config.add_enum(std::string("DCC_") + belname[0] + belname.substr(4) + ".MODE", "DCCA");
1010 cc.tilegroups.push_back(tg);
1011 }
1012 } else if (ci->type == ctx->id("DP16KD")) {
1013 TileGroup tg;
1014 Loc loc = ctx->getBelLocation(ci->bel);
1015 tg.tiles = get_bram_tiles(ctx, ci->bel);
1016 std::string ebr = "EBR" + std::to_string(loc.z);
1017
1018 if (ci->ramInfo.is_pdp) {
1019 tg.config.add_enum(ebr + ".MODE", "PDPW16KD");
1020 tg.config.add_enum(ebr + ".PDPW16KD.DATA_WIDTH_R",
1021 intstr_or_default(ci->params, ctx->id("DATA_WIDTH_B"), "36"));
1022 } else {
1023 tg.config.add_enum(ebr + ".MODE", "DP16KD");
1024 tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_A",
1025 intstr_or_default(ci->params, ctx->id("DATA_WIDTH_A"), "18"));
1026 tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_B",
1027 intstr_or_default(ci->params, ctx->id("DATA_WIDTH_B"), "18"));
1028 tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_A",
1029 str_or_default(ci->params, ctx->id("WRITEMODE_A"), "NORMAL"));
1030 tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_B",
1031 str_or_default(ci->params, ctx->id("WRITEMODE_B"), "NORMAL"));
1032 }
1033
1034 auto csd_a = str_to_bitvector(str_or_default(ci->params, ctx->id("CSDECODE_A"), "0b000"), 3),
1035 csd_b = str_to_bitvector(str_or_default(ci->params, ctx->id("CSDECODE_B"), "0b000"), 3);
1036
1037 tg.config.add_enum(ebr + ".REGMODE_A", str_or_default(ci->params, ctx->id("REGMODE_A"), "NOREG"));
1038 tg.config.add_enum(ebr + ".REGMODE_B", str_or_default(ci->params, ctx->id("REGMODE_B"), "NOREG"));
1039
1040 tg.config.add_enum(ebr + ".RESETMODE", str_or_default(ci->params, ctx->id("RESETMODE"), "SYNC"));
1041 tg.config.add_enum(ebr + ".ASYNC_RESET_RELEASE",
1042 str_or_default(ci->params, ctx->id("ASYNC_RESET_RELEASE"), "SYNC"));
1043 tg.config.add_enum(ebr + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
1044
1045 tg.config.add_word(ebr + ".WID",
1046 int_to_bitvector(bit_reverse(int_or_default(ci->attrs, ctx->id("WID"), 0), 9), 9));
1047
1048 // Tie signals as appropriate
1049 for (auto port : ci->ports) {
1050 if (ci->ramInfo.is_pdp && (port.first == id_WEA || port.first == id_WEB || port.first == id_ADA4))
1051 continue;
1052 if (port.second.net == nullptr && port.second.type == PORT_IN) {
1053 if (port.first == id_CLKA || port.first == id_CLKB || port.first == id_WEA ||
1054 port.first == id_WEB || port.first == id_RSTA || port.first == id_RSTB) {
1055 // CIB clock or LSR. Tie to "1" (also 0 in prjtrellis db?) in CIB
1056 // If MUX doesn't exist, set to INV to emulate default 0
1057 tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true);
1058 if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
1059 ci->params[ctx->id(port.first.str(ctx) + "MUX")] = std::string("INV");
1060 } else if (port.first == id_CEA || port.first == id_CEB || port.first == id_OCEA ||
1061 port.first == id_OCEB) {
1062 // CIB CE. Tie to "1" in CIB
1063 // If MUX doesn't exist, set to passthru to emulate default 1
1064 tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true);
1065 if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
1066 ci->params[ctx->id(port.first.str(ctx) + "MUX")] = port.first.str(ctx);
1067 } else if (port.first == id_CSA0 || port.first == id_CSA1 || port.first == id_CSA2 ||
1068 port.first == id_CSB0 || port.first == id_CSB1 || port.first == id_CSB2) {
1069 // CIB CE. Tie to "1" in CIB.
1070 // If MUX doesn't exist, set to INV to emulate default 0
1071 tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true);
1072 if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
1073 ci->params[ctx->id(port.first.str(ctx) + "MUX")] = std::string("INV");
1074 } else {
1075 // CIB ABCD signal
1076 // Tie signals low unless explicit MUX param specified
1077 bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false);
1078 tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), value);
1079 }
1080 }
1081 }
1082
1083 // Invert CSDECODE bits to emulate inversion muxes on CSA/CSB signals
1084 for (auto &port : {std::make_pair("CSA", std::ref(csd_a)), std::make_pair("CSB", std::ref(csd_b))}) {
1085 for (int bit = 0; bit < 3; bit++) {
1086 std::string sig = port.first + std::to_string(bit);
1087 if (str_or_default(ci->params, ctx->id(sig + "MUX"), sig) == "INV")
1088 port.second.at(bit) = !port.second.at(bit);
1089 }
1090 }
1091
1092 tg.config.add_enum(ebr + ".CLKAMUX", str_or_default(ci->params, ctx->id("CLKAMUX"), "CLKA"));
1093 tg.config.add_enum(ebr + ".CLKBMUX", str_or_default(ci->params, ctx->id("CLKBMUX"), "CLKB"));
1094
1095 tg.config.add_enum(ebr + ".RSTAMUX", str_or_default(ci->params, ctx->id("RSTAMUX"), "RSTA"));
1096 tg.config.add_enum(ebr + ".RSTBMUX", str_or_default(ci->params, ctx->id("RSTBMUX"), "RSTB"));
1097 if (!ci->ramInfo.is_pdp) {
1098 tg.config.add_enum(ebr + ".WEAMUX", str_or_default(ci->params, ctx->id("WEAMUX"), "WEA"));
1099 tg.config.add_enum(ebr + ".WEBMUX", str_or_default(ci->params, ctx->id("WEBMUX"), "WEB"));
1100 }
1101 tg.config.add_enum(ebr + ".CEAMUX", str_or_default(ci->params, ctx->id("CEAMUX"), "CEA"));
1102 tg.config.add_enum(ebr + ".CEBMUX", str_or_default(ci->params, ctx->id("CEBMUX"), "CEB"));
1103 tg.config.add_enum(ebr + ".OCEAMUX", str_or_default(ci->params, ctx->id("OCEAMUX"), "OCEA"));
1104 tg.config.add_enum(ebr + ".OCEBMUX", str_or_default(ci->params, ctx->id("OCEBMUX"), "OCEB"));
1105
1106 std::reverse(csd_a.begin(), csd_a.end());
1107 std::reverse(csd_b.begin(), csd_b.end());
1108
1109 tg.config.add_word(ebr + ".CSDECODE_A", csd_a);
1110 tg.config.add_word(ebr + ".CSDECODE_B", csd_b);
1111
1112 std::vector<uint16_t> init_data;
1113 init_data.resize(2048, 0x0);
1114 // INIT_00 .. INIT_3F
1115 for (int i = 0; i <= 0x3F; i++) {
1116 IdString param = ctx->id("INITVAL_" +
1117 fmt_str(std::hex << std::uppercase << std::setw(2) << std::setfill('0') << i));
1118 auto value = parse_init_str(get_or_default(ci->params, param, Property(0)), 320, ci->name.c_str(ctx));
1119 for (int j = 0; j < 16; j++) {
1120 // INIT parameter consists of 16 18-bit words with 2-bit padding
1121 int ofs = 20 * j;
1122 for (int k = 0; k < 18; k++) {
1123 if (value.at(ofs + k))
1124 init_data.at(i * 32 + j * 2 + (k / 9)) |= (1 << (k % 9));
1125 }
1126 }
1127 }
1128 int wid = int_or_default(ci->attrs, ctx->id("WID"), 0);
1129 NPNR_ASSERT(!cc.bram_data.count(wid));
1130 cc.bram_data[wid] = init_data;
1131 cc.tilegroups.push_back(tg);
1132 } else if (ci->type == id_MULT18X18D) {
1133 TileGroup tg;
1134 Loc loc = ctx->getBelLocation(ci->bel);
1135 tg.tiles = get_dsp_tiles(ctx, ci->bel);
1136 std::string dsp = "MULT18_" + std::to_string(loc.z);
1137 tg.config.add_enum(dsp + ".REG_INPUTA_CLK", str_or_default(ci->params, ctx->id("REG_INPUTA_CLK"), "NONE"));
1138 tg.config.add_enum(dsp + ".REG_INPUTA_CE", str_or_default(ci->params, ctx->id("REG_INPUTA_CE"), "CE0"));
1139 tg.config.add_enum(dsp + ".REG_INPUTA_RST", str_or_default(ci->params, ctx->id("REG_INPUTA_RST"), "RST0"));
1140 tg.config.add_enum(dsp + ".REG_INPUTB_CLK", str_or_default(ci->params, ctx->id("REG_INPUTB_CLK"), "NONE"));
1141 tg.config.add_enum(dsp + ".REG_INPUTB_CE", str_or_default(ci->params, ctx->id("REG_INPUTB_CE"), "CE0"));
1142 tg.config.add_enum(dsp + ".REG_INPUTB_RST", str_or_default(ci->params, ctx->id("REG_INPUTB_RST"), "RST0"));
1143 tg.config.add_enum(dsp + ".REG_INPUTC_CLK", str_or_default(ci->params, ctx->id("REG_INPUTC_CLK"), "NONE"));
1144 tg.config.add_enum(dsp + ".REG_PIPELINE_CLK",
1145 str_or_default(ci->params, ctx->id("REG_PIPELINE_CLK"), "NONE"));
1146 tg.config.add_enum(dsp + ".REG_PIPELINE_CE", str_or_default(ci->params, ctx->id("REG_PIPELINE_CE"), "CE0"));
1147 tg.config.add_enum(dsp + ".REG_PIPELINE_RST",
1148 str_or_default(ci->params, ctx->id("REG_PIPELINE_RST"), "RST0"));
1149 tg.config.add_enum(dsp + ".REG_OUTPUT_CLK", str_or_default(ci->params, ctx->id("REG_OUTPUT_CLK"), "NONE"));
1150 if (dsp == "MULT18_0" || dsp == "MULT18_4")
1151 tg.config.add_enum(dsp + ".REG_OUTPUT_RST",
1152 str_or_default(ci->params, ctx->id("REG_OUTPUT_RST"), "RST0"));
1153
1154 tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, ctx->id("CLK0_DIV"), "ENABLED"));
1155 tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, ctx->id("CLK1_DIV"), "ENABLED"));
1156 tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, ctx->id("CLK2_DIV"), "ENABLED"));
1157 tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, ctx->id("CLK3_DIV"), "ENABLED"));
1158 tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
1159 tg.config.add_enum(dsp + ".SOURCEB_MODE", str_or_default(ci->params, ctx->id("SOURCEB_MODE"), "B_SHIFT"));
1160 tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, ctx->id("RESETMODE"), "SYNC"));
1161
1162 tg.config.add_enum(dsp + ".MODE", "MULT18X18D");
1163 if (str_or_default(ci->params, ctx->id("REG_OUTPUT_CLK"), "NONE") == "NONE")
1164 tg.config.add_enum(dsp + ".CIBOUT_BYP", "ON");
1165
1166 if (loc.z < 4)
1167 tg.config.add_enum("DSP_LEFT.CIBOUT", "ON");
1168 else
1169 tg.config.add_enum("DSP_RIGHT.CIBOUT", "ON");
1170
1171 // Some muxes default to INV, make all pass-thru
1172 for (auto port : {"CLK", "CE", "RST"}) {
1173 for (int i = 0; i < 4; i++) {
1174 std::string sig = port + std::to_string(i);
1175 tg.config.add_enum(dsp + "." + sig + "MUX", sig);
1176 }
1177 }
1178
1179 tieoff_dsp_ports(ctx, cc, ci);
1180 cc.tilegroups.push_back(tg);
1181
1182 } else if (ci->type == id_ALU54B) {
1183 TileGroup tg;
1184 Loc loc = ctx->getBelLocation(ci->bel);
1185 tg.tiles = get_dsp_tiles(ctx, ci->bel);
1186 std::string dsp = "ALU54_" + std::to_string(loc.z);
1187 tg.config.add_enum(dsp + ".REG_INPUTC0_CLK",
1188 str_or_default(ci->params, ctx->id("REG_INPUTC0_CLK"), "NONE"));
1189 tg.config.add_enum(dsp + ".REG_INPUTC1_CLK",
1190 str_or_default(ci->params, ctx->id("REG_INPUTC1_CLK"), "NONE"));
1191 tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CLK",
1192 str_or_default(ci->params, ctx->id("REG_OPCODEOP0_0_CLK"), "NONE"));
1193 tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CE",
1194 str_or_default(ci->params, ctx->id("REG_OPCODEOP0_0_CE"), "CE0"));
1195 tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_RST",
1196 str_or_default(ci->params, ctx->id("REG_OPCODEOP0_0_RST"), "RST0"));
1197 tg.config.add_enum(dsp + ".REG_OPCODEOP1_0_CLK",
1198 str_or_default(ci->params, ctx->id("REG_OPCODEOP1_0_CLK"), "NONE"));
1199 tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CLK",
1200 str_or_default(ci->params, ctx->id("REG_OPCODEOP0_1_CLK"), "NONE"));
1201 tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CE",
1202 str_or_default(ci->params, ctx->id("REG_OPCODEOP0_1_CE"), "CE0"));
1203 tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_RST",
1204 str_or_default(ci->params, ctx->id("REG_OPCODEOP0_1_RST"), "RST0"));
1205 tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CLK",
1206 str_or_default(ci->params, ctx->id("REG_OPCODEIN_0_CLK"), "NONE"));
1207 tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CE",
1208 str_or_default(ci->params, ctx->id("REG_OPCODEIN_0_CE"), "CE0"));
1209 tg.config.add_enum(dsp + ".REG_OPCODEIN_0_RST",
1210 str_or_default(ci->params, ctx->id("REG_OPCODEIN_0_RST"), "RST0"));
1211 tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CLK",
1212 str_or_default(ci->params, ctx->id("REG_OPCODEIN_1_CLK"), "NONE"));
1213 tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CE",
1214 str_or_default(ci->params, ctx->id("REG_OPCODEIN_1_CE"), "CE0"));
1215 tg.config.add_enum(dsp + ".REG_OPCODEIN_1_RST",
1216 str_or_default(ci->params, ctx->id("REG_OPCODEIN_1_RST"), "RST0"));
1217 tg.config.add_enum(dsp + ".REG_OUTPUT0_CLK",
1218 str_or_default(ci->params, ctx->id("REG_OUTPUT0_CLK"), "NONE"));
1219 tg.config.add_enum(dsp + ".REG_OUTPUT1_CLK",
1220 str_or_default(ci->params, ctx->id("REG_OUTPUT1_CLK"), "NONE"));
1221 tg.config.add_enum(dsp + ".REG_FLAG_CLK", str_or_default(ci->params, ctx->id("REG_FLAG_CLK"), "NONE"));
1222 tg.config.add_enum(dsp + ".MCPAT_SOURCE", str_or_default(ci->params, ctx->id("MCPAT_SOURCE"), "STATIC"));
1223 tg.config.add_enum(dsp + ".MASKPAT_SOURCE",
1224 str_or_default(ci->params, ctx->id("MASKPAT_SOURCE"), "STATIC"));
1225 tg.config.add_word(dsp + ".MASK01",
1226 parse_init_str(str_or_default(ci->params, ctx->id("MASK01"), "0x00000000000000"), 56,
1227 ci->name.c_str(ctx)));
1228 tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, ctx->id("CLK0_DIV"), "ENABLED"));
1229 tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, ctx->id("CLK1_DIV"), "ENABLED"));
1230 tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, ctx->id("CLK2_DIV"), "ENABLED"));
1231 tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, ctx->id("CLK3_DIV"), "ENABLED"));
1232 tg.config.add_word(dsp + ".MCPAT",
1233 parse_init_str(str_or_default(ci->params, ctx->id("MCPAT"), "0x00000000000000"), 56,
1234 ci->name.c_str(ctx)));
1235 tg.config.add_word(dsp + ".MASKPAT",
1236 parse_init_str(str_or_default(ci->params, ctx->id("MASKPAT"), "0x00000000000000"), 56,
1237 ci->name.c_str(ctx)));
1238 tg.config.add_word(dsp + ".RNDPAT",
1239 parse_init_str(str_or_default(ci->params, ctx->id("RNDPAT"), "0x00000000000000"), 56,
1240 ci->name.c_str(ctx)));
1241 tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
1242 tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, ctx->id("RESETMODE"), "SYNC"));
1243 tg.config.add_enum(dsp + ".FORCE_ZERO_BARREL_SHIFT",
1244 str_or_default(ci->params, ctx->id("FORCE_ZERO_BARREL_SHIFT"), "DISABLED"));
1245 tg.config.add_enum(dsp + ".LEGACY", str_or_default(ci->params, ctx->id("LEGACY"), "DISABLED"));
1246
1247 tg.config.add_enum(dsp + ".MODE", "ALU54B");
1248
1249 if (loc.z < 4)
1250 tg.config.add_enum("DSP_LEFT.CIBOUT", "ON");
1251 else
1252 tg.config.add_enum("DSP_RIGHT.CIBOUT", "ON");
1253 if (str_or_default(ci->params, ctx->id("REG_FLAG_CLK"), "NONE") == "NONE") {
1254 if (dsp == "ALU54_7") {
1255 tg.config.add_enum("MULT18_5.CIBOUT_BYP", "ON");
1256 } else if (dsp == "ALU54_3") {
1257 tg.config.add_enum("MULT18_5.CIBOUT_BYP", "ON");
1258 }
1259 }
1260 if (str_or_default(ci->params, ctx->id("REG_OUTPUT0_CLK"), "NONE") == "NONE") {
1261 if (dsp == "ALU54_7") {
1262 tg.config.add_enum("MULT18_4.CIBOUT_BYP", "ON");
1263 } else if (dsp == "ALU54_3") {
1264 tg.config.add_enum("MULT18_0.CIBOUT_BYP", "ON");
1265 }
1266 }
1267 tieoff_dsp_ports(ctx, cc, ci);
1268 cc.tilegroups.push_back(tg);
1269 } else if (ci->type == id_EHXPLLL) {
1270 TileGroup tg;
1271 tg.tiles = get_pll_tiles(ctx, ci->bel);
1272
1273 tg.config.add_enum("MODE", "EHXPLLL");
1274
1275 tg.config.add_word("CLKI_DIV", int_to_bitvector(int_or_default(ci->params, ctx->id("CLKI_DIV"), 1) - 1, 7));
1276 tg.config.add_word("CLKFB_DIV",
1277 int_to_bitvector(int_or_default(ci->params, ctx->id("CLKFB_DIV"), 1) - 1, 7));
1278
1279 tg.config.add_enum("CLKOP_ENABLE", str_or_default(ci->params, ctx->id("CLKOP_ENABLE"), "ENABLED"));
1280 tg.config.add_enum("CLKOS_ENABLE", str_or_default(ci->params, ctx->id("CLKOS_ENABLE"), "ENABLED"));
1281 tg.config.add_enum("CLKOS2_ENABLE", str_or_default(ci->params, ctx->id("CLKOS2_ENABLE"), "ENABLED"));
1282 tg.config.add_enum("CLKOS3_ENABLE", str_or_default(ci->params, ctx->id("CLKOS3_ENABLE"), "ENABLED"));
1283
1284 for (std::string out : {"CLKOP", "CLKOS", "CLKOS2", "CLKOS3"}) {
1285 tg.config.add_word(out + "_DIV",
1286 int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_DIV"), 8) - 1, 7));
1287 tg.config.add_word(out + "_CPHASE",
1288 int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_CPHASE"), 0), 7));
1289 tg.config.add_word(out + "_FPHASE",
1290 int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_FPHASE"), 0), 3));
1291 }
1292
1293 tg.config.add_enum("FEEDBK_PATH", str_or_default(ci->params, ctx->id("FEEDBK_PATH"), "CLKOP"));
1294 tg.config.add_enum("CLKOP_TRIM_POL", str_or_default(ci->params, ctx->id("CLKOP_TRIM_POL"), "RISING"));
1295
1296 tg.config.add_enum("CLKOP_TRIM_DELAY", intstr_or_default(ci->params, ctx->id("CLKOP_TRIM_DELAY"), "0"));
1297
1298 tg.config.add_enum("CLKOS_TRIM_POL", str_or_default(ci->params, ctx->id("CLKOS_TRIM_POL"), "RISING"));
1299
1300 tg.config.add_enum("CLKOS_TRIM_DELAY", intstr_or_default(ci->params, ctx->id("CLKOS_TRIM_DELAY"), "0"));
1301
1302 tg.config.add_enum("OUTDIVIDER_MUXA", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXA"),
1303 get_net_or_empty(ci, id_CLKOP) ? "DIVA" : "REFCLK"));
1304 tg.config.add_enum("OUTDIVIDER_MUXB", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXB"),
1305 get_net_or_empty(ci, id_CLKOP) ? "DIVB" : "REFCLK"));
1306 tg.config.add_enum("OUTDIVIDER_MUXC", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXC"),
1307 get_net_or_empty(ci, id_CLKOP) ? "DIVC" : "REFCLK"));
1308 tg.config.add_enum("OUTDIVIDER_MUXD", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXD"),
1309 get_net_or_empty(ci, id_CLKOP) ? "DIVD" : "REFCLK"));
1310
1311 tg.config.add_word("PLL_LOCK_MODE",
1312 int_to_bitvector(int_or_default(ci->params, ctx->id("PLL_LOCK_MODE"), 0), 3));
1313
1314 tg.config.add_enum("STDBY_ENABLE", str_or_default(ci->params, ctx->id("STDBY_ENABLE"), "DISABLED"));
1315 tg.config.add_enum("REFIN_RESET", str_or_default(ci->params, ctx->id("REFIN_RESET"), "DISABLED"));
1316 tg.config.add_enum("SYNC_ENABLE", str_or_default(ci->params, ctx->id("SYNC_ENABLE"), "DISABLED"));
1317 tg.config.add_enum("INT_LOCK_STICKY", str_or_default(ci->params, ctx->id("INT_LOCK_STICKY"), "ENABLED"));
1318 tg.config.add_enum("DPHASE_SOURCE", str_or_default(ci->params, ctx->id("DPHASE_SOURCE"), "DISABLED"));
1319 tg.config.add_enum("PLLRST_ENA", str_or_default(ci->params, ctx->id("PLLRST_ENA"), "DISABLED"));
1320 tg.config.add_enum("INTFB_WAKE", str_or_default(ci->params, ctx->id("INTFB_WAKE"), "DISABLED"));
1321
1322 tg.config.add_word("KVCO", int_to_bitvector(int_or_default(ci->attrs, ctx->id("KVCO"), 0), 3));
1323 tg.config.add_word("LPF_CAPACITOR",
1324 int_to_bitvector(int_or_default(ci->attrs, ctx->id("LPF_CAPACITOR"), 0), 2));
1325 tg.config.add_word("LPF_RESISTOR",
1326 int_to_bitvector(int_or_default(ci->attrs, ctx->id("LPF_RESISTOR"), 0), 7));
1327 tg.config.add_word("ICP_CURRENT",
1328 int_to_bitvector(int_or_default(ci->attrs, ctx->id("ICP_CURRENT"), 0), 5));
1329 tg.config.add_word("FREQ_LOCK_ACCURACY",
1330 int_to_bitvector(int_or_default(ci->attrs, ctx->id("FREQ_LOCK_ACCURACY"), 0), 2));
1331
1332 tg.config.add_word("MFG_GMC_GAIN",
1333 int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_GAIN"), 0), 3));
1334 tg.config.add_word("MFG_GMC_TEST",
1335 int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_TEST"), 14), 4));
1336 tg.config.add_word("MFG1_TEST", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG1_TEST"), 0), 3));
1337 tg.config.add_word("MFG2_TEST", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG2_TEST"), 0), 3));
1338
1339 tg.config.add_word("MFG_FORCE_VFILTER",
1340 int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_FORCE_VFILTER"), 0), 1));
1341 tg.config.add_word("MFG_ICP_TEST",
1342 int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_ICP_TEST"), 0), 1));
1343 tg.config.add_word("MFG_EN_UP", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_EN_UP"), 0), 1));
1344 tg.config.add_word("MFG_FLOAT_ICP",
1345 int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_FLOAT_ICP"), 0), 1));
1346 tg.config.add_word("MFG_GMC_PRESET",
1347 int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_PRESET"), 0), 1));
1348 tg.config.add_word("MFG_LF_PRESET",
1349 int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_PRESET"), 0), 1));
1350 tg.config.add_word("MFG_GMC_RESET",
1351 int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_RESET"), 0), 1));
1352 tg.config.add_word("MFG_LF_RESET",
1353 int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_RESET"), 0), 1));
1354 tg.config.add_word("MFG_LF_RESGRND",
1355 int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_RESGRND"), 0), 1));
1356 tg.config.add_word("MFG_GMCREF_SEL",
1357 int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMCREF_SEL"), 0), 2));
1358 tg.config.add_word("MFG_ENABLE_FILTEROPAMP",
1359 int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_ENABLE_FILTEROPAMP"), 0), 1));
1360
1361 cc.tilegroups.push_back(tg);
1362 } else if (ci->type == id_IOLOGIC || ci->type == id_SIOLOGIC) {
1363 Loc pio_loc = ctx->getBelLocation(ci->bel);
1364 pio_loc.z -= ci->type == id_SIOLOGIC ? 2 : 4;
1365 std::string pic_tile = get_pic_tile(ctx, ctx->getBelByLocation(pio_loc));
1366 std::string prim = std::string("IOLOGIC") + "ABCD"[pio_loc.z];
1367 for (auto ¶m : ci->params) {
1368 if (param.first == ctx->id("DELAY.DEL_VALUE"))
1369 cc.tiles[pic_tile].add_word(prim + "." + param.first.str(ctx),
1370 int_to_bitvector(param.second.as_int64(), 7));
1371 else
1372 cc.tiles[pic_tile].add_enum(prim + "." + param.first.str(ctx), param.second.as_string());
1373 }
1374 if (get_net_or_empty(ci, id_LOADN) != nullptr) {
1375 cc.tiles[pic_tile].add_enum(prim + ".LOADNMUX", "LOADN");
1376 }
1377 } else if (ci->type == id_DCUA) {
1378 TileGroup tg;
1379 tg.tiles = get_dcu_tiles(ctx, ci->bel);
1380 tg.config.add_enum("DCU.MODE", "DCUA");
1381 #include "dcu_bitstream.h"
1382 cc.tilegroups.push_back(tg);
1383 tieoff_dcu_ports(ctx, cc, ci);
1384 } else if (ci->type == id_EXTREFB) {
1385 TileGroup tg;
1386 tg.tiles = get_dcu_tiles(ctx, ci->bel);
1387 tg.config.add_word(
1388 "EXTREF.REFCK_DCBIAS_EN",
1389 parse_config_str(get_or_default(ci->params, ctx->id("REFCK_DCBIAS_EN"), Property(0)), 1));
1390 tg.config.add_word("EXTREF.REFCK_RTERM",
1391 parse_config_str(get_or_default(ci->params, ctx->id("REFCK_RTERM"), Property(0)), 1));
1392 tg.config.add_word("EXTREF.REFCK_PWDNB",
1393 parse_config_str(get_or_default(ci->params, ctx->id("REFCK_PWDNB"), Property(0)), 1));
1394 cc.tilegroups.push_back(tg);
1395 } else if (ci->type == id_PCSCLKDIV) {
1396 Loc loc = ctx->getBelLocation(ci->bel);
1397 std::string tname = ctx->getTileByTypeAndLocation(loc.y + 1, loc.x, "BMID_0H");
1398 cc.tiles[tname].add_enum("PCSCLKDIV" + std::to_string(loc.z),
1399 str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
1400 } else if (ci->type == id_DTR) {
1401 cc.tiles[ctx->getTileByType("DTR")].add_enum("DTR.MODE", "DTR");
1402 } else if (ci->type == id_OSCG) {
1403 int div = int_or_default(ci->params, ctx->id("DIV"), 128);
1404 if (div == 128)
1405 div = 127;
1406 cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("OSC.DIV", std::to_string(div));
1407 cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("OSC.DIV", std::to_string(div));
1408 cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("OSC.MODE", "OSCG");
1409 cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("CCLK.MODE", "_NONE_");
1410 } else if (ci->type == id_USRMCLK) {
1411 if (str_or_default(ctx->settings, ctx->id("arch.sysconfig.MASTER_SPI_PORT"), "") == "ENABLE")
1412 log_warning("USRMCLK will not function correctly when MASTER_SPI_PORT is set to ENABLE.\n");
1413 cc.tiles[ctx->getTileByType("EFB3_PICB1")].add_enum("CCLK.MODE", "USRMCLK");
1414 } else if (ci->type == id_GSR) {
1415 cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum(
1416 "GSR.GSRMODE", str_or_default(ci->params, ctx->id("MODE"), "ACTIVE_LOW"));
1417 cc.tiles[ctx->getTileByType("VIQ_BUF")].add_enum("GSR.SYNCMODE",
1418 str_or_default(ci->params, ctx->id("SYNCMODE"), "ASYNC"));
1419 } else if (ci->type == id_JTAGG) {
1420 cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("JTAG.ER1",
1421 str_or_default(ci->params, ctx->id("ER1"), "ENABLED"));
1422 cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("JTAG.ER2",
1423 str_or_default(ci->params, ctx->id("ER2"), "ENABLED"));
1424 } else if (ci->type == id_CLKDIVF) {
1425 Loc loc = ctx->getBelLocation(ci->bel);
1426 bool r = loc.x > 5;
1427 std::string clkdiv = std::string("CLKDIV_") + (r ? "R" : "L") + std::to_string(loc.z);
1428 std::string tile = ctx->getTileByType(std::string("ECLK_") + (r ? "R" : "L"));
1429 cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, ctx->id("DIV"), "2.0"));
1430 cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
1431 } else if (ci->type == id_TRELLIS_ECLKBUF) {
1432 } else if (ci->type == id_DQSBUFM) {
1433 Loc loc = ctx->getBelLocation(ci->bel);
1434 bool l = loc.x < 10;
1435 std::string pic = l ? "PICL" : "PICR";
1436 TileGroup tg;
1437 tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y - 2, loc.x, pic + "1_DQS0"));
1438 tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y - 1, loc.x, pic + "2_DQS1"));
1439 tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, pic + "0_DQS2"));
1440 tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x, pic + "1_DQS3"));
1441 tg.config.add_enum("DQS.MODE", "DQSBUFM");
1442 tg.config.add_enum("DQS.DQS_LI_DEL_ADJ", str_or_default(ci->params, ctx->id("DQS_LI_DEL_ADJ"), "PLUS"));
1443 tg.config.add_enum("DQS.DQS_LO_DEL_ADJ", str_or_default(ci->params, ctx->id("DQS_LO_DEL_ADJ"), "PLUS"));
1444 int li_del_value = int_or_default(ci->params, ctx->id("DQS_LI_DEL_VAL"), 0);
1445 if (str_or_default(ci->params, ctx->id("DQS_LI_DEL_ADJ"), "PLUS") == "MINUS")
1446 li_del_value = (256 - li_del_value) & 0xFF;
1447 int lo_del_value = int_or_default(ci->params, ctx->id("DQS_LO_DEL_VAL"), 0);
1448 if (str_or_default(ci->params, ctx->id("DQS_LO_DEL_ADJ"), "PLUS") == "MINUS")
1449 lo_del_value = (256 - lo_del_value) & 0xFF;
1450 tg.config.add_word("DQS.DQS_LI_DEL_VAL", int_to_bitvector(li_del_value, 8));
1451 tg.config.add_word("DQS.DQS_LO_DEL_VAL", int_to_bitvector(lo_del_value, 8));
1452 tg.config.add_enum("DQS.WRLOADN_USED", get_net_or_empty(ci, id_WRLOADN) != nullptr ? "YES" : "NO");
1453 tg.config.add_enum("DQS.RDLOADN_USED", get_net_or_empty(ci, id_RDLOADN) != nullptr ? "YES" : "NO");
1454 tg.config.add_enum("DQS.PAUSE_USED", get_net_or_empty(ci, id_PAUSE) != nullptr ? "YES" : "NO");
1455 tg.config.add_enum("DQS.READ_USED",
1456 (get_net_or_empty(ci, id_READ0) != nullptr || get_net_or_empty(ci, id_READ1) != nullptr)
1457 ? "YES"
1458 : "NO");
1459 tg.config.add_enum("DQS.DDRDEL", get_net_or_empty(ci, id_DDRDEL) != nullptr ? "DDRDEL" : "0");
1460 tg.config.add_enum("DQS.GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
1461 cc.tilegroups.push_back(tg);
1462 } else if (ci->type == id_ECLKSYNCB) {
1463 Loc loc = ctx->getBelLocation(ci->bel);
1464 bool r = loc.x > 5;
1465 std::string eclksync = ctx->locInfo(bel)->bel_data[bel.index].name.get();
1466 std::string tile = ctx->getTileByType(std::string("ECLK_") + (r ? "R" : "L"));
1467 if (get_net_or_empty(ci, id_STOP) != nullptr)
1468 cc.tiles[tile].add_enum(eclksync + ".MODE", "ECLKSYNCB");
1469 } else if (ci->type == id_ECLKBRIDGECS) {
1470 Loc loc = ctx->getBelLocation(ci->bel);
1471 bool r = loc.x > 5;
1472 std::string eclkb = ctx->locInfo(bel)->bel_data[bel.index].name.get();
1473 std::string tile = ctx->getTileByType(std::string("ECLK_") + (r ? "R" : "L"));
1474 if (get_net_or_empty(ci, id_STOP) != nullptr)
1475 cc.tiles[tile].add_enum(eclkb + ".MODE", "ECLKBRIDGECS");
1476 } else if (ci->type == id_DDRDLL) {
1477 Loc loc = ctx->getBelLocation(ci->bel);
1478 bool u = loc.y<15, r = loc.x> 15;
1479 std::string tiletype = fmt_str("DDRDLL_" << (u ? 'U' : 'L') << (r ? 'R' : 'L'));
1480 if ((ctx->args.type == ArchArgs::LFE5U_12F || ctx->args.type == ArchArgs::LFE5U_25F ||
1481 ctx->args.type == ArchArgs::LFE5UM_25F || ctx->args.type == ArchArgs::LFE5UM5G_25F) &&
1482 u)
1483 tiletype += "A";
1484 std::string tile = ctx->getTileByType(tiletype);
1485 cc.tiles[tile].add_enum("DDRDLL.MODE", "DDRDLLA");
1486 cc.tiles[tile].add_enum("DDRDLL.GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
1487 cc.tiles[tile].add_enum("DDRDLL.FORCE_MAX_DELAY",
1488 str_or_default(ci->params, ctx->id("FORCE_MAX_DELAY"), "NO"));
1489 } else {
1490 NPNR_ASSERT_FALSE("unsupported cell type");
1491 }
1492 }
1493
1494 // Add some SYSCONFIG settings
1495 const std::string prefix = "arch.sysconfig.";
1496 for (auto &setting : ctx->settings) {
1497 std::string key = setting.first.str(ctx);
1498 if (key.substr(0, prefix.length()) != prefix)
1499 continue;
1500 key = key.substr(prefix.length());
1501 std::string value = setting.second.as_string();
1502 if (key == "SLAVE_SPI_PORT" || key == "DONE_EX") {
1503 cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value);
1504 cc.tiles[ctx->getTileByType("EFB2_PICB0")].add_enum("SYSCONFIG." + key, value);
1505 } else if (key == "SLAVE_PARALLEL_PORT" || key == "BACKGROUND_RECONFIG" || key == "WAKE_UP") {
1506 cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value);
1507 } else if (key == "MASTER_SPI_PORT") {
1508 cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("SYSCONFIG." + key, value);
1509 } else if (key == "TRANSFR") {
1510 cc.tiles[ctx->getTileByType("EFB0_PICB0")].add_enum("SYSCONFIG." + key, value);
1511 cc.tiles[ctx->getTileByType("EFB1_PICB1")].add_enum("SYSCONFIG." + key, value);
1512 } else {
1513 cc.sysconfig[key] = value;
1514 }
1515 }
1516
1517 // Fixup tile names
1518 fix_tile_names(ctx, cc);
1519 // Configure chip
1520 if (!text_config_file.empty()) {
1521 std::ofstream out_config(text_config_file);
1522 out_config << cc;
1523 }
1524 }
1525
1526 NEXTPNR_NAMESPACE_END
1527