1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Zhao Yakui <yakui.zhao@intel.com> 26 * 27 */ 28 29 #ifndef _INTEL_COMMON_VPP_INTERNAL_H_ 30 #define _INTEL_COMMON_VPP_INTERNAL_H_ 31 32 /* the below is defined for YUV420 format scaling */ 33 #define SRC_MSB 0x0001 34 #define DST_MSB 0x0002 35 #define SRC_PACKED 0x0004 36 #define DST_PACKED 0x0008 37 #define PACKED_MASK 0x000C 38 39 #define BTI_SCALING_INPUT_Y 0 40 #define BTI_SCALING_OUTPUT_Y 8 41 42 #define SRC_FORMAT_I420 0 43 #define SRC_FORMAT_YV12 1 44 #define SRC_FORMAT_NV12 2 45 #define SRC_FORMAT_P010 3 46 #define SRC_FORMAT_I010 4 47 #define SRC_FORMAT_YUY2 5 48 #define SRC_FORMAT_UYVY 6 49 #define SRC_FORMAT_RGBA 7 50 #define SRC_FORMAT_RGBX 8 51 #define SRC_FORMAT_BGRA 9 52 #define SRC_FORMAT_BGRX 10 53 54 #define DST_FORMAT_I420 0 55 #define DST_FORMAT_YV12 1 56 #define DST_FORMAT_NV12 2 57 #define DST_FORMAT_P010 3 58 #define DST_FORMAT_I010 4 59 #define DST_FORMAT_YUY2 5 60 #define DST_FORMAT_UYVY 6 61 #define DST_FORMAT_RGBA 7 62 #define DST_FORMAT_RGBX 8 63 #define DST_FORMAT_BGRA 9 64 #define DST_FORMAT_BGRX 10 65 66 /* 67 * 32 DWs or 4 GRFs 68 */ 69 struct scaling_input_parameter { 70 float inv_width; 71 float inv_height; 72 73 struct { 74 unsigned int src_msb : 1; 75 unsigned int dst_msb : 1; 76 unsigned int src_packed : 1; /* packed UV */ 77 unsigned int dst_packed : 1; /* packed UV */ 78 unsigned int reserved : 12; 79 unsigned int src_format : 8; 80 unsigned int dst_format : 8; 81 } dw2; 82 83 int x_dst; 84 int y_dst; 85 float x_factor; // src_rect_width / dst_rect_width / Surface_width 86 float y_factor; // src_rect_height / dst_rect_height / Surface_height 87 float x_orig; 88 float y_orig; 89 unsigned int bti_input; 90 unsigned int bti_output; 91 unsigned int reserved0; 92 float coef_ry; 93 float coef_ru; 94 float coef_rv; 95 float coef_yd; 96 float coef_gy; 97 float coef_gu; 98 float coef_gv; 99 float coef_ud; 100 float coef_by; 101 float coef_bu; 102 float coef_bv; 103 float coef_vd; 104 unsigned int reserved[8]; 105 }; 106 107 VAStatus 108 gen9_yuv420p8_scaling_post_processing( 109 VADriverContextP ctx, 110 struct i965_post_processing_context *pp_context, 111 struct i965_surface *src_surface, 112 VARectangle *src_rect, 113 struct i965_surface *dst_surface, 114 VARectangle *dst_rect); 115 116 VAStatus 117 gen8_yuv420p8_scaling_post_processing( 118 VADriverContextP ctx, 119 struct i965_post_processing_context *pp_context, 120 struct i965_surface *src_surface, 121 VARectangle *src_rect, 122 struct i965_surface *dst_surface, 123 VARectangle *dst_rect); 124 125 VAStatus 126 gen9_10bit_8bit_scaling_post_processing(VADriverContextP ctx, 127 struct i965_post_processing_context *pp_context, 128 struct i965_surface *src_surface, 129 VARectangle *src_rect, 130 struct i965_surface *dst_surface, 131 VARectangle *dst_rect); 132 133 VAStatus 134 gen8_8bit_420_rgb32_scaling_post_processing(VADriverContextP ctx, 135 struct i965_post_processing_context *pp_context, 136 struct i965_surface *src_surface, 137 VARectangle *src_rect, 138 struct i965_surface *dst_surface, 139 VARectangle *dst_rect); 140 141 VAStatus 142 gen9_8bit_420_rgb32_scaling_post_processing(VADriverContextP ctx, 143 struct i965_post_processing_context *pp_context, 144 struct i965_surface *src_surface, 145 VARectangle *src_rect, 146 struct i965_surface *dst_surface, 147 VARectangle *dst_rect); 148 149 VAStatus 150 gen9_p010_scaling_post_processing(VADriverContextP ctx, 151 struct i965_post_processing_context *pp_context, 152 struct i965_surface *src_surface, 153 VARectangle *src_rect, 154 struct i965_surface *dst_surface, 155 VARectangle *dst_rect); 156 157 #endif // _INTEL_COMMON_VPP_INTERNAL_H_ 158