1 /*
2 * sPAPR CPU core device.
3 *
4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 */
9 #ifndef HW_SPAPR_CPU_CORE_H
10 #define HW_SPAPR_CPU_CORE_H
11
12 #include "hw/cpu/core.h"
13 #include "hw/qdev-core.h"
14 #include "target/ppc/cpu-qom.h"
15 #include "target/ppc/cpu.h"
16 #include "qom/object.h"
17
18 #define TYPE_SPAPR_CPU_CORE "spapr-cpu-core"
19 OBJECT_DECLARE_TYPE(SpaprCpuCore, SpaprCpuCoreClass,
20 SPAPR_CPU_CORE)
21
22 #define SPAPR_CPU_CORE_TYPE_NAME(model) model "-" TYPE_SPAPR_CPU_CORE
23
24 struct SpaprCpuCore {
25 /*< private >*/
26 CPUCore parent_obj;
27
28 /*< public >*/
29 PowerPCCPU **threads;
30 int node_id;
31 bool pre_3_0_migration; /* older machine don't know about SpaprCpuState */
32 };
33
34 struct SpaprCpuCoreClass {
35 DeviceClass parent_class;
36 const char *cpu_type;
37 };
38
39 const char *spapr_get_cpu_core_type(const char *cpu_type);
40 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
41 target_ulong r1, target_ulong r3,
42 target_ulong r4);
43
44 struct nested_ppc_state;
45
46 typedef struct SpaprCpuState {
47 uint64_t vpa_addr;
48 uint64_t slb_shadow_addr, slb_shadow_size;
49 uint64_t dtl_addr, dtl_size;
50 bool prod; /* not migrated, only used to improve dispatch latencies */
51 struct ICPState *icp;
52 struct XiveTCTX *tctx;
53
54 /* Fields for nested-HV support */
55 bool in_nested; /* true while the L2 is executing */
56 struct nested_ppc_state *nested_host_state; /* holds the L1 state while L2 executes */
57 } SpaprCpuState;
58
spapr_cpu_state(PowerPCCPU * cpu)59 static inline SpaprCpuState *spapr_cpu_state(PowerPCCPU *cpu)
60 {
61 return (SpaprCpuState *)cpu->machine_data;
62 }
63
64 #endif
65