1 /******************************************************************************
2
3 Copyright (c) 2001-2014, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33
34 #include <sys/param.h>
35 #include <sys/kernel.h>
36 #include <sys/sysctl.h>
37 #include <net/if.h>
38 #include <net/if_media.h>
39
40 #include "e1000_api.h"
41 #include "e1000_dragonfly.h"
42
43 SYSCTL_NODE(_hw, OID_AUTO, ig_hal, CTLFLAG_RW, 0, "Intel 1Ge HAL");
44
45 int e1000_debug;
46
47 TUNABLE_INT("hw.ig_hal.debug", &e1000_debug);
48 SYSCTL_INT(_hw_ig_hal, OID_AUTO, debug, CTLFLAG_RW, &e1000_debug, 0,
49 "Enable Intel 1Ge HAL debug");
50
51 /*
52 * NOTE: the following routines using the e1000
53 * naming style are provided to the shared
54 * code but are OS specific
55 */
56
57 void
e1000_write_pci_cfg(struct e1000_hw * hw,uint32_t reg,uint16_t * value)58 e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
59 {
60 pci_write_config(((struct e1000_osdep *)hw->back)->dev, reg, *value, 2);
61 }
62
63 void
e1000_read_pci_cfg(struct e1000_hw * hw,uint32_t reg,uint16_t * value)64 e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
65 {
66 *value = pci_read_config(((struct e1000_osdep *)hw->back)->dev, reg, 2);
67 }
68
69 void
e1000_pci_set_mwi(struct e1000_hw * hw)70 e1000_pci_set_mwi(struct e1000_hw *hw)
71 {
72 pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND,
73 (hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2);
74 }
75
76 void
e1000_pci_clear_mwi(struct e1000_hw * hw)77 e1000_pci_clear_mwi(struct e1000_hw *hw)
78 {
79 pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND,
80 (hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2);
81 }
82
83 /*
84 * Read the PCI Express capabilities
85 */
86 int32_t
e1000_read_pcie_cap_reg(struct e1000_hw * hw,uint32_t reg,uint16_t * value)87 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
88 {
89 device_t dev = ((struct e1000_osdep *)hw->back)->dev;
90 uint8_t pcie_ptr;
91
92 pcie_ptr = pci_get_pciecap_ptr(dev);
93 if (pcie_ptr == 0)
94 return E1000_NOT_IMPLEMENTED;
95
96 *value = pci_read_config(dev, pcie_ptr + reg, 2);
97 return E1000_SUCCESS;
98 }
99
100 int32_t
e1000_write_pcie_cap_reg(struct e1000_hw * hw,uint32_t reg,uint16_t * value)101 e1000_write_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
102 {
103 device_t dev = ((struct e1000_osdep *)hw->back)->dev;
104 uint8_t pcie_ptr;
105
106 pcie_ptr = pci_get_pciecap_ptr(dev);
107 if (pcie_ptr == 0)
108 return E1000_NOT_IMPLEMENTED;
109
110 pci_write_config(dev, pcie_ptr + reg, *value, 2);
111 return E1000_SUCCESS;
112 }
113
114 void
e1000_fc2str(enum e1000_fc_mode fc,char * str,int len)115 e1000_fc2str(enum e1000_fc_mode fc, char *str, int len)
116 {
117 const char *fc_str = IFM_ETH_FC_NONE;
118
119 switch (fc) {
120 case e1000_fc_full:
121 fc_str = IFM_ETH_FC_FULL;
122 break;
123
124 case e1000_fc_rx_pause:
125 fc_str = IFM_ETH_FC_RXPAUSE;
126 break;
127
128 case e1000_fc_tx_pause:
129 fc_str = IFM_ETH_FC_TXPAUSE;
130 break;
131
132 default:
133 break;
134 }
135 strlcpy(str, fc_str, len);
136 }
137
138 enum e1000_fc_mode
e1000_ifmedia2fc(int ifm)139 e1000_ifmedia2fc(int ifm)
140 {
141 int fc_opt = ifm & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
142
143 switch (fc_opt) {
144 case (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE):
145 return e1000_fc_full;
146
147 case IFM_ETH_RXPAUSE:
148 return e1000_fc_rx_pause;
149
150 case IFM_ETH_TXPAUSE:
151 return e1000_fc_tx_pause;
152
153 default:
154 return e1000_fc_none;
155 }
156 }
157
158 int
e1000_fc2ifmedia(enum e1000_fc_mode fc)159 e1000_fc2ifmedia(enum e1000_fc_mode fc)
160 {
161 switch (fc) {
162 case e1000_fc_full:
163 return (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
164
165 case e1000_fc_rx_pause:
166 return IFM_ETH_RXPAUSE;
167
168 case e1000_fc_tx_pause:
169 return IFM_ETH_TXPAUSE;
170
171 default:
172 return 0;
173 }
174 }
175
176 void
e1000_force_flowctrl(struct e1000_hw * hw,int ifm)177 e1000_force_flowctrl(struct e1000_hw *hw, int ifm)
178 {
179 enum e1000_fc_mode fc;
180
181 fc = e1000_ifmedia2fc(ifm);
182 if (hw->fc.current_mode != fc) {
183 hw->fc.requested_mode = fc;
184 hw->fc.current_mode = fc;
185 e1000_force_mac_fc(hw);
186 }
187 }
188
189 /* Module glue */
190 static moduledata_t ig_hal_mod = { "ig_hal" };
191 DECLARE_MODULE(ig_hal, ig_hal_mod, SI_SUB_DRIVERS, SI_ORDER_MIDDLE);
192 MODULE_VERSION(ig_hal, 1);
193