1 //===-- ArchSpec.h ----------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_UTILITY_ARCHSPEC_H 10 #define LLDB_UTILITY_ARCHSPEC_H 11 12 #include "lldb/Utility/CompletionRequest.h" 13 #include "lldb/Utility/ConstString.h" 14 #include "lldb/lldb-enumerations.h" 15 #include "lldb/lldb-forward.h" 16 #include "lldb/lldb-private-enumerations.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/Triple.h" 19 #include <cstddef> 20 #include <cstdint> 21 #include <string> 22 23 namespace lldb_private { 24 25 /// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture 26 /// specification class. 27 /// 28 /// A class designed to be created from a cpu type and subtype, a 29 /// string representation, or an llvm::Triple. Keeping all of the conversions 30 /// of strings to architecture enumeration values confined to this class 31 /// allows new architecture support to be added easily. 32 class ArchSpec { 33 public: 34 enum MIPSSubType { 35 eMIPSSubType_unknown, 36 eMIPSSubType_mips32, 37 eMIPSSubType_mips32r2, 38 eMIPSSubType_mips32r6, 39 eMIPSSubType_mips32el, 40 eMIPSSubType_mips32r2el, 41 eMIPSSubType_mips32r6el, 42 eMIPSSubType_mips64, 43 eMIPSSubType_mips64r2, 44 eMIPSSubType_mips64r6, 45 eMIPSSubType_mips64el, 46 eMIPSSubType_mips64r2el, 47 eMIPSSubType_mips64r6el, 48 }; 49 50 // Masks for the ases word of an ABI flags structure. 51 enum MIPSASE { 52 eMIPSAse_dsp = 0x00000001, // DSP ASE 53 eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE 54 eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme 55 eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE 56 eMIPSAse_mdmx = 0x00000010, // MDMX ASE 57 eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE 58 eMIPSAse_mt = 0x00000040, // MT ASE 59 eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE 60 eMIPSAse_virt = 0x00000100, // VZ ASE 61 eMIPSAse_msa = 0x00000200, // MSA ASE 62 eMIPSAse_mips16 = 0x00000400, // MIPS16 ASE 63 eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE 64 eMIPSAse_xpa = 0x00001000, // XPA ASE 65 eMIPSAse_mask = 0x00001fff, 66 eMIPSABI_O32 = 0x00002000, 67 eMIPSABI_N32 = 0x00004000, 68 eMIPSABI_N64 = 0x00008000, 69 eMIPSABI_O64 = 0x00020000, 70 eMIPSABI_EABI32 = 0x00040000, 71 eMIPSABI_EABI64 = 0x00080000, 72 eMIPSABI_mask = 0x000ff000 73 }; 74 75 // MIPS Floating point ABI Values 76 enum MIPS_ABI_FP { 77 eMIPS_ABI_FP_ANY = 0x00000000, 78 eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float 79 eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float 80 eMIPS_ABI_FP_SOFT = 0x00300000, // soft float 81 eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64 82 eMIPS_ABI_FP_XX = 0x00500000, // -mfpxx 83 eMIPS_ABI_FP_64 = 0x00600000, // -mips32r2 -mfp64 84 eMIPS_ABI_FP_64A = 0x00700000, // -mips32r2 -mfp64 -mno-odd-spreg 85 eMIPS_ABI_FP_mask = 0x00700000 86 }; 87 88 // ARM specific e_flags 89 enum ARMeflags { 90 eARM_abi_soft_float = 0x00000200, 91 eARM_abi_hard_float = 0x00000400 92 }; 93 94 enum RISCVeflags { 95 eRISCV_rvc = 0x00000001, /// RVC, +c 96 eRISCV_float_abi_soft = 0x00000000, /// soft float 97 eRISCV_float_abi_single = 0x00000002, /// single precision floating point, +f 98 eRISCV_float_abi_double = 0x00000004, /// double precision floating point, +d 99 eRISCV_float_abi_quad = 0x00000006, /// quad precision floating point, +q 100 eRISCV_float_abi_mask = 0x00000006, 101 eRISCV_rve = 0x00000008, /// RVE, +e 102 eRISCV_tso = 0x00000010, /// RVTSO (total store ordering) 103 }; 104 105 enum RISCVSubType { 106 eRISCVSubType_unknown, 107 eRISCVSubType_riscv32, 108 eRISCVSubType_riscv64, 109 }; 110 111 enum LoongArchSubType { 112 eLoongArchSubType_unknown, 113 eLoongArchSubType_loongarch32, 114 eLoongArchSubType_loongarch64, 115 }; 116 117 enum Core { 118 eCore_arm_generic, 119 eCore_arm_armv4, 120 eCore_arm_armv4t, 121 eCore_arm_armv5, 122 eCore_arm_armv5e, 123 eCore_arm_armv5t, 124 eCore_arm_armv6, 125 eCore_arm_armv6m, 126 eCore_arm_armv7, 127 eCore_arm_armv7l, 128 eCore_arm_armv7f, 129 eCore_arm_armv7s, 130 eCore_arm_armv7k, 131 eCore_arm_armv7m, 132 eCore_arm_armv7em, 133 eCore_arm_xscale, 134 135 eCore_thumb, 136 eCore_thumbv4t, 137 eCore_thumbv5, 138 eCore_thumbv5e, 139 eCore_thumbv6, 140 eCore_thumbv6m, 141 eCore_thumbv7, 142 eCore_thumbv7s, 143 eCore_thumbv7k, 144 eCore_thumbv7f, 145 eCore_thumbv7m, 146 eCore_thumbv7em, 147 eCore_arm_arm64, 148 eCore_arm_armv8, 149 eCore_arm_armv8l, 150 eCore_arm_arm64e, 151 eCore_arm_arm64_32, 152 eCore_arm_aarch64, 153 154 eCore_mips32, 155 eCore_mips32r2, 156 eCore_mips32r3, 157 eCore_mips32r5, 158 eCore_mips32r6, 159 eCore_mips32el, 160 eCore_mips32r2el, 161 eCore_mips32r3el, 162 eCore_mips32r5el, 163 eCore_mips32r6el, 164 eCore_mips64, 165 eCore_mips64r2, 166 eCore_mips64r3, 167 eCore_mips64r5, 168 eCore_mips64r6, 169 eCore_mips64el, 170 eCore_mips64r2el, 171 eCore_mips64r3el, 172 eCore_mips64r5el, 173 eCore_mips64r6el, 174 175 eCore_ppc_generic, 176 eCore_ppc_ppc601, 177 eCore_ppc_ppc602, 178 eCore_ppc_ppc603, 179 eCore_ppc_ppc603e, 180 eCore_ppc_ppc603ev, 181 eCore_ppc_ppc604, 182 eCore_ppc_ppc604e, 183 eCore_ppc_ppc620, 184 eCore_ppc_ppc750, 185 eCore_ppc_ppc7400, 186 eCore_ppc_ppc7450, 187 eCore_ppc_ppc970, 188 189 eCore_ppc64le_generic, 190 eCore_ppc64_generic, 191 eCore_ppc64_ppc970_64, 192 193 eCore_s390x_generic, 194 195 eCore_sparc_generic, 196 197 eCore_sparc9_generic, 198 199 eCore_x86_32_i386, 200 eCore_x86_32_i486, 201 eCore_x86_32_i486sx, 202 eCore_x86_32_i686, 203 204 eCore_x86_64_x86_64, 205 eCore_x86_64_x86_64h, // Haswell enabled x86_64 206 eCore_x86_64_amd64, 207 eCore_hexagon_generic, 208 eCore_hexagon_hexagonv4, 209 eCore_hexagon_hexagonv5, 210 211 eCore_riscv32, 212 eCore_riscv64, 213 214 eCore_loongarch32, 215 eCore_loongarch64, 216 217 eCore_uknownMach32, 218 eCore_uknownMach64, 219 220 eCore_arc, // little endian ARC 221 222 eCore_avr, 223 224 eCore_wasm32, 225 226 kNumCores, 227 228 kCore_invalid, 229 // The following constants are used for wildcard matching only 230 kCore_any, 231 kCore_arm_any, 232 kCore_ppc_any, 233 kCore_ppc64_any, 234 kCore_x86_32_any, 235 kCore_x86_64_any, 236 kCore_hexagon_any, 237 238 kCore_arm_first = eCore_arm_generic, 239 kCore_arm_last = eCore_arm_xscale, 240 241 kCore_thumb_first = eCore_thumb, 242 kCore_thumb_last = eCore_thumbv7em, 243 244 kCore_ppc_first = eCore_ppc_generic, 245 kCore_ppc_last = eCore_ppc_ppc970, 246 247 kCore_ppc64_first = eCore_ppc64_generic, 248 kCore_ppc64_last = eCore_ppc64_ppc970_64, 249 250 kCore_x86_32_first = eCore_x86_32_i386, 251 kCore_x86_32_last = eCore_x86_32_i686, 252 253 kCore_x86_64_first = eCore_x86_64_x86_64, 254 kCore_x86_64_last = eCore_x86_64_x86_64h, 255 256 kCore_hexagon_first = eCore_hexagon_generic, 257 kCore_hexagon_last = eCore_hexagon_hexagonv5, 258 259 kCore_mips32_first = eCore_mips32, 260 kCore_mips32_last = eCore_mips32r6, 261 262 kCore_mips32el_first = eCore_mips32el, 263 kCore_mips32el_last = eCore_mips32r6el, 264 265 kCore_mips64_first = eCore_mips64, 266 kCore_mips64_last = eCore_mips64r6, 267 268 kCore_mips64el_first = eCore_mips64el, 269 kCore_mips64el_last = eCore_mips64r6el, 270 271 kCore_mips_first = eCore_mips32, 272 kCore_mips_last = eCore_mips64r6el 273 274 }; 275 276 /// Default constructor. 277 /// 278 /// Default constructor that initializes the object with invalid cpu type 279 /// and subtype values. 280 ArchSpec(); 281 282 /// Constructor over triple. 283 /// 284 /// Constructs an ArchSpec with properties consistent with the given Triple. 285 explicit ArchSpec(const llvm::Triple &triple); 286 explicit ArchSpec(const char *triple_cstr); 287 explicit ArchSpec(llvm::StringRef triple_str); 288 /// Constructor over architecture name. 289 /// 290 /// Constructs an ArchSpec with properties consistent with the given object 291 /// type and architecture name. 292 explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type, 293 uint32_t cpu_subtype); 294 295 /// Destructor. 296 ~ArchSpec(); 297 298 /// Returns true if the OS, vendor and environment fields of the triple are 299 /// unset. The triple is expected to be normalized 300 /// (llvm::Triple::normalize). 301 static bool ContainsOnlyArch(const llvm::Triple &normalized_triple); 302 303 static void ListSupportedArchNames(StringList &list); 304 static void AutoComplete(CompletionRequest &request); 305 306 /// Returns a static string representing the current architecture. 307 /// 308 /// \return A static string corresponding to the current 309 /// architecture. 310 const char *GetArchitectureName() const; 311 312 /// if MIPS architecture return true. 313 /// 314 /// \return a boolean value. 315 bool IsMIPS() const; 316 317 /// Returns a string representing current architecture as a target CPU for 318 /// tools like compiler, disassembler etc. 319 /// 320 /// \return A string representing target CPU for the current 321 /// architecture. 322 std::string GetClangTargetCPU() const; 323 324 /// Return a string representing target application ABI. 325 /// 326 /// \return A string representing target application ABI. 327 std::string GetTargetABI() const; 328 329 /// Clears the object state. 330 /// 331 /// Clears the object state back to a default invalid state. 332 void Clear(); 333 334 /// Returns the size in bytes of an address of the current architecture. 335 /// 336 /// \return The byte size of an address of the current architecture. 337 uint32_t GetAddressByteSize() const; 338 339 /// Returns a machine family for the current architecture. 340 /// 341 /// \return An LLVM arch type. 342 llvm::Triple::ArchType GetMachine() const; 343 344 /// Returns the distribution id of the architecture. 345 /// 346 /// This will be something like "ubuntu", "fedora", etc. on Linux. 347 /// 348 /// \return A ConstString ref containing the distribution id, 349 /// potentially empty. 350 ConstString GetDistributionId() const; 351 352 /// Set the distribution id of the architecture. 353 /// 354 /// This will be something like "ubuntu", "fedora", etc. on Linux. This 355 /// should be the same value returned by HostInfo::GetDistributionId (). 356 void SetDistributionId(const char *distribution_id); 357 358 /// Tests if this ArchSpec is valid. 359 /// 360 /// \return True if the current architecture is valid, false 361 /// otherwise. IsValid()362 bool IsValid() const { 363 return m_core >= eCore_arm_generic && m_core < kNumCores; 364 } 365 explicit operator bool() const { return IsValid(); } 366 TripleVendorWasSpecified()367 bool TripleVendorWasSpecified() const { 368 return !m_triple.getVendorName().empty(); 369 } 370 TripleOSWasSpecified()371 bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); } 372 TripleEnvironmentWasSpecified()373 bool TripleEnvironmentWasSpecified() const { 374 return m_triple.hasEnvironment(); 375 } 376 377 /// Merges fields from another ArchSpec into this ArchSpec. 378 /// 379 /// This will use the supplied ArchSpec to fill in any fields of the triple 380 /// in this ArchSpec which were unspecified. This can be used to refine a 381 /// generic ArchSpec with a more specific one. For example, if this 382 /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we 383 /// have a triple which is x64-pc-windows-msvc, then merging that triple 384 /// into this one will result in the triple i386-pc-windows-msvc. 385 /// 386 void MergeFrom(const ArchSpec &other); 387 388 /// Change the architecture object type, CPU type and OS type. 389 /// 390 /// \param[in] arch_type The object type of this ArchSpec. 391 /// 392 /// \param[in] cpu The required CPU type. 393 /// 394 /// \param[in] os The optional OS type 395 /// The default value of 0 was chosen to from the ELF spec value 396 /// ELFOSABI_NONE. ELF is the only one using this parameter. If another 397 /// format uses this parameter and 0 does not work, use a value over 398 /// 255 because in the ELF header this is value is only a byte. 399 /// 400 /// \return True if the object, and CPU were successfully set. 401 /// 402 /// As a side effect, the vendor value is usually set to unknown. The 403 /// exceptions are 404 /// aarch64-apple-ios 405 /// arm-apple-ios 406 /// thumb-apple-ios 407 /// x86-apple- 408 /// x86_64-apple- 409 /// 410 /// As a side effect, the os value is usually set to unknown The exceptions 411 /// are 412 /// *-*-aix 413 /// aarch64-apple-ios 414 /// arm-apple-ios 415 /// thumb-apple-ios 416 /// powerpc-apple-darwin 417 /// *-*-freebsd 418 /// *-*-linux 419 /// *-*-netbsd 420 /// *-*-openbsd 421 /// *-*-solaris 422 bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, 423 uint32_t os = 0); 424 425 /// Returns the byte order for the architecture specification. 426 /// 427 /// \return The endian enumeration for the current endianness of 428 /// the architecture specification 429 lldb::ByteOrder GetByteOrder() const; 430 431 /// Sets this ArchSpec's byte order. 432 /// 433 /// In the common case there is no need to call this method as the byte 434 /// order can almost always be determined by the architecture. However, many 435 /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed 436 /// byte order may be incorrect. SetByteOrder(lldb::ByteOrder byte_order)437 void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; } 438 439 uint32_t GetMinimumOpcodeByteSize() const; 440 441 uint32_t GetMaximumOpcodeByteSize() const; 442 GetCore()443 Core GetCore() const { return m_core; } 444 445 uint32_t GetMachOCPUType() const; 446 447 uint32_t GetMachOCPUSubType() const; 448 449 /// Architecture data byte width accessor 450 /// 451 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 452 /// from the Architecture's data bus 453 uint32_t GetDataByteSize() const; 454 455 /// Architecture code byte width accessor 456 /// 457 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 458 /// from the Architecture's code bus 459 uint32_t GetCodeByteSize() const; 460 461 /// Architecture triple accessor. 462 /// 463 /// \return A triple describing this ArchSpec. GetTriple()464 llvm::Triple &GetTriple() { return m_triple; } 465 466 /// Architecture triple accessor. 467 /// 468 /// \return A triple describing this ArchSpec. GetTriple()469 const llvm::Triple &GetTriple() const { return m_triple; } 470 471 void DumpTriple(llvm::raw_ostream &s) const; 472 473 /// Architecture triple setter. 474 /// 475 /// Configures this ArchSpec according to the given triple. If the triple 476 /// has unknown components in all of the vendor, OS, and the optional 477 /// environment field (i.e. "i386-unknown-unknown") then default values are 478 /// taken from the host. Architecture and environment components are used 479 /// to further resolve the CPU type and subtype, endian characteristics, 480 /// etc. 481 /// 482 /// \return A triple describing this ArchSpec. 483 bool SetTriple(const llvm::Triple &triple); 484 485 bool SetTriple(llvm::StringRef triple_str); 486 487 /// Returns the default endianness of the architecture. 488 /// 489 /// \return The endian enumeration for the default endianness of 490 /// the architecture. 491 lldb::ByteOrder GetDefaultEndian() const; 492 493 /// Returns true if 'char' is a signed type by default in the architecture 494 /// false otherwise 495 /// 496 /// \return True if 'char' is a signed type by default on the 497 /// architecture and false otherwise. 498 bool CharIsSignedByDefault() const; 499 500 enum MatchType : bool { CompatibleMatch, ExactMatch }; 501 502 /// Compare this ArchSpec to another ArchSpec. \a match specifies the kind of 503 /// matching that is to be done. CompatibleMatch requires only a compatible 504 /// cpu type (e.g., armv7s is compatible with armv7). ExactMatch requires an 505 /// exact match (armv7s is not an exact match with armv7). 506 /// 507 /// \return true if the two ArchSpecs match. 508 bool IsMatch(const ArchSpec &rhs, MatchType match) const; 509 510 /// Shorthand for IsMatch(rhs, ExactMatch). IsExactMatch(const ArchSpec & rhs)511 bool IsExactMatch(const ArchSpec &rhs) const { 512 return IsMatch(rhs, ExactMatch); 513 } 514 515 /// Shorthand for IsMatch(rhs, CompatibleMatch). IsCompatibleMatch(const ArchSpec & rhs)516 bool IsCompatibleMatch(const ArchSpec &rhs) const { 517 return IsMatch(rhs, CompatibleMatch); 518 } 519 520 bool IsFullySpecifiedTriple() const; 521 522 void PiecewiseTripleCompare(const ArchSpec &other, bool &arch_different, 523 bool &vendor_different, bool &os_different, 524 bool &os_version_different, 525 bool &env_different) const; 526 527 /// Detect whether this architecture uses thumb code exclusively 528 /// 529 /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute 530 /// the Thumb instructions, never Arm. We should normally pick up 531 /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints 532 /// on each function - but when doing bare-boards low level debugging 533 /// (especially common with these embedded processors), we may not have 534 /// those things easily accessible. 535 /// 536 /// \return true if this is an arm ArchSpec which can only execute Thumb 537 /// instructions 538 bool IsAlwaysThumbInstructions() const; 539 GetFlags()540 uint32_t GetFlags() const { return m_flags; } 541 SetFlags(uint32_t flags)542 void SetFlags(uint32_t flags) { m_flags = flags; } 543 544 void SetFlags(const std::string &elf_abi); 545 546 protected: 547 void UpdateCore(); 548 549 llvm::Triple m_triple; 550 Core m_core = kCore_invalid; 551 lldb::ByteOrder m_byte_order = lldb::eByteOrderInvalid; 552 553 // Additional arch flags which we cannot get from triple and core For MIPS 554 // these are application specific extensions like micromips, mips16 etc. 555 uint32_t m_flags = 0; 556 557 ConstString m_distribution_id; 558 559 // Called when m_def or m_entry are changed. Fills in all remaining members 560 // with default values. 561 void CoreUpdated(bool update_triple); 562 }; 563 564 /// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than 565 /// operator. 566 /// 567 /// Tests two ArchSpec objects to see if \a lhs is less than \a rhs. 568 /// 569 /// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in] 570 /// rhs The Left Hand Side ArchSpec object to compare. 571 /// 572 /// \return true if \a lhs is less than \a rhs 573 bool operator<(const ArchSpec &lhs, const ArchSpec &rhs); 574 bool operator==(const ArchSpec &lhs, const ArchSpec &rhs); 575 576 bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch); 577 578 } // namespace lldb_private 579 580 #endif // LLDB_UTILITY_ARCHSPEC_H 581