xref: /openbsd/sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h (revision f005ef32)
1 /*
2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 #ifndef __AMDGPU_UMC_H__
22 #define __AMDGPU_UMC_H__
23 #include "amdgpu_ras.h"
24 
25 /*
26  * (addr / 256) * 4096, the higher 26 bits in ErrorAddr
27  * is the index of 4KB block
28  */
29 #define ADDR_OF_4KB_BLOCK(addr)			(((addr) & ~0xffULL) << 4)
30 /*
31  * (addr / 256) * 8192, the higher 26 bits in ErrorAddr
32  * is the index of 8KB block
33  */
34 #define ADDR_OF_8KB_BLOCK(addr)			(((addr) & ~0xffULL) << 5)
35 /* channel index is the index of 256B block */
36 #define ADDR_OF_256B_BLOCK(channel_index)	((channel_index) << 8)
37 /* offset in 256B block */
38 #define OFFSET_IN_256B_BLOCK(addr)		((addr) & 0xffULL)
39 
40 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++)
41 #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++)
42 #define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst))
43 
44 #define LOOP_UMC_NODE_INST(node_inst) \
45 		for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num)
46 
47 #define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \
48 		LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst))
49 
50 
51 typedef int (*umc_func)(struct amdgpu_device *adev, uint32_t node_inst,
52 			uint32_t umc_inst, uint32_t ch_inst, void *data);
53 
54 struct amdgpu_umc_ras {
55 	struct amdgpu_ras_block_object ras_block;
56 	void (*err_cnt_init)(struct amdgpu_device *adev);
57 	bool (*query_ras_poison_mode)(struct amdgpu_device *adev);
58 	void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev,
59 				      void *ras_error_status);
60 	void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev,
61 					void *ras_error_status);
62 	/* support different eeprom table version for different asic */
63 	void (*set_eeprom_table_version)(struct amdgpu_ras_eeprom_table_header *hdr);
64 };
65 
66 struct amdgpu_umc_funcs {
67 	void (*init_registers)(struct amdgpu_device *adev);
68 };
69 
70 struct amdgpu_umc {
71 	/* max error count in one ras query call */
72 	uint32_t max_ras_err_cnt_per_query;
73 	/* number of umc channel instance with memory map register access */
74 	uint32_t channel_inst_num;
75 	/* number of umc instance with memory map register access */
76 	uint32_t umc_inst_num;
77 
78 	/* Total number of umc node instance including harvest one */
79 	uint32_t node_inst_num;
80 
81 	/* UMC regiser per channel offset */
82 	uint32_t channel_offs;
83 	/* how many pages are retired in one UE */
84 	uint32_t retire_unit;
85 	/* channel index table of interleaved memory */
86 	const uint32_t *channel_idx_tbl;
87 	struct ras_common_if *ras_if;
88 
89 	const struct amdgpu_umc_funcs *funcs;
90 	struct amdgpu_umc_ras *ras;
91 
92 	/* active mask for umc node instance */
93 	unsigned long active_mask;
94 };
95 
96 int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev);
97 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
98 int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset);
99 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
100 		struct amdgpu_irq_src *source,
101 		struct amdgpu_iv_entry *entry);
102 void amdgpu_umc_fill_error_record(struct ras_err_data *err_data,
103 		uint64_t err_addr,
104 		uint64_t retired_page,
105 		uint32_t channel_index,
106 		uint32_t umc_inst);
107 
108 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
109 		void *ras_error_status,
110 		struct amdgpu_iv_entry *entry);
111 int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev,
112 			uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst);
113 
114 int amdgpu_umc_loop_channels(struct amdgpu_device *adev,
115 			umc_func func, void *data);
116 #endif
117