1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003 Marcel Moolenaar
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include "opt_acpi.h"
30 #include "opt_platform.h"
31 #include "opt_uart.h"
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/conf.h>
37 #include <sys/kernel.h>
38 #include <sys/sysctl.h>
39 #include <machine/bus.h>
40
41 #ifdef FDT
42 #include <dev/fdt/fdt_common.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45 #endif
46
47 #include <dev/uart/uart.h>
48 #include <dev/uart/uart_cpu.h>
49 #ifdef FDT
50 #include <dev/uart/uart_cpu_fdt.h>
51 #endif
52 #include <dev/uart/uart_bus.h>
53 #include <dev/uart/uart_dev_ns8250.h>
54 #include <dev/uart/uart_ppstypes.h>
55 #ifdef DEV_ACPI
56 #include <dev/uart/uart_cpu_acpi.h>
57 #include <contrib/dev/acpica/include/acpi.h>
58 #endif
59
60 #include <dev/ic/ns16550.h>
61
62 #include "uart_if.h"
63
64 #define DEFAULT_RCLK 1843200
65
66 /*
67 * Set the default baudrate tolerance to 3.0%.
68 *
69 * Some embedded boards have odd reference clocks (eg 25MHz)
70 * and we need to handle higher variances in the target baud rate.
71 */
72 #ifndef UART_DEV_TOLERANCE_PCT
73 #define UART_DEV_TOLERANCE_PCT 30
74 #endif /* UART_DEV_TOLERANCE_PCT */
75
76 static int broken_txfifo = 0;
77 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN,
78 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
79
80 /*
81 * To use early printf on x86, add the following to your kernel config:
82 *
83 * options UART_NS8250_EARLY_PORT=0x3f8
84 * options EARLY_PRINTF=ns8250
85 */
86 #if CHECK_EARLY_PRINTF(ns8250)
87 #if !(defined(__amd64__) || defined(__i386__))
88 #error ns8250 early putc is x86 specific as it uses inb/outb
89 #endif
90 static void
uart_ns8250_early_putc(int c)91 uart_ns8250_early_putc(int c)
92 {
93 u_int stat = UART_NS8250_EARLY_PORT + REG_LSR;
94 u_int tx = UART_NS8250_EARLY_PORT + REG_DATA;
95 int limit = 10000; /* 10ms is plenty of time */
96
97 while ((inb(stat) & LSR_THRE) == 0 && --limit > 0)
98 continue;
99 outb(tx, c);
100 }
101 early_putc_t *early_putc = uart_ns8250_early_putc;
102 #endif /* EARLY_PRINTF */
103
104 /*
105 * Clear pending interrupts. THRE is cleared by reading IIR. Data
106 * that may have been received gets lost here.
107 */
108 static void
ns8250_clrint(struct uart_bas * bas)109 ns8250_clrint(struct uart_bas *bas)
110 {
111 uint8_t iir, lsr;
112
113 iir = uart_getreg(bas, REG_IIR);
114 while ((iir & IIR_NOPEND) == 0) {
115 iir &= IIR_IMASK;
116 if (iir == IIR_RLS) {
117 lsr = uart_getreg(bas, REG_LSR);
118 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
119 (void)uart_getreg(bas, REG_DATA);
120 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
121 (void)uart_getreg(bas, REG_DATA);
122 else if (iir == IIR_MLSC)
123 (void)uart_getreg(bas, REG_MSR);
124 uart_barrier(bas);
125 iir = uart_getreg(bas, REG_IIR);
126 }
127 }
128
129 static int
ns8250_delay(struct uart_bas * bas)130 ns8250_delay(struct uart_bas *bas)
131 {
132 int divisor;
133 u_char lcr;
134
135 lcr = uart_getreg(bas, REG_LCR);
136 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
137 uart_barrier(bas);
138 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
139 uart_barrier(bas);
140 uart_setreg(bas, REG_LCR, lcr);
141 uart_barrier(bas);
142
143 /* 1/10th the time to transmit 1 character (estimate). */
144 if (divisor <= 134)
145 return (16000000 * divisor / bas->rclk);
146 return (16000 * divisor / (bas->rclk / 1000));
147 }
148
149 static int
ns8250_divisor(int rclk,int baudrate)150 ns8250_divisor(int rclk, int baudrate)
151 {
152 int actual_baud, divisor;
153 int error;
154
155 if (baudrate == 0)
156 return (0);
157
158 divisor = (rclk / (baudrate << 3) + 1) >> 1;
159 if (divisor == 0 || divisor >= 65536)
160 return (0);
161 actual_baud = rclk / (divisor << 4);
162
163 /* 10 times error in percent: */
164 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2;
165
166 /* enforce maximum error tolerance: */
167 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT)
168 return (0);
169
170 return (divisor);
171 }
172
173 static int
ns8250_drain(struct uart_bas * bas,int what)174 ns8250_drain(struct uart_bas *bas, int what)
175 {
176 int delay, limit;
177
178 delay = ns8250_delay(bas);
179
180 if (what & UART_DRAIN_TRANSMITTER) {
181 /*
182 * Pick an arbitrary high limit to avoid getting stuck in
183 * an infinite loop when the hardware is broken. Make the
184 * limit high enough to handle large FIFOs.
185 */
186 limit = 10*1024;
187 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
188 DELAY(delay);
189 if (limit == 0) {
190 /* printf("ns8250: transmitter appears stuck... "); */
191 return (EIO);
192 }
193 }
194
195 if (what & UART_DRAIN_RECEIVER) {
196 /*
197 * Pick an arbitrary high limit to avoid getting stuck in
198 * an infinite loop when the hardware is broken. Make the
199 * limit high enough to handle large FIFOs and integrated
200 * UARTs. The HP rx2600 for example has 3 UARTs on the
201 * management board that tend to get a lot of data send
202 * to it when the UART is first activated. Assume that we
203 * have finished draining if LSR_RXRDY is not asserted both
204 * prior to and after a DELAY; but as long as LSR_RXRDY is
205 * asserted, read (and discard) characters as quickly as
206 * possible.
207 */
208 limit=10*4096;
209 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
210 do {
211 (void)uart_getreg(bas, REG_DATA);
212 uart_barrier(bas);
213 } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit);
214 uart_barrier(bas);
215 DELAY(delay << 2);
216 }
217 if (limit == 0) {
218 /* printf("ns8250: receiver appears broken... "); */
219 return (EIO);
220 }
221 }
222
223 return (0);
224 }
225
226 /*
227 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
228 * drained. WARNING: this function clobbers the FIFO setting!
229 */
230 static void
ns8250_flush(struct uart_bas * bas,int what)231 ns8250_flush(struct uart_bas *bas, int what)
232 {
233 uint8_t fcr;
234 uint8_t lsr;
235 int drain = 0;
236
237 fcr = FCR_ENABLE;
238 if (what & UART_FLUSH_TRANSMITTER)
239 fcr |= FCR_XMT_RST;
240 if (what & UART_FLUSH_RECEIVER)
241 fcr |= FCR_RCV_RST;
242 uart_setreg(bas, REG_FCR, fcr);
243 uart_barrier(bas);
244
245 /*
246 * Detect and work around emulated UARTs which don't implement the
247 * FCR register; on these systems we need to drain the FIFO since
248 * the flush we request doesn't happen. One such system is the
249 * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code:
250 * https://github.com/rust-vmm/vm-superio/issues/83
251 */
252 lsr = uart_getreg(bas, REG_LSR);
253 if (((lsr & LSR_TEMT) == 0) && (what & UART_FLUSH_TRANSMITTER))
254 drain |= UART_DRAIN_TRANSMITTER;
255 if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER))
256 drain |= UART_DRAIN_RECEIVER;
257 if (drain != 0) {
258 printf("ns8250: UART FCR is broken\n");
259 ns8250_drain(bas, drain);
260 }
261 }
262
263 static int
ns8250_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)264 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
265 int parity)
266 {
267 int divisor;
268 uint8_t lcr;
269
270 /* Don't change settings when running on Hyper-V */
271 if (vm_guest == VM_GUEST_HV)
272 return (0);
273
274 lcr = 0;
275 if (databits >= 8)
276 lcr |= LCR_8BITS;
277 else if (databits == 7)
278 lcr |= LCR_7BITS;
279 else if (databits == 6)
280 lcr |= LCR_6BITS;
281 else
282 lcr |= LCR_5BITS;
283 if (stopbits > 1)
284 lcr |= LCR_STOPB;
285 lcr |= parity << 3;
286
287 /* Set baudrate. */
288 if (baudrate > 0) {
289 divisor = ns8250_divisor(bas->rclk, baudrate);
290 if (divisor == 0)
291 return (EINVAL);
292 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
293 uart_barrier(bas);
294 uart_setreg(bas, REG_DLL, divisor & 0xff);
295 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
296 uart_barrier(bas);
297 }
298
299 /* Set LCR and clear DLAB. */
300 uart_setreg(bas, REG_LCR, lcr);
301 uart_barrier(bas);
302 return (0);
303 }
304
305 /*
306 * Low-level UART interface.
307 */
308 static int ns8250_probe(struct uart_bas *bas);
309 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
310 static void ns8250_term(struct uart_bas *bas);
311 static void ns8250_putc(struct uart_bas *bas, int);
312 static int ns8250_rxready(struct uart_bas *bas);
313 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
314
315 struct uart_ops uart_ns8250_ops = {
316 .probe = ns8250_probe,
317 .init = ns8250_init,
318 .term = ns8250_term,
319 .putc = ns8250_putc,
320 .rxready = ns8250_rxready,
321 .getc = ns8250_getc,
322 };
323
324 static int
ns8250_probe(struct uart_bas * bas)325 ns8250_probe(struct uart_bas *bas)
326 {
327 u_char val;
328
329 /* Check known 0 bits that don't depend on DLAB. */
330 val = uart_getreg(bas, REG_IIR);
331 if (val & 0x30)
332 return (ENXIO);
333 /*
334 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
335 * chip, but otherwise doesn't seem to have a function. In
336 * other words, uart(4) works regardless. Ignore that bit so
337 * the probe succeeds.
338 */
339 val = uart_getreg(bas, REG_MCR);
340 if (val & 0xa0)
341 return (ENXIO);
342
343 return (0);
344 }
345
346 static void
ns8250_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)347 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
348 int parity)
349 {
350 u_char ier;
351
352 if (bas->rclk == 0)
353 bas->rclk = DEFAULT_RCLK;
354 ns8250_param(bas, baudrate, databits, stopbits, parity);
355
356 /* Disable all interrupt sources. */
357 /*
358 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
359 * UARTs split the receive time-out interrupt bit out separately as
360 * 0x10. This gets handled by ier_mask and ier_rxbits below.
361 */
362 ier = uart_getreg(bas, REG_IER) & 0xe0;
363 uart_setreg(bas, REG_IER, ier);
364 uart_barrier(bas);
365
366 /* Disable the FIFO (if present). */
367 uart_setreg(bas, REG_FCR, 0);
368 uart_barrier(bas);
369
370 /* Set RTS & DTR. */
371 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
372 uart_barrier(bas);
373
374 ns8250_clrint(bas);
375 }
376
377 static void
ns8250_term(struct uart_bas * bas)378 ns8250_term(struct uart_bas *bas)
379 {
380
381 /* Clear RTS & DTR. */
382 uart_setreg(bas, REG_MCR, MCR_IE);
383 uart_barrier(bas);
384 }
385
386 static void
ns8250_putc(struct uart_bas * bas,int c)387 ns8250_putc(struct uart_bas *bas, int c)
388 {
389 int limit;
390
391 if (vm_guest != VM_GUEST_HV) {
392 limit = 250000;
393 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
394 DELAY(4);
395 }
396 uart_setreg(bas, REG_DATA, c);
397 uart_barrier(bas);
398 }
399
400 static int
ns8250_rxready(struct uart_bas * bas)401 ns8250_rxready(struct uart_bas *bas)
402 {
403
404 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
405 }
406
407 static int
ns8250_getc(struct uart_bas * bas,struct mtx * hwmtx)408 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
409 {
410 int c;
411
412 uart_lock(hwmtx);
413
414 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
415 uart_unlock(hwmtx);
416 DELAY(4);
417 uart_lock(hwmtx);
418 }
419
420 c = uart_getreg(bas, REG_DATA);
421
422 uart_unlock(hwmtx);
423
424 return (c);
425 }
426
427 static kobj_method_t ns8250_methods[] = {
428 KOBJMETHOD(uart_attach, ns8250_bus_attach),
429 KOBJMETHOD(uart_detach, ns8250_bus_detach),
430 KOBJMETHOD(uart_flush, ns8250_bus_flush),
431 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
432 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
433 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
434 KOBJMETHOD(uart_param, ns8250_bus_param),
435 KOBJMETHOD(uart_probe, ns8250_bus_probe),
436 KOBJMETHOD(uart_receive, ns8250_bus_receive),
437 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
438 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
439 KOBJMETHOD(uart_txbusy, ns8250_bus_txbusy),
440 KOBJMETHOD(uart_grab, ns8250_bus_grab),
441 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
442 KOBJMETHOD_END
443 };
444
445 struct uart_class uart_ns8250_class = {
446 "ns8250",
447 ns8250_methods,
448 sizeof(struct ns8250_softc),
449 .uc_ops = &uart_ns8250_ops,
450 .uc_range = 8,
451 .uc_rclk = DEFAULT_RCLK,
452 .uc_rshift = 0
453 };
454 UART_CLASS(uart_ns8250_class);
455
456 /*
457 * XXX -- refactor out ACPI and FDT ifdefs
458 */
459 #ifdef DEV_ACPI
460 static struct acpi_uart_compat_data acpi_compat_data[] = {
461 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
462 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
463 {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"},
464 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"},
465 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"},
466 {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"},
467 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"},
468 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"},
469 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"},
470 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"},
471 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"},
472 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"},
473 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"},
474 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"},
475 {NULL, NULL, 0, 0 , 0, 0, 0, NULL},
476 };
477 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data);
478 #endif
479
480 #ifdef FDT
481 static struct ofw_compat_data compat_data[] = {
482 {"ns16550", (uintptr_t)&uart_ns8250_class},
483 {"ns16550a", (uintptr_t)&uart_ns8250_class},
484 {NULL, (uintptr_t)NULL},
485 };
486 UART_FDT_CLASS_AND_DEVICE(compat_data);
487 #endif
488
489 /* Use token-pasting to form SER_ and MSR_ named constants. */
490 #define SER(sig) SER_##sig
491 #define SERD(sig) SER_D##sig
492 #define MSR(sig) MSR_##sig
493 #define MSRD(sig) MSR_D##sig
494
495 /*
496 * Detect signal changes using software delta detection. The previous state of
497 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
498 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
499 * new state of both the signal and the delta bits.
500 */
501 #define SIGCHGSW(var, msr, sig) \
502 if ((msr) & MSR(sig)) { \
503 if ((var & SER(sig)) == 0) \
504 var |= SERD(sig) | SER(sig); \
505 } else { \
506 if ((var & SER(sig)) != 0) \
507 var = SERD(sig) | (var & ~SER(sig)); \
508 }
509
510 /*
511 * Detect signal changes using the hardware msr delta bits. This is currently
512 * used only when PPS timing information is being captured using the "narrow
513 * pulse" option. With a narrow PPS pulse the signal may not still be asserted
514 * by time the interrupt handler is invoked. The hardware will latch the fact
515 * that it changed in the delta bits.
516 */
517 #define SIGCHGHW(var, msr, sig) \
518 if ((msr) & MSRD(sig)) { \
519 if (((msr) & MSR(sig)) != 0) \
520 var |= SERD(sig) | SER(sig); \
521 else \
522 var = SERD(sig) | (var & ~SER(sig)); \
523 }
524
525 int
ns8250_bus_attach(struct uart_softc * sc)526 ns8250_bus_attach(struct uart_softc *sc)
527 {
528 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
529 struct uart_bas *bas;
530 unsigned int ivar;
531 #ifdef FDT
532 phandle_t node;
533 pcell_t cell;
534 #endif
535
536 #ifdef FDT
537 /* Check whether uart has a broken txfifo. */
538 node = ofw_bus_get_node(sc->sc_dev);
539 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
540 broken_txfifo = cell ? 1 : 0;
541 #endif
542
543 bas = &sc->sc_bas;
544
545 ns8250->busy_detect = bas->busy_detect;
546 ns8250->mcr = uart_getreg(bas, REG_MCR);
547 ns8250->fcr = FCR_ENABLE;
548 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
549 &ivar)) {
550 if (UART_FLAGS_FCR_RX_LOW(ivar))
551 ns8250->fcr |= FCR_RX_LOW;
552 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
553 ns8250->fcr |= FCR_RX_MEDL;
554 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
555 ns8250->fcr |= FCR_RX_HIGH;
556 else
557 ns8250->fcr |= FCR_RX_MEDH;
558 } else
559 ns8250->fcr |= FCR_RX_MEDH;
560
561 /* Get IER mask */
562 ivar = 0xf0;
563 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
564 &ivar);
565 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
566
567 /* Get IER RX interrupt bits */
568 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
569 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
570 &ivar);
571 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
572
573 uart_setreg(bas, REG_FCR, ns8250->fcr);
574 uart_barrier(bas);
575 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
576
577 if (ns8250->mcr & MCR_DTR)
578 sc->sc_hwsig |= SER_DTR;
579 if (ns8250->mcr & MCR_RTS)
580 sc->sc_hwsig |= SER_RTS;
581 ns8250_bus_getsig(sc);
582
583 ns8250_clrint(bas);
584 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
585 ns8250->ier |= ns8250->ier_rxbits;
586 uart_setreg(bas, REG_IER, ns8250->ier);
587 uart_barrier(bas);
588
589 /*
590 * Timing of the H/W access was changed with r253161 of uart_core.c
591 * It has been observed that an ITE IT8513E would signal a break
592 * condition with pretty much every character it received, unless
593 * it had enough time to settle between ns8250_bus_attach() and
594 * ns8250_bus_ipend() -- which it accidentally had before r253161.
595 * It's not understood why the UART chip behaves this way and it
596 * could very well be that the DELAY make the H/W work in the same
597 * accidental manner as before. More analysis is warranted, but
598 * at least now we fixed a known regression.
599 */
600 DELAY(200);
601 return (0);
602 }
603
604 int
ns8250_bus_detach(struct uart_softc * sc)605 ns8250_bus_detach(struct uart_softc *sc)
606 {
607 struct ns8250_softc *ns8250;
608 struct uart_bas *bas;
609 u_char ier;
610
611 ns8250 = (struct ns8250_softc *)sc;
612 bas = &sc->sc_bas;
613 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
614 uart_setreg(bas, REG_IER, ier);
615 uart_barrier(bas);
616 ns8250_clrint(bas);
617 return (0);
618 }
619
620 int
ns8250_bus_flush(struct uart_softc * sc,int what)621 ns8250_bus_flush(struct uart_softc *sc, int what)
622 {
623 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
624 struct uart_bas *bas;
625 int error;
626
627 bas = &sc->sc_bas;
628 uart_lock(sc->sc_hwmtx);
629 if (sc->sc_rxfifosz > 1) {
630 ns8250_flush(bas, what);
631 uart_setreg(bas, REG_FCR, ns8250->fcr);
632 uart_barrier(bas);
633 error = 0;
634 } else
635 error = ns8250_drain(bas, what);
636 uart_unlock(sc->sc_hwmtx);
637 return (error);
638 }
639
640 int
ns8250_bus_getsig(struct uart_softc * sc)641 ns8250_bus_getsig(struct uart_softc *sc)
642 {
643 uint32_t old, sig;
644 uint8_t msr;
645
646 /*
647 * The delta bits are reputed to be broken on some hardware, so use
648 * software delta detection by default. Use the hardware delta bits
649 * when capturing PPS pulses which are too narrow for software detection
650 * to see the edges. Hardware delta for RI doesn't work like the
651 * others, so always use software for it. Other threads may be changing
652 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully
653 * update without other changes happening. Note that the SIGCHGxx()
654 * macros carefully preserve the delta bits when we have to loop several
655 * times and a signal transitions between iterations.
656 */
657 do {
658 old = sc->sc_hwsig;
659 sig = old;
660 uart_lock(sc->sc_hwmtx);
661 msr = uart_getreg(&sc->sc_bas, REG_MSR);
662 uart_unlock(sc->sc_hwmtx);
663 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
664 SIGCHGHW(sig, msr, DSR);
665 SIGCHGHW(sig, msr, CTS);
666 SIGCHGHW(sig, msr, DCD);
667 } else {
668 SIGCHGSW(sig, msr, DSR);
669 SIGCHGSW(sig, msr, CTS);
670 SIGCHGSW(sig, msr, DCD);
671 }
672 SIGCHGSW(sig, msr, RI);
673 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
674 return (sig);
675 }
676
677 int
ns8250_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)678 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
679 {
680 struct uart_bas *bas;
681 int baudrate, divisor, error;
682 uint8_t efr, lcr;
683
684 bas = &sc->sc_bas;
685 error = 0;
686 uart_lock(sc->sc_hwmtx);
687 switch (request) {
688 case UART_IOCTL_BREAK:
689 lcr = uart_getreg(bas, REG_LCR);
690 if (data)
691 lcr |= LCR_SBREAK;
692 else
693 lcr &= ~LCR_SBREAK;
694 uart_setreg(bas, REG_LCR, lcr);
695 uart_barrier(bas);
696 break;
697 case UART_IOCTL_IFLOW:
698 lcr = uart_getreg(bas, REG_LCR);
699 uart_barrier(bas);
700 uart_setreg(bas, REG_LCR, 0xbf);
701 uart_barrier(bas);
702 efr = uart_getreg(bas, REG_EFR);
703 if (data)
704 efr |= EFR_RTS;
705 else
706 efr &= ~EFR_RTS;
707 uart_setreg(bas, REG_EFR, efr);
708 uart_barrier(bas);
709 uart_setreg(bas, REG_LCR, lcr);
710 uart_barrier(bas);
711 break;
712 case UART_IOCTL_OFLOW:
713 lcr = uart_getreg(bas, REG_LCR);
714 uart_barrier(bas);
715 uart_setreg(bas, REG_LCR, 0xbf);
716 uart_barrier(bas);
717 efr = uart_getreg(bas, REG_EFR);
718 if (data)
719 efr |= EFR_CTS;
720 else
721 efr &= ~EFR_CTS;
722 uart_setreg(bas, REG_EFR, efr);
723 uart_barrier(bas);
724 uart_setreg(bas, REG_LCR, lcr);
725 uart_barrier(bas);
726 break;
727 case UART_IOCTL_BAUD:
728 lcr = uart_getreg(bas, REG_LCR);
729 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
730 uart_barrier(bas);
731 divisor = uart_getreg(bas, REG_DLL) |
732 (uart_getreg(bas, REG_DLH) << 8);
733 uart_barrier(bas);
734 uart_setreg(bas, REG_LCR, lcr);
735 uart_barrier(bas);
736 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
737 if (baudrate > 0)
738 *(int*)data = baudrate;
739 else
740 error = ENXIO;
741 break;
742 default:
743 error = EINVAL;
744 break;
745 }
746 uart_unlock(sc->sc_hwmtx);
747 return (error);
748 }
749
750 int
ns8250_bus_ipend(struct uart_softc * sc)751 ns8250_bus_ipend(struct uart_softc *sc)
752 {
753 struct uart_bas *bas;
754 struct ns8250_softc *ns8250;
755 int ipend;
756 uint8_t iir, lsr;
757
758 ns8250 = (struct ns8250_softc *)sc;
759 bas = &sc->sc_bas;
760 uart_lock(sc->sc_hwmtx);
761 iir = uart_getreg(bas, REG_IIR);
762
763 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
764 (void)uart_getreg(bas, DW_REG_USR);
765 uart_unlock(sc->sc_hwmtx);
766 return (0);
767 }
768 if (iir & IIR_NOPEND) {
769 uart_unlock(sc->sc_hwmtx);
770 return (0);
771 }
772 ipend = 0;
773 if (iir & IIR_RXRDY) {
774 lsr = uart_getreg(bas, REG_LSR);
775 if (lsr & LSR_OE)
776 ipend |= SER_INT_OVERRUN;
777 if (lsr & LSR_BI)
778 ipend |= SER_INT_BREAK;
779 if (lsr & LSR_RXRDY)
780 ipend |= SER_INT_RXREADY;
781 } else {
782 if (iir & IIR_TXRDY) {
783 ipend |= SER_INT_TXIDLE;
784 ns8250->ier &= ~IER_ETXRDY;
785 uart_setreg(bas, REG_IER, ns8250->ier);
786 uart_barrier(bas);
787 } else
788 ipend |= SER_INT_SIGCHG;
789 }
790 if (ipend == 0)
791 ns8250_clrint(bas);
792 uart_unlock(sc->sc_hwmtx);
793 return (ipend);
794 }
795
796 int
ns8250_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)797 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
798 int stopbits, int parity)
799 {
800 struct ns8250_softc *ns8250;
801 struct uart_bas *bas;
802 int error, limit;
803
804 ns8250 = (struct ns8250_softc*)sc;
805 bas = &sc->sc_bas;
806 uart_lock(sc->sc_hwmtx);
807 /*
808 * When using DW UART with BUSY detection it is necessary to wait
809 * until all serial transfers are finished before manipulating the
810 * line control. LCR will not be affected when UART is busy.
811 */
812 if (ns8250->busy_detect != 0) {
813 /*
814 * Pick an arbitrary high limit to avoid getting stuck in
815 * an infinite loop in case when the hardware is broken.
816 */
817 limit = 10 * 1024;
818 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
819 --limit)
820 DELAY(4);
821
822 if (limit <= 0) {
823 /* UART appears to be stuck */
824 uart_unlock(sc->sc_hwmtx);
825 return (EIO);
826 }
827 }
828
829 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
830 uart_unlock(sc->sc_hwmtx);
831 return (error);
832 }
833
834 int
ns8250_bus_probe(struct uart_softc * sc)835 ns8250_bus_probe(struct uart_softc *sc)
836 {
837 struct uart_bas *bas;
838 int count, delay, error, limit;
839 uint8_t lsr, mcr, ier;
840
841 bas = &sc->sc_bas;
842
843 error = ns8250_probe(bas);
844 if (error)
845 return (error);
846
847 mcr = MCR_IE;
848 if (sc->sc_sysdev == NULL) {
849 /* By using ns8250_init() we also set DTR and RTS. */
850 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
851 } else
852 mcr |= MCR_DTR | MCR_RTS;
853
854 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
855 if (error)
856 return (error);
857
858 /*
859 * Set loopback mode. This avoids having garbage on the wire and
860 * also allows us send and receive data. We set DTR and RTS to
861 * avoid the possibility that automatic flow-control prevents
862 * any data from being sent.
863 */
864 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
865 uart_barrier(bas);
866
867 /*
868 * Enable FIFOs. And check that the UART has them. If not, we're
869 * done. Since this is the first time we enable the FIFOs, we reset
870 * them.
871 */
872 uart_setreg(bas, REG_FCR, FCR_ENABLE);
873 uart_barrier(bas);
874 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
875 /*
876 * NS16450 or INS8250. We don't bother to differentiate
877 * between them. They're too old to be interesting.
878 */
879 uart_setreg(bas, REG_MCR, mcr);
880 uart_barrier(bas);
881 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
882 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
883 return (0);
884 }
885
886 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
887 uart_barrier(bas);
888
889 count = 0;
890 delay = ns8250_delay(bas);
891
892 /* We have FIFOs. Drain the transmitter and receiver. */
893 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
894 if (error) {
895 uart_setreg(bas, REG_MCR, mcr);
896 uart_setreg(bas, REG_FCR, 0);
897 uart_barrier(bas);
898 goto describe;
899 }
900
901 /*
902 * We should have a sufficiently clean "pipe" to determine the
903 * size of the FIFOs. We send as much characters as is reasonable
904 * and wait for the overflow bit in the LSR register to be
905 * asserted, counting the characters as we send them. Based on
906 * that count we know the FIFO size.
907 */
908 do {
909 uart_setreg(bas, REG_DATA, 0);
910 uart_barrier(bas);
911 count++;
912
913 limit = 30;
914 lsr = 0;
915 /*
916 * LSR bits are cleared upon read, so we must accumulate
917 * them to be able to test LSR_OE below.
918 */
919 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
920 --limit)
921 DELAY(delay);
922 if (limit == 0) {
923 /* See the comment in ns8250_init(). */
924 ier = uart_getreg(bas, REG_IER) & 0xe0;
925 uart_setreg(bas, REG_IER, ier);
926 uart_setreg(bas, REG_MCR, mcr);
927 uart_setreg(bas, REG_FCR, 0);
928 uart_barrier(bas);
929 count = 0;
930 goto describe;
931 }
932 } while ((lsr & LSR_OE) == 0 && count < 260);
933 count--;
934
935 uart_setreg(bas, REG_MCR, mcr);
936
937 /* Reset FIFOs. */
938 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
939
940 describe:
941 if (count >= 14 && count <= 16) {
942 sc->sc_rxfifosz = 16;
943 device_set_desc(sc->sc_dev, "16550 or compatible");
944 } else if (count >= 28 && count <= 32) {
945 sc->sc_rxfifosz = 32;
946 device_set_desc(sc->sc_dev, "16650 or compatible");
947 } else if (count >= 56 && count <= 64) {
948 sc->sc_rxfifosz = 64;
949 device_set_desc(sc->sc_dev, "16750 or compatible");
950 } else if (count >= 112 && count <= 128) {
951 sc->sc_rxfifosz = 128;
952 device_set_desc(sc->sc_dev, "16950 or compatible");
953 } else if (count >= 224 && count <= 256) {
954 sc->sc_rxfifosz = 256;
955 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO");
956 } else {
957 sc->sc_rxfifosz = 16;
958 device_set_desc(sc->sc_dev,
959 "Non-standard ns8250 class UART with FIFOs");
960 }
961
962 /*
963 * Force the Tx FIFO size to 16 bytes for now. We don't program the
964 * Tx trigger. Also, we assume that all data has been sent when the
965 * interrupt happens.
966 */
967 sc->sc_txfifosz = 16;
968
969 #if 0
970 /*
971 * XXX there are some issues related to hardware flow control and
972 * it's likely that uart(4) is the cause. This basically needs more
973 * investigation, but we avoid using for hardware flow control
974 * until then.
975 */
976 /* 16650s or higher have automatic flow control. */
977 if (sc->sc_rxfifosz > 16) {
978 sc->sc_hwiflow = 1;
979 sc->sc_hwoflow = 1;
980 }
981 #endif
982
983 return (0);
984 }
985
986 int
ns8250_bus_receive(struct uart_softc * sc)987 ns8250_bus_receive(struct uart_softc *sc)
988 {
989 struct uart_bas *bas;
990 int xc;
991 uint8_t lsr;
992
993 bas = &sc->sc_bas;
994 uart_lock(sc->sc_hwmtx);
995 lsr = uart_getreg(bas, REG_LSR);
996 while (lsr & LSR_RXRDY) {
997 if (uart_rx_full(sc)) {
998 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
999 break;
1000 }
1001 xc = uart_getreg(bas, REG_DATA);
1002 if (lsr & LSR_FE)
1003 xc |= UART_STAT_FRAMERR;
1004 if (lsr & LSR_PE)
1005 xc |= UART_STAT_PARERR;
1006 uart_rx_put(sc, xc);
1007 lsr = uart_getreg(bas, REG_LSR);
1008 }
1009 /* Discard everything left in the Rx FIFO. */
1010 while (lsr & LSR_RXRDY) {
1011 (void)uart_getreg(bas, REG_DATA);
1012 uart_barrier(bas);
1013 lsr = uart_getreg(bas, REG_LSR);
1014 }
1015 uart_unlock(sc->sc_hwmtx);
1016 return (0);
1017 }
1018
1019 int
ns8250_bus_setsig(struct uart_softc * sc,int sig)1020 ns8250_bus_setsig(struct uart_softc *sc, int sig)
1021 {
1022 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1023 struct uart_bas *bas;
1024 uint32_t new, old;
1025
1026 bas = &sc->sc_bas;
1027 do {
1028 old = sc->sc_hwsig;
1029 new = old;
1030 if (sig & SER_DDTR) {
1031 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
1032 }
1033 if (sig & SER_DRTS) {
1034 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
1035 }
1036 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
1037 uart_lock(sc->sc_hwmtx);
1038 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
1039 if (new & SER_DTR)
1040 ns8250->mcr |= MCR_DTR;
1041 if (new & SER_RTS)
1042 ns8250->mcr |= MCR_RTS;
1043 uart_setreg(bas, REG_MCR, ns8250->mcr);
1044 uart_barrier(bas);
1045 uart_unlock(sc->sc_hwmtx);
1046 return (0);
1047 }
1048
1049 int
ns8250_bus_transmit(struct uart_softc * sc)1050 ns8250_bus_transmit(struct uart_softc *sc)
1051 {
1052 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1053 struct uart_bas *bas;
1054 int i;
1055
1056 bas = &sc->sc_bas;
1057 uart_lock(sc->sc_hwmtx);
1058 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
1059 DELAY(4);
1060 for (i = 0; i < sc->sc_txdatasz; i++) {
1061 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
1062 uart_barrier(bas);
1063 }
1064 if (!broken_txfifo)
1065 ns8250->ier |= IER_ETXRDY;
1066 uart_setreg(bas, REG_IER, ns8250->ier);
1067 uart_barrier(bas);
1068 if (broken_txfifo)
1069 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
1070 else
1071 sc->sc_txbusy = 1;
1072 uart_unlock(sc->sc_hwmtx);
1073 if (broken_txfifo)
1074 uart_sched_softih(sc, SER_INT_TXIDLE);
1075 return (0);
1076 }
1077
1078 bool
ns8250_bus_txbusy(struct uart_softc * sc)1079 ns8250_bus_txbusy(struct uart_softc *sc)
1080 {
1081 struct uart_bas *bas = &sc->sc_bas;
1082
1083 if ((uart_getreg(bas, REG_LSR) & (LSR_TEMT | LSR_THRE)) !=
1084 (LSR_TEMT | LSR_THRE))
1085 return (true);
1086 return (false);
1087 }
1088
1089 void
ns8250_bus_grab(struct uart_softc * sc)1090 ns8250_bus_grab(struct uart_softc *sc)
1091 {
1092 struct uart_bas *bas = &sc->sc_bas;
1093 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1094 u_char ier;
1095
1096 /*
1097 * turn off all interrupts to enter polling mode. Leave the
1098 * saved mask alone. We'll restore whatever it was in ungrab.
1099 * All pending interrupt signals are reset when IER is set to 0.
1100 */
1101 uart_lock(sc->sc_hwmtx);
1102 ier = uart_getreg(bas, REG_IER);
1103 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
1104 uart_barrier(bas);
1105 uart_unlock(sc->sc_hwmtx);
1106 }
1107
1108 void
ns8250_bus_ungrab(struct uart_softc * sc)1109 ns8250_bus_ungrab(struct uart_softc *sc)
1110 {
1111 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1112 struct uart_bas *bas = &sc->sc_bas;
1113
1114 /*
1115 * Restore previous interrupt mask
1116 */
1117 uart_lock(sc->sc_hwmtx);
1118 uart_setreg(bas, REG_IER, ns8250->ier);
1119 uart_barrier(bas);
1120 uart_unlock(sc->sc_hwmtx);
1121 }
1122