xref: /freebsd/sys/dev/bxe/bxe_elink.h (revision 685dc743)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26  * THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 #ifndef ELINK_H
31 #define ELINK_H
32 
33 #define ELINK_DEBUG
34 
35 
36 
37 
38 
39 
40 /***********************************************************/
41 /*                  CLC Call backs functions               */
42 /***********************************************************/
43 /* CLC device structure */
44 struct bxe_softc;
45 
46 extern uint32_t elink_cb_reg_read(struct bxe_softc *sc, uint32_t reg_addr);
47 extern void elink_cb_reg_write(struct bxe_softc *sc, uint32_t reg_addr, uint32_t val);
48 /* wb_write - pointer to 2 32 bits vars to be passed to the DMAE*/
49 extern void elink_cb_reg_wb_write(struct bxe_softc *sc, uint32_t offset,
50 				uint32_t *wb_write, uint16_t len);
51 extern void elink_cb_reg_wb_read(struct bxe_softc *sc, uint32_t offset,
52 			       uint32_t *wb_write, uint16_t len);
53 
54 /* mode - 0( LOW ) /1(HIGH)*/
55 extern uint8_t elink_cb_gpio_write(struct bxe_softc *sc,
56 			    uint16_t gpio_num,
57 			    uint8_t mode, uint8_t port);
58 extern uint8_t elink_cb_gpio_mult_write(struct bxe_softc *sc,
59 			    uint8_t pins,
60 			    uint8_t mode);
61 
62 extern uint32_t elink_cb_gpio_read(struct bxe_softc *sc, uint16_t gpio_num, uint8_t port);
63 extern uint8_t elink_cb_gpio_int_write(struct bxe_softc *sc,
64 				uint16_t gpio_num,
65 				uint8_t mode, uint8_t port);
66 
67 extern uint32_t elink_cb_fw_command(struct bxe_softc *sc, uint32_t command, uint32_t param);
68 
69 /* Delay */
70 extern void elink_cb_udelay(struct bxe_softc *sc, uint32_t microsecond);
71 
72 /* This function is called every 1024 bytes downloading of phy firmware.
73 Driver can use it to print to screen indication for download progress */
74 extern void elink_cb_download_progress(struct bxe_softc *sc, uint32_t cur, uint32_t total);
75 
76 /* Each log type has its own parameters */
77 typedef enum elink_log_id {
78 	ELINK_LOG_ID_UNQUAL_IO_MODULE	= 0, /* uint8_t port, const char* vendor_name, const char* vendor_pn */
79 	ELINK_LOG_ID_OVER_CURRENT	= 1, /* uint8_t port */
80 	ELINK_LOG_ID_PHY_UNINITIALIZED	= 2, /* uint8_t port */
81 	ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */
82 	ELINK_LOG_ID_NON_10G_MODULE	= 4, /* uint8_t port */
83 }elink_log_id_t;
84 
85 typedef enum elink_status {
86 	ELINK_STATUS_OK = 0,
87 	ELINK_STATUS_ERROR,
88 	ELINK_STATUS_TIMEOUT,
89 	ELINK_STATUS_NO_LINK,
90 	ELINK_STATUS_INVALID_IMAGE,
91 	ELINK_OP_NOT_SUPPORTED = 122
92 } elink_status_t;
93 extern void elink_cb_event_log(struct bxe_softc *sc, const elink_log_id_t log_id, ...);
94 extern void elink_cb_load_warpcore_microcode(void);
95 
96 extern uint8_t elink_cb_path_id(struct bxe_softc *sc);
97 
98 extern void elink_cb_notify_link_changed(struct bxe_softc *sc);
99 
100 #define ELINK_EVENT_LOG_LEVEL_ERROR 	1
101 #define ELINK_EVENT_LOG_LEVEL_WARNING 	2
102 #define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE 	1
103 #define ELINK_EVENT_ID_SFP_POWER_FAULT 		2
104 
105 #define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
106 /* Debug prints */
107 #ifdef ELINK_DEBUG
108 
109 extern void elink_cb_dbg(struct bxe_softc *sc,  char *fmt);
110 extern void elink_cb_dbg1(struct bxe_softc *sc,  char *fmt, uint32_t arg1);
111 extern void elink_cb_dbg2(struct bxe_softc *sc,  char *fmt, uint32_t arg1, uint32_t arg2);
112 extern void elink_cb_dbg3(struct bxe_softc *sc,  char *fmt, uint32_t arg1, uint32_t arg2,
113 			  uint32_t arg3);
114 
115 #define ELINK_DEBUG_P0(sc, fmt) 		elink_cb_dbg(sc, fmt)
116 #define ELINK_DEBUG_P1(sc, fmt, arg1) 		elink_cb_dbg1(sc, fmt, arg1)
117 #define ELINK_DEBUG_P2(sc, fmt, arg1, arg2)	elink_cb_dbg2(sc, fmt, arg1, arg2)
118 #define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) \
119 					elink_cb_dbg3(sc, fmt, arg1, arg2, arg3)
120 #else
121 #define ELINK_DEBUG_P0(sc, fmt)
122 #define ELINK_DEBUG_P1(sc, fmt, arg1)
123 #define ELINK_DEBUG_P2(sc, fmt, arg1, arg2)
124 #define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3)
125 #endif
126 
127 /***********************************************************/
128 /*                         Defines                         */
129 /***********************************************************/
130 #define ELINK_DEFAULT_PHY_DEV_ADDR	3
131 #define ELINK_E2_DEFAULT_PHY_DEV_ADDR	5
132 
133 
134 #define DUPLEX_FULL			1
135 #define DUPLEX_HALF			2
136 
137 #define ELINK_FLOW_CTRL_AUTO		PORT_FEATURE_FLOW_CONTROL_AUTO
138 #define ELINK_FLOW_CTRL_TX		PORT_FEATURE_FLOW_CONTROL_TX
139 #define ELINK_FLOW_CTRL_RX		PORT_FEATURE_FLOW_CONTROL_RX
140 #define ELINK_FLOW_CTRL_BOTH		PORT_FEATURE_FLOW_CONTROL_BOTH
141 #define ELINK_FLOW_CTRL_NONE		PORT_FEATURE_FLOW_CONTROL_NONE
142 
143 #define ELINK_NET_SERDES_IF_XFI		1
144 #define ELINK_NET_SERDES_IF_SFI		2
145 #define ELINK_NET_SERDES_IF_KR		3
146 #define ELINK_NET_SERDES_IF_DXGXS	4
147 
148 #define ELINK_SPEED_AUTO_NEG		0
149 #define ELINK_SPEED_10			10
150 #define ELINK_SPEED_100			100
151 #define ELINK_SPEED_1000		1000
152 #define ELINK_SPEED_2500		2500
153 #define ELINK_SPEED_10000		10000
154 #define ELINK_SPEED_20000		20000
155 
156 #define ELINK_I2C_DEV_ADDR_A0			0xa0
157 #define ELINK_I2C_DEV_ADDR_A2			0xa2
158 
159 #define ELINK_SFP_EEPROM_PAGE_SIZE			16
160 #define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR		0x14
161 #define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE		16
162 #define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR		0x25
163 #define ELINK_SFP_EEPROM_VENDOR_OUI_SIZE		3
164 #define ELINK_SFP_EEPROM_PART_NO_ADDR			0x28
165 #define ELINK_SFP_EEPROM_PART_NO_SIZE			16
166 #define ELINK_SFP_EEPROM_REVISION_ADDR		0x38
167 #define ELINK_SFP_EEPROM_REVISION_SIZE		4
168 #define ELINK_SFP_EEPROM_SERIAL_ADDR			0x44
169 #define ELINK_SFP_EEPROM_SERIAL_SIZE			16
170 #define ELINK_SFP_EEPROM_DATE_ADDR			0x54 /* ASCII YYMMDD */
171 #define ELINK_SFP_EEPROM_DATE_SIZE			6
172 #define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR			0x5c
173 #define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE			1
174 #define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ		(1<<2)
175 #define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR		0x5e
176 #define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE		1
177 #define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_ADDR	0x60
178 #define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_SIZE	16
179 
180 
181 #define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE		0x5e
182 #define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR			0x5f
183 
184 #define ELINK_PWR_FLT_ERR_MSG_LEN			250
185 
186 #define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \
187 		((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
188 #define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \
189 		(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
190 		 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
191 #define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \
192 		((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
193 
194 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
195 #define ELINK_SINGLE_MEDIA_DIRECT(params)	(params->num_phys == 1)
196 /* Single Media board contains single external phy */
197 #define ELINK_SINGLE_MEDIA(params)		(params->num_phys == 2)
198 /* Dual Media board contains two external phy with different media */
199 #define ELINK_DUAL_MEDIA(params)		(params->num_phys == 3)
200 
201 #define ELINK_FW_PARAM_PHY_ADDR_MASK		0x000000FF
202 #define ELINK_FW_PARAM_PHY_TYPE_MASK		0x0000FF00
203 #define ELINK_FW_PARAM_MDIO_CTRL_MASK		0xFFFF0000
204 #define ELINK_FW_PARAM_MDIO_CTRL_OFFSET		16
205 #define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
206 					   ELINK_FW_PARAM_PHY_ADDR_MASK)
207 #define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
208 					   ELINK_FW_PARAM_PHY_TYPE_MASK)
209 #define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
210 					    ELINK_FW_PARAM_MDIO_CTRL_MASK) >> \
211 					    ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
212 #define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
213 	(phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
214 
215 
216 #define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD				170
217 #define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD				250
218 
219 #define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
220 
221 #define ELINK_BMAC_CONTROL_RX_ENABLE		2
222 /***********************************************************/
223 /*                         Structs                         */
224 /***********************************************************/
225 #define ELINK_INT_PHY		0
226 #define ELINK_EXT_PHY1	1
227 #define ELINK_EXT_PHY2	2
228 #define ELINK_MAX_PHYS	3
229 
230 /* Same configuration is shared between the XGXS and the first external phy */
231 #define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1)
232 #define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \
233 					 0 : (_phy_idx - 1))
234 /***********************************************************/
235 /*                      elink_phy struct                   */
236 /*  Defines the required arguments and function per phy    */
237 /***********************************************************/
238 struct elink_vars;
239 struct elink_params;
240 struct elink_phy;
241 
242 typedef uint8_t (*config_init_t)(struct elink_phy *phy, struct elink_params *params,
243 			    struct elink_vars *vars);
244 typedef uint8_t (*read_status_t)(struct elink_phy *phy, struct elink_params *params,
245 			    struct elink_vars *vars);
246 typedef void (*link_reset_t)(struct elink_phy *phy,
247 			     struct elink_params *params);
248 typedef void (*config_loopback_t)(struct elink_phy *phy,
249 				  struct elink_params *params);
250 typedef uint8_t (*format_fw_ver_t)(uint32_t raw, uint8_t *str, uint16_t *len);
251 typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params);
252 typedef void (*set_link_led_t)(struct elink_phy *phy,
253 			       struct elink_params *params, uint8_t mode);
254 typedef void (*phy_specific_func_t)(struct elink_phy *phy,
255 				    struct elink_params *params, uint32_t action);
256 struct elink_reg_set {
257 	uint8_t  devad;
258 	uint16_t reg;
259 	uint16_t val;
260 };
261 
262 struct elink_phy {
263 	uint32_t type;
264 
265 	/* Loaded during init */
266 	uint8_t addr;
267 	uint8_t def_md_devad;
268 	uint16_t flags;
269 	/* No Over-Current detection */
270 #define ELINK_FLAGS_NOC			(1<<1)
271 	/* Fan failure detection required */
272 #define ELINK_FLAGS_FAN_FAILURE_DET_REQ	(1<<2)
273 	/* Initialize first the XGXS and only then the phy itself */
274 #define ELINK_FLAGS_INIT_XGXS_FIRST		(1<<3)
275 #define ELINK_FLAGS_WC_DUAL_MODE		(1<<4)
276 #define ELINK_FLAGS_4_PORT_MODE		(1<<5)
277 #define ELINK_FLAGS_REARM_LATCH_SIGNAL		(1<<6)
278 #define ELINK_FLAGS_SFP_NOT_APPROVED		(1<<7)
279 #define ELINK_FLAGS_MDC_MDIO_WA		(1<<8)
280 #define ELINK_FLAGS_DUMMY_READ			(1<<9)
281 #define ELINK_FLAGS_MDC_MDIO_WA_B0		(1<<10)
282 #define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC	(1<<11)
283 #define ELINK_FLAGS_TX_ERROR_CHECK		(1<<12)
284 #define ELINK_FLAGS_EEE			(1<<13)
285 #define ELINK_FLAGS_TEMPERATURE		(1<<14)
286 #define ELINK_FLAGS_MDC_MDIO_WA_G		(1<<15)
287 
288 	/* preemphasis values for the rx side */
289 	uint16_t rx_preemphasis[4];
290 
291 	/* preemphasis values for the tx side */
292 	uint16_t tx_preemphasis[4];
293 
294 	/* EMAC address for access MDIO */
295 	uint32_t mdio_ctrl;
296 
297 	uint32_t supported;
298 #define ELINK_SUPPORTED_10baseT_Half		(1<<0)
299 #define ELINK_SUPPORTED_10baseT_Full		(1<<1)
300 #define ELINK_SUPPORTED_100baseT_Half		(1<<2)
301 #define ELINK_SUPPORTED_100baseT_Full 		(1<<3)
302 #define ELINK_SUPPORTED_1000baseT_Full 	(1<<4)
303 #define ELINK_SUPPORTED_2500baseX_Full 	(1<<5)
304 #define ELINK_SUPPORTED_10000baseT_Full 	(1<<6)
305 #define ELINK_SUPPORTED_TP 			(1<<7)
306 #define ELINK_SUPPORTED_FIBRE 			(1<<8)
307 #define ELINK_SUPPORTED_Autoneg 		(1<<9)
308 #define ELINK_SUPPORTED_Pause 			(1<<10)
309 #define ELINK_SUPPORTED_Asym_Pause		(1<<11)
310 #define ELINK_SUPPORTED_1000baseKX_Full		(1<<17)
311 #define ELINK_SUPPORTED_10000baseKR_Full	(1<<19)
312 #define ELINK_SUPPORTED_20000baseMLD2_Full	(1<<21)
313 #define ELINK_SUPPORTED_20000baseKR2_Full	(1<<22)
314 
315 	uint32_t media_type;
316 #define	ELINK_ETH_PHY_UNSPECIFIED	0x0
317 #define	ELINK_ETH_PHY_SFPP_10G_FIBER	0x1
318 #define	ELINK_ETH_PHY_XFP_FIBER		0x2
319 #define	ELINK_ETH_PHY_DA_TWINAX		0x3
320 #define	ELINK_ETH_PHY_BASE_T		0x4
321 #define ELINK_ETH_PHY_SFP_1G_FIBER	0x5
322 #define	ELINK_ETH_PHY_KR		0xf0
323 #define	ELINK_ETH_PHY_CX4		0xf1
324 #define	ELINK_ETH_PHY_NOT_PRESENT	0xff
325 
326 	/* The address in which version is located*/
327 	uint32_t ver_addr;
328 
329 	uint16_t req_flow_ctrl;
330 
331 	uint16_t req_line_speed;
332 
333 	uint32_t speed_cap_mask;
334 
335 	uint16_t req_duplex;
336 	uint16_t rsrv;
337 	/* Called per phy/port init, and it configures LASI, speed, autoneg,
338 	 duplex, flow control negotiation, etc. */
339 	config_init_t config_init;
340 
341 	/* Called due to interrupt. It determines the link, speed */
342 	read_status_t read_status;
343 
344 	/* Called when driver is unloading. Should reset the phy */
345 	link_reset_t link_reset;
346 
347 	/* Set the loopback configuration for the phy */
348 	config_loopback_t config_loopback;
349 
350 	/* Format the given raw number into str up to len */
351 	format_fw_ver_t format_fw_ver;
352 
353 	/* Reset the phy (both ports) */
354 	hw_reset_t hw_reset;
355 
356 	/* Set link led mode (on/off/oper)*/
357 	set_link_led_t set_link_led;
358 
359 	/* PHY Specific tasks */
360 	phy_specific_func_t phy_specific_func;
361 #define ELINK_DISABLE_TX	1
362 #define ELINK_ENABLE_TX	2
363 #define ELINK_PHY_INIT	3
364 };
365 
366 /* Inputs parameters to the CLC */
367 struct elink_params {
368 
369 	uint8_t port;
370 
371 	/* Default / User Configuration */
372 	uint8_t loopback_mode;
373 #define ELINK_LOOPBACK_NONE		0
374 #define ELINK_LOOPBACK_EMAC		1
375 #define ELINK_LOOPBACK_BMAC		2
376 #define ELINK_LOOPBACK_XGXS		3
377 #define ELINK_LOOPBACK_EXT_PHY		4
378 #define ELINK_LOOPBACK_EXT		5
379 #define ELINK_LOOPBACK_UMAC		6
380 #define ELINK_LOOPBACK_XMAC		7
381 
382 	/* Device parameters */
383 	uint8_t mac_addr[6];
384 
385 	uint16_t req_duplex[ELINK_LINK_CONFIG_SIZE];
386 	uint16_t req_flow_ctrl[ELINK_LINK_CONFIG_SIZE];
387 
388 	uint16_t req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
389 
390 	/* shmem parameters */
391 	uint32_t shmem_base;
392 	uint32_t shmem2_base;
393 	uint32_t speed_cap_mask[ELINK_LINK_CONFIG_SIZE];
394 	uint32_t switch_cfg;
395 #define ELINK_SWITCH_CFG_1G		PORT_FEATURE_CON_SWITCH_1G_SWITCH
396 #define ELINK_SWITCH_CFG_10G		PORT_FEATURE_CON_SWITCH_10G_SWITCH
397 #define ELINK_SWITCH_CFG_AUTO_DETECT	PORT_FEATURE_CON_SWITCH_AUTO_DETECT
398 
399 	uint32_t lane_config;
400 
401 	/* Phy register parameter */
402 	uint32_t chip_id;
403 
404 	/* features */
405 	uint32_t feature_config_flags;
406 #define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED	(1<<0)
407 #define ELINK_FEATURE_CONFIG_PFC_ENABLED			(1<<1)
408 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY		(1<<2)
409 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY	(1<<3)
410 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC			(1<<4)
411 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC			(1<<5)
412 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC			(1<<6)
413 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC			(1<<7)
414 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX			(1<<8)
415 #define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED		(1<<9)
416 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED	(1<<10)
417 #define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET		(1<<11)
418 #define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST			(1<<12)
419 #define ELINK_FEATURE_CONFIG_MT_SUPPORT			(1<<13)
420 #define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN			(1<<14)
421 #define ELINK_FEATURE_CONFIG_DISABLE_PD				(1<<15)
422 
423 	/* Will be populated during common init */
424 	struct elink_phy phy[ELINK_MAX_PHYS];
425 
426 	/* Will be populated during common init */
427 	uint8_t num_phys;
428 
429 	uint8_t rsrv;
430 
431 	/* Used to configure the EEE Tx LPI timer, has several modes of
432 	 * operation, according to bits 29:28 -
433 	 * 2'b00: Timer will be configured by nvram, output will be the value
434 	 *        from nvram.
435 	 * 2'b01: Timer will be configured by nvram, output will be in
436 	 *        microseconds.
437 	 * 2'b10: bits 1:0 contain an nvram value which will be used instead
438 	 *        of the one located in the nvram. Output will be that value.
439 	 * 2'b11: bits 19:0 contain the idle timer in microseconds; output
440 	 *        will be in microseconds.
441 	 * Bits 31:30 should be 2'b11 in order for EEE to be enabled.
442 	 */
443 	uint32_t eee_mode;
444 #define ELINK_EEE_MODE_NVRAM_BALANCED_TIME		(0xa00)
445 #define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME		(0x100)
446 #define ELINK_EEE_MODE_NVRAM_LATENCY_TIME		(0x6000)
447 #define ELINK_EEE_MODE_NVRAM_MASK		(0x3)
448 #define ELINK_EEE_MODE_TIMER_MASK		(0xfffff)
449 #define ELINK_EEE_MODE_OUTPUT_TIME		(1<<28)
450 #define ELINK_EEE_MODE_OVERRIDE_NVRAM		(1<<29)
451 #define ELINK_EEE_MODE_ENABLE_LPI		(1<<30)
452 #define ELINK_EEE_MODE_ADV_LPI			(1<<31)
453 
454 	uint16_t hw_led_mode; /* part of the hw_config read from the shmem */
455 	uint32_t multi_phy_config;
456 
457 	/* Device pointer passed to all callback functions */
458 	struct bxe_softc *sc;
459 	uint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when
460 				req_flow_ctrl is set to AUTO */
461 	uint16_t link_flags;
462 #define ELINK_LINK_FLAGS_INT_DISABLED		(1<<0)
463 #define ELINK_PHY_INITIALIZED		(1<<1)
464 	uint32_t lfa_base;
465 
466 	/* The same definitions as the shmem2 parameter */
467 	uint32_t link_attr_sync;
468 };
469 
470 /* Output parameters */
471 struct elink_vars {
472 	uint8_t phy_flags;
473 #define PHY_XGXS_FLAG			(1<<0)
474 #define PHY_SGMII_FLAG			(1<<1)
475 #define PHY_PHYSICAL_LINK_FLAG		(1<<2)
476 #define PHY_HALF_OPEN_CONN_FLAG		(1<<3)
477 #define PHY_OVER_CURRENT_FLAG		(1<<4)
478 #define PHY_SFP_TX_FAULT_FLAG		(1<<5)
479 
480 	uint8_t mac_type;
481 #define ELINK_MAC_TYPE_NONE		0
482 #define ELINK_MAC_TYPE_EMAC		1
483 #define ELINK_MAC_TYPE_BMAC		2
484 #define ELINK_MAC_TYPE_UMAC		3
485 #define ELINK_MAC_TYPE_XMAC		4
486 
487 	uint8_t phy_link_up; /* internal phy link indication */
488 	uint8_t link_up;
489 
490 	uint16_t line_speed;
491 	uint16_t duplex;
492 
493 	uint16_t flow_ctrl;
494 	uint16_t ieee_fc;
495 
496 	/* The same definitions as the shmem parameter */
497 	uint32_t link_status;
498 	uint32_t eee_status;
499 	uint8_t fault_detected;
500 	uint8_t check_kr2_recovery_cnt;
501 #define ELINK_CHECK_KR2_RECOVERY_CNT	5
502 	uint16_t periodic_flags;
503 #define ELINK_PERIODIC_FLAGS_LINK_EVENT	0x0001
504 
505 	uint32_t aeu_int_mask;
506 	uint8_t rx_tx_asic_rst;
507 	uint8_t turn_to_run_wc_rt;
508 	uint16_t rsrv2;
509 
510 };
511 
512 /***********************************************************/
513 /*                         Functions                       */
514 /***********************************************************/
515 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars);
516 
517 /* Reset the link. Should be called when driver or interface goes down
518    Before calling phy firmware upgrade, the reset_ext_phy should be set
519    to 0 */
520 elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars,
521 		     uint8_t reset_ext_phy);
522 elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars);
523 /* elink_link_update should be called upon link interrupt */
524 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars);
525 
526 /* use the following phy functions to read/write from external_phy
527   In order to use it to read/write internal phy registers, use
528   ELINK_DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
529   the register */
530 elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr,
531 		   uint8_t devad, uint16_t reg, uint16_t *ret_val);
532 
533 elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr,
534 		    uint8_t devad, uint16_t reg, uint16_t val);
535 
536 /* Reads the link_status from the shmem,
537    and update the link vars accordingly */
538 void elink_link_status_update(struct elink_params *input,
539 			    struct elink_vars *output);
540 /* returns string representing the fw_version of the external phy */
541 elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, uint8_t *version,
542 				 uint16_t len);
543 
544 /* Set/Unset the led
545    Basically, the CLC takes care of the led for the link, but in case one needs
546    to set/unset the led unnaturally, set the "mode" to ELINK_LED_MODE_OPER to
547    blink the led, and ELINK_LED_MODE_OFF to set the led off.*/
548 elink_status_t elink_set_led(struct elink_params *params,
549 		  struct elink_vars *vars, uint8_t mode, uint32_t speed);
550 #define ELINK_LED_MODE_OFF			0
551 #define ELINK_LED_MODE_ON			1
552 #define ELINK_LED_MODE_OPER			2
553 #define ELINK_LED_MODE_FRONT_PANEL_OFF	3
554 
555 /* elink_handle_module_detect_int should be called upon module detection
556    interrupt */
557 void elink_handle_module_detect_int(struct elink_params *params);
558 
559 /* Get the actual link status. In case it returns ELINK_STATUS_OK, link is up,
560 	otherwise link is down*/
561 elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars,
562 		    uint8_t is_serdes);
563 
564 
565 /* One-time initialization for external phy after power up */
566 elink_status_t elink_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base_path[],
567 			  uint32_t shmem2_base_path[], uint32_t chip_id, uint8_t one_port_enabled);
568 
569 /* Reset the external PHY using GPIO */
570 void elink_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port);
571 
572 /* Reset the external of SFX7101 */
573 void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy);
574 
575 /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
576 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
577 				 struct elink_params *params, uint8_t dev_addr,
578 				 uint16_t addr, uint16_t byte_cnt, uint8_t *o_buf);
579 
580 void elink_hw_reset_phy(struct elink_params *params);
581 
582 /* Check swap bit and adjust PHY order */
583 uint32_t elink_phy_selection(struct elink_params *params);
584 
585 /* Probe the phys on board, and populate them in "params" */
586 elink_status_t elink_phy_probe(struct elink_params *params);
587 
588 /* Checks if fan failure detection is required on one of the phys on board */
589 uint8_t elink_fan_failure_det_req(struct bxe_softc *sc, uint32_t shmem_base,
590 			     uint32_t shmem2_base, uint8_t port);
591 
592 /* Open / close the gate between the NIG and the BRB */
593 void elink_set_rx_filter(struct elink_params *params, uint8_t en);
594 
595 /* DCBX structs */
596 
597 /* Number of maximum COS per chip */
598 #define ELINK_DCBX_E2E3_MAX_NUM_COS		(2)
599 #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0	(6)
600 #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1	(3)
601 #define ELINK_DCBX_E3B0_MAX_NUM_COS		( \
602 			ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \
603 			    ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1))
604 
605 #define ELINK_DCBX_MAX_NUM_COS			( \
606 			ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \
607 			    ELINK_DCBX_E2E3_MAX_NUM_COS))
608 
609 /* PFC port configuration params */
610 struct elink_nig_brb_pfc_port_params {
611 	/* NIG */
612 	uint32_t pause_enable;
613 	uint32_t llfc_out_en;
614 	uint32_t llfc_enable;
615 	uint32_t pkt_priority_to_cos;
616 	uint8_t num_of_rx_cos_priority_mask;
617 	uint32_t rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS];
618 	uint32_t llfc_high_priority_classes;
619 	uint32_t llfc_low_priority_classes;
620 };
621 
622 
623 /* ETS port configuration params */
624 struct elink_ets_bw_params {
625 	uint8_t bw;
626 };
627 
628 struct elink_ets_sp_params {
629 	/**
630 	 * valid values are 0 - 5. 0 is highest strict priority.
631 	 * There can't be two COS's with the same pri.
632 	 */
633 	uint8_t pri;
634 };
635 
636 enum elink_cos_state {
637 	elink_cos_state_strict = 0,
638 	elink_cos_state_bw = 1,
639 };
640 
641 struct elink_ets_cos_params {
642 	enum elink_cos_state state ;
643 	union {
644 		struct elink_ets_bw_params bw_params;
645 		struct elink_ets_sp_params sp_params;
646 	} params;
647 };
648 
649 struct elink_ets_params {
650 	uint8_t num_of_cos; /* Number of valid COS entries*/
651 	struct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS];
652 };
653 
654 /* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
655  * when link is already up
656  */
657 elink_status_t elink_update_pfc(struct elink_params *params,
658 		      struct elink_vars *vars,
659 		      struct elink_nig_brb_pfc_port_params *pfc_params);
660 
661 
662 /* Used to configure the ETS to disable */
663 elink_status_t elink_ets_disabled(struct elink_params *params,
664 		       struct elink_vars *vars);
665 
666 /* Used to configure the ETS to BW limited */
667 void elink_ets_bw_limit(const struct elink_params *params, const uint32_t cos0_bw,
668 			const uint32_t cos1_bw);
669 
670 /* Used to configure the ETS to strict */
671 elink_status_t elink_ets_strict(const struct elink_params *params, const uint8_t strict_cos);
672 
673 
674 /*  Configure the COS to ETS according to BW and SP settings.*/
675 elink_status_t elink_ets_e3b0_config(const struct elink_params *params,
676 			 const struct elink_vars *vars,
677 			 struct elink_ets_params *ets_params);
678 /* Read pfc statistic*/
679 void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
680 						 uint32_t pfc_frames_sent[2],
681 						 uint32_t pfc_frames_received[2]);
682 void elink_init_mod_abs_int(struct bxe_softc *sc, struct elink_vars *vars,
683 			    uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,
684 			    uint8_t port);
685 //elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
686 //			       struct elink_params *params);
687 
688 void elink_period_func(struct elink_params *params, struct elink_vars *vars);
689 
690 //elink_status_t elink_check_half_open_conn(struct elink_params *params,
691 //			            struct elink_vars *vars, uint8_t notify);
692 
693 void elink_enable_pmd_tx(struct elink_params *params);
694 
695 
696 
697 #endif /* ELINK_H */
698 
699