xref: /openbsd/sys/dev/pci/if_em_hw.c (revision 9593dc34)
1 /*******************************************************************************
2 
3   Copyright (c) 2001-2005, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
8 
9    1. Redistributions of source code must retain the above copyright notice,
10       this list of conditions and the following disclaimer.
11 
12    2. Redistributions in binary form must reproduce the above copyright
13       notice, this list of conditions and the following disclaimer in the
14       documentation and/or other materials provided with the distribution.
15 
16    3. Neither the name of the Intel Corporation nor the names of its
17       contributors may be used to endorse or promote products derived from
18       this software without specific prior written permission.
19 
20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30   POSSIBILITY OF SUCH DAMAGE.
31 
32 *******************************************************************************/
33 
34 /* $OpenBSD: if_em_hw.c,v 1.123 2024/09/04 07:54:52 mglocker Exp $ */
35 /*
36  * if_em_hw.c Shared functions for accessing and configuring the MAC
37  */
38 
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/device.h>
42 
43 #include <net/if.h>
44 #include <net/if_media.h>
45 
46 #include <netinet/in.h>
47 #include <netinet/if_ether.h>
48 
49 #include <dev/pci/if_em.h>
50 #include <dev/pci/if_em_hw.h>
51 #include <dev/pci/if_em_soc.h>
52 
53 #include <dev/mii/rgephyreg.h>
54 
55 #define STATIC
56 
57 static int32_t	em_swfw_sync_acquire(struct em_hw *, uint16_t);
58 static void	em_swfw_sync_release(struct em_hw *, uint16_t);
59 static int32_t	em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *);
60 static int32_t	em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t);
61 static int32_t	em_get_software_semaphore(struct em_hw *);
62 static void	em_release_software_semaphore(struct em_hw *);
63 
64 static int32_t	em_check_downshift(struct em_hw *);
65 static void	em_clear_vfta(struct em_hw *);
66 void		em_clear_vfta_i350(struct em_hw *);
67 static int32_t	em_commit_shadow_ram(struct em_hw *);
68 static int32_t	em_config_dsp_after_link_change(struct em_hw *, boolean_t);
69 static int32_t	em_config_fc_after_link_up(struct em_hw *);
70 static int32_t	em_match_gig_phy(struct em_hw *);
71 static int32_t	em_detect_gig_phy(struct em_hw *);
72 static int32_t	em_erase_ich8_4k_segment(struct em_hw *, uint32_t);
73 static int32_t	em_get_auto_rd_done(struct em_hw *);
74 static int32_t	em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *);
75 static int32_t	em_get_hw_eeprom_semaphore(struct em_hw *);
76 static int32_t	em_get_phy_cfg_done(struct em_hw *);
77 static int32_t	em_get_software_flag(struct em_hw *);
78 static int32_t	em_ich8_cycle_init(struct em_hw *);
79 static int32_t	em_ich8_flash_cycle(struct em_hw *, uint32_t);
80 static int32_t	em_id_led_init(struct em_hw *);
81 static int32_t	em_init_lcd_from_nvm_config_region(struct em_hw *,  uint32_t,
82 		    uint32_t);
83 static int32_t	em_init_lcd_from_nvm(struct em_hw *);
84 static int32_t	em_phy_no_cable_workaround(struct em_hw *);
85 static void	em_init_rx_addrs(struct em_hw *);
86 static void	em_initialize_hardware_bits(struct em_softc *);
87 static void	em_toggle_lanphypc_pch_lpt(struct em_hw *);
88 static int	em_disable_ulp_lpt_lp(struct em_hw *hw, bool force);
89 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *);
90 static int32_t	em_kumeran_lock_loss_workaround(struct em_hw *);
91 static int32_t	em_mng_enable_host_if(struct em_hw *);
92 static int32_t	em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t,
93 		    uint16_t *);
94 static int32_t	em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t,
95 		    uint16_t *data);
96 static int32_t	em_poll_eerd_eewr_done(struct em_hw *, int);
97 static void	em_put_hw_eeprom_semaphore(struct em_hw *);
98 static int32_t	em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *);
99 static int32_t	em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t);
100 static int32_t	em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t);
101 static int32_t	em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *);
102 static int32_t	em_read_ich8_dword(struct em_hw *, uint32_t, uint32_t *);
103 static int32_t	em_read_ich8_data(struct em_hw *, uint32_t, uint32_t,
104 		    uint16_t *);
105 static int32_t	em_write_ich8_data(struct em_hw *, uint32_t, uint32_t,
106 		    uint16_t);
107 static int32_t	em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t,
108 		    uint16_t *);
109 static int32_t	em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t,
110 		    uint16_t *);
111 static int32_t	em_read_invm_i210(struct em_hw *, uint16_t, uint16_t,
112 		    uint16_t *);
113 static int32_t	em_read_invm_word_i210(struct em_hw *, uint16_t, uint16_t *);
114 static void	em_release_software_flag(struct em_hw *);
115 static int32_t	em_set_d3_lplu_state(struct em_hw *, boolean_t);
116 static int32_t	em_set_d0_lplu_state(struct em_hw *, boolean_t);
117 static int32_t	em_set_lplu_state_pchlan(struct em_hw *, boolean_t);
118 static int32_t	em_set_pci_ex_no_snoop(struct em_hw *, uint32_t);
119 static void	em_set_pci_express_master_disable(struct em_hw *);
120 static int32_t	em_wait_autoneg(struct em_hw *);
121 static void	em_write_reg_io(struct em_hw *, uint32_t, uint32_t);
122 static int32_t	em_set_phy_type(struct em_hw *);
123 static void	em_phy_init_script(struct em_hw *);
124 static int32_t	em_setup_copper_link(struct em_hw *);
125 static int32_t	em_setup_fiber_serdes_link(struct em_hw *);
126 static int32_t	em_adjust_serdes_amplitude(struct em_hw *);
127 static int32_t	em_phy_force_speed_duplex(struct em_hw *);
128 static int32_t	em_config_mac_to_phy(struct em_hw *);
129 static void	em_raise_mdi_clk(struct em_hw *, uint32_t *);
130 static void	em_lower_mdi_clk(struct em_hw *, uint32_t *);
131 static void	em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t);
132 static uint16_t	em_shift_in_mdi_bits(struct em_hw *);
133 static int32_t	em_phy_reset_dsp(struct em_hw *);
134 static int32_t	em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t,
135 		    uint16_t *);
136 static int32_t	em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t,
137 		    uint16_t *);
138 static int32_t	em_spi_eeprom_ready(struct em_hw *);
139 static void	em_raise_ee_clk(struct em_hw *, uint32_t *);
140 static void	em_lower_ee_clk(struct em_hw *, uint32_t *);
141 static void	em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t);
142 static int32_t	em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t);
143 static int32_t	em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *);
144 static uint16_t	em_shift_in_ee_bits(struct em_hw *, uint16_t);
145 static int32_t	em_acquire_eeprom(struct em_hw *);
146 static void	em_release_eeprom(struct em_hw *);
147 static void	em_standby_eeprom(struct em_hw *);
148 static int32_t	em_set_vco_speed(struct em_hw *);
149 static int32_t	em_polarity_reversal_workaround(struct em_hw *);
150 static int32_t	em_set_phy_mode(struct em_hw *);
151 static int32_t	em_host_if_read_cookie(struct em_hw *, uint8_t *);
152 static uint8_t	em_calculate_mng_checksum(char *, uint32_t);
153 static int32_t	em_configure_kmrn_for_10_100(struct em_hw *, uint16_t);
154 static int32_t	em_configure_kmrn_for_1000(struct em_hw *);
155 static int32_t	em_set_pciex_completion_timeout(struct em_hw *hw);
156 static int32_t	em_set_mdio_slow_mode_hv(struct em_hw *);
157 int32_t		em_hv_phy_workarounds_ich8lan(struct em_hw *);
158 int32_t		em_lv_phy_workarounds_ich8lan(struct em_hw *);
159 int32_t		em_link_stall_workaround_hv(struct em_hw *);
160 int32_t		em_k1_gig_workaround_hv(struct em_hw *, boolean_t);
161 int32_t		em_k1_workaround_lv(struct em_hw *);
162 int32_t		em_k1_workaround_lpt_lp(struct em_hw *, boolean_t);
163 int32_t		em_configure_k1_ich8lan(struct em_hw *, boolean_t);
164 void		em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t);
165 int32_t		em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t,
166 		    uint16_t *, boolean_t);
167 int32_t		em_access_phy_debug_regs_hv(struct em_hw *, uint32_t,
168 		    uint16_t *, boolean_t);
169 int32_t		em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *,
170 		    boolean_t);
171 int32_t		em_oem_bits_config_pchlan(struct em_hw *, boolean_t);
172 void		em_power_up_serdes_link_82575(struct em_hw *);
173 int32_t		em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *,
174     uint16_t *);
175 int32_t		em_set_eee_i350(struct em_hw *);
176 int32_t		em_set_eee_pchlan(struct em_hw *);
177 int32_t		em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *);
178 int32_t		em_initialize_M88E1512_phy(struct em_hw *);
179 
180 /* IGP cable length table */
181 static const uint16_t
182 em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
183     {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
184     5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
185     25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
186     40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
187     60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
188     90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
189     100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
190     110,
191     110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120,
192     120};
193 
194 static const uint16_t
195 em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
196     {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
197     0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
198     6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
199     21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
200     40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
201     60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
202     83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118,
203     121, 124};
204 
205 /******************************************************************************
206  * Set the phy type member in the hw struct.
207  *
208  * hw - Struct containing variables accessed by shared code
209  *****************************************************************************/
210 STATIC int32_t
em_set_phy_type(struct em_hw * hw)211 em_set_phy_type(struct em_hw *hw)
212 {
213 	DEBUGFUNC("em_set_phy_type");
214 
215 	if (hw->mac_type == em_undefined)
216 		return -E1000_ERR_PHY_TYPE;
217 
218 	switch (hw->phy_id) {
219 	case M88E1000_E_PHY_ID:
220 	case M88E1000_I_PHY_ID:
221 	case M88E1011_I_PHY_ID:
222 	case M88E1111_I_PHY_ID:
223 	case M88E1112_E_PHY_ID:
224 	case M88E1543_E_PHY_ID:
225 	case M88E1512_E_PHY_ID:
226 	case I210_I_PHY_ID:
227 	case I347AT4_E_PHY_ID:
228 		hw->phy_type = em_phy_m88;
229 		break;
230 	case IGP01E1000_I_PHY_ID:
231 		if (hw->mac_type == em_82541 ||
232 		    hw->mac_type == em_82541_rev_2 ||
233 		    hw->mac_type == em_82547 ||
234 		    hw->mac_type == em_82547_rev_2) {
235 			hw->phy_type = em_phy_igp;
236 			break;
237 		}
238 	case IGP03E1000_E_PHY_ID:
239 	case IGP04E1000_E_PHY_ID:
240 		hw->phy_type = em_phy_igp_3;
241 		break;
242 	case IFE_E_PHY_ID:
243 	case IFE_PLUS_E_PHY_ID:
244 	case IFE_C_E_PHY_ID:
245 		hw->phy_type = em_phy_ife;
246 		break;
247 	case M88E1141_E_PHY_ID:
248 		hw->phy_type = em_phy_oem;
249 		break;
250 	case I82577_E_PHY_ID:
251 		hw->phy_type = em_phy_82577;
252 		break;
253 	case I82578_E_PHY_ID:
254 		hw->phy_type = em_phy_82578;
255 		break;
256 	case I82579_E_PHY_ID:
257 		hw->phy_type = em_phy_82579;
258 		break;
259 	case I217_E_PHY_ID:
260 		hw->phy_type = em_phy_i217;
261 		break;
262 	case I82580_I_PHY_ID:
263 	case I350_I_PHY_ID:
264 		hw->phy_type = em_phy_82580;
265 		break;
266 	case RTL8211_E_PHY_ID:
267 		hw->phy_type = em_phy_rtl8211;
268 		break;
269 	case BME1000_E_PHY_ID:
270 		if (hw->phy_revision == 1) {
271 			hw->phy_type = em_phy_bm;
272 			break;
273 		}
274 		/* FALLTHROUGH */
275 	case GG82563_E_PHY_ID:
276 		if (hw->mac_type == em_80003es2lan) {
277 			hw->phy_type = em_phy_gg82563;
278 			break;
279 		}
280 		/* FALLTHROUGH */
281 	default:
282 		/* Should never have loaded on this device */
283 		hw->phy_type = em_phy_undefined;
284 		return -E1000_ERR_PHY_TYPE;
285 	}
286 
287 	return E1000_SUCCESS;
288 }
289 
290 /******************************************************************************
291  * IGP phy init script - initializes the GbE PHY
292  *
293  * hw - Struct containing variables accessed by shared code
294  *****************************************************************************/
295 static void
em_phy_init_script(struct em_hw * hw)296 em_phy_init_script(struct em_hw *hw)
297 {
298 	uint16_t phy_saved_data;
299 	DEBUGFUNC("em_phy_init_script");
300 
301 	if (hw->phy_init_script) {
302 		msec_delay(20);
303 		/*
304 		 * Save off the current value of register 0x2F5B to be
305 		 * restored at the end of this routine.
306 		 */
307 		em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
308 
309 		/* Disabled the PHY transmitter */
310 		em_write_phy_reg(hw, 0x2F5B, 0x0003);
311 		msec_delay(20);
312 		em_write_phy_reg(hw, 0x0000, 0x0140);
313 		msec_delay(5);
314 
315 		switch (hw->mac_type) {
316 		case em_82541:
317 		case em_82547:
318 			em_write_phy_reg(hw, 0x1F95, 0x0001);
319 			em_write_phy_reg(hw, 0x1F71, 0xBD21);
320 			em_write_phy_reg(hw, 0x1F79, 0x0018);
321 			em_write_phy_reg(hw, 0x1F30, 0x1600);
322 			em_write_phy_reg(hw, 0x1F31, 0x0014);
323 			em_write_phy_reg(hw, 0x1F32, 0x161C);
324 			em_write_phy_reg(hw, 0x1F94, 0x0003);
325 			em_write_phy_reg(hw, 0x1F96, 0x003F);
326 			em_write_phy_reg(hw, 0x2010, 0x0008);
327 			break;
328 		case em_82541_rev_2:
329 		case em_82547_rev_2:
330 			em_write_phy_reg(hw, 0x1F73, 0x0099);
331 			break;
332 		default:
333 			break;
334 		}
335 
336 		em_write_phy_reg(hw, 0x0000, 0x3300);
337 		msec_delay(20);
338 
339 		/* Now enable the transmitter */
340 		em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
341 
342 		if (hw->mac_type == em_82547) {
343 			uint16_t fused, fine, coarse;
344 			/* Move to analog registers page */
345 			em_read_phy_reg(hw,
346 			    IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
347 
348 			if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
349 				em_read_phy_reg(hw,
350 				    IGP01E1000_ANALOG_FUSE_STATUS, &fused);
351 
352 				fine = fused &
353 				    IGP01E1000_ANALOG_FUSE_FINE_MASK;
354 				coarse = fused &
355 				    IGP01E1000_ANALOG_FUSE_COARSE_MASK;
356 
357 				if (coarse >
358 				    IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
359 					coarse -=
360 					    IGP01E1000_ANALOG_FUSE_COARSE_10;
361 					fine -=
362 					    IGP01E1000_ANALOG_FUSE_FINE_1;
363 				} else if (coarse ==
364 				    IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
365 					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
366 
367 				fused = (fused &
368 				    IGP01E1000_ANALOG_FUSE_POLY_MASK) |
369 				    (fine &
370 				    IGP01E1000_ANALOG_FUSE_FINE_MASK) |
371 				    (coarse &
372 				    IGP01E1000_ANALOG_FUSE_COARSE_MASK);
373 
374 				em_write_phy_reg(hw,
375 				    IGP01E1000_ANALOG_FUSE_CONTROL,
376 				    fused);
377 
378 				em_write_phy_reg(hw,
379 				    IGP01E1000_ANALOG_FUSE_BYPASS,
380 				    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
381 			}
382 		}
383 	}
384 }
385 
386 /******************************************************************************
387  * Set the mac type member in the hw struct.
388  *
389  * hw - Struct containing variables accessed by shared code
390  *****************************************************************************/
391 int32_t
em_set_mac_type(struct em_hw * hw)392 em_set_mac_type(struct em_hw *hw)
393 {
394 	DEBUGFUNC("em_set_mac_type");
395 
396 	switch (hw->device_id) {
397 	case E1000_DEV_ID_82542:
398 		switch (hw->revision_id) {
399 		case E1000_82542_2_0_REV_ID:
400 			hw->mac_type = em_82542_rev2_0;
401 			break;
402 		case E1000_82542_2_1_REV_ID:
403 			hw->mac_type = em_82542_rev2_1;
404 			break;
405 		default:
406 			/* Invalid 82542 revision ID */
407 			return -E1000_ERR_MAC_TYPE;
408 		}
409 		break;
410 	case E1000_DEV_ID_82543GC_FIBER:
411 	case E1000_DEV_ID_82543GC_COPPER:
412 		hw->mac_type = em_82543;
413 		break;
414 	case E1000_DEV_ID_82544EI_COPPER:
415 	case E1000_DEV_ID_82544EI_FIBER:
416 	case E1000_DEV_ID_82544GC_COPPER:
417 	case E1000_DEV_ID_82544GC_LOM:
418 		hw->mac_type = em_82544;
419 		break;
420 	case E1000_DEV_ID_82540EM:
421 	case E1000_DEV_ID_82540EM_LOM:
422 	case E1000_DEV_ID_82540EP:
423 	case E1000_DEV_ID_82540EP_LOM:
424 	case E1000_DEV_ID_82540EP_LP:
425 		hw->mac_type = em_82540;
426 		break;
427 	case E1000_DEV_ID_82545EM_COPPER:
428 	case E1000_DEV_ID_82545EM_FIBER:
429 		hw->mac_type = em_82545;
430 		break;
431 	case E1000_DEV_ID_82545GM_COPPER:
432 	case E1000_DEV_ID_82545GM_FIBER:
433 	case E1000_DEV_ID_82545GM_SERDES:
434 		hw->mac_type = em_82545_rev_3;
435 		break;
436 	case E1000_DEV_ID_82546EB_COPPER:
437 	case E1000_DEV_ID_82546EB_FIBER:
438 	case E1000_DEV_ID_82546EB_QUAD_COPPER:
439 		hw->mac_type = em_82546;
440 		break;
441 	case E1000_DEV_ID_82546GB_COPPER:
442 	case E1000_DEV_ID_82546GB_FIBER:
443 	case E1000_DEV_ID_82546GB_SERDES:
444 	case E1000_DEV_ID_82546GB_PCIE:
445 	case E1000_DEV_ID_82546GB_QUAD_COPPER:
446 	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
447 	case E1000_DEV_ID_82546GB_2:
448 		hw->mac_type = em_82546_rev_3;
449 		break;
450 	case E1000_DEV_ID_82541EI:
451 	case E1000_DEV_ID_82541EI_MOBILE:
452 	case E1000_DEV_ID_82541ER_LOM:
453 		hw->mac_type = em_82541;
454 		break;
455 	case E1000_DEV_ID_82541ER:
456 	case E1000_DEV_ID_82541GI:
457 	case E1000_DEV_ID_82541GI_LF:
458 	case E1000_DEV_ID_82541GI_MOBILE:
459 		hw->mac_type = em_82541_rev_2;
460 		break;
461 	case E1000_DEV_ID_82547EI:
462 	case E1000_DEV_ID_82547EI_MOBILE:
463 		hw->mac_type = em_82547;
464 		break;
465 	case E1000_DEV_ID_82547GI:
466 		hw->mac_type = em_82547_rev_2;
467 		break;
468 	case E1000_DEV_ID_82571EB_AF:
469 	case E1000_DEV_ID_82571EB_AT:
470 	case E1000_DEV_ID_82571EB_COPPER:
471 	case E1000_DEV_ID_82571EB_FIBER:
472 	case E1000_DEV_ID_82571EB_SERDES:
473 	case E1000_DEV_ID_82571EB_QUAD_COPPER:
474 	case E1000_DEV_ID_82571EB_QUAD_FIBER:
475 	case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
476 	case E1000_DEV_ID_82571EB_SERDES_DUAL:
477 	case E1000_DEV_ID_82571EB_SERDES_QUAD:
478 	case E1000_DEV_ID_82571PT_QUAD_COPPER:
479 		hw->mac_type = em_82571;
480 		break;
481 	case E1000_DEV_ID_82572EI_COPPER:
482 	case E1000_DEV_ID_82572EI_FIBER:
483 	case E1000_DEV_ID_82572EI_SERDES:
484 	case E1000_DEV_ID_82572EI:
485 		hw->mac_type = em_82572;
486 		break;
487 	case E1000_DEV_ID_82573E:
488 	case E1000_DEV_ID_82573E_IAMT:
489 	case E1000_DEV_ID_82573E_PM:
490 	case E1000_DEV_ID_82573L:
491 	case E1000_DEV_ID_82573L_PL_1:
492 	case E1000_DEV_ID_82573L_PL_2:
493 	case E1000_DEV_ID_82573V_PM:
494 		hw->mac_type = em_82573;
495 		break;
496 	case E1000_DEV_ID_82574L:
497 	case E1000_DEV_ID_82574LA:
498 	case E1000_DEV_ID_82583V:
499 		hw->mac_type = em_82574;
500 		break;
501 	case E1000_DEV_ID_82575EB_PT:
502 	case E1000_DEV_ID_82575EB_PF:
503 	case E1000_DEV_ID_82575GB_QP:
504 	case E1000_DEV_ID_82575GB_QP_PM:
505 		hw->mac_type = em_82575;
506 		hw->initialize_hw_bits_disable = 1;
507 		break;
508 	case E1000_DEV_ID_82576:
509 	case E1000_DEV_ID_82576_FIBER:
510 	case E1000_DEV_ID_82576_SERDES:
511 	case E1000_DEV_ID_82576_QUAD_COPPER:
512 	case E1000_DEV_ID_82576_QUAD_CU_ET2:
513 	case E1000_DEV_ID_82576_NS:
514 	case E1000_DEV_ID_82576_NS_SERDES:
515 	case E1000_DEV_ID_82576_SERDES_QUAD:
516 		hw->mac_type = em_82576;
517 		hw->initialize_hw_bits_disable = 1;
518 		break;
519 	case E1000_DEV_ID_82580_COPPER:
520 	case E1000_DEV_ID_82580_FIBER:
521 	case E1000_DEV_ID_82580_QUAD_FIBER:
522 	case E1000_DEV_ID_82580_SERDES:
523 	case E1000_DEV_ID_82580_SGMII:
524 	case E1000_DEV_ID_82580_COPPER_DUAL:
525 	case E1000_DEV_ID_DH89XXCC_SGMII:
526 	case E1000_DEV_ID_DH89XXCC_SERDES:
527 	case E1000_DEV_ID_DH89XXCC_BACKPLANE:
528 	case E1000_DEV_ID_DH89XXCC_SFP:
529 		hw->mac_type = em_82580;
530 		hw->initialize_hw_bits_disable = 1;
531 		break;
532 	case E1000_DEV_ID_I210_COPPER:
533 	case E1000_DEV_ID_I210_COPPER_OEM1:
534 	case E1000_DEV_ID_I210_COPPER_IT:
535 	case E1000_DEV_ID_I210_FIBER:
536 	case E1000_DEV_ID_I210_SERDES:
537 	case E1000_DEV_ID_I210_SGMII:
538 	case E1000_DEV_ID_I210_COPPER_FLASHLESS:
539 	case E1000_DEV_ID_I210_SERDES_FLASHLESS:
540 	case E1000_DEV_ID_I211_COPPER:
541 		hw->mac_type = em_i210;
542 		hw->initialize_hw_bits_disable = 1;
543 		hw->eee_enable = 1;
544 		break;
545 	case E1000_DEV_ID_I350_COPPER:
546 	case E1000_DEV_ID_I350_FIBER:
547 	case E1000_DEV_ID_I350_SERDES:
548 	case E1000_DEV_ID_I350_SGMII:
549 	case E1000_DEV_ID_I350_DA4:
550 	case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
551 	case E1000_DEV_ID_I354_SGMII:
552 	case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
553 		hw->mac_type = em_i350;
554 		hw->initialize_hw_bits_disable = 1;
555 		hw->eee_enable = 1;
556 		break;
557 	case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
558 	case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
559 	case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
560 	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
561 		hw->mac_type = em_80003es2lan;
562 		break;
563 	case E1000_DEV_ID_ICH8_IFE:
564 	case E1000_DEV_ID_ICH8_IFE_G:
565 	case E1000_DEV_ID_ICH8_IFE_GT:
566 	case E1000_DEV_ID_ICH8_IGP_AMT:
567 	case E1000_DEV_ID_ICH8_IGP_C:
568 	case E1000_DEV_ID_ICH8_IGP_M:
569 	case E1000_DEV_ID_ICH8_IGP_M_AMT:
570 	case E1000_DEV_ID_ICH8_82567V_3:
571 		hw->mac_type = em_ich8lan;
572 		break;
573 	case E1000_DEV_ID_ICH9_BM:
574 	case E1000_DEV_ID_ICH9_IFE:
575 	case E1000_DEV_ID_ICH9_IFE_G:
576 	case E1000_DEV_ID_ICH9_IFE_GT:
577 	case E1000_DEV_ID_ICH9_IGP_AMT:
578 	case E1000_DEV_ID_ICH9_IGP_C:
579 	case E1000_DEV_ID_ICH9_IGP_M:
580 	case E1000_DEV_ID_ICH9_IGP_M_AMT:
581 	case E1000_DEV_ID_ICH9_IGP_M_V:
582 	case E1000_DEV_ID_ICH10_R_BM_LF:
583 	case E1000_DEV_ID_ICH10_R_BM_LM:
584 	case E1000_DEV_ID_ICH10_R_BM_V:
585 		hw->mac_type = em_ich9lan;
586 		break;
587 	case E1000_DEV_ID_ICH10_D_BM_LF:
588 	case E1000_DEV_ID_ICH10_D_BM_LM:
589 	case E1000_DEV_ID_ICH10_D_BM_V:
590 		hw->mac_type = em_ich10lan;
591 		break;
592 	case E1000_DEV_ID_PCH_M_HV_LC:
593 	case E1000_DEV_ID_PCH_M_HV_LM:
594 	case E1000_DEV_ID_PCH_D_HV_DC:
595 	case E1000_DEV_ID_PCH_D_HV_DM:
596 		hw->mac_type = em_pchlan;
597 		hw->eee_enable = 1;
598 		break;
599 	case E1000_DEV_ID_PCH2_LV_LM:
600 	case E1000_DEV_ID_PCH2_LV_V:
601 		hw->mac_type = em_pch2lan;
602 		break;
603 	case E1000_DEV_ID_PCH_LPT_I217_LM:
604 	case E1000_DEV_ID_PCH_LPT_I217_V:
605 	case E1000_DEV_ID_PCH_LPTLP_I218_LM:
606 	case E1000_DEV_ID_PCH_LPTLP_I218_V:
607 	case E1000_DEV_ID_PCH_I218_LM2:
608 	case E1000_DEV_ID_PCH_I218_V2:
609 	case E1000_DEV_ID_PCH_I218_LM3:
610 	case E1000_DEV_ID_PCH_I218_V3:
611 		hw->mac_type = em_pch_lpt;
612 		break;
613 	case E1000_DEV_ID_PCH_SPT_I219_LM:
614 	case E1000_DEV_ID_PCH_SPT_I219_V:
615 	case E1000_DEV_ID_PCH_SPT_I219_LM2:
616 	case E1000_DEV_ID_PCH_SPT_I219_V2:
617 	case E1000_DEV_ID_PCH_LBG_I219_LM3:
618 	case E1000_DEV_ID_PCH_SPT_I219_LM4:
619 	case E1000_DEV_ID_PCH_SPT_I219_V4:
620 	case E1000_DEV_ID_PCH_SPT_I219_LM5:
621 	case E1000_DEV_ID_PCH_SPT_I219_V5:
622 	case E1000_DEV_ID_PCH_CMP_I219_LM12:
623 	case E1000_DEV_ID_PCH_CMP_I219_V12:
624 		hw->mac_type = em_pch_spt;
625 		break;
626 	case E1000_DEV_ID_PCH_CNP_I219_LM6:
627 	case E1000_DEV_ID_PCH_CNP_I219_V6:
628 	case E1000_DEV_ID_PCH_CNP_I219_LM7:
629 	case E1000_DEV_ID_PCH_CNP_I219_V7:
630 	case E1000_DEV_ID_PCH_ICP_I219_LM8:
631 	case E1000_DEV_ID_PCH_ICP_I219_V8:
632 	case E1000_DEV_ID_PCH_ICP_I219_LM9:
633 	case E1000_DEV_ID_PCH_ICP_I219_V9:
634 	case E1000_DEV_ID_PCH_CMP_I219_LM10:
635 	case E1000_DEV_ID_PCH_CMP_I219_V10:
636 	case E1000_DEV_ID_PCH_CMP_I219_LM11:
637 	case E1000_DEV_ID_PCH_CMP_I219_V11:
638 		hw->mac_type = em_pch_cnp;
639 		break;
640 	case E1000_DEV_ID_PCH_TGP_I219_LM13:
641 	case E1000_DEV_ID_PCH_TGP_I219_V13:
642 	case E1000_DEV_ID_PCH_TGP_I219_LM14:
643 	case E1000_DEV_ID_PCH_TGP_I219_V14:
644 	case E1000_DEV_ID_PCH_TGP_I219_LM15:
645 	case E1000_DEV_ID_PCH_TGP_I219_V15:
646 		hw->mac_type = em_pch_tgp;
647 		break;
648 	case E1000_DEV_ID_PCH_ADP_I219_LM16:
649 	case E1000_DEV_ID_PCH_ADP_I219_V16:
650 	case E1000_DEV_ID_PCH_ADP_I219_LM17:
651 	case E1000_DEV_ID_PCH_ADP_I219_V17:
652 	case E1000_DEV_ID_PCH_RPL_I219_LM22:
653 	case E1000_DEV_ID_PCH_RPL_I219_V22:
654 	case E1000_DEV_ID_PCH_RPL_I219_LM23:
655 	case E1000_DEV_ID_PCH_RPL_I219_V23:
656 		hw->mac_type = em_pch_adp;
657 		break;
658 	case E1000_DEV_ID_PCH_MTP_I219_LM18:
659 	case E1000_DEV_ID_PCH_MTP_I219_V18:
660 	case E1000_DEV_ID_PCH_MTP_I219_LM19:
661 	case E1000_DEV_ID_PCH_MTP_I219_V19:
662 	case E1000_DEV_ID_PCH_LNP_I219_LM20:
663 	case E1000_DEV_ID_PCH_LNP_I219_V20:
664 	case E1000_DEV_ID_PCH_LNP_I219_LM21:
665 	case E1000_DEV_ID_PCH_LNP_I219_V21:
666 	case E1000_DEV_ID_PCH_ARL_I219_LM24:
667 	case E1000_DEV_ID_PCH_ARL_I219_V24:
668 		hw->mac_type = em_pch_adp;	/* pch_mtp */
669 		break;
670 	case E1000_DEV_ID_EP80579_LAN_1:
671 		hw->mac_type = em_icp_xxxx;
672 		hw->icp_xxxx_port_num = 0;
673 		break;
674 	case E1000_DEV_ID_EP80579_LAN_2:
675 	case E1000_DEV_ID_EP80579_LAN_4:
676 		hw->mac_type = em_icp_xxxx;
677 		hw->icp_xxxx_port_num = 1;
678 		break;
679 	case E1000_DEV_ID_EP80579_LAN_3:
680 	case E1000_DEV_ID_EP80579_LAN_5:
681 		hw->mac_type = em_icp_xxxx;
682 		hw->icp_xxxx_port_num = 2;
683 		break;
684 	case E1000_DEV_ID_EP80579_LAN_6:
685 		hw->mac_type = em_icp_xxxx;
686 		hw->icp_xxxx_port_num = 3;
687 		break;
688 	default:
689 		/* Should never have loaded on this device */
690 		return -E1000_ERR_MAC_TYPE;
691 	}
692 
693 	switch (hw->mac_type) {
694 	case em_ich8lan:
695 	case em_ich9lan:
696 	case em_ich10lan:
697 	case em_pchlan:
698 	case em_pch2lan:
699 	case em_pch_lpt:
700 	case em_pch_spt:
701 	case em_pch_cnp:
702 	case em_pch_tgp:
703 	case em_pch_adp:
704 		hw->swfwhw_semaphore_present = TRUE;
705 		hw->asf_firmware_present = TRUE;
706 		break;
707 	case em_80003es2lan:
708 	case em_82575:
709 	case em_82576:
710 	case em_82580:
711 	case em_i210:
712 	case em_i350:
713 		hw->swfw_sync_present = TRUE;
714 		/* FALLTHROUGH */
715 	case em_82571:
716 	case em_82572:
717 	case em_82573:
718 	case em_82574:
719 		hw->eeprom_semaphore_present = TRUE;
720 		/* FALLTHROUGH */
721 	case em_82541:
722 	case em_82547:
723 	case em_82541_rev_2:
724 	case em_82547_rev_2:
725 		hw->asf_firmware_present = TRUE;
726 		break;
727 	default:
728 		break;
729 	}
730 
731 	return E1000_SUCCESS;
732 }
733 
734 /**
735  *  em_set_sfp_media_type_82575 - derives SFP module media type.
736  *  @hw: pointer to the HW structure
737  *
738  *  The media type is chosen based on SFP module.
739  *  compatibility flags retrieved from SFP ID EEPROM.
740  **/
em_set_sfp_media_type_82575(struct em_hw * hw)741 STATIC int32_t em_set_sfp_media_type_82575(struct em_hw *hw)
742 {
743 	struct sfp_e1000_flags eth_flags;
744 	int32_t ret_val = E1000_ERR_CONFIG;
745 	uint32_t ctrl_ext = 0;
746 	uint8_t transceiver_type = 0;
747 	int32_t timeout = 3;
748 
749 	/* Turn I2C interface ON and power on sfp cage */
750 	ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
751 	ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
752 	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
753 
754 	E1000_WRITE_FLUSH(hw);
755 
756 	/* Read SFP module data */
757 	while (timeout) {
758 		ret_val = em_read_sfp_data_byte(hw,
759 			E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
760 			&transceiver_type);
761 		if (ret_val == E1000_SUCCESS)
762 			break;
763 		msec_delay(100);
764 		timeout--;
765 	}
766 	if (ret_val != E1000_SUCCESS)
767 		goto out;
768 
769 	ret_val = em_read_sfp_data_byte(hw,
770 			E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
771 			(uint8_t *)&eth_flags);
772 	if (ret_val != E1000_SUCCESS)
773 		goto out;
774 
775 	/* Check if there is some SFP module plugged and powered */
776 	if ((transceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
777 	    (transceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
778 		if (eth_flags.e1000_base_lx || eth_flags.e1000_base_sx) {
779 			hw->media_type = em_media_type_internal_serdes;
780 		} else if (eth_flags.e100_base_fx || eth_flags.e100_base_lx) {
781 			hw->media_type = em_media_type_internal_serdes;
782 			hw->sgmii_active = TRUE;
783 		} else if (eth_flags.e1000_base_t) {
784 			hw->media_type = em_media_type_copper;
785 			hw->sgmii_active = TRUE;
786 		} else {
787 			DEBUGOUT("PHY module has not been recognized\n");
788 			ret_val = E1000_ERR_CONFIG;
789 			goto out;
790 		}
791 	} else {
792 		ret_val = E1000_ERR_CONFIG;
793 		goto out;
794 	}
795 	ret_val = E1000_SUCCESS;
796 out:
797 	/* Restore I2C interface setting */
798 	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
799 	return ret_val;
800 }
801 
802 
803 /*****************************************************************************
804  * Set media type and TBI compatibility.
805  *
806  * hw - Struct containing variables accessed by shared code
807  * **************************************************************************/
808 void
em_set_media_type(struct em_hw * hw)809 em_set_media_type(struct em_hw *hw)
810 {
811 	uint32_t status, ctrl_ext, mdic;
812 	DEBUGFUNC("em_set_media_type");
813 
814 	if (hw->mac_type != em_82543) {
815 		/* tbi_compatibility is only valid on 82543 */
816 		hw->tbi_compatibility_en = FALSE;
817 	}
818 
819 	if (hw->mac_type == em_82575 || hw->mac_type == em_82580 ||
820 	    hw->mac_type == em_82576 ||
821 	    hw->mac_type == em_i210 || hw->mac_type == em_i350) {
822 		hw->media_type = em_media_type_copper;
823 		hw->sgmii_active = FALSE;
824 
825 		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
826 		switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
827 		case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
828 			hw->media_type = em_media_type_internal_serdes;
829 			ctrl_ext |= E1000_CTRL_I2C_ENA;
830 			break;
831 		case E1000_CTRL_EXT_LINK_MODE_SGMII:
832 			mdic = EM_READ_REG(hw, E1000_MDICNFG);
833 			ctrl_ext |= E1000_CTRL_I2C_ENA;
834 			if (mdic & E1000_MDICNFG_EXT_MDIO) {
835 				hw->media_type = em_media_type_copper;
836 				hw->sgmii_active = TRUE;
837 				break;
838 			}
839 			/* FALLTHROUGH */
840 		case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
841 			ctrl_ext |= E1000_CTRL_I2C_ENA;
842 			if (em_set_sfp_media_type_82575(hw) != 0) {
843 				hw->media_type = em_media_type_internal_serdes;
844 				if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) ==
845 				    E1000_CTRL_EXT_LINK_MODE_SGMII) {
846 					hw->media_type = em_media_type_copper;
847 					hw->sgmii_active = TRUE;
848 				}
849 			}
850 
851 			ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
852 			if (hw->sgmii_active)
853 				ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
854 			else
855 				ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
856 			break;
857 		default:
858 			ctrl_ext &= ~E1000_CTRL_I2C_ENA;
859 			break;
860 		}
861 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
862 		return;
863 	}
864 
865 	switch (hw->device_id) {
866 	case E1000_DEV_ID_82545GM_SERDES:
867 	case E1000_DEV_ID_82546GB_SERDES:
868 	case E1000_DEV_ID_82571EB_SERDES:
869 	case E1000_DEV_ID_82571EB_SERDES_DUAL:
870 	case E1000_DEV_ID_82571EB_SERDES_QUAD:
871 	case E1000_DEV_ID_82572EI_SERDES:
872 	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
873 		hw->media_type = em_media_type_internal_serdes;
874 		break;
875 	case E1000_DEV_ID_EP80579_LAN_1:
876 	case E1000_DEV_ID_EP80579_LAN_2:
877 	case E1000_DEV_ID_EP80579_LAN_3:
878 	case E1000_DEV_ID_EP80579_LAN_4:
879 	case E1000_DEV_ID_EP80579_LAN_5:
880 	case E1000_DEV_ID_EP80579_LAN_6:
881 		hw->media_type = em_media_type_copper;
882 		break;
883 	default:
884 		switch (hw->mac_type) {
885 		case em_82542_rev2_0:
886 		case em_82542_rev2_1:
887 			hw->media_type = em_media_type_fiber;
888 			break;
889 		case em_ich8lan:
890 		case em_ich9lan:
891 		case em_ich10lan:
892 		case em_pchlan:
893 		case em_pch2lan:
894 		case em_pch_lpt:
895 		case em_pch_spt:
896 		case em_pch_cnp:
897 		case em_pch_tgp:
898 		case em_pch_adp:
899 		case em_82573:
900 		case em_82574:
901 			/*
902 			 * The STATUS_TBIMODE bit is reserved or reused for
903 			 * the this device.
904 			 */
905 			hw->media_type = em_media_type_copper;
906 			break;
907 		default:
908 			status = E1000_READ_REG(hw, STATUS);
909 			if (status & E1000_STATUS_TBIMODE) {
910 				hw->media_type = em_media_type_fiber;
911 				/* tbi_compatibility not valid on fiber */
912 				hw->tbi_compatibility_en = FALSE;
913 			} else {
914 				hw->media_type = em_media_type_copper;
915 			}
916 			break;
917 		}
918 	}
919 }
920 /******************************************************************************
921  * Reset the transmit and receive units; mask and clear all interrupts.
922  *
923  * hw - Struct containing variables accessed by shared code
924  *****************************************************************************/
925 int32_t
em_reset_hw(struct em_hw * hw)926 em_reset_hw(struct em_hw *hw)
927 {
928 	uint32_t ctrl;
929 	uint32_t ctrl_ext;
930 	uint32_t icr;
931 	uint32_t manc;
932 	uint32_t led_ctrl;
933 	uint32_t timeout;
934 	uint32_t extcnf_ctrl;
935 	int32_t  ret_val;
936 	DEBUGFUNC("em_reset_hw");
937 
938 	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
939 	if (hw->mac_type == em_82542_rev2_0) {
940 		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
941 		em_pci_clear_mwi(hw);
942 	}
943 	if (hw->bus_type == em_bus_type_pci_express) {
944 		/*
945 		 * Prevent the PCI-E bus from sticking if there is no TLP
946 		 * connection on the last TLP read/write transaction when MAC
947 		 * is reset.
948 		 */
949 		if (em_disable_pciex_master(hw) != E1000_SUCCESS) {
950 			DEBUGOUT("PCI-E Master disable polling has failed.\n");
951 		}
952 	}
953 
954         /* Set the completion timeout for 82575 chips */
955         if (hw->mac_type == em_82575 || hw->mac_type == em_82580 ||
956 	    hw->mac_type == em_82576 ||
957 	    hw->mac_type == em_i210 || hw->mac_type == em_i350) {
958                 ret_val = em_set_pciex_completion_timeout(hw);
959                 if (ret_val) {
960                         DEBUGOUT("PCI-E Set completion timeout has failed.\n");
961                 }
962         }
963 
964 	/* Clear interrupt mask to stop board from generating interrupts */
965 	DEBUGOUT("Masking off all interrupts\n");
966 	E1000_WRITE_REG(hw, IMC, 0xffffffff);
967 	/*
968 	 * Disable the Transmit and Receive units.  Then delay to allow any
969 	 * pending transactions to complete before we hit the MAC with the
970 	 * global reset.
971 	 */
972 	E1000_WRITE_REG(hw, RCTL, 0);
973 	E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
974 	E1000_WRITE_FLUSH(hw);
975 	/*
976 	 * The tbi_compatibility_on Flag must be cleared when Rctl is
977 	 * cleared.
978 	 */
979 	hw->tbi_compatibility_on = FALSE;
980 	/*
981 	 * Delay to allow any outstanding PCI transactions to complete before
982 	 * resetting the device
983 	 */
984 	msec_delay(10);
985 
986 	ctrl = E1000_READ_REG(hw, CTRL);
987 
988 	/* Must reset the PHY before resetting the MAC */
989 	if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
990 		E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
991 		msec_delay(5);
992 	}
993 	/*
994 	 * Must acquire the MDIO ownership before MAC reset. Ownership
995 	 * defaults to firmware after a reset.
996 	 */
997 	if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
998 		timeout = 10;
999 
1000 		extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
1001 		extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
1002 
1003 		do {
1004 			E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
1005 			extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
1006 
1007 			if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
1008 				break;
1009 			else
1010 				extcnf_ctrl |=
1011 				    E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
1012 
1013 			msec_delay(2);
1014 			timeout--;
1015 		} while (timeout);
1016 	}
1017 	/* Workaround for ICH8 bit corruption issue in FIFO memory */
1018 	if (hw->mac_type == em_ich8lan) {
1019 		/* Set Tx and Rx buffer allocation to 8k apiece. */
1020 		E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
1021 		/* Set Packet Buffer Size to 16k. */
1022 		E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
1023 	}
1024 	/*
1025 	 * Issue a global reset to the MAC.  This will reset the chip's
1026 	 * transmit, receive, DMA, and link units.  It will not effect the
1027 	 * current PCI configuration.  The global reset bit is self-
1028 	 * clearing, and should clear within a microsecond.
1029 	 */
1030 	DEBUGOUT("Issuing a global reset to MAC\n");
1031 
1032 	switch (hw->mac_type) {
1033 	case em_82544:
1034 	case em_82540:
1035 	case em_82545:
1036 	case em_82546:
1037 	case em_82541:
1038 	case em_82541_rev_2:
1039 		/*
1040 		 * These controllers can't ack the 64-bit write when issuing
1041 		 * the reset, so use IO-mapping as a workaround to issue the
1042 		 * reset
1043 		 */
1044 		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
1045 		break;
1046 	case em_82545_rev_3:
1047 	case em_82546_rev_3:
1048 		/* Reset is performed on a shadow of the control register */
1049 		E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
1050 		break;
1051 	case em_ich8lan:
1052 	case em_ich9lan:
1053 	case em_ich10lan:
1054 	case em_pchlan:
1055 	case em_pch2lan:
1056 	case em_pch_lpt:
1057 	case em_pch_spt:
1058 	case em_pch_cnp:
1059 	case em_pch_tgp:
1060 	case em_pch_adp:
1061 		if (!hw->phy_reset_disable &&
1062 		    em_check_phy_reset_block(hw) == E1000_SUCCESS) {
1063 			/*
1064 			 * PHY HW reset requires MAC CORE reset at the same
1065 			 * time to make sure the interface between MAC and
1066 			 * the external PHY is reset.
1067 			 */
1068 			ctrl |= E1000_CTRL_PHY_RST;
1069 			/*
1070 			 * Gate automatic PHY configuration by hardware on
1071 			 * non-managed 82579
1072 			 */
1073 			if ((hw->mac_type == em_pch2lan) &&
1074 				!(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) {
1075 				em_gate_hw_phy_config_ich8lan(hw, TRUE);
1076 			}
1077 		}
1078 		em_get_software_flag(hw);
1079 		E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1080 		/* HW reset releases software_flag */
1081 		hw->sw_flag = 0;
1082 		msec_delay(20);
1083 
1084 		/* Ungate automatic PHY configuration on non-managed 82579 */
1085 		if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable &&
1086 		    !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) {
1087 			msec_delay(10);
1088 			em_gate_hw_phy_config_ich8lan(hw, FALSE);
1089 		}
1090  		break;
1091 	default:
1092 		E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1093 		break;
1094 	}
1095 
1096 	if (em_check_phy_reset_block(hw) == E1000_SUCCESS) {
1097 		if (hw->mac_type == em_pchlan) {
1098 			ret_val = em_hv_phy_workarounds_ich8lan(hw);
1099 			if (ret_val)
1100 				return ret_val;
1101 		}
1102 		else if (hw->mac_type == em_pch2lan) {
1103 			ret_val = em_lv_phy_workarounds_ich8lan(hw);
1104 			if (ret_val)
1105 				return ret_val;
1106 		}
1107 	}
1108 
1109 	/*
1110 	 * After MAC reset, force reload of EEPROM to restore power-on
1111 	 * settings to device.  Later controllers reload the EEPROM
1112 	 * automatically, so just wait for reload to complete.
1113 	 */
1114 	switch (hw->mac_type) {
1115 	case em_82542_rev2_0:
1116 	case em_82542_rev2_1:
1117 	case em_82543:
1118 	case em_82544:
1119 		/* Wait for reset to complete */
1120 		usec_delay(10);
1121 		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1122 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1123 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1124 		E1000_WRITE_FLUSH(hw);
1125 		/* Wait for EEPROM reload */
1126 		msec_delay(2);
1127 		break;
1128 	case em_82541:
1129 	case em_82541_rev_2:
1130 	case em_82547:
1131 	case em_82547_rev_2:
1132 		/* Wait for EEPROM reload */
1133 		msec_delay(20);
1134 		break;
1135 	case em_82573:
1136 	case em_82574:
1137 		if (em_is_onboard_nvm_eeprom(hw) == FALSE) {
1138 			usec_delay(10);
1139 			ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1140 			ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1141 			E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1142 			E1000_WRITE_FLUSH(hw);
1143 		}
1144 		/* FALLTHROUGH */
1145 
1146 		/* Auto read done will delay 5ms or poll based on mac type */
1147 		ret_val = em_get_auto_rd_done(hw);
1148 		if (ret_val)
1149 			return ret_val;
1150 		break;
1151 	default:
1152 		/* Wait for EEPROM reload (it happens automatically) */
1153 		msec_delay(5);
1154 		break;
1155 	}
1156 
1157 	/* Disable HW ARPs on ASF enabled adapters */
1158 	if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 &&
1159 	    hw->mac_type != em_icp_xxxx) {
1160 		manc = E1000_READ_REG(hw, MANC);
1161 		manc &= ~(E1000_MANC_ARP_EN);
1162 		E1000_WRITE_REG(hw, MANC, manc);
1163 	}
1164 	if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
1165 		em_phy_init_script(hw);
1166 
1167 		/* Configure activity LED after PHY reset */
1168 		led_ctrl = E1000_READ_REG(hw, LEDCTL);
1169 		led_ctrl &= IGP_ACTIVITY_LED_MASK;
1170 		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1171 		E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1172 	}
1173 
1174 	/*
1175 	 * For PCH, this write will make sure that any noise
1176 	 * will be detected as a CRC error and be dropped rather than show up
1177 	 * as a bad packet to the DMA engine.
1178 	 */
1179 	if (hw->mac_type == em_pchlan)
1180 		E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565);
1181 
1182 	/* Clear interrupt mask to stop board from generating interrupts */
1183 	DEBUGOUT("Masking off all interrupts\n");
1184 	E1000_WRITE_REG(hw, IMC, 0xffffffff);
1185 
1186 	/* Clear any pending interrupt events. */
1187 	icr = E1000_READ_REG(hw, ICR);
1188 
1189 	/* If MWI was previously enabled, reenable it. */
1190 	if (hw->mac_type == em_82542_rev2_0) {
1191 		if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1192 			em_pci_set_mwi(hw);
1193 	}
1194 	if (IS_ICH8(hw->mac_type)) {
1195 		uint32_t kab = E1000_READ_REG(hw, KABGTXD);
1196 		kab |= E1000_KABGTXD_BGSQLBIAS;
1197 		E1000_WRITE_REG(hw, KABGTXD, kab);
1198 	}
1199 
1200 	if (hw->mac_type == em_82580 || hw->mac_type == em_i350) {
1201 		uint32_t mdicnfg;
1202 		uint16_t nvm_data;
1203 
1204 		/* clear global device reset status bit */
1205 		EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET);
1206 
1207 		em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A +
1208 		    NVM_82580_LAN_FUNC_OFFSET(hw->bus_func), 1,
1209 		    &nvm_data);
1210 
1211 		mdicnfg = EM_READ_REG(hw, E1000_MDICNFG);
1212 		if (nvm_data & NVM_WORD24_EXT_MDIO)
1213 			mdicnfg |= E1000_MDICNFG_EXT_MDIO;
1214 		if (nvm_data & NVM_WORD24_COM_MDIO)
1215 			mdicnfg |= E1000_MDICNFG_COM_MDIO;
1216 		EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
1217 	}
1218 
1219 	if (hw->mac_type == em_i210 || hw->mac_type == em_i350)
1220 		em_set_eee_i350(hw);
1221 
1222 	return E1000_SUCCESS;
1223 }
1224 
1225 /******************************************************************************
1226  *
1227  * Initialize a number of hardware-dependent bits
1228  *
1229  * hw: Struct containing variables accessed by shared code
1230  *
1231  *****************************************************************************/
1232 STATIC void
em_initialize_hardware_bits(struct em_softc * sc)1233 em_initialize_hardware_bits(struct em_softc *sc)
1234 {
1235 	struct em_hw *hw = &sc->hw;
1236 	struct em_queue *que;
1237 
1238 	DEBUGFUNC("em_initialize_hardware_bits");
1239 
1240 	if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) {
1241 		/* Settings common to all silicon */
1242 		uint32_t reg_ctrl, reg_ctrl_ext;
1243 		uint32_t reg_tarc0, reg_tarc1;
1244 		uint32_t reg_tctl;
1245 		uint32_t reg_txdctl;
1246 		reg_tarc0 = E1000_READ_REG(hw, TARC0);
1247 		reg_tarc0 &= ~0x78000000;	/* Clear bits 30, 29, 28, and
1248 						 * 27 */
1249 		FOREACH_QUEUE(sc, que) {
1250 			reg_txdctl = E1000_READ_REG(hw, TXDCTL(que->me));
1251 			reg_txdctl |= E1000_TXDCTL_COUNT_DESC;	/* Set bit 22 */
1252 			E1000_WRITE_REG(hw, TXDCTL(que->me), reg_txdctl);
1253 		}
1254 
1255 		/*
1256 		 * Old code always initialized queue 1,
1257 		 * even when unused, keep behaviour
1258 		 */
1259 		if (sc->num_queues == 1) {
1260 			reg_txdctl = E1000_READ_REG(hw, TXDCTL(1));
1261 			reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1262 			E1000_WRITE_REG(hw, TXDCTL(1), reg_txdctl);
1263 		}
1264 
1265 		switch (hw->mac_type) {
1266 		case em_82571:
1267 		case em_82572:
1268 			reg_tarc1 = E1000_READ_REG(hw, TARC1);
1269 			reg_tctl = E1000_READ_REG(hw, TCTL);
1270 
1271 			/* Set the phy Tx compatible mode bits */
1272 			reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */
1273 
1274 			reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */
1275 			reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */
1276 
1277 			if (reg_tctl & E1000_TCTL_MULR)
1278 				/* Clear bit 28 if MULR is 1b */
1279 				reg_tarc1 &= ~0x10000000;
1280 			else
1281 				/* Set bit 28 if MULR is 0b */
1282 				reg_tarc1 |= 0x10000000;
1283 
1284 			E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1285 			break;
1286 		case em_82573:
1287 		case em_82574:
1288 			reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1289 			reg_ctrl = E1000_READ_REG(hw, CTRL);
1290 
1291 			reg_ctrl_ext &= ~0x00800000;	/* Clear bit 23 */
1292 			reg_ctrl_ext |= 0x00400000;	/* Set bit 22 */
1293 			reg_ctrl &= ~0x20000000;	/* Clear bit 29 */
1294 
1295 			E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1296 			E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1297 			break;
1298 		case em_80003es2lan:
1299 			if ((hw->media_type == em_media_type_fiber) ||
1300 			(hw->media_type == em_media_type_internal_serdes)) {
1301 				/* Clear bit 20 */
1302 				reg_tarc0 &= ~0x00100000;
1303 			}
1304 			reg_tctl = E1000_READ_REG(hw, TCTL);
1305 			reg_tarc1 = E1000_READ_REG(hw, TARC1);
1306 			if (reg_tctl & E1000_TCTL_MULR)
1307 				/* Clear bit 28 if MULR is 1b */
1308 				reg_tarc1 &= ~0x10000000;
1309 			else
1310 				/* Set bit 28 if MULR is 0b */
1311 				reg_tarc1 |= 0x10000000;
1312 
1313 			E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1314 			break;
1315 		case em_ich8lan:
1316 		case em_ich9lan:
1317 		case em_ich10lan:
1318 		case em_pchlan:
1319 		case em_pch2lan:
1320 		case em_pch_lpt:
1321 		case em_pch_spt:
1322 		case em_pch_cnp:
1323 		case em_pch_tgp:
1324 		case em_pch_adp:
1325 			if (hw->mac_type == em_ich8lan)
1326 				/* Set TARC0 bits 29 and 28 */
1327 				reg_tarc0 |= 0x30000000;
1328 
1329 			reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1330 			reg_ctrl_ext |= 0x00400000;	/* Set bit 22 */
1331 			/* Enable PHY low-power state when MAC is at D3 w/o WoL */
1332 			if (hw->mac_type >= em_pchlan)
1333 				reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN;
1334 			E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1335 
1336 			reg_tarc0 |= 0x0d800000;	/* Set TARC0 bits 23,
1337 							 * 24, 26, 27 */
1338 
1339 			reg_tarc1 = E1000_READ_REG(hw, TARC1);
1340 			reg_tctl = E1000_READ_REG(hw, TCTL);
1341 
1342 			if (reg_tctl & E1000_TCTL_MULR)
1343 				/* Clear bit 28 if MULR is 1b */
1344 				reg_tarc1 &= ~0x10000000;
1345 			else
1346 				/* Set bit 28 if MULR is 0b */
1347 				reg_tarc1 |= 0x10000000;
1348 
1349 			reg_tarc1 |= 0x45000000;	/* Set bit 24, 26 and
1350 							 * 30 */
1351 
1352 			E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1353 			break;
1354 		default:
1355 			break;
1356 		}
1357 
1358 		E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1359 	}
1360 }
1361 
1362 /**
1363  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
1364  *  @hw: pointer to the HW structure
1365  *
1366  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
1367  *  used to reset the PHY to a quiescent state when necessary.
1368  **/
1369 static void
em_toggle_lanphypc_pch_lpt(struct em_hw * hw)1370 em_toggle_lanphypc_pch_lpt(struct em_hw *hw)
1371 {
1372 	uint32_t mac_reg;
1373 
1374 	DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
1375 
1376 	/* Set Phy Config Counter to 50msec */
1377 	mac_reg = E1000_READ_REG(hw, FEXTNVM3);
1378 	mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
1379 	mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
1380 	E1000_WRITE_REG(hw, FEXTNVM3, mac_reg);
1381 
1382 	/* Toggle LANPHYPC Value bit */
1383 	mac_reg = E1000_READ_REG(hw, CTRL);
1384 	mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
1385 	mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
1386 	E1000_WRITE_REG(hw, CTRL, mac_reg);
1387 	E1000_WRITE_FLUSH(hw);
1388 	msec_delay(1);
1389 	mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
1390 	E1000_WRITE_REG(hw, CTRL, mac_reg);
1391 	E1000_WRITE_FLUSH(hw);
1392 
1393 	if (hw->mac_type < em_pch_lpt) {
1394 		msec_delay(50);
1395 	} else {
1396 		uint16_t count = 20;
1397 
1398 		do {
1399 			msec_delay(5);
1400 		} while (!(E1000_READ_REG(hw, CTRL_EXT) &
1401 		    E1000_CTRL_EXT_LPCD) && count--);
1402 
1403 		msec_delay(30);
1404 	}
1405 }
1406 
1407 /**
1408  *  em_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1409  *  @hw: pointer to the HW structure
1410  *  @force: boolean indicating whether or not to force disabling ULP
1411  *
1412  *  Un-configure ULP mode when link is up, the system is transitioned from
1413  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1414  *  system, poll for an indication from ME that ULP has been un-configured.
1415  *  If not on an ME enabled system, un-configure the ULP mode by software.
1416  *
1417  *  During nominal operation, this function is called when link is acquired
1418  *  to disable ULP mode (force=FALSE); otherwise, for example when unloading
1419  *  the driver or during Sx->S0 transitions, this is called with force=TRUE
1420  *  to forcibly disable ULP.
1421  */
1422 static int
em_disable_ulp_lpt_lp(struct em_hw * hw,bool force)1423 em_disable_ulp_lpt_lp(struct em_hw *hw, bool force)
1424 {
1425 	int ret_val = E1000_SUCCESS;
1426 	uint32_t mac_reg;
1427 	uint16_t phy_reg;
1428 	int i = 0;
1429 
1430 	if ((hw->mac_type < em_pch_lpt) ||
1431 	    (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1432 	    (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1433 	    (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1434 	    (hw->device_id == E1000_DEV_ID_PCH_I218_V2))
1435 		return 0;
1436 
1437 	if (E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID) {
1438 		if (force) {
1439 			/* Request ME un-configure ULP mode in the PHY */
1440 			mac_reg = E1000_READ_REG(hw, H2ME);
1441 			mac_reg &= ~E1000_H2ME_ULP;
1442 			mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1443 			E1000_WRITE_REG(hw, H2ME, mac_reg);
1444 		}
1445 
1446 		/* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1447 		while (E1000_READ_REG(hw, FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1448 			if (i++ == 30) {
1449 				ret_val = -E1000_ERR_PHY;
1450 				goto out;
1451 			}
1452 
1453 			msec_delay(10);
1454 		}
1455 		DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1456 
1457 		if (force) {
1458 			mac_reg = E1000_READ_REG(hw, H2ME);
1459 			mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1460 			E1000_WRITE_REG(hw, H2ME, mac_reg);
1461 		} else {
1462 			/* Clear H2ME.ULP after ME ULP configuration */
1463 			mac_reg = E1000_READ_REG(hw, H2ME);
1464 			mac_reg &= ~E1000_H2ME_ULP;
1465 			E1000_WRITE_REG(hw, H2ME, mac_reg);
1466 		}
1467 
1468 		goto out;
1469 	}
1470 
1471 	ret_val = em_get_software_flag(hw);
1472 	if (ret_val)
1473 		goto out;
1474 
1475 	if (force)
1476 		/* Toggle LANPHYPC Value bit */
1477 		em_toggle_lanphypc_pch_lpt(hw);
1478 
1479 	/* Unforce SMBus mode in PHY */
1480 	ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg);
1481 	if (ret_val) {
1482 		/* The MAC might be in PCIe mode, so temporarily force to
1483 		 * SMBus mode in order to access the PHY.
1484 		 */
1485 		mac_reg = E1000_READ_REG(hw, CTRL_EXT);
1486 		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1487 		E1000_WRITE_REG(hw, CTRL_EXT, mac_reg);
1488 
1489 		msec_delay(50);
1490 
1491 		ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg);
1492 		if (ret_val)
1493 			goto release;
1494 	}
1495 	phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1496 	em_write_phy_reg(hw, CV_SMB_CTRL, phy_reg);
1497 
1498 	/* Unforce SMBus mode in MAC */
1499 	mac_reg = E1000_READ_REG(hw, CTRL_EXT);
1500 	mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1501 	E1000_WRITE_REG(hw, CTRL_EXT, mac_reg);
1502 
1503 	/* When ULP mode was previously entered, K1 was disabled by the
1504 	 * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1505 	 */
1506 	ret_val = em_read_phy_reg(hw, HV_PM_CTRL, &phy_reg);
1507 	if (ret_val)
1508 		goto release;
1509 	phy_reg |= HV_PM_CTRL_K1_ENABLE;
1510 	em_write_phy_reg(hw, HV_PM_CTRL, phy_reg);
1511 
1512 	/* Clear ULP enabled configuration */
1513 	ret_val = em_read_phy_reg(hw, I218_ULP_CONFIG1, &phy_reg);
1514 	if (ret_val)
1515 		goto release;
1516 	phy_reg &= ~(I218_ULP_CONFIG1_IND |
1517 		     I218_ULP_CONFIG1_STICKY_ULP |
1518 		     I218_ULP_CONFIG1_RESET_TO_SMBUS |
1519 		     I218_ULP_CONFIG1_WOL_HOST |
1520 		     I218_ULP_CONFIG1_INBAND_EXIT |
1521 		     I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1522 		     I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1523 		     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1524 	em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg);
1525 
1526 	/* Commit ULP changes by starting auto ULP configuration */
1527 	phy_reg |= I218_ULP_CONFIG1_START;
1528 	em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg);
1529 
1530 	/* Clear Disable SMBus Release on PERST# in MAC */
1531 	mac_reg = E1000_READ_REG(hw, FEXTNVM7);
1532 	mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1533 	E1000_WRITE_REG(hw, FEXTNVM7, mac_reg);
1534 
1535 release:
1536 	em_release_software_flag(hw);
1537 	if (force) {
1538 		em_phy_reset(hw);
1539 		msec_delay(50);
1540 	}
1541 out:
1542 	if (ret_val)
1543 		DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1544 
1545 	return ret_val;
1546 }
1547 
1548 /******************************************************************************
1549  * Performs basic configuration of the adapter.
1550  *
1551  * hw - Struct containing variables accessed by shared code
1552  *
1553  * Assumes that the controller has previously been reset and is in a
1554  * post-reset uninitialized state. Initializes the receive address registers,
1555  * multicast table, and VLAN filter table. Calls routines to setup link
1556  * configuration and flow control settings. Clears all on-chip counters. Leaves
1557  * the transmit and receive units disabled and uninitialized.
1558  *****************************************************************************/
1559 int32_t
em_init_hw(struct em_softc * sc)1560 em_init_hw(struct em_softc *sc)
1561 {
1562 	struct em_hw *hw = &sc->hw;
1563 	struct em_queue *que;
1564 	uint32_t ctrl;
1565 	uint32_t i;
1566 	int32_t  ret_val;
1567 	uint16_t pcix_cmd_word;
1568 	uint16_t pcix_stat_hi_word;
1569 	uint16_t cmd_mmrbc;
1570 	uint16_t stat_mmrbc;
1571 	uint32_t mta_size;
1572 	uint32_t reg_data;
1573 	uint32_t ctrl_ext;
1574 	uint32_t snoop;
1575 	uint32_t fwsm;
1576 	DEBUGFUNC("em_init_hw");
1577 
1578 	/* force full DMA clock frequency for ICH8 */
1579 	if (hw->mac_type == em_ich8lan) {
1580 		reg_data = E1000_READ_REG(hw, STATUS);
1581 		reg_data &= ~0x80000000;
1582 		E1000_WRITE_REG(hw, STATUS, reg_data);
1583 	}
1584 
1585 	if (hw->mac_type == em_pchlan ||
1586 		hw->mac_type == em_pch2lan ||
1587 		hw->mac_type == em_pch_lpt ||
1588 		hw->mac_type == em_pch_spt ||
1589 		hw->mac_type == em_pch_cnp ||
1590 		hw->mac_type == em_pch_tgp ||
1591 		hw->mac_type == em_pch_adp) {
1592 		/*
1593 		 * The MAC-PHY interconnect may still be in SMBus mode
1594 		 * after Sx->S0.  Toggle the LANPHYPC Value bit to force
1595 		 * the interconnect to PCIe mode, but only if there is no
1596 		 * firmware present otherwise firmware will have done it.
1597 		 */
1598 		fwsm = E1000_READ_REG(hw, FWSM);
1599 		if ((fwsm & E1000_FWSM_FW_VALID) == 0) {
1600 			ctrl = E1000_READ_REG(hw, CTRL);
1601 			ctrl |=  E1000_CTRL_LANPHYPC_OVERRIDE;
1602 			ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
1603 			E1000_WRITE_REG(hw, CTRL, ctrl);
1604 			usec_delay(10);
1605 			ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
1606 			E1000_WRITE_REG(hw, CTRL, ctrl);
1607 			msec_delay(50);
1608 		}
1609 
1610 		/* Gate automatic PHY configuration on non-managed 82579 */
1611 		if (hw->mac_type == em_pch2lan)
1612 			em_gate_hw_phy_config_ich8lan(hw, TRUE);
1613 
1614 		em_disable_ulp_lpt_lp(hw, TRUE);
1615 		/*
1616 		 * Reset the PHY before any access to it.  Doing so,
1617 		 * ensures that the PHY is in a known good state before
1618 		 * we read/write PHY registers.  The generic reset is
1619 		 * sufficient here, because we haven't determined
1620 		 * the PHY type yet.
1621 		 */
1622 		em_phy_reset(hw);
1623 
1624 		/* Ungate automatic PHY configuration on non-managed 82579 */
1625 		if (hw->mac_type == em_pch2lan &&
1626 			(fwsm & E1000_FWSM_FW_VALID) == 0)
1627 			em_gate_hw_phy_config_ich8lan(hw, FALSE);
1628 
1629 		/* Set MDIO slow mode before any other MDIO access */
1630 		ret_val = em_set_mdio_slow_mode_hv(hw);
1631 		if (ret_val)
1632 			return ret_val;
1633 	}
1634 
1635 	/* Initialize Identification LED */
1636 	ret_val = em_id_led_init(hw);
1637 	if (ret_val) {
1638 		DEBUGOUT("Error Initializing Identification LED\n");
1639 		return ret_val;
1640 	}
1641 	/* Set the media type and TBI compatibility */
1642 	em_set_media_type(hw);
1643 
1644 	/* Magic delay that improves problems with i219LM on HP Elitebook */
1645 	msec_delay(1);
1646 	/* Must be called after em_set_media_type because media_type is used */
1647 	em_initialize_hardware_bits(sc);
1648 
1649 	/* Disabling VLAN filtering. */
1650 	DEBUGOUT("Initializing the IEEE VLAN\n");
1651 	/* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */
1652 	if (!IS_ICH8(hw->mac_type)) {
1653 		if (hw->mac_type < em_82545_rev_3)
1654 			E1000_WRITE_REG(hw, VET, 0);
1655 		if (hw->mac_type == em_i350)
1656 			em_clear_vfta_i350(hw);
1657 		else
1658 			em_clear_vfta(hw);
1659 	}
1660 	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1661 	if (hw->mac_type == em_82542_rev2_0) {
1662 		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1663 		em_pci_clear_mwi(hw);
1664 		E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1665 		E1000_WRITE_FLUSH(hw);
1666 		msec_delay(5);
1667 	}
1668 	/*
1669 	 * Setup the receive address. This involves initializing all of the
1670 	 * Receive Address Registers (RARs 0 - 15).
1671 	 */
1672 	em_init_rx_addrs(hw);
1673 
1674 	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/
1675 	if (hw->mac_type == em_82542_rev2_0) {
1676 		E1000_WRITE_REG(hw, RCTL, 0);
1677 		E1000_WRITE_FLUSH(hw);
1678 		msec_delay(1);
1679 		if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1680 			em_pci_set_mwi(hw);
1681 	}
1682 	/* Zero out the Multicast HASH table */
1683 	DEBUGOUT("Zeroing the MTA\n");
1684 	mta_size = E1000_MC_TBL_SIZE;
1685 	if (IS_ICH8(hw->mac_type))
1686 		mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1687 	for (i = 0; i < mta_size; i++) {
1688 		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1689 		/*
1690 		 * use write flush to prevent Memory Write Block (MWB) from
1691 		 * occurring when accessing our register space
1692 		 */
1693 		E1000_WRITE_FLUSH(hw);
1694 	}
1695 	/*
1696 	 * Set the PCI priority bit correctly in the CTRL register.  This
1697 	 * determines if the adapter gives priority to receives, or if it
1698 	 * gives equal priority to transmits and receives.  Valid only on
1699 	 * 82542 and 82543 silicon.
1700 	 */
1701 	if (hw->dma_fairness && hw->mac_type <= em_82543) {
1702 		ctrl = E1000_READ_REG(hw, CTRL);
1703 		E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1704 	}
1705 	switch (hw->mac_type) {
1706 	case em_82545_rev_3:
1707 	case em_82546_rev_3:
1708 		break;
1709 	default:
1710 		/*
1711 		 * Workaround for PCI-X problem when BIOS sets MMRBC
1712 		 * incorrectly.
1713 		 */
1714 		if (hw->bus_type == em_bus_type_pcix) {
1715 			em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER,
1716 			    &pcix_cmd_word);
1717 			em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
1718 			    &pcix_stat_hi_word);
1719 			cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK)
1720 			    >> PCIX_COMMAND_MMRBC_SHIFT;
1721 			stat_mmrbc = (pcix_stat_hi_word &
1722 			    PCIX_STATUS_HI_MMRBC_MASK) >>
1723 			    PCIX_STATUS_HI_MMRBC_SHIFT;
1724 
1725 			if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1726 				stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1727 			if (cmd_mmrbc > stat_mmrbc) {
1728 				pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1729 				pcix_cmd_word |= stat_mmrbc <<
1730 				    PCIX_COMMAND_MMRBC_SHIFT;
1731 				em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
1732 				    &pcix_cmd_word);
1733 			}
1734 		}
1735 		break;
1736 	}
1737 
1738 	/* More time needed for PHY to initialize */
1739 	if (IS_ICH8(hw->mac_type))
1740 		msec_delay(15);
1741 
1742         /*
1743 	 * The 82578 Rx buffer will stall if wakeup is enabled in host and
1744 	 * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
1745 	 * Reset the phy after disabling host wakeup to reset the Rx buffer.
1746 	 */
1747 	if (hw->phy_type == em_phy_82578) {
1748 		em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1),
1749 		    (uint16_t *)&reg_data);
1750 		ret_val = em_phy_reset(hw);
1751 		if (ret_val)
1752 			return ret_val;
1753 	}
1754 
1755 	/* Call a subroutine to configure the link and setup flow control. */
1756 	ret_val = em_setup_link(hw);
1757 
1758 	/* Set the transmit descriptor write-back policy */
1759 	if (hw->mac_type > em_82544) {
1760 		FOREACH_QUEUE(sc, que) {
1761 			ctrl = E1000_READ_REG(hw, TXDCTL(que->me));
1762 			ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) |
1763 			    E1000_TXDCTL_FULL_TX_DESC_WB;
1764 			E1000_WRITE_REG(hw, TXDCTL(que->me), ctrl);
1765 		}
1766 	}
1767 	if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
1768 		em_enable_tx_pkt_filtering(hw);
1769 	}
1770 	switch (hw->mac_type) {
1771 	default:
1772 		break;
1773 	case em_80003es2lan:
1774 		/* Enable retransmit on late collisions */
1775 		reg_data = E1000_READ_REG(hw, TCTL);
1776 		reg_data |= E1000_TCTL_RTLC;
1777 		E1000_WRITE_REG(hw, TCTL, reg_data);
1778 
1779 		/* Configure Gigabit Carry Extend Padding */
1780 		reg_data = E1000_READ_REG(hw, TCTL_EXT);
1781 		reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1782 		reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1783 		E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1784 
1785 		/* Configure Transmit Inter-Packet Gap */
1786 		reg_data = E1000_READ_REG(hw, TIPG);
1787 		reg_data &= ~E1000_TIPG_IPGT_MASK;
1788 		reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1789 		E1000_WRITE_REG(hw, TIPG, reg_data);
1790 
1791 		reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1792 		reg_data &= ~0x00100000;
1793 		E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1794 		/* FALLTHROUGH */
1795 	case em_82571:
1796 	case em_82572:
1797 	case em_82575:
1798 	case em_82576:
1799 	case em_82580:
1800 	case em_i210:
1801 	case em_i350:
1802 	case em_ich8lan:
1803 	case em_ich9lan:
1804 	case em_ich10lan:
1805 	case em_pchlan:
1806 	case em_pch2lan:
1807 	case em_pch_lpt:
1808 	case em_pch_spt:
1809 	case em_pch_cnp:
1810 	case em_pch_tgp:
1811 	case em_pch_adp:
1812 		/*
1813 		 * Old code always initialized queue 1,
1814 		 * even when unused, keep behaviour
1815 		 */
1816 		if (sc->num_queues == 1) {
1817 			ctrl = E1000_READ_REG(hw, TXDCTL(1));
1818 			ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) |
1819 			    E1000_TXDCTL_FULL_TX_DESC_WB;
1820 			E1000_WRITE_REG(hw, TXDCTL(1), ctrl);
1821 		}
1822 		break;
1823 	}
1824 
1825 	if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
1826 		uint32_t gcr = E1000_READ_REG(hw, GCR);
1827 		gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1828 		E1000_WRITE_REG(hw, GCR, gcr);
1829 	}
1830 	/*
1831 	 * Clear all of the statistics registers (clear on read).  It is
1832 	 * important that we do this after we have tried to establish link
1833 	 * because the symbol error count will increment wildly if there is
1834 	 * no link.
1835 	 */
1836 	em_clear_hw_cntrs(hw);
1837 	/*
1838 	 * ICH8 No-snoop bits are opposite polarity. Set to snoop by default
1839 	 * after reset.
1840 	 */
1841 	if (IS_ICH8(hw->mac_type)) {
1842 		if (hw->mac_type == em_ich8lan)
1843 			snoop = PCI_EX_82566_SNOOP_ALL;
1844 		else
1845 			snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL);
1846 
1847 		em_set_pci_ex_no_snoop(hw, snoop);
1848 	}
1849 
1850 	/* ungate DMA clock to avoid packet loss */
1851 	if (hw->mac_type >= em_pch_tgp) {
1852 		uint32_t fflt_dbg = E1000_READ_REG(hw, FFLT_DBG);
1853 		fflt_dbg |= (1 << 12);
1854 		E1000_WRITE_REG(hw, FFLT_DBG, fflt_dbg);
1855 	}
1856 
1857 	if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1858 	    hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1859 		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1860 		/*
1861 		 * Relaxed ordering must be disabled to avoid a parity error
1862 		 * crash in a PCI slot.
1863 		 */
1864 		ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1865 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1866 	}
1867 	return ret_val;
1868 }
1869 
1870 /******************************************************************************
1871  * Adjust SERDES output amplitude based on EEPROM setting.
1872  *
1873  * hw - Struct containing variables accessed by shared code.
1874  *****************************************************************************/
1875 static int32_t
em_adjust_serdes_amplitude(struct em_hw * hw)1876 em_adjust_serdes_amplitude(struct em_hw *hw)
1877 {
1878 	uint16_t eeprom_data;
1879 	int32_t  ret_val;
1880 	DEBUGFUNC("em_adjust_serdes_amplitude");
1881 
1882 	if (hw->media_type != em_media_type_internal_serdes ||
1883 	    hw->mac_type >= em_82575)
1884 		return E1000_SUCCESS;
1885 
1886 	switch (hw->mac_type) {
1887 	case em_82545_rev_3:
1888 	case em_82546_rev_3:
1889 		break;
1890 	default:
1891 		return E1000_SUCCESS;
1892 	}
1893 
1894 	ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1895 	if (ret_val) {
1896 		return ret_val;
1897 	}
1898 	if (eeprom_data != EEPROM_RESERVED_WORD) {
1899 		/* Adjust SERDES output amplitude only. */
1900 		eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1901 		ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
1902 		    eeprom_data);
1903 		if (ret_val)
1904 			return ret_val;
1905 	}
1906 	return E1000_SUCCESS;
1907 }
1908 
1909 /******************************************************************************
1910  * Configures flow control and link settings.
1911  *
1912  * hw - Struct containing variables accessed by shared code
1913  *
1914  * Determines which flow control settings to use. Calls the appropriate media-
1915  * specific link configuration function. Configures the flow control settings.
1916  * Assuming the adapter has a valid link partner, a valid link should be
1917  * established. Assumes the hardware has previously been reset and the
1918  * transmitter and receiver are not enabled.
1919  *****************************************************************************/
1920 int32_t
em_setup_link(struct em_hw * hw)1921 em_setup_link(struct em_hw *hw)
1922 {
1923 	uint32_t ctrl_ext;
1924 	int32_t  ret_val;
1925 	uint16_t eeprom_data;
1926 	uint16_t eeprom_control2_reg_offset;
1927 	DEBUGFUNC("em_setup_link");
1928 
1929 	eeprom_control2_reg_offset =
1930 	    (hw->mac_type != em_icp_xxxx)
1931 	    ? EEPROM_INIT_CONTROL2_REG
1932 	    : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num);
1933 	/*
1934 	 * In the case of the phy reset being blocked, we already have a
1935 	 * link. We do not have to set it up again.
1936 	 */
1937 	if (em_check_phy_reset_block(hw))
1938 		return E1000_SUCCESS;
1939 	/*
1940 	 * Read and store word 0x0F of the EEPROM. This word contains bits
1941 	 * that determine the hardware's default PAUSE (flow control) mode, a
1942 	 * bit that determines whether the HW defaults to enabling or
1943 	 * disabling auto-negotiation, and the direction of the SW defined
1944 	 * pins. If there is no SW over-ride of the flow control setting,
1945 	 * then the variable hw->fc will be initialized based on a value in
1946 	 * the EEPROM.
1947 	 */
1948 	if (hw->fc == E1000_FC_DEFAULT) {
1949 		switch (hw->mac_type) {
1950 		case em_ich8lan:
1951 		case em_ich9lan:
1952 		case em_ich10lan:
1953 		case em_pchlan:
1954 		case em_pch2lan:
1955 		case em_pch_lpt:
1956 		case em_pch_spt:
1957 		case em_pch_cnp:
1958 		case em_pch_tgp:
1959 		case em_pch_adp:
1960 		case em_82573:
1961 		case em_82574:
1962 			hw->fc = E1000_FC_FULL;
1963 			break;
1964 		default:
1965 			ret_val = em_read_eeprom(hw,
1966 			    eeprom_control2_reg_offset, 1, &eeprom_data);
1967 			if (ret_val) {
1968 				DEBUGOUT("EEPROM Read Error\n");
1969 				return -E1000_ERR_EEPROM;
1970 			}
1971 			if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1972 				hw->fc = E1000_FC_NONE;
1973 			else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1974 			    EEPROM_WORD0F_ASM_DIR)
1975 				hw->fc = E1000_FC_TX_PAUSE;
1976 			else
1977 				hw->fc = E1000_FC_FULL;
1978 			break;
1979 		}
1980 	}
1981 	/*
1982 	 * We want to save off the original Flow Control configuration just
1983 	 * in case we get disconnected and then reconnected into a different
1984 	 * hub or switch with different Flow Control capabilities.
1985 	 */
1986 	if (hw->mac_type == em_82542_rev2_0)
1987 		hw->fc &= (~E1000_FC_TX_PAUSE);
1988 
1989 	if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
1990 		hw->fc &= (~E1000_FC_RX_PAUSE);
1991 
1992 	hw->original_fc = hw->fc;
1993 
1994 	DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1995 	/*
1996 	 * Take the 4 bits from EEPROM word 0x0F that determine the initial
1997 	 * polarity value for the SW controlled pins, and setup the Extended
1998 	 * Device Control reg with that info. This is needed because one of
1999 	 * the SW controlled pins is used for signal detection.  So this
2000 	 * should be done before em_setup_pcs_link() or em_phy_setup() is
2001 	 * called.
2002 	 */
2003 	if (hw->mac_type == em_82543) {
2004 		ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
2005 		    1, &eeprom_data);
2006 		if (ret_val) {
2007 			DEBUGOUT("EEPROM Read Error\n");
2008 			return -E1000_ERR_EEPROM;
2009 		}
2010 		ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
2011 		    SWDPIO__EXT_SHIFT);
2012 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2013 	}
2014 	/* Make sure we have a valid PHY */
2015 	ret_val = em_detect_gig_phy(hw);
2016 	if (ret_val) {
2017 		DEBUGOUT("Error, did not detect valid phy.\n");
2018 		if (hw->mac_type == em_icp_xxxx)
2019 			return E1000_DEFER_INIT;
2020 		else
2021 			return ret_val;
2022 	}
2023 	DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
2024 
2025 	/* Call the necessary subroutine to configure the link. */
2026 	switch (hw->media_type) {
2027 	case em_media_type_copper:
2028 	case em_media_type_oem:
2029 		ret_val = em_setup_copper_link(hw);
2030 		break;
2031 	default:
2032 		ret_val = em_setup_fiber_serdes_link(hw);
2033 		break;
2034 	}
2035 	/*
2036 	 * Initialize the flow control address, type, and PAUSE timer
2037 	 * registers to their default values.  This is done even if flow
2038 	 * control is disabled, because it does not hurt anything to
2039 	 * initialize these registers.
2040 	 */
2041 	DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"
2042 	    );
2043 
2044 	/*
2045          * FCAL/H and FCT are hardcoded to standard values in
2046          * em_ich8lan / em_ich9lan / em_ich10lan.
2047          */
2048 	if (!IS_ICH8(hw->mac_type)) {
2049 		E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
2050 		E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
2051 		E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
2052 	}
2053 	E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
2054 
2055 	if (hw->phy_type == em_phy_82577 ||
2056 	    hw->phy_type == em_phy_82578 ||
2057 	    hw->phy_type == em_phy_82579 ||
2058 	    hw->phy_type == em_phy_i217) {
2059 		E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000);
2060 		em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
2061 		    hw->fc_pause_time);
2062 	}
2063 
2064 	/*
2065 	 * Set the flow control receive threshold registers.  Normally, these
2066 	 * registers will be set to a default threshold that may be adjusted
2067 	 * later by the driver's runtime code.  However, if the ability to
2068 	 * transmit pause frames in not enabled, then these registers will be
2069 	 * set to 0.
2070 	 */
2071 	if (!(hw->fc & E1000_FC_TX_PAUSE)) {
2072 		E1000_WRITE_REG(hw, FCRTL, 0);
2073 		E1000_WRITE_REG(hw, FCRTH, 0);
2074 	} else {
2075 		/*
2076 		 * We need to set up the Receive Threshold high and low water
2077 		 * marks as well as (optionally) enabling the transmission of
2078 		 * XON frames.
2079 		 */
2080 		if (hw->fc_send_xon) {
2081 			E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water
2082 			    | E1000_FCRTL_XONE));
2083 			E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2084 		} else {
2085 			E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2086 			E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2087 		}
2088 	}
2089 	return ret_val;
2090 }
2091 
2092 void
em_power_up_serdes_link_82575(struct em_hw * hw)2093 em_power_up_serdes_link_82575(struct em_hw *hw)
2094 {
2095 	uint32_t reg;
2096 
2097 	if (hw->media_type != em_media_type_internal_serdes &&
2098 	    hw->sgmii_active == FALSE)
2099 		return;
2100 
2101 	/* Enable PCS to turn on link */
2102 	reg = E1000_READ_REG(hw, PCS_CFG0);
2103 	reg |= E1000_PCS_CFG_PCS_EN;
2104 	E1000_WRITE_REG(hw, PCS_CFG0, reg);
2105 
2106 	/* Power up the laser */
2107 	reg = E1000_READ_REG(hw, CTRL_EXT);
2108 	reg &= ~E1000_CTRL_EXT_SDP3_DATA;
2109 	E1000_WRITE_REG(hw, CTRL_EXT, reg);
2110 
2111 	/* flush the write to verify completion */
2112 	E1000_WRITE_FLUSH(hw);
2113 	delay(5);
2114 }
2115 
2116 /******************************************************************************
2117  * Sets up link for a fiber based or serdes based adapter
2118  *
2119  * hw - Struct containing variables accessed by shared code
2120  *
2121  * Manipulates Physical Coding Sublayer functions in order to configure
2122  * link. Assumes the hardware has been previously reset and the transmitter
2123  * and receiver are not enabled.
2124  *****************************************************************************/
2125 static int32_t
em_setup_fiber_serdes_link(struct em_hw * hw)2126 em_setup_fiber_serdes_link(struct em_hw *hw)
2127 {
2128 	uint32_t ctrl, ctrl_ext, reg;
2129 	uint32_t status;
2130 	uint32_t txcw = 0;
2131 	uint32_t i;
2132 	uint32_t signal = 0;
2133 	int32_t  ret_val;
2134 	DEBUGFUNC("em_setup_fiber_serdes_link");
2135 
2136 	if (hw->media_type != em_media_type_internal_serdes &&
2137 	    hw->sgmii_active == FALSE)
2138 		return -E1000_ERR_CONFIG;
2139 
2140 	/*
2141 	 * On 82571 and 82572 Fiber connections, SerDes loopback mode
2142 	 * persists until explicitly turned off or a power cycle is
2143 	 * performed.  A read to the register does not indicate its status.
2144 	 * Therefore, we ensure loopback mode is disabled during
2145 	 * initialization.
2146 	 */
2147 	if (hw->mac_type == em_82571 || hw->mac_type == em_82572 ||
2148 	    hw->mac_type >= em_82575)
2149 		E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
2150 
2151 	if (hw->mac_type >= em_82575)
2152 		em_power_up_serdes_link_82575(hw);
2153 
2154 	/*
2155 	 * On adapters with a MAC newer than 82544, SWDP 1 will be set when
2156 	 * the optics detect a signal. On older adapters, it will be cleared
2157 	 * when there is a signal.  This applies to fiber media only. If
2158 	 * we're on serdes media, adjust the output amplitude to value set in
2159 	 * the EEPROM.
2160 	 */
2161 	ctrl = E1000_READ_REG(hw, CTRL);
2162 	if (hw->media_type == em_media_type_fiber)
2163 		signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
2164 
2165 	ret_val = em_adjust_serdes_amplitude(hw);
2166 	if (ret_val)
2167 		return ret_val;
2168 
2169 	/* Take the link out of reset */
2170 	ctrl &= ~(E1000_CTRL_LRST);
2171 
2172 	if (hw->mac_type >= em_82575) {
2173 		/* set both sw defined pins on 82575/82576*/
2174 		ctrl |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
2175 
2176 		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2177 		switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
2178 		case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
2179 		case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
2180 			/* the backplane is always connected */
2181 			reg = E1000_READ_REG(hw, PCS_LCTL);
2182 			reg |= E1000_PCS_LCTL_FORCE_FCTRL;
2183 			reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
2184 			reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
2185 			DEBUGOUT("Configuring Forced Link\n");
2186 			E1000_WRITE_REG(hw, PCS_LCTL, reg);
2187 			em_force_mac_fc(hw);
2188 			hw->autoneg_failed = 0;
2189 			return E1000_SUCCESS;
2190 			break;
2191 		default:
2192 			/* Set switch control to serdes energy detect */
2193 			reg = E1000_READ_REG(hw, CONNSW);
2194 			reg |= E1000_CONNSW_ENRGSRC;
2195 			E1000_WRITE_REG(hw, CONNSW, reg);
2196 			break;
2197 		}
2198 	}
2199 
2200 	/* Adjust VCO speed to improve BER performance */
2201 	ret_val = em_set_vco_speed(hw);
2202 	if (ret_val)
2203 		return ret_val;
2204 
2205 	em_config_collision_dist(hw);
2206 	/*
2207 	 * Check for a software override of the flow control settings, and
2208 	 * setup the device accordingly.  If auto-negotiation is enabled,
2209 	 * then software will have to set the "PAUSE" bits to the correct
2210 	 * value in the Tranmsit Config Word Register (TXCW) and re-start
2211 	 * auto-negotiation.  However, if auto-negotiation is disabled, then
2212 	 * software will have to manually configure the two flow control
2213 	 * enable bits in the CTRL register.
2214 	 *
2215 	 * The possible values of the "fc" parameter are: 0:  Flow control is
2216 	 * completely disabled 1:  Rx flow control is enabled (we can receive
2217 	 * pause frames, but not send pause frames). 2:  Tx flow control is
2218 	 * enabled (we can send pause frames but we do not support receiving
2219 	 * pause frames). 3:  Both Rx and TX flow control (symmetric) are
2220 	 * enabled.
2221 	 */
2222 	switch (hw->fc) {
2223 	case E1000_FC_NONE:
2224 		/*
2225 		 * Flow control is completely disabled by a software
2226 		 * over-ride.
2227 		 */
2228 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2229 		break;
2230 	case E1000_FC_RX_PAUSE:
2231 		/*
2232 		 * RX Flow control is enabled and TX Flow control is disabled
2233 		 * by a software over-ride. Since there really isn't a way to
2234 		 * advertise that we are capable of RX Pause ONLY, we will
2235 		 * advertise that we support both symmetric and asymmetric RX
2236 		 * PAUSE. Later, we will disable the adapter's ability to
2237 		 * send PAUSE frames.
2238 		 */
2239 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD |
2240 		    E1000_TXCW_PAUSE_MASK);
2241 		break;
2242 	case E1000_FC_TX_PAUSE:
2243 		/*
2244 		 * TX Flow control is enabled, and RX Flow control is
2245 		 * disabled, by a software over-ride.
2246 		 */
2247 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2248 		break;
2249 	case E1000_FC_FULL:
2250 		/*
2251 		 * Flow control (both RX and TX) is enabled by a software
2252 		 * over-ride.
2253 		 */
2254 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD |
2255 		    E1000_TXCW_PAUSE_MASK);
2256 		break;
2257 	default:
2258 		DEBUGOUT("Flow control param set incorrectly\n");
2259 		return -E1000_ERR_CONFIG;
2260 		break;
2261 	}
2262 	/*
2263 	 * Since auto-negotiation is enabled, take the link out of reset (the
2264 	 * link will be in reset, because we previously reset the chip). This
2265 	 * will restart auto-negotiation.  If auto-negotiation is successful
2266 	 * then the link-up status bit will be set and the flow control
2267 	 * enable bits (RFCE and TFCE) will be set according to their
2268 	 * negotiated value.
2269 	 */
2270 	DEBUGOUT("Auto-negotiation enabled\n");
2271 
2272 	E1000_WRITE_REG(hw, TXCW, txcw);
2273 	E1000_WRITE_REG(hw, CTRL, ctrl);
2274 	E1000_WRITE_FLUSH(hw);
2275 
2276 	hw->txcw = txcw;
2277 	msec_delay(1);
2278 	/*
2279 	 * If we have a signal (the cable is plugged in) then poll for a
2280 	 * "Link-Up" indication in the Device Status Register.  Time-out if a
2281 	 * link isn't seen in 500 milliseconds seconds (Auto-negotiation
2282 	 * should complete in less than 500 milliseconds even if the other
2283 	 * end is doing it in SW). For internal serdes, we just assume a
2284 	 * signal is present, then poll.
2285 	 */
2286 	if (hw->media_type == em_media_type_internal_serdes ||
2287 	    (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2288 		DEBUGOUT("Looking for Link\n");
2289 		for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2290 			msec_delay(10);
2291 			status = E1000_READ_REG(hw, STATUS);
2292 			if (status & E1000_STATUS_LU)
2293 				break;
2294 		}
2295 		if (i == (LINK_UP_TIMEOUT / 10)) {
2296 			DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2297 			hw->autoneg_failed = 1;
2298 			/*
2299 			 * AutoNeg failed to achieve a link, so we'll call
2300 			 * em_check_for_link. This routine will force the
2301 			 * link up if we detect a signal. This will allow us
2302 			 * to communicate with non-autonegotiating link
2303 			 * partners.
2304 			 */
2305 			ret_val = em_check_for_link(hw);
2306 			if (ret_val) {
2307 				DEBUGOUT("Error while checking for link\n");
2308 				return ret_val;
2309 			}
2310 			hw->autoneg_failed = 0;
2311 		} else {
2312 			hw->autoneg_failed = 0;
2313 			DEBUGOUT("Valid Link Found\n");
2314 		}
2315 	} else {
2316 		DEBUGOUT("No Signal Detected\n");
2317 	}
2318 	return E1000_SUCCESS;
2319 }
2320 
2321 /******************************************************************************
2322  * Make sure we have a valid PHY and change PHY mode before link setup.
2323  *
2324  * hw - Struct containing variables accessed by shared code
2325  *****************************************************************************/
2326 static int32_t
em_copper_link_preconfig(struct em_hw * hw)2327 em_copper_link_preconfig(struct em_hw *hw)
2328 {
2329 	uint32_t ctrl;
2330 	int32_t  ret_val;
2331 	uint16_t phy_data;
2332 	DEBUGFUNC("em_copper_link_preconfig");
2333 
2334 	ctrl = E1000_READ_REG(hw, CTRL);
2335 	/*
2336 	 * With 82543, we need to force speed and duplex on the MAC equal to
2337 	 * what the PHY speed and duplex configuration is. In addition, we
2338 	 * need to perform a hardware reset on the PHY to take it out of
2339 	 * reset.
2340 	 */
2341 	if (hw->mac_type > em_82543) {
2342 		ctrl |= E1000_CTRL_SLU;
2343 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2344 		E1000_WRITE_REG(hw, CTRL, ctrl);
2345 	} else {
2346 		ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX |
2347 		    E1000_CTRL_SLU);
2348 		E1000_WRITE_REG(hw, CTRL, ctrl);
2349 		ret_val = em_phy_hw_reset(hw);
2350 		if (ret_val)
2351 			return ret_val;
2352 	}
2353 
2354 	/* Set PHY to class A mode (if necessary) */
2355 	ret_val = em_set_phy_mode(hw);
2356 	if (ret_val)
2357 		return ret_val;
2358 
2359 	if ((hw->mac_type == em_82545_rev_3) ||
2360 	    (hw->mac_type == em_82546_rev_3)) {
2361 		ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2362 		    &phy_data);
2363 		phy_data |= 0x00000008;
2364 		ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2365 		    phy_data);
2366 	}
2367 	if (hw->mac_type <= em_82543 ||
2368 	    hw->mac_type == em_82541 || hw->mac_type == em_82547 ||
2369 	    hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2)
2370 		hw->phy_reset_disable = FALSE;
2371 	if ((hw->mac_type == em_82575 || hw->mac_type == em_82580 ||
2372 	    hw->mac_type == em_82576 ||
2373 	    hw->mac_type == em_i210 || hw->mac_type == em_i350) &&
2374 	    hw->sgmii_active) {
2375 		/* allow time for SFP cage time to power up phy */
2376 		msec_delay(300);
2377 
2378 		/*
2379 		 * SFP documentation requires the following to configure the SFP module
2380 		 * to work on SGMII.  No further documentation is given.
2381 		 */
2382 		em_write_phy_reg(hw, 0x1B, 0x8084);
2383 		em_phy_hw_reset(hw);
2384 	}
2385 
2386 	return E1000_SUCCESS;
2387 }
2388 
2389 /******************************************************************************
2390  * Copper link setup for em_phy_igp series.
2391  *
2392  * hw - Struct containing variables accessed by shared code
2393  *****************************************************************************/
2394 static int32_t
em_copper_link_igp_setup(struct em_hw * hw)2395 em_copper_link_igp_setup(struct em_hw *hw)
2396 {
2397 	uint32_t led_ctrl;
2398 	int32_t  ret_val;
2399 	uint16_t phy_data;
2400 	DEBUGFUNC("em_copper_link_igp_setup");
2401 
2402 	if (hw->phy_reset_disable)
2403 		return E1000_SUCCESS;
2404 
2405 	ret_val = em_phy_reset(hw);
2406 	if (ret_val) {
2407 		DEBUGOUT("Error Resetting the PHY\n");
2408 		return ret_val;
2409 	}
2410 	/* Wait 15ms for MAC to configure PHY from eeprom settings */
2411 	msec_delay(15);
2412 	if (hw->mac_type != em_ich8lan &&
2413 	    hw->mac_type != em_ich9lan &&
2414 	    hw->mac_type != em_ich10lan) {
2415 		/* Configure activity LED after PHY reset */
2416 		led_ctrl = E1000_READ_REG(hw, LEDCTL);
2417 		led_ctrl &= IGP_ACTIVITY_LED_MASK;
2418 		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2419 		E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2420 	}
2421 	/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2422 	if (hw->phy_type == em_phy_igp) {
2423 		/* disable lplu d3 during driver init */
2424 		ret_val = em_set_d3_lplu_state(hw, FALSE);
2425 		if (ret_val) {
2426 			DEBUGOUT("Error Disabling LPLU D3\n");
2427 			return ret_val;
2428 		}
2429 	}
2430 	/* disable lplu d0 during driver init */
2431 	if (hw->mac_type == em_pchlan ||
2432 		hw->mac_type == em_pch2lan ||
2433 		hw->mac_type == em_pch_lpt ||
2434 		hw->mac_type == em_pch_spt ||
2435 		hw->mac_type == em_pch_cnp ||
2436 		hw->mac_type == em_pch_tgp ||
2437 		hw->mac_type == em_pch_adp)
2438 		ret_val = em_set_lplu_state_pchlan(hw, FALSE);
2439 	else
2440 		ret_val = em_set_d0_lplu_state(hw, FALSE);
2441 	if (ret_val) {
2442 		DEBUGOUT("Error Disabling LPLU D0\n");
2443 		return ret_val;
2444 	}
2445 	/* Configure mdi-mdix settings */
2446 	ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2447 	if (ret_val)
2448 		return ret_val;
2449 
2450 	if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
2451 		hw->dsp_config_state = em_dsp_config_disabled;
2452 		/* Force MDI for earlier revs of the IGP PHY */
2453 		phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
2454 		    IGP01E1000_PSCR_FORCE_MDI_MDIX);
2455 		hw->mdix = 1;
2456 
2457 	} else {
2458 		hw->dsp_config_state = em_dsp_config_enabled;
2459 		phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2460 
2461 		switch (hw->mdix) {
2462 		case 1:
2463 			phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2464 			break;
2465 		case 2:
2466 			phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2467 			break;
2468 		case 0:
2469 		default:
2470 			phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2471 			break;
2472 		}
2473 	}
2474 	ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2475 	if (ret_val)
2476 		return ret_val;
2477 
2478 	/* set auto-master slave resolution settings */
2479 	if (hw->autoneg) {
2480 		em_ms_type phy_ms_setting = hw->master_slave;
2481 		if (hw->ffe_config_state == em_ffe_config_active)
2482 			hw->ffe_config_state = em_ffe_config_enabled;
2483 
2484 		if (hw->dsp_config_state == em_dsp_config_activated)
2485 			hw->dsp_config_state = em_dsp_config_enabled;
2486 		/*
2487 		 * when autonegotiation advertisement is only 1000Mbps then
2488 		 * we should disable SmartSpeed and enable Auto MasterSlave
2489 		 * resolution as hardware default.
2490 		 */
2491 		if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2492 			/* Disable SmartSpeed */
2493 			ret_val = em_read_phy_reg(hw,
2494 			    IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2495 			if (ret_val)
2496 				return ret_val;
2497 
2498 			phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2499 			ret_val = em_write_phy_reg(hw,
2500 			    IGP01E1000_PHY_PORT_CONFIG, phy_data);
2501 			if (ret_val)
2502 				return ret_val;
2503 			/* Set auto Master/Slave resolution process */
2504 			ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
2505 			    &phy_data);
2506 			if (ret_val)
2507 				return ret_val;
2508 
2509 			phy_data &= ~CR_1000T_MS_ENABLE;
2510 			ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
2511 			    phy_data);
2512 			if (ret_val)
2513 				return ret_val;
2514 		}
2515 		ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2516 		if (ret_val)
2517 			return ret_val;
2518 
2519 		/* load defaults for future use */
2520 		hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2521 		    ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master :
2522 		    em_ms_force_slave) : em_ms_auto;
2523 
2524 		switch (phy_ms_setting) {
2525 		case em_ms_force_master:
2526 			phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2527 			break;
2528 		case em_ms_force_slave:
2529 			phy_data |= CR_1000T_MS_ENABLE;
2530 			phy_data &= ~(CR_1000T_MS_VALUE);
2531 			break;
2532 		case em_ms_auto:
2533 			phy_data &= ~CR_1000T_MS_ENABLE;
2534 			break;
2535 		default:
2536 			break;
2537 		}
2538 		ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2539 		if (ret_val)
2540 			return ret_val;
2541 	}
2542 	return E1000_SUCCESS;
2543 }
2544 
2545 /******************************************************************************
2546  * Copper link setup for em_phy_gg82563 series.
2547  *
2548  * hw - Struct containing variables accessed by shared code
2549  *****************************************************************************/
2550 static int32_t
em_copper_link_ggp_setup(struct em_hw * hw)2551 em_copper_link_ggp_setup(struct em_hw *hw)
2552 {
2553 	int32_t  ret_val;
2554 	uint16_t phy_data;
2555 	uint32_t reg_data;
2556 	DEBUGFUNC("em_copper_link_ggp_setup");
2557 
2558 	if (!hw->phy_reset_disable) {
2559 
2560 		/* Enable CRS on TX for half-duplex operation. */
2561 		ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
2562 		    &phy_data);
2563 		if (ret_val)
2564 			return ret_val;
2565 
2566 		phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2567 		/* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2568 		phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2569 
2570 		ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
2571 		    phy_data);
2572 		if (ret_val)
2573 			return ret_val;
2574 		/*
2575 		 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1
2576 		 * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only
2577 		 * (MDI-X for 10/100Base-T modes)
2578 		 */
2579 		ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL,
2580 		    &phy_data);
2581 
2582 		if (ret_val)
2583 			return ret_val;
2584 
2585 		phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2586 
2587 		switch (hw->mdix) {
2588 		case 1:
2589 			phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2590 			break;
2591 		case 2:
2592 			phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2593 			break;
2594 		case 0:
2595 		default:
2596 			phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2597 			break;
2598 		}
2599 		/*
2600 		 * Options: disable_polarity_correction = 0 (default)
2601 		 * Automatic Correction for Reversed Cable Polarity 0 -
2602 		 * Disabled 1 - Enabled
2603 		 */
2604 		phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2605 		if (hw->disable_polarity_correction == 1)
2606 			phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2607 		ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL,
2608 		    phy_data);
2609 
2610 		if (ret_val)
2611 			return ret_val;
2612 
2613 		/* SW Reset the PHY so all changes take effect */
2614 		ret_val = em_phy_reset(hw);
2615 		if (ret_val) {
2616 			DEBUGOUT("Error Resetting the PHY\n");
2617 			return ret_val;
2618 		}
2619 	}			/* phy_reset_disable */
2620 	if (hw->mac_type == em_80003es2lan) {
2621 		/* Bypass RX and TX FIFO's */
2622 		ret_val = em_write_kmrn_reg(hw,
2623 		    E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2624 		    E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
2625 		    E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2626 		if (ret_val)
2627 			return ret_val;
2628 
2629 		ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2,
2630 		    &phy_data);
2631 		if (ret_val)
2632 			return ret_val;
2633 
2634 		phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2635 		ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2,
2636 		    phy_data);
2637 
2638 		if (ret_val)
2639 			return ret_val;
2640 
2641 		reg_data = E1000_READ_REG(hw, CTRL_EXT);
2642 		reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2643 		E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2644 
2645 		ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
2646 		    &phy_data);
2647 		if (ret_val)
2648 			return ret_val;
2649 		/*
2650 		 * Do not init these registers when the HW is in IAMT mode,
2651 		 * since the firmware will have already initialized them. We
2652 		 * only initialize them if the HW is not in IAMT mode.
2653 		 */
2654 		if (em_check_mng_mode(hw) == FALSE) {
2655 			/* Enable Electrical Idle on the PHY */
2656 			phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2657 			ret_val = em_write_phy_reg(hw,
2658 			    GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2659 			if (ret_val)
2660 				return ret_val;
2661 
2662 			ret_val = em_read_phy_reg(hw,
2663 			    GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2664 			if (ret_val)
2665 				return ret_val;
2666 
2667 			phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2668 			ret_val = em_write_phy_reg(hw,
2669 			    GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2670 
2671 			if (ret_val)
2672 				return ret_val;
2673 		}
2674 		/*
2675 		 * Workaround: Disable padding in Kumeran interface in the
2676 		 * MAC and in the PHY to avoid CRC errors.
2677 		 */
2678 		ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
2679 		    &phy_data);
2680 		if (ret_val)
2681 			return ret_val;
2682 		phy_data |= GG82563_ICR_DIS_PADDING;
2683 		ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
2684 		    phy_data);
2685 		if (ret_val)
2686 			return ret_val;
2687 	}
2688 	return E1000_SUCCESS;
2689 }
2690 
2691 /******************************************************************************
2692  * Copper link setup for em_phy_m88 series.
2693  *
2694  * hw - Struct containing variables accessed by shared code
2695  *****************************************************************************/
2696 static int32_t
em_copper_link_mgp_setup(struct em_hw * hw)2697 em_copper_link_mgp_setup(struct em_hw *hw)
2698 {
2699 	int32_t  ret_val;
2700 	uint16_t phy_data;
2701 	DEBUGFUNC("em_copper_link_mgp_setup");
2702 
2703 	if (hw->phy_reset_disable)
2704 		return E1000_SUCCESS;
2705 
2706 	/* disable lplu d0 during driver init */
2707 	if (hw->mac_type == em_pchlan ||
2708 		hw->mac_type == em_pch2lan ||
2709 		hw->mac_type == em_pch_lpt ||
2710 		hw->mac_type == em_pch_spt ||
2711 		hw->mac_type == em_pch_cnp ||
2712 		hw->mac_type == em_pch_tgp ||
2713 		hw->mac_type == em_pch_adp)
2714 		ret_val = em_set_lplu_state_pchlan(hw, FALSE);
2715 
2716 	/* Enable CRS on TX. This must be set for half-duplex operation. */
2717 	ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2718 	if (ret_val)
2719 		return ret_val;
2720 
2721 	if (hw->phy_id == M88E1141_E_PHY_ID) {
2722 		phy_data |= 0x00000008;
2723 		ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2724 		    phy_data);
2725 		if (ret_val)
2726 			return ret_val;
2727 
2728 		ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2729 		    &phy_data);
2730 		if (ret_val)
2731 			return ret_val;
2732 
2733 		phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX;
2734 
2735 	}
2736 	/* For BM PHY this bit is downshift enable */
2737 	else if (hw->phy_type != em_phy_bm)
2738 		phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2739 	/*
2740 	 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI
2741 	 * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for
2742 	 * 10/100Base-T modes)
2743 	 */
2744 	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2745 
2746 	switch (hw->mdix) {
2747 	case 1:
2748 		phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2749 		break;
2750 	case 2:
2751 		phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2752 		break;
2753 	case 3:
2754 		phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2755 		break;
2756 	case 0:
2757 	default:
2758 		phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2759 		break;
2760 	}
2761 	/*
2762 	 * Options: disable_polarity_correction = 0 (default) Automatic
2763 	 * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled
2764 	 */
2765 	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2766 	if (hw->disable_polarity_correction == 1)
2767 		phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
2768 
2769 	/* Enable downshift on BM (disabled by default) */
2770 	if (hw->phy_type == em_phy_bm)
2771 		phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
2772 
2773 	ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2774 	if (ret_val)
2775 		return ret_val;
2776 
2777 	if (((hw->phy_type == em_phy_m88) &&
2778 	    (hw->phy_revision < M88E1011_I_REV_4) &&
2779 	    (hw->phy_id != BME1000_E_PHY_ID)) ||
2780 	    (hw->phy_type == em_phy_oem)) {
2781 		/*
2782 		 * Force TX_CLK in the Extended PHY Specific Control Register
2783 		 * to 25MHz clock.
2784 		 */
2785 		ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
2786 		    &phy_data);
2787 		if (ret_val)
2788 			return ret_val;
2789 
2790 		if (hw->phy_type == em_phy_oem) {
2791 			phy_data |= M88E1000_EPSCR_TX_TIME_CTRL;
2792 			phy_data |= M88E1000_EPSCR_RX_TIME_CTRL;
2793 		}
2794 		phy_data |= M88E1000_EPSCR_TX_CLK_25;
2795 
2796 		if ((hw->phy_revision == E1000_REVISION_2) &&
2797 		    (hw->phy_id == M88E1111_I_PHY_ID)) {
2798 			/* Vidalia Phy, set the downshift counter to 5x */
2799 			phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2800 			phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2801 			ret_val = em_write_phy_reg(hw,
2802 			    M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2803 			if (ret_val)
2804 				return ret_val;
2805 		} else {
2806 			/* Configure Master and Slave downshift values */
2807 			phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
2808 			    M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2809 			phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
2810 			    M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2811 			ret_val = em_write_phy_reg(hw,
2812 			    M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2813 			if (ret_val)
2814 				return ret_val;
2815 		}
2816 	}
2817 	if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) {
2818 		/*
2819 	    	 * Set PHY page 0, register 29 to 0x0003
2820 	         * The next two writes are supposed to lower BER for gig
2821 	         * connection
2822 		 */
2823 		ret_val = em_write_phy_reg(hw, BM_REG_BIAS1, 0x0003);
2824 		if (ret_val)
2825 			return ret_val;
2826 
2827 		/* Set PHY page 0, register 30 to 0x0000 */
2828 		ret_val = em_write_phy_reg(hw, BM_REG_BIAS2, 0x0000);
2829 		if (ret_val)
2830 			return ret_val;
2831 	}
2832 	if (hw->phy_type == em_phy_82578) {
2833 		ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
2834 		    &phy_data);
2835 		if (ret_val)
2836 			return ret_val;
2837 
2838 		/* 82578 PHY - set the downshift count to 1x. */
2839 		phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
2840 		phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
2841 		ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
2842 		    phy_data);
2843 		if (ret_val)
2844 			return ret_val;
2845 	}
2846 	/* SW Reset the PHY so all changes take effect */
2847 	ret_val = em_phy_reset(hw);
2848 	if (ret_val) {
2849 		DEBUGOUT("Error Resetting the PHY\n");
2850 		return ret_val;
2851 	}
2852 	return E1000_SUCCESS;
2853 }
2854 
2855 /******************************************************************************
2856  * Copper link setup for em_phy_82577 series.
2857  *
2858  * hw - Struct containing variables accessed by shared code
2859  *****************************************************************************/
2860 static int32_t
em_copper_link_82577_setup(struct em_hw * hw)2861 em_copper_link_82577_setup(struct em_hw *hw)
2862 {
2863 	int32_t  ret_val;
2864 	uint16_t phy_data;
2865 	uint32_t led_ctl;
2866 	DEBUGFUNC("em_copper_link_82577_setup");
2867 
2868 	if (hw->phy_reset_disable)
2869 		return E1000_SUCCESS;
2870 
2871 	/* Enable CRS on TX for half-duplex operation. */
2872 	ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data);
2873 	if (ret_val)
2874 		return ret_val;
2875 
2876 	phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX |
2877 	    I82577_PHY_CFG_ENABLE_DOWNSHIFT;
2878 
2879 	ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data);
2880 	if (ret_val)
2881 		return ret_val;
2882 
2883 	/* Wait 15ms for MAC to configure PHY from eeprom settings */
2884 	msec_delay(15);
2885 	led_ctl = hw->ledctl_mode1;
2886 
2887 	/* disable lplu d0 during driver init */
2888 	ret_val = em_set_lplu_state_pchlan(hw, FALSE);
2889 	if (ret_val) {
2890 		DEBUGOUT("Error Disabling LPLU D0\n");
2891 		return ret_val;
2892 	}
2893 
2894 	E1000_WRITE_REG(hw, LEDCTL, led_ctl);
2895 
2896 	return E1000_SUCCESS;
2897 }
2898 
2899 static int32_t
em_copper_link_82580_setup(struct em_hw * hw)2900 em_copper_link_82580_setup(struct em_hw *hw)
2901 {
2902 	int32_t ret_val;
2903 	uint16_t phy_data;
2904 
2905 	if (hw->phy_reset_disable)
2906 		return E1000_SUCCESS;
2907 
2908 	ret_val = em_phy_reset(hw);
2909 	if (ret_val)
2910 		goto out;
2911 
2912 	/* Enable CRS on TX. This must be set for half-duplex operation. */
2913 	ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data);
2914 	if (ret_val)
2915 		goto out;
2916 
2917 	phy_data |= I82580_CFG_ASSERT_CRS_ON_TX |
2918 	    I82580_CFG_ENABLE_DOWNSHIFT;
2919 
2920 	ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data);
2921 
2922 out:
2923 	return ret_val;
2924 }
2925 
2926 static int32_t
em_copper_link_rtl8211_setup(struct em_hw * hw)2927 em_copper_link_rtl8211_setup(struct em_hw *hw)
2928 {
2929 	int32_t ret_val;
2930 	uint16_t phy_data;
2931 
2932 	DEBUGFUNC("em_copper_link_rtl8211_setup: begin");
2933 
2934 	if (!hw) {
2935 		return -1;
2936 	}
2937 	/* SW Reset the PHY so all changes take effect */
2938 	em_phy_hw_reset(hw);
2939 
2940 	/* Enable CRS on TX. This must be set for half-duplex operation. */
2941 	phy_data = 0;
2942 
2943 	ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data);
2944 	if (ret_val) {
2945 		printf("Unable to read RGEPHY_CR register\n");
2946 		return ret_val;
2947 	}
2948 	DEBUGOUT3("RTL8211: Rx phy_id=%X addr=%X SPEC_CTRL=%X\n", hw->phy_id,
2949 	    hw->phy_addr, phy_data);
2950 	phy_data |= RGEPHY_CR_ASSERT_CRS;
2951 
2952 	ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data);
2953 	if (ret_val) {
2954 		printf("Unable to write RGEPHY_CR register\n");
2955 		return ret_val;
2956 	}
2957 
2958 	phy_data = 0; /* LED Control Register 0x18 */
2959 	ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC, &phy_data);
2960 	if (ret_val) {
2961 		printf("Unable to read RGEPHY_LC register\n");
2962 		return ret_val;
2963 	}
2964 
2965 	phy_data &= 0x80FF; /* bit-15=0 disable, clear bit 8-10 */
2966 	ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data);
2967 	if (ret_val) {
2968 		printf("Unable to write RGEPHY_LC register\n");
2969 		return ret_val;
2970 	}
2971 	/* LED Control and Definition Register 0x11, PHY spec status reg */
2972 	phy_data = 0;
2973 	ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data);
2974 	if (ret_val) {
2975 		printf("Unable to read RGEPHY_SR register\n");
2976 		return ret_val;
2977 	}
2978 
2979 	phy_data |= 0x0010; /* LED active Low */
2980 	ret_val = em_write_phy_reg_ex(hw, RGEPHY_SR, phy_data);
2981 	if (ret_val) {
2982 		printf("Unable to write RGEPHY_SR register\n");
2983 		return ret_val;
2984 	}
2985 
2986 	phy_data = 0;
2987 	ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data);
2988 	if (ret_val) {
2989 		printf("Unable to read RGEPHY_SR register\n");
2990 		return ret_val;
2991 	}
2992 
2993 	/* Switch to Page2 */
2994 	phy_data = RGEPHY_PS_PAGE_2;
2995 	ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data);
2996 	if (ret_val) {
2997 		printf("Unable to write PHY RGEPHY_PS register\n");
2998 		return ret_val;
2999 	}
3000 
3001 	phy_data = 0x0000;
3002 	ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data);
3003 	if (ret_val) {
3004 		printf("Unable to write RGEPHY_LC_P2 register\n");
3005 		return ret_val;
3006 	}
3007 	usec_delay(5);
3008 
3009 
3010 	/* LED Configuration Control Reg for setting for 0x1A Register */
3011 	phy_data = 0;
3012 	ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data);
3013 	if (ret_val) {
3014 		printf("Unable to read RGEPHY_LC_P2 register\n");
3015 		return ret_val;
3016 	}
3017 
3018 	phy_data &= 0xF000;
3019 	phy_data |= 0x0F24;
3020 	ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data);
3021 	if (ret_val) {
3022 		printf("Unable to write RGEPHY_LC_P2 register\n");
3023 		return ret_val;
3024 	}
3025 	phy_data = 0;
3026 	ret_val= em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data);
3027 	if (ret_val) {
3028 		printf("Unable to read RGEPHY_LC_P2 register\n");
3029 		return ret_val;
3030 	}
3031 	DEBUGOUT1("RTL8211:ReadBack for check, LED_CFG->data=%X\n", phy_data);
3032 
3033 
3034 	/* After setting Page2, go back to Page 0 */
3035 	phy_data = 0;
3036 	ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data);
3037 	if (ret_val) {
3038 		printf("Unable to write PHY RGEPHY_PS register\n");
3039 		return ret_val;
3040 	}
3041 
3042 	/* pulse stretching= 42-84ms, blink rate=84mm */
3043 	phy_data = 0x140 | RGEPHY_LC_PULSE_42MS | RGEPHY_LC_LINK |
3044 	    RGEPHY_LC_DUPLEX | RGEPHY_LC_RX;
3045 
3046 	ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data);
3047 	if (ret_val) {
3048 		printf("Unable to write RGEPHY_LC register\n");
3049 		return ret_val;
3050 	}
3051 	return E1000_SUCCESS;
3052 }
3053 
3054 /******************************************************************************
3055  * Setup auto-negotiation and flow control advertisements,
3056  * and then perform auto-negotiation.
3057  *
3058  * hw - Struct containing variables accessed by shared code
3059  *****************************************************************************/
3060 int32_t
em_copper_link_autoneg(struct em_hw * hw)3061 em_copper_link_autoneg(struct em_hw *hw)
3062 {
3063 	int32_t  ret_val;
3064 	uint16_t phy_data;
3065 	DEBUGFUNC("em_copper_link_autoneg");
3066 	/*
3067 	 * Perform some bounds checking on the hw->autoneg_advertised
3068 	 * parameter.  If this variable is zero, then set it to the default.
3069 	 */
3070 	hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
3071 	/*
3072 	 * If autoneg_advertised is zero, we assume it was not defaulted by
3073 	 * the calling code so we set to advertise full capability.
3074 	 */
3075 	if (hw->autoneg_advertised == 0)
3076 		hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
3077 
3078 	/* IFE phy only supports 10/100 */
3079 	if (hw->phy_type == em_phy_ife)
3080 		hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
3081 
3082 	DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
3083 	ret_val = em_phy_setup_autoneg(hw);
3084 	if (ret_val) {
3085 		DEBUGOUT("Error Setting up Auto-Negotiation\n");
3086 		return ret_val;
3087 	}
3088 	DEBUGOUT("Restarting Auto-Neg\n");
3089 	/*
3090 	 * Restart auto-negotiation by setting the Auto Neg Enable bit and
3091 	 * the Auto Neg Restart bit in the PHY control register.
3092 	 */
3093 	ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
3094 	if (ret_val)
3095 		return ret_val;
3096 
3097 	phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
3098 	ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
3099 	if (ret_val)
3100 		return ret_val;
3101 	/*
3102 	 * Does the user want to wait for Auto-Neg to complete here, or check
3103 	 * at a later time (for example, callback routine).
3104 	 */
3105 	if (hw->wait_autoneg_complete) {
3106 		ret_val = em_wait_autoneg(hw);
3107 		if (ret_val) {
3108 			DEBUGOUT("Error while waiting for autoneg to complete\n"
3109 			    );
3110 			return ret_val;
3111 		}
3112 	}
3113 	hw->get_link_status = TRUE;
3114 
3115 	return E1000_SUCCESS;
3116 }
3117 
3118 /******************************************************************************
3119  * Config the MAC and the PHY after link is up.
3120  *   1) Set up the MAC to the current PHY speed/duplex
3121  *      if we are on 82543.  If we
3122  *      are on newer silicon, we only need to configure
3123  *      collision distance in the Transmit Control Register.
3124  *   2) Set up flow control on the MAC to that established with
3125  *      the link partner.
3126  *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
3127  *
3128  * hw - Struct containing variables accessed by shared code
3129  *****************************************************************************/
3130 int32_t
em_copper_link_postconfig(struct em_hw * hw)3131 em_copper_link_postconfig(struct em_hw *hw)
3132 {
3133 	int32_t ret_val;
3134 	DEBUGFUNC("em_copper_link_postconfig");
3135 
3136 	if (hw->mac_type >= em_82544 &&
3137 	    hw->mac_type != em_icp_xxxx) {
3138 		em_config_collision_dist(hw);
3139 	} else {
3140 		ret_val = em_config_mac_to_phy(hw);
3141 		if (ret_val) {
3142 			DEBUGOUT("Error configuring MAC to PHY settings\n");
3143 			return ret_val;
3144 		}
3145 	}
3146 	ret_val = em_config_fc_after_link_up(hw);
3147 	if (ret_val) {
3148 		DEBUGOUT("Error Configuring Flow Control\n");
3149 		return ret_val;
3150 	}
3151 	/* Config DSP to improve Giga link quality */
3152 	if (hw->phy_type == em_phy_igp) {
3153 		ret_val = em_config_dsp_after_link_change(hw, TRUE);
3154 		if (ret_val) {
3155 			DEBUGOUT("Error Configuring DSP after link up\n");
3156 			return ret_val;
3157 		}
3158 	}
3159 	return E1000_SUCCESS;
3160 }
3161 
3162 /******************************************************************************
3163  * Detects which PHY is present and setup the speed and duplex
3164  *
3165  * hw - Struct containing variables accessed by shared code
3166  *****************************************************************************/
3167 static int32_t
em_setup_copper_link(struct em_hw * hw)3168 em_setup_copper_link(struct em_hw *hw)
3169 {
3170 	int32_t         ret_val;
3171 	uint16_t        i;
3172 	uint16_t        phy_data;
3173 	uint16_t        reg_data;
3174 	DEBUGFUNC("em_setup_copper_link");
3175 
3176 	switch (hw->mac_type) {
3177 	case em_80003es2lan:
3178 	case em_ich8lan:
3179 	case em_ich9lan:
3180 	case em_ich10lan:
3181 	case em_pchlan:
3182 	case em_pch2lan:
3183 	case em_pch_lpt:
3184 	case em_pch_spt:
3185 	case em_pch_cnp:
3186 	case em_pch_tgp:
3187 	case em_pch_adp:
3188 		/*
3189 		 * Set the mac to wait the maximum time between each
3190 		 * iteration and increase the max iterations when polling the
3191 		 * phy; this fixes erroneous timeouts at 10Mbps.
3192 		 */
3193 		ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
3194 		if (ret_val)
3195 			return ret_val;
3196 		ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9),
3197 		    &reg_data);
3198 		if (ret_val)
3199 			return ret_val;
3200 		reg_data |= 0x3F;
3201 		ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9),
3202 		    reg_data);
3203 		if (ret_val)
3204 			return ret_val;
3205 	default:
3206 		break;
3207 	}
3208 
3209 	/* Check if it is a valid PHY and set PHY mode if necessary. */
3210 	ret_val = em_copper_link_preconfig(hw);
3211 	if (ret_val)
3212 		return ret_val;
3213 
3214 	switch (hw->mac_type) {
3215 	case em_80003es2lan:
3216 		/* Kumeran registers are written-only */
3217 		reg_data =
3218 		    E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3219 		reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3220 		ret_val = em_write_kmrn_reg(hw,
3221 		    E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3222 		if (ret_val)
3223 			return ret_val;
3224 		break;
3225 	default:
3226 		break;
3227 	}
3228 
3229 	if (hw->phy_type == em_phy_igp ||
3230 	    hw->phy_type == em_phy_igp_3 ||
3231 	    hw->phy_type == em_phy_igp_2) {
3232 		ret_val = em_copper_link_igp_setup(hw);
3233 		if (ret_val)
3234 			return ret_val;
3235 	} else if (hw->phy_type == em_phy_m88 ||
3236 	    hw->phy_type == em_phy_bm ||
3237 	    hw->phy_type == em_phy_oem ||
3238 	    hw->phy_type == em_phy_82578) {
3239 		ret_val = em_copper_link_mgp_setup(hw);
3240 		if (ret_val)
3241 			return ret_val;
3242 	} else if (hw->phy_type == em_phy_gg82563) {
3243 		ret_val = em_copper_link_ggp_setup(hw);
3244 		if (ret_val)
3245 			return ret_val;
3246 	} else if (hw->phy_type == em_phy_82577 ||
3247 		hw->phy_type == em_phy_82579 ||
3248 		hw->phy_type == em_phy_i217) {
3249 		ret_val = em_copper_link_82577_setup(hw);
3250 		if (ret_val)
3251 			return ret_val;
3252 	} else if (hw->phy_type == em_phy_82580) {
3253 		ret_val = em_copper_link_82580_setup(hw);
3254 		if (ret_val)
3255 			return ret_val;
3256 	} else if (hw->phy_type == em_phy_rtl8211) {
3257 		ret_val = em_copper_link_rtl8211_setup(hw);
3258 		if (ret_val)
3259 			return ret_val;
3260 	}
3261 	if (hw->autoneg) {
3262 		/*
3263 		 * Setup autoneg and flow control advertisement and perform
3264 		 * autonegotiation
3265 		 */
3266 		ret_val = em_copper_link_autoneg(hw);
3267 		if (ret_val)
3268 			return ret_val;
3269 	} else {
3270 		/*
3271 		 * PHY will be set to 10H, 10F, 100H,or 100F depending on
3272 		 * value from forced_speed_duplex.
3273 		 */
3274 		DEBUGOUT("Forcing speed and duplex\n");
3275 		ret_val = em_phy_force_speed_duplex(hw);
3276 		if (ret_val) {
3277 			DEBUGOUT("Error Forcing Speed and Duplex\n");
3278 			return ret_val;
3279 		}
3280 	}
3281 	/*
3282 	 * Check link status. Wait up to 100 microseconds for link to become
3283 	 * valid.
3284 	 */
3285 	for (i = 0; i < 10; i++) {
3286 		ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3287 		if (ret_val)
3288 			return ret_val;
3289 		ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3290 		if (ret_val)
3291 			return ret_val;
3292 
3293 		hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0;
3294 
3295 		if (phy_data & MII_SR_LINK_STATUS) {
3296 			/* Config the MAC and PHY after link is up */
3297 			ret_val = em_copper_link_postconfig(hw);
3298 			if (ret_val)
3299 				return ret_val;
3300 
3301 			DEBUGOUT("Valid link established!!!\n");
3302 			return E1000_SUCCESS;
3303 		}
3304 		usec_delay(10);
3305 	}
3306 
3307 	DEBUGOUT("Unable to establish link!!!\n");
3308 	return E1000_SUCCESS;
3309 }
3310 
3311 /******************************************************************************
3312  * Configure the MAC-to-PHY interface for 10/100Mbps
3313  *
3314  * hw - Struct containing variables accessed by shared code
3315  *****************************************************************************/
3316 static int32_t
em_configure_kmrn_for_10_100(struct em_hw * hw,uint16_t duplex)3317 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex)
3318 {
3319 	int32_t  ret_val = E1000_SUCCESS;
3320 	uint32_t tipg;
3321 	uint16_t reg_data;
3322 	DEBUGFUNC("em_configure_kmrn_for_10_100");
3323 
3324 	reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3325 	ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
3326 	    reg_data);
3327 	if (ret_val)
3328 		return ret_val;
3329 
3330 	/* Configure Transmit Inter-Packet Gap */
3331 	tipg = E1000_READ_REG(hw, TIPG);
3332 	tipg &= ~E1000_TIPG_IPGT_MASK;
3333 	tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3334 	E1000_WRITE_REG(hw, TIPG, tipg);
3335 
3336 	ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3337 
3338 	if (ret_val)
3339 		return ret_val;
3340 
3341 	if (duplex == HALF_DUPLEX)
3342 		reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3343 	else
3344 		reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3345 
3346 	ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3347 
3348 	return ret_val;
3349 }
3350 
3351 static int32_t
em_configure_kmrn_for_1000(struct em_hw * hw)3352 em_configure_kmrn_for_1000(struct em_hw *hw)
3353 {
3354 	int32_t  ret_val = E1000_SUCCESS;
3355 	uint16_t reg_data;
3356 	uint32_t tipg;
3357 	DEBUGFUNC("em_configure_kmrn_for_1000");
3358 
3359 	reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3360 	ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
3361 	    reg_data);
3362 	if (ret_val)
3363 		return ret_val;
3364 
3365 	/* Configure Transmit Inter-Packet Gap */
3366 	tipg = E1000_READ_REG(hw, TIPG);
3367 	tipg &= ~E1000_TIPG_IPGT_MASK;
3368 	tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3369 	E1000_WRITE_REG(hw, TIPG, tipg);
3370 
3371 	ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3372 
3373 	if (ret_val)
3374 		return ret_val;
3375 
3376 	reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3377 	ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3378 
3379 	return ret_val;
3380 }
3381 
3382 /******************************************************************************
3383  * Configures PHY autoneg and flow control advertisement settings
3384  *
3385  * hw - Struct containing variables accessed by shared code
3386  *****************************************************************************/
3387 int32_t
em_phy_setup_autoneg(struct em_hw * hw)3388 em_phy_setup_autoneg(struct em_hw *hw)
3389 {
3390 	int32_t  ret_val;
3391 	uint16_t mii_autoneg_adv_reg;
3392 	uint16_t mii_1000t_ctrl_reg;
3393 	DEBUGFUNC("em_phy_setup_autoneg");
3394 
3395 	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
3396 	ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3397 	if (ret_val)
3398 		return ret_val;
3399 
3400 	if (hw->phy_type != em_phy_ife) {
3401 		/* Read the MII 1000Base-T Control Register (Address 9). */
3402 		ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
3403 		    &mii_1000t_ctrl_reg);
3404 		if (ret_val)
3405 			return ret_val;
3406 	} else
3407 		mii_1000t_ctrl_reg = 0;
3408 	/*
3409 	 * Need to parse both autoneg_advertised and fc and set up the
3410 	 * appropriate PHY registers.  First we will parse for
3411 	 * autoneg_advertised software override.  Since we can advertise a
3412 	 * plethora of combinations, we need to check each bit individually.
3413 	 */
3414 	/*
3415 	 * First we clear all the 10/100 mb speed bits in the Auto-Neg
3416 	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
3417 	 * the  1000Base-T Control Register (Address 9).
3418 	 */
3419 	mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3420 	mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3421 
3422 	DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
3423 
3424 	/* Do we want to advertise 10 Mb Half Duplex? */
3425 	if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3426 		DEBUGOUT("Advertise 10mb Half duplex\n");
3427 		mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3428 	}
3429 	/* Do we want to advertise 10 Mb Full Duplex? */
3430 	if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3431 		DEBUGOUT("Advertise 10mb Full duplex\n");
3432 		mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3433 	}
3434 	/* Do we want to advertise 100 Mb Half Duplex? */
3435 	if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3436 		DEBUGOUT("Advertise 100mb Half duplex\n");
3437 		mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3438 	}
3439 	/* Do we want to advertise 100 Mb Full Duplex? */
3440 	if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3441 		DEBUGOUT("Advertise 100mb Full duplex\n");
3442 		mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3443 	}
3444 	/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3445 	if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3446 		DEBUGOUT("Advertise 1000mb Half duplex requested, request"
3447 		    " denied!\n");
3448 	}
3449 	/* Do we want to advertise 1000 Mb Full Duplex? */
3450 	if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3451 		DEBUGOUT("Advertise 1000mb Full duplex\n");
3452 		mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3453 		if (hw->phy_type == em_phy_ife) {
3454 			DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is"
3455 			    " not supported.\n");
3456 		}
3457 	}
3458 	/*
3459 	 * Check for a software override of the flow control settings, and
3460 	 * setup the PHY advertisement registers accordingly.  If
3461 	 * auto-negotiation is enabled, then software will have to set the
3462 	 * "PAUSE" bits to the correct value in the Auto-Negotiation
3463 	 * Advertisement Register (PHY_AUTONEG_ADV) and re-start
3464 	 * auto-negotiation.
3465 	 *
3466 	 * The possible values of the "fc" parameter are: 0:  Flow control is
3467 	 * completely disabled 1:  Rx flow control is enabled (we can receive
3468 	 * pause frames but not send pause frames). 2:  Tx flow control is
3469 	 * enabled (we can send pause frames but we do not support receiving
3470 	 * pause frames). 3:  Both Rx and TX flow control (symmetric) are
3471 	 * enabled. other:  No software override.  The flow control
3472 	 * configuration in the EEPROM is used.
3473 	 */
3474 	switch (hw->fc) {
3475 	case E1000_FC_NONE:	/* 0 */
3476 		/*
3477 		 * Flow control (RX & TX) is completely disabled by a
3478 		 * software over-ride.
3479 		 */
3480 		mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3481 		break;
3482 	case E1000_FC_RX_PAUSE:/* 1 */
3483 		/*
3484 		 * RX Flow control is enabled, and TX Flow control is
3485 		 * disabled, by a software over-ride.
3486 		 */
3487 		/*
3488 		 * Since there really isn't a way to advertise that we are
3489 		 * capable of RX Pause ONLY, we will advertise that we
3490 		 * support both symmetric and asymmetric RX PAUSE.  Later (in
3491 		 * em_config_fc_after_link_up) we will disable the hw's
3492 		 * ability to send PAUSE frames.
3493 		 */
3494 		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3495 		break;
3496 	case E1000_FC_TX_PAUSE:/* 2 */
3497 		/*
3498 		 * TX Flow control is enabled, and RX Flow control is
3499 		 * disabled, by a software over-ride.
3500 		 */
3501 		mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3502 		mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3503 		break;
3504 	case E1000_FC_FULL:	/* 3 */
3505 		/*
3506 		 * Flow control (both RX and TX) is enabled by a software
3507 		 * over-ride.
3508 		 */
3509 		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3510 		break;
3511 	default:
3512 		DEBUGOUT("Flow control param set incorrectly\n");
3513 		return -E1000_ERR_CONFIG;
3514 	}
3515 
3516 	ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3517 	if (ret_val)
3518 		return ret_val;
3519 
3520 	DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3521 
3522 	if (hw->phy_type != em_phy_ife) {
3523 		ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
3524 		    mii_1000t_ctrl_reg);
3525 		if (ret_val)
3526 			return ret_val;
3527 	}
3528 	return E1000_SUCCESS;
3529 }
3530 /******************************************************************************
3531  * Force PHY speed and duplex settings to hw->forced_speed_duplex
3532  *
3533  * hw - Struct containing variables accessed by shared code
3534  *****************************************************************************/
3535 static int32_t
em_phy_force_speed_duplex(struct em_hw * hw)3536 em_phy_force_speed_duplex(struct em_hw *hw)
3537 {
3538 	uint32_t ctrl;
3539 	int32_t  ret_val;
3540 	uint16_t mii_ctrl_reg;
3541 	uint16_t mii_status_reg;
3542 	uint16_t phy_data;
3543 	uint16_t i;
3544 	DEBUGFUNC("em_phy_force_speed_duplex");
3545 
3546 	/* Turn off Flow control if we are forcing speed and duplex. */
3547 	hw->fc = E1000_FC_NONE;
3548 
3549 	DEBUGOUT1("hw->fc = %d\n", hw->fc);
3550 
3551 	/* Read the Device Control Register. */
3552 	ctrl = E1000_READ_REG(hw, CTRL);
3553 
3554 	/* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
3555 	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3556 	ctrl &= ~(DEVICE_SPEED_MASK);
3557 
3558 	/* Clear the Auto Speed Detect Enable bit. */
3559 	ctrl &= ~E1000_CTRL_ASDE;
3560 
3561 	/* Read the MII Control Register. */
3562 	ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
3563 	if (ret_val)
3564 		return ret_val;
3565 
3566 	/* We need to disable autoneg in order to force link and duplex. */
3567 
3568 	mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
3569 
3570 	/* Are we forcing Full or Half Duplex? */
3571 	if (hw->forced_speed_duplex == em_100_full ||
3572 	    hw->forced_speed_duplex == em_10_full) {
3573 		/*
3574 		 * We want to force full duplex so we SET the full duplex
3575 		 * bits in the Device and MII Control Registers.
3576 		 */
3577 		ctrl |= E1000_CTRL_FD;
3578 		mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
3579 		DEBUGOUT("Full Duplex\n");
3580 	} else {
3581 		/*
3582 		 * We want to force half duplex so we CLEAR the full duplex
3583 		 * bits in the Device and MII Control Registers.
3584 		 */
3585 		ctrl &= ~E1000_CTRL_FD;
3586 		mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
3587 		DEBUGOUT("Half Duplex\n");
3588 	}
3589 
3590 	/* Are we forcing 100Mbps??? */
3591 	if (hw->forced_speed_duplex == em_100_full ||
3592 	    hw->forced_speed_duplex == em_100_half) {
3593 		/* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
3594 		ctrl |= E1000_CTRL_SPD_100;
3595 		mii_ctrl_reg |= MII_CR_SPEED_100;
3596 		mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
3597 		DEBUGOUT("Forcing 100mb ");
3598 	} else {
3599 		/* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
3600 		ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
3601 		mii_ctrl_reg |= MII_CR_SPEED_10;
3602 		mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
3603 		DEBUGOUT("Forcing 10mb ");
3604 	}
3605 
3606 	em_config_collision_dist(hw);
3607 
3608 	/* Write the configured values back to the Device Control Reg. */
3609 	E1000_WRITE_REG(hw, CTRL, ctrl);
3610 
3611 	if ((hw->phy_type == em_phy_m88) ||
3612 	    (hw->phy_type == em_phy_gg82563) ||
3613 	    (hw->phy_type == em_phy_bm) ||
3614 	    (hw->phy_type == em_phy_oem ||
3615 	    (hw->phy_type == em_phy_82578))) {
3616 		ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
3617 		    &phy_data);
3618 		if (ret_val)
3619 			return ret_val;
3620 		/*
3621 		 * Clear Auto-Crossover to force MDI manually. M88E1000
3622 		 * requires MDI forced whenever speed are duplex are forced.
3623 		 */
3624 		phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
3625 		ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
3626 		    phy_data);
3627 		if (ret_val)
3628 			return ret_val;
3629 
3630 		DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
3631 
3632 		/* Need to reset the PHY or these changes will be ignored */
3633 		mii_ctrl_reg |= MII_CR_RESET;
3634 
3635 	}
3636 	else if (hw->phy_type == em_phy_rtl8211) {
3637 		ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data);
3638 		if(ret_val) {
3639 			printf("Unable to read RGEPHY_CR register\n"
3640 			    );
3641 			return ret_val;
3642 		}
3643 
3644 		/*
3645 		 * Clear Auto-Crossover to force MDI manually. RTL8211 requires
3646 		 * MDI forced whenever speed are duplex are forced.
3647 		 */
3648 
3649 		phy_data |= RGEPHY_CR_MDI_MASK;  // enable MDIX
3650 		ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data);
3651 		if(ret_val) {
3652 			printf("Unable to write RGEPHY_CR register\n");
3653 			return ret_val;
3654 		}
3655 		mii_ctrl_reg |= MII_CR_RESET;
3656 
3657 	}
3658 	/* Disable MDI-X support for 10/100 */
3659 	else if (hw->phy_type == em_phy_ife) {
3660 		ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
3661 		if (ret_val)
3662 			return ret_val;
3663 
3664 		phy_data &= ~IFE_PMC_AUTO_MDIX;
3665 		phy_data &= ~IFE_PMC_FORCE_MDIX;
3666 
3667 		ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
3668 		if (ret_val)
3669 			return ret_val;
3670 	} else {
3671 		/*
3672 		 * Clear Auto-Crossover to force MDI manually.  IGP requires
3673 		 * MDI forced whenever speed or duplex are forced.
3674 		 */
3675 		ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
3676 		    &phy_data);
3677 		if (ret_val)
3678 			return ret_val;
3679 
3680 		phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
3681 		phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
3682 
3683 		ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
3684 		    phy_data);
3685 		if (ret_val)
3686 			return ret_val;
3687 	}
3688 
3689 	/* Write back the modified PHY MII control register. */
3690 	ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
3691 	if (ret_val)
3692 		return ret_val;
3693 
3694 	usec_delay(1);
3695 	/*
3696 	 * The wait_autoneg_complete flag may be a little misleading here.
3697 	 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
3698 	 * But we do want to delay for a period while forcing only so we
3699 	 * don't generate false No Link messages.  So we will wait here only
3700 	 * if the user has set wait_autoneg_complete to 1, which is the
3701 	 * default.
3702 	 */
3703 	if (hw->wait_autoneg_complete) {
3704 		/* We will wait for autoneg to complete. */
3705 		DEBUGOUT("Waiting for forced speed/duplex link.\n");
3706 		mii_status_reg = 0;
3707 		/*
3708 		 * We will wait for autoneg to complete or 4.5 seconds to
3709 		 * expire.
3710 		 */
3711 		for (i = PHY_FORCE_TIME; i > 0; i--) {
3712 			/*
3713 			 * Read the MII Status Register and wait for Auto-Neg
3714 			 * Complete bit to be set.
3715 			 */
3716 			ret_val = em_read_phy_reg(hw, PHY_STATUS,
3717 			    &mii_status_reg);
3718 			if (ret_val)
3719 				return ret_val;
3720 
3721 			ret_val = em_read_phy_reg(hw, PHY_STATUS,
3722 			    &mii_status_reg);
3723 			if (ret_val)
3724 				return ret_val;
3725 
3726 			if (mii_status_reg & MII_SR_LINK_STATUS)
3727 				break;
3728 			msec_delay(100);
3729 		}
3730 		if ((i == 0) &&
3731 		    ((hw->phy_type == em_phy_m88) ||
3732 		    (hw->phy_type == em_phy_gg82563) ||
3733 		    (hw->phy_type == em_phy_bm))) {
3734 			/*
3735 			 * We didn't get link.  Reset the DSP and wait again
3736 			 * for link.
3737 			 */
3738 			ret_val = em_phy_reset_dsp(hw);
3739 			if (ret_val) {
3740 				DEBUGOUT("Error Resetting PHY DSP\n");
3741 				return ret_val;
3742 			}
3743 		}
3744 		/*
3745 		 * This loop will early-out if the link condition has been
3746 		 * met.
3747 		 */
3748 		for (i = PHY_FORCE_TIME; i > 0; i--) {
3749 			if (mii_status_reg & MII_SR_LINK_STATUS)
3750 				break;
3751 			msec_delay(100);
3752 			/*
3753 			 * Read the MII Status Register and wait for Auto-Neg
3754 			 * Complete bit to be set.
3755 			 */
3756 			ret_val = em_read_phy_reg(hw, PHY_STATUS,
3757 			    &mii_status_reg);
3758 			if (ret_val)
3759 				return ret_val;
3760 
3761 			ret_val = em_read_phy_reg(hw, PHY_STATUS,
3762 			    &mii_status_reg);
3763 			if (ret_val)
3764 				return ret_val;
3765 		}
3766 	}
3767 	if (hw->phy_type == em_phy_m88 ||
3768 	    hw->phy_type == em_phy_bm ||
3769 	    hw->phy_type == em_phy_oem) {
3770 		/*
3771 		 * Because we reset the PHY above, we need to re-force TX_CLK
3772 		 * in the Extended PHY Specific Control Register to 25MHz
3773 		 * clock.  This value defaults back to a 2.5MHz clock when
3774 		 * the PHY is reset.
3775 		 */
3776 		ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
3777 		    &phy_data);
3778 		if (ret_val)
3779 			return ret_val;
3780 
3781 		phy_data |= M88E1000_EPSCR_TX_CLK_25;
3782 		ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
3783 		    phy_data);
3784 		if (ret_val)
3785 			return ret_val;
3786 		/*
3787 		 * In addition, because of the s/w reset above, we need to
3788 		 * enable CRS on TX.  This must be set for both full and half
3789 		 * duplex operation.
3790 		 */
3791 		ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
3792 		    &phy_data);
3793 		if (ret_val)
3794 			return ret_val;
3795 
3796 		if (hw->phy_id == M88E1141_E_PHY_ID)
3797 			phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX;
3798 		else
3799 			phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
3800 
3801 		ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
3802 		    phy_data);
3803 		if (ret_val)
3804 			return ret_val;
3805 
3806 		if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) &&
3807 		    (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full ||
3808 		    hw->forced_speed_duplex == em_10_half)) {
3809 			ret_val = em_polarity_reversal_workaround(hw);
3810 			if (ret_val)
3811 				return ret_val;
3812 		}
3813 	} else if (hw->phy_type == em_phy_rtl8211) {
3814 		/*
3815 		* In addition, because of the s/w reset above, we need to enable
3816 		* CRX on TX.  This must be set for both full and half duplex
3817 		* operation.
3818 		*/
3819 
3820 		ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data);
3821 		if(ret_val) {
3822 			printf("Unable to read RGEPHY_CR register\n");
3823 			return ret_val;
3824 		}
3825 
3826 		phy_data &= ~RGEPHY_CR_ASSERT_CRS;
3827 		ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data);
3828 		if(ret_val) {
3829 			printf("Unable to write RGEPHY_CR register\n");
3830 			return ret_val;
3831 		}
3832 	} else if (hw->phy_type == em_phy_gg82563) {
3833 		/*
3834 		 * The TX_CLK of the Extended PHY Specific Control Register
3835 		 * defaults to 2.5MHz on a reset.  We need to re-force it
3836 		 * back to 25MHz, if we're not in a forced 10/duplex
3837 		 * configuration.
3838 		 */
3839 		ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
3840 		    &phy_data);
3841 		if (ret_val)
3842 			return ret_val;
3843 
3844 		phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
3845 		if ((hw->forced_speed_duplex == em_10_full) ||
3846 		    (hw->forced_speed_duplex == em_10_half))
3847 			phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
3848 		else
3849 			phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
3850 
3851 		/* Also due to the reset, we need to enable CRS on Tx. */
3852 		phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
3853 
3854 		ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
3855 		    phy_data);
3856 		if (ret_val)
3857 			return ret_val;
3858 	}
3859 	return E1000_SUCCESS;
3860 }
3861 
3862 /******************************************************************************
3863  * Sets the collision distance in the Transmit Control register
3864  *
3865  * hw - Struct containing variables accessed by shared code
3866  *
3867  * Link should have been established previously. Reads the speed and duplex
3868  * information from the Device Status register.
3869  *****************************************************************************/
3870 void
em_config_collision_dist(struct em_hw * hw)3871 em_config_collision_dist(struct em_hw *hw)
3872 {
3873 	uint32_t tctl, coll_dist;
3874 	DEBUGFUNC("em_config_collision_dist");
3875 
3876 	if (hw->mac_type < em_82543)
3877 		coll_dist = E1000_COLLISION_DISTANCE_82542;
3878 	else
3879 		coll_dist = E1000_COLLISION_DISTANCE;
3880 
3881 	tctl = E1000_READ_REG(hw, TCTL);
3882 
3883 	tctl &= ~E1000_TCTL_COLD;
3884 	tctl |= coll_dist << E1000_COLD_SHIFT;
3885 
3886 	E1000_WRITE_REG(hw, TCTL, tctl);
3887 	E1000_WRITE_FLUSH(hw);
3888 }
3889 
3890 /******************************************************************************
3891  * Sets MAC speed and duplex settings to reflect the those in the PHY
3892  *
3893  * hw - Struct containing variables accessed by shared code
3894  * mii_reg - data to write to the MII control register
3895  *
3896  * The contents of the PHY register containing the needed information need to
3897  * be passed in.
3898  *****************************************************************************/
3899 static int32_t
em_config_mac_to_phy(struct em_hw * hw)3900 em_config_mac_to_phy(struct em_hw *hw)
3901 {
3902 	uint32_t ctrl;
3903 	int32_t  ret_val;
3904 	uint16_t phy_data;
3905 	DEBUGFUNC("em_config_mac_to_phy");
3906 	/*
3907 	 * 82544 or newer MAC, Auto Speed Detection takes care of MAC
3908 	 * speed/duplex configuration.
3909 	 */
3910 	if (hw->mac_type >= em_82544
3911 	    && hw->mac_type != em_icp_xxxx)
3912 		return E1000_SUCCESS;
3913 	/*
3914 	 * Read the Device Control Register and set the bits to Force Speed
3915 	 * and Duplex.
3916 	 */
3917 	ctrl = E1000_READ_REG(hw, CTRL);
3918 	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3919 	ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
3920 	/*
3921 	 * Set up duplex in the Device Control and Transmit Control registers
3922 	 * depending on negotiated values.
3923 	 */
3924 	ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3925 	if (ret_val)
3926 		return ret_val;
3927 
3928 	if (phy_data & M88E1000_PSSR_DPLX)
3929 		ctrl |= E1000_CTRL_FD;
3930 	else
3931 		ctrl &= ~E1000_CTRL_FD;
3932 
3933 	em_config_collision_dist(hw);
3934 	/*
3935 	 * Set up speed in the Device Control register depending on
3936 	 * negotiated values.
3937 	 */
3938 	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3939 		ctrl |= E1000_CTRL_SPD_1000;
3940 	else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3941 		ctrl |= E1000_CTRL_SPD_100;
3942 
3943 	/* Write the configured values back to the Device Control Reg. */
3944 	E1000_WRITE_REG(hw, CTRL, ctrl);
3945 	return E1000_SUCCESS;
3946 }
3947 
3948 /******************************************************************************
3949  * Forces the MAC's flow control settings.
3950  *
3951  * hw - Struct containing variables accessed by shared code
3952  *
3953  * Sets the TFCE and RFCE bits in the device control register to reflect
3954  * the adapter settings. TFCE and RFCE need to be explicitly set by
3955  * software when a Copper PHY is used because autonegotiation is managed
3956  * by the PHY rather than the MAC. Software must also configure these
3957  * bits when link is forced on a fiber connection.
3958  *****************************************************************************/
3959 int32_t
em_force_mac_fc(struct em_hw * hw)3960 em_force_mac_fc(struct em_hw *hw)
3961 {
3962 	uint32_t ctrl;
3963 	DEBUGFUNC("em_force_mac_fc");
3964 
3965 	/* Get the current configuration of the Device Control Register */
3966 	ctrl = E1000_READ_REG(hw, CTRL);
3967 	/*
3968 	 * Because we didn't get link via the internal auto-negotiation
3969 	 * mechanism (we either forced link or we got link via PHY auto-neg),
3970 	 * we have to manually enable/disable transmit an receive flow
3971 	 * control.
3972 	 *
3973 	 * The "Case" statement below enables/disable flow control according to
3974 	 * the "hw->fc" parameter.
3975 	 *
3976 	 * The possible values of the "fc" parameter are: 0:  Flow control is
3977 	 * completely disabled 1:  Rx flow control is enabled (we can receive
3978 	 * pause frames but not send pause frames). 2:  Tx flow control is
3979 	 * enabled (we can send pause frames but we do not receive
3980 	 * pause frames). 3:  Both Rx and TX flow control (symmetric) is
3981 	 * enabled. other:  No other values should be possible at this point.
3982 	 */
3983 
3984 	switch (hw->fc) {
3985 	case E1000_FC_NONE:
3986 		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3987 		break;
3988 	case E1000_FC_RX_PAUSE:
3989 		ctrl &= (~E1000_CTRL_TFCE);
3990 		ctrl |= E1000_CTRL_RFCE;
3991 		break;
3992 	case E1000_FC_TX_PAUSE:
3993 		ctrl &= (~E1000_CTRL_RFCE);
3994 		ctrl |= E1000_CTRL_TFCE;
3995 		break;
3996 	case E1000_FC_FULL:
3997 		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3998 		break;
3999 	default:
4000 		DEBUGOUT("Flow control param set incorrectly\n");
4001 		return -E1000_ERR_CONFIG;
4002 	}
4003 
4004 	/* Disable TX Flow Control for 82542 (rev 2.0) */
4005 	if (hw->mac_type == em_82542_rev2_0)
4006 		ctrl &= (~E1000_CTRL_TFCE);
4007 
4008 	E1000_WRITE_REG(hw, CTRL, ctrl);
4009 	return E1000_SUCCESS;
4010 }
4011 /******************************************************************************
4012  * Configures flow control settings after link is established
4013  *
4014  * hw - Struct containing variables accessed by shared code
4015  *
4016  * Should be called immediately after a valid link has been established.
4017  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
4018  * and autonegotiation is enabled, the MAC flow control settings will be set
4019  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
4020  * and RFCE bits will be automatically set to the negotiated flow control mode.
4021  *****************************************************************************/
4022 STATIC int32_t
em_config_fc_after_link_up(struct em_hw * hw)4023 em_config_fc_after_link_up(struct em_hw *hw)
4024 {
4025 	int32_t  ret_val;
4026 	uint16_t mii_status_reg;
4027 	uint16_t mii_nway_adv_reg;
4028 	uint16_t mii_nway_lp_ability_reg;
4029 	uint16_t speed;
4030 	uint16_t duplex;
4031 	DEBUGFUNC("em_config_fc_after_link_up");
4032 	/*
4033 	 * Check for the case where we have fiber media and auto-neg failed
4034 	 * so we had to force link.  In this case, we need to force the
4035 	 * configuration of the MAC to match the "fc" parameter.
4036 	 */
4037 	if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed))
4038 	    || ((hw->media_type == em_media_type_internal_serdes) &&
4039 	    (hw->autoneg_failed)) ||
4040 	    ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) ||
4041 	    ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) {
4042 		ret_val = em_force_mac_fc(hw);
4043 		if (ret_val) {
4044 			DEBUGOUT("Error forcing flow control settings\n");
4045 			return ret_val;
4046 		}
4047 	}
4048 	/*
4049 	 * Check for the case where we have copper media and auto-neg is
4050 	 * enabled.  In this case, we need to check and see if Auto-Neg has
4051 	 * completed, and if so, how the PHY and link partner has flow
4052 	 * control configured.
4053 	 */
4054 	if ((hw->media_type == em_media_type_copper ||
4055 	    (hw->media_type == em_media_type_oem)) &&
4056 	    hw->autoneg) {
4057 		/*
4058 		 * Read the MII Status Register and check to see if AutoNeg
4059 		 * has completed.  We read this twice because this reg has
4060 		 * some "sticky" (latched) bits.
4061 		 */
4062 		ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
4063 		if (ret_val)
4064 			return ret_val;
4065 		ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
4066 		if (ret_val)
4067 			return ret_val;
4068 
4069 		if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
4070 			/*
4071 			 * The AutoNeg process has completed, so we now need
4072 			 * to read both the Auto Negotiation Advertisement
4073 			 * Register (Address 4) and the Auto_Negotiation Base
4074 			 * Page Ability Register (Address 5) to determine how
4075 			 * flow control was negotiated.
4076 			 */
4077 			ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
4078 			    &mii_nway_adv_reg);
4079 			if (ret_val)
4080 				return ret_val;
4081 			ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
4082 			    &mii_nway_lp_ability_reg);
4083 			if (ret_val)
4084 				return ret_val;
4085 			/*
4086 			 * Two bits in the Auto Negotiation Advertisement
4087 			 * Register (Address 4) and two bits in the Auto
4088 			 * Negotiation Base Page Ability Register (Address 5)
4089 			 * determine flow control for both the PHY and the
4090 			 * link partner.  The following table, taken out of
4091 			 * the IEEE 802.3ab/D6.0 dated March 25, 1999,
4092 			 * describes these PAUSE resolution bits and how flow
4093 			 * control is determined based upon these settings.
4094 			 * NOTE:  DC = Don't Care
4095 			 *
4096 			 *   LOCAL DEVICE   |   LINK PARTNER  |
4097 			 *  PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
4098 			 * -------|---------|-------|---------|---------------
4099 			 *    0   |    0    |  DC   |   DC    | em_fc_none
4100  			 *    0   |    1    |   0   |   DC    | em_fc_none
4101 			 *    0   |    1    |   1   |    0    | em_fc_none
4102 			 *    0   |    1    |   1   |    1    | em_fc_tx_pause
4103 			 *    1   |    0    |   0   |   DC    | em_fc_none
4104 			 *    1   |   DC    |   1   |   DC    | em_fc_full
4105 			 *    1   |    1    |   0   |    0    | em_fc_none
4106 			 *    1   |    1    |   0   |    1    | em_fc_rx_pause
4107 			 *
4108 			 */
4109 			/*
4110 			 * Are both PAUSE bits set to 1?  If so, this implies
4111 			 * Symmetric Flow Control is enabled at both ends.
4112 			 * The ASM_DIR bits are irrelevant per the spec.
4113 			 *
4114 			 * For Symmetric Flow Control:
4115 			 *
4116 			 *   LOCAL DEVICE  |   LINK PARTNER
4117 			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
4118 			 * -------|---------|-------|---------|---------------
4119 			 *    1   |   DC    |   1   |   DC    | em_fc_full
4120 			 *
4121 			 */
4122 			if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
4123 			    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
4124 				/*
4125 				 * Now we need to check if the user selected
4126 				 * RX ONLY of pause frames.  In this case, we
4127 				 * had to advertise FULL flow control because
4128 				 * we could not advertise RX ONLY. Hence, we
4129 				 * must now check to see if we need to turn
4130 				 * OFF  the TRANSMISSION of PAUSE frames.
4131 				 */
4132 				if (hw->original_fc == E1000_FC_FULL) {
4133 					hw->fc = E1000_FC_FULL;
4134 					DEBUGOUT("Flow Control = FULL.\n");
4135 				} else {
4136 					hw->fc = E1000_FC_RX_PAUSE;
4137 					DEBUGOUT("Flow Control = RX PAUSE"
4138 					    " frames only.\n");
4139 				}
4140 			}
4141 			/*
4142 			 * For receiving PAUSE frames ONLY.
4143 			 *
4144 			 * LOCAL DEVICE  |   LINK PARTNER PAUSE | ASM_DIR |
4145 			 * PAUSE | ASM_DIR | Result
4146 			 * -------|---------|-------|---------|---------------
4147 			 * ----- 0   |    1    |   1   |    1    |
4148 			 * em_fc_tx_pause
4149 			 *
4150 			 */
4151 			else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
4152 			    (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
4153 			    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
4154 			    (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
4155 				hw->fc = E1000_FC_TX_PAUSE;
4156 				DEBUGOUT("Flow Control = TX PAUSE frames only."
4157 				    "\n");
4158 			}
4159 			/*
4160 			 * For transmitting PAUSE frames ONLY.
4161 			 *
4162 			 *    LOCAL DEVICE  |   LINK PARTNER
4163 			 *  PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
4164 			 * -------|---------|-------|---------|---------------
4165 			 *    1   |    1    |   0   |    1    | em_fc_rx_pause
4166 			 *
4167 			 */
4168 			else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
4169 			    (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
4170 			    !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
4171 			    (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
4172 				hw->fc = E1000_FC_RX_PAUSE;
4173 				DEBUGOUT("Flow Control = RX PAUSE frames only."
4174 				    "\n");
4175 			}
4176 			/*
4177 			 * Per the IEEE spec, at this point flow control
4178 			 * should be disabled.  However, we want to consider
4179 			 * that we could be connected to a legacy switch that
4180 			 * doesn't advertise desired flow control, but can be
4181 			 * forced on the link partner.  So if we advertised
4182 			 * no flow control, that is what we will resolve to.
4183 			 * If we advertised some kind of receive capability
4184 			 * (Rx Pause Only or Full Flow Control) and the link
4185 			 * partner advertised none, we will configure
4186 			 * ourselves to enable Rx Flow Control only.  We can
4187 			 * do this safely for two reasons:  If the link
4188 			 * partner really didn't want flow control enabled,
4189 			 * and we enable Rx, no harm done since we won't be
4190 			 * receiving any PAUSE frames anyway.  If the intent
4191 			 * on the link partner was to have flow control
4192 			 * enabled, then by us enabling RX only, we can at
4193 			 * least receive pause frames and process them. This
4194 			 * is a good idea because in most cases, since we are
4195 			 * predominantly a server NIC, more times than not we
4196 			 * will be asked to delay transmission of packets
4197 			 * than asking our link partner to pause transmission
4198 			 * of frames.
4199 			 */
4200 			else if ((hw->original_fc == E1000_FC_NONE ||
4201 			    hw->original_fc == E1000_FC_TX_PAUSE) ||
4202 			    hw->fc_strict_ieee) {
4203 				hw->fc = E1000_FC_NONE;
4204 				DEBUGOUT("Flow Control = NONE.\n");
4205 			} else {
4206 				hw->fc = E1000_FC_RX_PAUSE;
4207 				DEBUGOUT("Flow Control = RX PAUSE frames only."
4208 				    "\n");
4209 			}
4210 			/*
4211 			 * Now we need to do one last check...  If we auto-
4212 			 * negotiated to HALF DUPLEX, flow control should not
4213 			 * be enabled per IEEE 802.3 spec.
4214 			 */
4215 			ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
4216 			if (ret_val) {
4217 				DEBUGOUT("Error getting link speed and duplex"
4218 				    "\n");
4219 				return ret_val;
4220 			}
4221 			if (duplex == HALF_DUPLEX)
4222 				hw->fc = E1000_FC_NONE;
4223 			/*
4224 			 * Now we call a subroutine to actually force the MAC
4225 			 * controller to use the correct flow control
4226 			 * settings.
4227 			 */
4228 			ret_val = em_force_mac_fc(hw);
4229 			if (ret_val) {
4230 				DEBUGOUT("Error forcing flow control settings"
4231 				    "\n");
4232 				return ret_val;
4233 			}
4234 		} else {
4235 			DEBUGOUT("Copper PHY and Auto Neg has not completed."
4236 			    "\n");
4237 		}
4238 	}
4239 	return E1000_SUCCESS;
4240 }
4241 /******************************************************************************
4242  * Checks to see if the link status of the hardware has changed.
4243  *
4244  * hw - Struct containing variables accessed by shared code
4245  *
4246  * Called by any function that needs to check the link status of the adapter.
4247  *****************************************************************************/
4248 int32_t
em_check_for_link(struct em_hw * hw)4249 em_check_for_link(struct em_hw *hw)
4250 {
4251 	uint32_t rxcw = 0;
4252 	uint32_t ctrl;
4253 	uint32_t status;
4254 	uint32_t rctl;
4255 	uint32_t icr;
4256 	uint32_t signal = 0;
4257 	int32_t  ret_val;
4258 	uint16_t phy_data;
4259 	DEBUGFUNC("em_check_for_link");
4260 	uint16_t speed, duplex;
4261 
4262 	if (hw->mac_type >= em_82575 &&
4263 	    hw->media_type != em_media_type_copper) {
4264 		ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed,
4265 		    &duplex);
4266 		hw->get_link_status = hw->serdes_link_down;
4267 
4268 		return (ret_val);
4269 	}
4270 
4271 	ctrl = E1000_READ_REG(hw, CTRL);
4272 	status = E1000_READ_REG(hw, STATUS);
4273 	/*
4274 	 * On adapters with a MAC newer than 82544, SW Definable pin 1 will
4275 	 * be set when the optics detect a signal. On older adapters, it will
4276 	 * be cleared when there is a signal.  This applies to fiber media
4277 	 * only.
4278 	 */
4279 	if ((hw->media_type == em_media_type_fiber) ||
4280 	    (hw->media_type == em_media_type_internal_serdes)) {
4281 		rxcw = E1000_READ_REG(hw, RXCW);
4282 
4283 		if (hw->media_type == em_media_type_fiber) {
4284 			signal = (hw->mac_type > em_82544) ?
4285 			    E1000_CTRL_SWDPIN1 : 0;
4286 			if (status & E1000_STATUS_LU)
4287 				hw->get_link_status = FALSE;
4288 		}
4289 	}
4290 	/*
4291 	 * If we have a copper PHY then we only want to go out to the PHY
4292 	 * registers to see if Auto-Neg has completed and/or if our link
4293 	 * status has changed.  The get_link_status flag will be set if we
4294 	 * receive a Link Status Change interrupt or we have Rx Sequence
4295 	 * Errors.
4296 	 */
4297 	if ((hw->media_type == em_media_type_copper ||
4298 	    (hw->media_type == em_media_type_oem)) &&
4299 	    hw->get_link_status) {
4300 		/*
4301 		 * First we want to see if the MII Status Register reports
4302 		 * link.  If so, then we want to get the current speed/duplex
4303 		 * of the PHY. Read the register twice since the link bit is
4304 		 * sticky.
4305 		 */
4306 		ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4307 		if (ret_val)
4308 			return ret_val;
4309 		ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4310 		if (ret_val)
4311 			return ret_val;
4312 
4313 		hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0;
4314 
4315 		if (hw->mac_type == em_pchlan) {
4316 			ret_val = em_k1_gig_workaround_hv(hw,
4317 			    hw->icp_xxxx_is_link_up);
4318 			if (ret_val)
4319 				return ret_val;
4320 		}
4321 
4322 		if (phy_data & MII_SR_LINK_STATUS) {
4323 			hw->get_link_status = FALSE;
4324 
4325 			if (hw->phy_type == em_phy_82578) {
4326 				ret_val = em_link_stall_workaround_hv(hw);
4327 				if (ret_val)
4328 					return ret_val;
4329 			}
4330 
4331 			if (hw->mac_type == em_pch2lan) {
4332 				ret_val = em_k1_workaround_lv(hw);
4333 				if (ret_val)
4334 					return ret_val;
4335 			}
4336 			/* Work-around I218 hang issue */
4337 			if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4338 			    (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4339 			    (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4340 			    (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
4341 				ret_val = em_k1_workaround_lpt_lp(hw,
4342 				    hw->icp_xxxx_is_link_up);
4343 				if (ret_val)
4344 					return ret_val;
4345 			}
4346 
4347 			/*
4348 			 * Check if there was DownShift, must be checked
4349 			 * immediately after link-up
4350 			 */
4351 			em_check_downshift(hw);
4352 
4353 			/* Enable/Disable EEE after link up */
4354 			if (hw->mac_type == em_pch2lan ||
4355 			    hw->mac_type == em_pch_lpt ||
4356 			    hw->mac_type == em_pch_spt ||
4357 			    hw->mac_type == em_pch_cnp ||
4358 			    hw->mac_type == em_pch_tgp ||
4359 			    hw->mac_type == em_pch_adp) {
4360 				ret_val = em_set_eee_pchlan(hw);
4361 				if (ret_val)
4362 					return ret_val;
4363 			}
4364 
4365 			/*
4366 			 * If we are on 82544 or 82543 silicon and
4367 			 * speed/duplex are forced to 10H or 10F, then we
4368 			 * will implement the polarity reversal workaround.
4369 			 * We disable interrupts first, and upon returning,
4370 			 * place the devices interrupt state to its previous
4371 			 * value except for the link status change interrupt
4372 			 * which will happen due to the execution of this
4373 			 * workaround.
4374 			 */
4375 			if ((hw->mac_type == em_82544 ||
4376 			    hw->mac_type == em_82543) && (!hw->autoneg) &&
4377 			    (hw->forced_speed_duplex == em_10_full ||
4378 			    hw->forced_speed_duplex == em_10_half)) {
4379 				E1000_WRITE_REG(hw, IMC, 0xffffffff);
4380 				ret_val = em_polarity_reversal_workaround(hw);
4381 				icr = E1000_READ_REG(hw, ICR);
4382 				E1000_WRITE_REG(hw, ICS,
4383 				    (icr & ~E1000_ICS_LSC));
4384 				E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
4385 			}
4386 		} else {
4387 			/* No link detected */
4388 			em_config_dsp_after_link_change(hw, FALSE);
4389 			return 0;
4390 		}
4391 		/*
4392 		 * If we are forcing speed/duplex, then we simply return
4393 		 * since we have already determined whether we have link or
4394 		 * not.
4395 		 */
4396 		if (!hw->autoneg)
4397 			return -E1000_ERR_CONFIG;
4398 
4399 		/* optimize the dsp settings for the igp phy */
4400 		em_config_dsp_after_link_change(hw, TRUE);
4401 		/*
4402 		 * We have a M88E1000 PHY and Auto-Neg is enabled.  If we
4403 		 * have Si on board that is 82544 or newer, Auto Speed
4404 		 * Detection takes care of MAC speed/duplex configuration.
4405 		 * So we only need to configure Collision Distance in the
4406 		 * MAC.  Otherwise, we need to force speed/duplex on the MAC
4407 		 * to the current PHY speed/duplex settings.
4408 		 */
4409 		if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) {
4410 			em_config_collision_dist(hw);
4411 		} else {
4412 			ret_val = em_config_mac_to_phy(hw);
4413 			if (ret_val) {
4414 				DEBUGOUT("Error configuring MAC to PHY"
4415 				    " settings\n");
4416 				return ret_val;
4417 			}
4418 		}
4419 		/*
4420 		 * Configure Flow Control now that Auto-Neg has completed.
4421 		 * First, we need to restore the desired flow control
4422 		 * settings because we may have had to re-autoneg with a
4423 		 * different link partner.
4424 		 */
4425 		ret_val = em_config_fc_after_link_up(hw);
4426 		if (ret_val) {
4427 			DEBUGOUT("Error configuring flow control\n");
4428 			return ret_val;
4429 		}
4430 		/*
4431 		 * At this point we know that we are on copper and we have
4432 		 * auto-negotiated link.  These are conditions for checking
4433 		 * the link partner capability register.  We use the link
4434 		 * speed to determine if TBI compatibility needs to be turned
4435 		 * on or off.  If the link is not at gigabit speed, then TBI
4436 		 * compatibility is not needed.  If we are at gigabit speed,
4437 		 * we turn on TBI compatibility.
4438 		 */
4439 		if (hw->tbi_compatibility_en) {
4440 			uint16_t speed, duplex;
4441 			ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
4442 			if (ret_val) {
4443 				DEBUGOUT("Error getting link speed and duplex"
4444 				    "\n");
4445 				return ret_val;
4446 			}
4447 			if (speed != SPEED_1000) {
4448 				/*
4449 				 * If link speed is not set to gigabit speed,
4450 				 * we do not need to enable TBI
4451 				 * compatibility.
4452 				 */
4453 				if (hw->tbi_compatibility_on) {
4454 					/*
4455 					 * If we previously were in the mode,
4456 					 * turn it off.
4457 					 */
4458 					rctl = E1000_READ_REG(hw, RCTL);
4459 					rctl &= ~E1000_RCTL_SBP;
4460 					E1000_WRITE_REG(hw, RCTL, rctl);
4461 					hw->tbi_compatibility_on = FALSE;
4462 				}
4463 			} else {
4464 				/*
4465 				 * If TBI compatibility is was previously
4466 				 * off, turn it on. For compatibility with a
4467 				 * TBI link partner, we will store bad
4468 				 * packets. Some frames have an additional
4469 				 * byte on the end and will look like CRC
4470 				 * errors to the hardware.
4471 				 */
4472 				if (!hw->tbi_compatibility_on) {
4473 					hw->tbi_compatibility_on = TRUE;
4474 					rctl = E1000_READ_REG(hw, RCTL);
4475 					rctl |= E1000_RCTL_SBP;
4476 					E1000_WRITE_REG(hw, RCTL, rctl);
4477 				}
4478 			}
4479 		}
4480 	}
4481 	/*
4482 	 * If we don't have link (auto-negotiation failed or link partner
4483 	 * cannot auto-negotiate), the cable is plugged in (we have signal),
4484 	 * and our link partner is not trying to auto-negotiate with us (we
4485 	 * are receiving idles or data), we need to force link up. We also
4486 	 * need to give auto-negotiation time to complete, in case the cable
4487 	 * was just plugged in. The autoneg_failed flag does this.
4488 	 */
4489 	else if ((((hw->media_type == em_media_type_fiber) &&
4490 	    ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
4491 	    (hw->media_type == em_media_type_internal_serdes)) &&
4492 	    (!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
4493 		if (hw->autoneg_failed == 0) {
4494 			hw->autoneg_failed = 1;
4495 			return 0;
4496 		}
4497 		DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
4498 
4499 		/* Disable auto-negotiation in the TXCW register */
4500 		E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
4501 
4502 		/* Force link-up and also force full-duplex. */
4503 		ctrl = E1000_READ_REG(hw, CTRL);
4504 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
4505 		E1000_WRITE_REG(hw, CTRL, ctrl);
4506 
4507 		/* Configure Flow Control after forcing link up. */
4508 		ret_val = em_config_fc_after_link_up(hw);
4509 		if (ret_val) {
4510 			DEBUGOUT("Error configuring flow control\n");
4511 			return ret_val;
4512 		}
4513 	}
4514 	/*
4515 	 * If we are forcing link and we are receiving /C/ ordered sets,
4516 	 * re-enable auto-negotiation in the TXCW register and disable forced
4517 	 * link in the Device Control register in an attempt to
4518 	 * auto-negotiate with our link partner.
4519 	 */
4520 	else if (((hw->media_type == em_media_type_fiber) ||
4521 	    (hw->media_type == em_media_type_internal_serdes)) &&
4522 	    (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
4523 		DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
4524 		E1000_WRITE_REG(hw, TXCW, hw->txcw);
4525 		E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
4526 
4527 		hw->serdes_link_down = FALSE;
4528 	}
4529 	/*
4530 	 * If we force link for non-auto-negotiation switch, check link
4531 	 * status based on MAC synchronization for internal serdes media
4532 	 * type.
4533 	 */
4534 	else if ((hw->media_type == em_media_type_internal_serdes) &&
4535 	    !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
4536 		/* SYNCH bit and IV bit are sticky. */
4537 		usec_delay(10);
4538 		if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
4539 			if (!(rxcw & E1000_RXCW_IV)) {
4540 				hw->serdes_link_down = FALSE;
4541 				DEBUGOUT("SERDES: Link is up.\n");
4542 			}
4543 		} else {
4544 			hw->serdes_link_down = TRUE;
4545 			DEBUGOUT("SERDES: Link is down.\n");
4546 		}
4547 	}
4548 	if ((hw->media_type == em_media_type_internal_serdes) &&
4549 	    (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
4550 		hw->serdes_link_down = !(E1000_STATUS_LU &
4551 		    E1000_READ_REG(hw, STATUS));
4552 	}
4553 	return E1000_SUCCESS;
4554 }
4555 
4556 int32_t
em_get_pcs_speed_and_duplex_82575(struct em_hw * hw,uint16_t * speed,uint16_t * duplex)4557 em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed,
4558     uint16_t *duplex)
4559 {
4560 	uint32_t pcs;
4561 
4562 	hw->serdes_link_down = TRUE;
4563 	*speed = 0;
4564 	*duplex = 0;
4565 
4566 	/*
4567 	 * Read the PCS Status register for link state. For non-copper mode,
4568 	 * the status register is not accurate. The PCS status register is
4569 	 * used instead.
4570 	 */
4571 	pcs = E1000_READ_REG(hw, PCS_LSTAT);
4572 
4573 	/*
4574 	 * The link up bit determines when link is up on autoneg. The sync ok
4575 	 * gets set once both sides sync up and agree upon link. Stable link
4576 	 * can be determined by checking for both link up and link sync ok
4577 	 */
4578 	if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
4579 		hw->serdes_link_down = FALSE;
4580 
4581 		/* Detect and store PCS speed */
4582 		if (pcs & E1000_PCS_LSTS_SPEED_1000) {
4583 			*speed = SPEED_1000;
4584 		} else if (pcs & E1000_PCS_LSTS_SPEED_100) {
4585 			*speed = SPEED_100;
4586 		} else {
4587 			*speed = SPEED_10;
4588 		}
4589 
4590 		/* Detect and store PCS duplex */
4591 		if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
4592 			*duplex = FULL_DUPLEX;
4593 		} else {
4594 			*duplex = HALF_DUPLEX;
4595 		}
4596 	}
4597 
4598 	return (0);
4599 }
4600 
4601 
4602 /******************************************************************************
4603  * Detects the current speed and duplex settings of the hardware.
4604  *
4605  * hw - Struct containing variables accessed by shared code
4606  * speed - Speed of the connection
4607  * duplex - Duplex setting of the connection
4608  *****************************************************************************/
4609 int32_t
em_get_speed_and_duplex(struct em_hw * hw,uint16_t * speed,uint16_t * duplex)4610 em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex)
4611 {
4612 	uint32_t status;
4613 	int32_t  ret_val;
4614 	uint16_t phy_data;
4615 	DEBUGFUNC("em_get_speed_and_duplex");
4616 
4617 	if (hw->mac_type >= em_82575 && hw->media_type != em_media_type_copper)
4618 		return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex);
4619 
4620 	if (hw->mac_type >= em_82543) {
4621 		status = E1000_READ_REG(hw, STATUS);
4622 		if (status & E1000_STATUS_SPEED_1000) {
4623 			*speed = SPEED_1000;
4624 			DEBUGOUT("1000 Mbs, ");
4625 		} else if (status & E1000_STATUS_SPEED_100) {
4626 			*speed = SPEED_100;
4627 			DEBUGOUT("100 Mbs, ");
4628 		} else {
4629 			*speed = SPEED_10;
4630 			DEBUGOUT("10 Mbs, ");
4631 		}
4632 
4633 		if (status & E1000_STATUS_FD) {
4634 			*duplex = FULL_DUPLEX;
4635 			DEBUGOUT("Full Duplex\n");
4636 		} else {
4637 			*duplex = HALF_DUPLEX;
4638 			DEBUGOUT(" Half Duplex\n");
4639 		}
4640 	} else {
4641 		DEBUGOUT("1000 Mbs, Full Duplex\n");
4642 		*speed = SPEED_1000;
4643 		*duplex = FULL_DUPLEX;
4644 	}
4645 	/*
4646 	 * IGP01 PHY may advertise full duplex operation after speed
4647 	 * downgrade even if it is operating at half duplex.  Here we set the
4648 	 * duplex settings to match the duplex in the link partner's
4649 	 * capabilities.
4650 	 */
4651 	if (hw->phy_type == em_phy_igp && hw->speed_downgraded) {
4652 		ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
4653 		if (ret_val)
4654 			return ret_val;
4655 
4656 		if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
4657 			*duplex = HALF_DUPLEX;
4658 		else {
4659 			ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
4660 			    &phy_data);
4661 			if (ret_val)
4662 				return ret_val;
4663 			if ((*speed == SPEED_100 &&
4664 			    !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
4665 			    (*speed == SPEED_10 &&
4666 			    !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
4667 				*duplex = HALF_DUPLEX;
4668 		}
4669 	}
4670 	if ((hw->mac_type == em_80003es2lan) &&
4671 	    (hw->media_type == em_media_type_copper)) {
4672 		if (*speed == SPEED_1000)
4673 			ret_val = em_configure_kmrn_for_1000(hw);
4674 		else
4675 			ret_val = em_configure_kmrn_for_10_100(hw, *duplex);
4676 		if (ret_val)
4677 			return ret_val;
4678 	}
4679 	if ((hw->mac_type == em_ich8lan) &&
4680 	    (hw->phy_type == em_phy_igp_3) &&
4681 	    (*speed == SPEED_1000)) {
4682 		ret_val = em_kumeran_lock_loss_workaround(hw);
4683 		if (ret_val)
4684 			return ret_val;
4685 	}
4686 	return E1000_SUCCESS;
4687 }
4688 
4689 /******************************************************************************
4690  * Blocks until autoneg completes or times out (~4.5 seconds)
4691  *
4692  * hw - Struct containing variables accessed by shared code
4693  *****************************************************************************/
4694 STATIC int32_t
em_wait_autoneg(struct em_hw * hw)4695 em_wait_autoneg(struct em_hw *hw)
4696 {
4697 	int32_t  ret_val;
4698 	uint16_t i;
4699 	uint16_t phy_data;
4700 	DEBUGFUNC("em_wait_autoneg");
4701 	DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4702 
4703 	/* We will wait for autoneg to complete or 4.5 seconds to expire. */
4704 	for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4705 		/*
4706 		 * Read the MII Status Register and wait for Auto-Neg
4707 		 * Complete bit to be set.
4708 		 */
4709 		ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4710 		if (ret_val)
4711 			return ret_val;
4712 		ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4713 		if (ret_val)
4714 			return ret_val;
4715 		if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4716 			return E1000_SUCCESS;
4717 		}
4718 		msec_delay(100);
4719 	}
4720 	return E1000_SUCCESS;
4721 }
4722 
4723 /******************************************************************************
4724  * Raises the Management Data Clock
4725  *
4726  * hw - Struct containing variables accessed by shared code
4727  * ctrl - Device control register's current value
4728  *****************************************************************************/
4729 static void
em_raise_mdi_clk(struct em_hw * hw,uint32_t * ctrl)4730 em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl)
4731 {
4732 	/*
4733 	 * Raise the clock input to the Management Data Clock (by setting the
4734 	 * MDC bit), and then delay 10 microseconds.
4735 	 */
4736 	E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4737 	E1000_WRITE_FLUSH(hw);
4738 	usec_delay(10);
4739 }
4740 
4741 /******************************************************************************
4742  * Lowers the Management Data Clock
4743  *
4744  * hw - Struct containing variables accessed by shared code
4745  * ctrl - Device control register's current value
4746  *****************************************************************************/
4747 static void
em_lower_mdi_clk(struct em_hw * hw,uint32_t * ctrl)4748 em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl)
4749 {
4750 	/*
4751 	 * Lower the clock input to the Management Data Clock (by clearing
4752 	 * the MDC bit), and then delay 10 microseconds.
4753 	 */
4754 	E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4755 	E1000_WRITE_FLUSH(hw);
4756 	usec_delay(10);
4757 }
4758 
4759 /******************************************************************************
4760  * Shifts data bits out to the PHY
4761  *
4762  * hw - Struct containing variables accessed by shared code
4763  * data - Data to send out to the PHY
4764  * count - Number of bits to shift out
4765  *
4766  * Bits are shifted out in MSB to LSB order.
4767  *****************************************************************************/
4768 static void
em_shift_out_mdi_bits(struct em_hw * hw,uint32_t data,uint16_t count)4769 em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count)
4770 {
4771 	uint32_t ctrl;
4772 	uint32_t mask;
4773 	/*
4774 	 * We need to shift "count" number of bits out to the PHY. So, the
4775 	 * value in the "data" parameter will be shifted out to the PHY one
4776 	 * bit at a time. In order to do this, "data" must be broken down
4777 	 * into bits.
4778 	 */
4779 	mask = 0x01;
4780 	mask <<= (count - 1);
4781 
4782 	ctrl = E1000_READ_REG(hw, CTRL);
4783 
4784 	/* Set MDIO_DIR and MDC_DIR direction bits to be used as output
4785 	 * pins.
4786 	 */
4787 	ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4788 
4789 	while (mask) {
4790 		/*
4791 		 * A "1" is shifted out to the PHY by setting the MDIO bit to
4792 		 * "1" and then raising and lowering the Management Data
4793 		 * Clock. A "0" is shifted out to the PHY by setting the MDIO
4794 		 * bit to "0" and then raising and lowering the clock.
4795 		 */
4796 		if (data & mask)
4797 			ctrl |= E1000_CTRL_MDIO;
4798 		else
4799 			ctrl &= ~E1000_CTRL_MDIO;
4800 
4801 		E1000_WRITE_REG(hw, CTRL, ctrl);
4802 		E1000_WRITE_FLUSH(hw);
4803 
4804 		usec_delay(10);
4805 
4806 		em_raise_mdi_clk(hw, &ctrl);
4807 		em_lower_mdi_clk(hw, &ctrl);
4808 
4809 		mask = mask >> 1;
4810 	}
4811 }
4812 
4813 /******************************************************************************
4814  * Shifts data bits in from the PHY
4815  *
4816  * hw - Struct containing variables accessed by shared code
4817  *
4818  * Bits are shifted in in MSB to LSB order.
4819  *****************************************************************************/
4820 static uint16_t
em_shift_in_mdi_bits(struct em_hw * hw)4821 em_shift_in_mdi_bits(struct em_hw *hw)
4822 {
4823 	uint32_t ctrl;
4824 	uint16_t data = 0;
4825 	uint8_t  i;
4826 	/*
4827 	 * In order to read a register from the PHY, we need to shift in a
4828 	 * total of 18 bits from the PHY. The first two bit (turnaround)
4829 	 * times are used to avoid contention on the MDIO pin when a read
4830 	 * operation is performed. These two bits are ignored by us and
4831 	 * thrown away. Bits are "shifted in" by raising the input to the
4832 	 * Management Data Clock (setting the MDC bit), and then reading the
4833 	 * value of the MDIO bit.
4834 	 */
4835 	ctrl = E1000_READ_REG(hw, CTRL);
4836 	/*
4837 	 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
4838 	 * input.
4839 	 */
4840 	ctrl &= ~E1000_CTRL_MDIO_DIR;
4841 	ctrl &= ~E1000_CTRL_MDIO;
4842 
4843 	E1000_WRITE_REG(hw, CTRL, ctrl);
4844 	E1000_WRITE_FLUSH(hw);
4845 	/*
4846 	 * Raise and Lower the clock before reading in the data. This
4847 	 * accounts for the turnaround bits. The first clock occurred when we
4848 	 * clocked out the last bit of the Register Address.
4849 	 */
4850 	em_raise_mdi_clk(hw, &ctrl);
4851 	em_lower_mdi_clk(hw, &ctrl);
4852 
4853 	for (data = 0, i = 0; i < 16; i++) {
4854 		data = data << 1;
4855 		em_raise_mdi_clk(hw, &ctrl);
4856 		ctrl = E1000_READ_REG(hw, CTRL);
4857 		/* Check to see if we shifted in a "1". */
4858 		if (ctrl & E1000_CTRL_MDIO)
4859 			data |= 1;
4860 		em_lower_mdi_clk(hw, &ctrl);
4861 	}
4862 
4863 	em_raise_mdi_clk(hw, &ctrl);
4864 	em_lower_mdi_clk(hw, &ctrl);
4865 
4866 	return data;
4867 }
4868 
4869 STATIC int32_t
em_swfw_sync_acquire(struct em_hw * hw,uint16_t mask)4870 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask)
4871 {
4872 	uint32_t swfw_sync = 0;
4873 	uint32_t swmask = mask;
4874 	uint32_t fwmask = mask << 16;
4875 	int32_t  timeout = 200;
4876 	DEBUGFUNC("em_swfw_sync_acquire");
4877 
4878 	if (hw->swfwhw_semaphore_present)
4879 		return em_get_software_flag(hw);
4880 
4881 	if (!hw->swfw_sync_present)
4882 		return em_get_hw_eeprom_semaphore(hw);
4883 
4884 	while (timeout) {
4885 		if (em_get_hw_eeprom_semaphore(hw))
4886 			return -E1000_ERR_SWFW_SYNC;
4887 
4888 		swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
4889 		if (!(swfw_sync & (fwmask | swmask))) {
4890 			break;
4891 		}
4892 		/*
4893 		 * firmware currently using resource (fwmask)
4894 		 * or other software thread currently using resource (swmask)
4895 		 */
4896 		em_put_hw_eeprom_semaphore(hw);
4897 		msec_delay_irq(5);
4898 		timeout--;
4899 	}
4900 
4901 	if (!timeout) {
4902 		DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout."
4903 		    "\n");
4904 		return -E1000_ERR_SWFW_SYNC;
4905 	}
4906 	swfw_sync |= swmask;
4907 	E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
4908 
4909 	em_put_hw_eeprom_semaphore(hw);
4910 	return E1000_SUCCESS;
4911 }
4912 
4913 STATIC void
em_swfw_sync_release(struct em_hw * hw,uint16_t mask)4914 em_swfw_sync_release(struct em_hw *hw, uint16_t mask)
4915 {
4916 	uint32_t swfw_sync;
4917 	uint32_t swmask = mask;
4918 	DEBUGFUNC("em_swfw_sync_release");
4919 
4920 	if (hw->swfwhw_semaphore_present) {
4921 		em_release_software_flag(hw);
4922 		return;
4923 	}
4924 	if (!hw->swfw_sync_present) {
4925 		em_put_hw_eeprom_semaphore(hw);
4926 		return;
4927 	}
4928 	/*
4929 	 * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC;
4930 	 */
4931 	while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
4932 	/* empty */
4933 
4934 	swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
4935 	swfw_sync &= ~swmask;
4936 	E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
4937 
4938 	em_put_hw_eeprom_semaphore(hw);
4939 }
4940 
4941 /****************************************************************************
4942  *  Read BM PHY wakeup register.  It works as such:
4943  *  1) Set page 769, register 17, bit 2 = 1
4944  *  2) Set page to 800 for host (801 if we were manageability)
4945  *  3) Write the address using the address opcode (0x11)
4946  *  4) Read or write the data using the data opcode (0x12)
4947  *  5) Restore 769_17.2 to its original value
4948  ****************************************************************************/
4949 int32_t
em_access_phy_wakeup_reg_bm(struct em_hw * hw,uint32_t reg_addr,uint16_t * phy_data,boolean_t read)4950 em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr,
4951     uint16_t *phy_data, boolean_t read)
4952 {
4953 	int32_t ret_val;
4954 	uint16_t reg = BM_PHY_REG_NUM(reg_addr);
4955 	uint16_t phy_reg = 0;
4956 
4957 	/* All operations in this function are phy address 1 */
4958 	hw->phy_addr = 1;
4959 
4960 	/* Set page 769 */
4961 	em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
4962 	    (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT));
4963 
4964 	ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg);
4965 	if (ret_val)
4966 		goto out;
4967 
4968 	/* First clear bit 4 to avoid a power state change */
4969 	phy_reg &= ~(BM_WUC_HOST_WU_BIT);
4970 	ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg);
4971 	if (ret_val)
4972 		goto out;
4973 
4974 	/* Write bit 2 = 1, and clear bit 4 to 769_17 */
4975 	ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG,
4976 	    phy_reg | BM_WUC_ENABLE_BIT);
4977 	if (ret_val)
4978 		goto out;
4979 
4980 	/* Select page 800 */
4981 	ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
4982 	    (BM_WUC_PAGE << PHY_PAGE_SHIFT));
4983 
4984 	/* Write the page 800 offset value using opcode 0x11 */
4985 	ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg);
4986 	if (ret_val)
4987 		goto out;
4988 
4989 	if (read)
4990 	        /* Read the page 800 value using opcode 0x12 */
4991 		ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE,
4992 		    phy_data);
4993 	else
4994 	        /* Write the page 800 value using opcode 0x12 */
4995 		ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE,
4996 		    *phy_data);
4997 
4998 	if (ret_val)
4999 		goto out;
5000 
5001 	/*
5002 	 * Restore 769_17.2 to its original value
5003 	 * Set page 769
5004 	 */
5005 	em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
5006 	    (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT));
5007 
5008 	/* Clear 769_17.2 */
5009 	ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg);
5010 	if (ret_val)
5011 		goto out;
5012 
5013 out:
5014 	return ret_val;
5015 }
5016 
5017 /***************************************************************************
5018  *  Read HV PHY vendor specific high registers
5019  ***************************************************************************/
5020 int32_t
em_access_phy_debug_regs_hv(struct em_hw * hw,uint32_t reg_addr,uint16_t * phy_data,boolean_t read)5021 em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr,
5022     uint16_t *phy_data, boolean_t read)
5023 {
5024 	int32_t ret_val;
5025 	uint32_t addr_reg = 0;
5026 	uint32_t data_reg = 0;
5027 
5028 	/* This takes care of the difference with desktop vs mobile phy */
5029 	addr_reg = (hw->phy_type == em_phy_82578) ?
5030 	           I82578_PHY_ADDR_REG : I82577_PHY_ADDR_REG;
5031 	data_reg = addr_reg + 1;
5032 
5033 	/* All operations in this function are phy address 2 */
5034 	hw->phy_addr = 2;
5035 
5036 	/* masking with 0x3F to remove the page from offset */
5037 	ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F);
5038 	if (ret_val) {
5039 		printf("Could not write PHY the HV address register\n");
5040 		goto out;
5041 	}
5042 
5043 	/* Read or write the data value next */
5044 	if (read)
5045 		ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data);
5046 	else
5047 		ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data);
5048 
5049 	if (ret_val) {
5050 		printf("Could not read data value from HV data register\n");
5051 		goto out;
5052 	}
5053 
5054 out:
5055 	return ret_val;
5056 }
5057 
5058 /******************************************************************************
5059  * Reads or writes the value from a PHY register, if the value is on a specific
5060  * non zero page, sets the page first.
5061  * hw - Struct containing variables accessed by shared code
5062  * reg_addr - address of the PHY register to read
5063  *****************************************************************************/
5064 int32_t
em_access_phy_reg_hv(struct em_hw * hw,uint32_t reg_addr,uint16_t * phy_data,boolean_t read)5065 em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data,
5066     boolean_t read)
5067 {
5068 	uint32_t ret_val;
5069 	uint16_t swfw;
5070 	uint16_t page = BM_PHY_REG_PAGE(reg_addr);
5071 	uint16_t reg = BM_PHY_REG_NUM(reg_addr);
5072 
5073 	DEBUGFUNC("em_access_phy_reg_hv");
5074 
5075 	swfw = E1000_SWFW_PHY0_SM;
5076 
5077 	if (em_swfw_sync_acquire(hw, swfw))
5078 		return -E1000_ERR_SWFW_SYNC;
5079 
5080 	if (page == BM_WUC_PAGE) {
5081 		ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr,
5082 		    phy_data, read);
5083 		goto release;
5084 	}
5085 
5086 	if (page >= HV_INTC_FC_PAGE_START)
5087 		hw->phy_addr = 1;
5088 	else
5089 		hw->phy_addr = 2;
5090 
5091 	if (page == HV_INTC_FC_PAGE_START)
5092 		page = 0;
5093 
5094 	/*
5095 	 * Workaround MDIO accesses being disabled after entering IEEE Power
5096 	 * Down (whenever bit 11 of the PHY Control register is set)
5097 	 */
5098 	if (!read &&
5099 	    (hw->phy_type == em_phy_82578) &&
5100 	    (hw->phy_revision >= 1) &&
5101 	    (hw->phy_addr == 2) &&
5102 	    ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
5103 	    (*phy_data & (1 << 11))) {
5104 		uint16_t data2 = 0x7EFF;
5105 
5106 		ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
5107 		    &data2, FALSE);
5108 		if (ret_val)
5109 			return ret_val;
5110 	}
5111 
5112 	if (reg_addr > MAX_PHY_MULTI_PAGE_REG) {
5113 		ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
5114 		    (page << PHY_PAGE_SHIFT));
5115 		if (ret_val)
5116 			return ret_val;
5117 	}
5118 	if (read)
5119 		ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg,
5120 		    phy_data);
5121 	else
5122 		ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg,
5123 		    *phy_data);
5124 release:
5125 	em_swfw_sync_release(hw, swfw);
5126 	return ret_val;
5127 }
5128 
5129 /******************************************************************************
5130  * Reads the value from a PHY register, if the value is on a specific non zero
5131  * page, sets the page first.
5132  * hw - Struct containing variables accessed by shared code
5133  * reg_addr - address of the PHY register to read
5134  *****************************************************************************/
5135 int32_t
em_read_phy_reg(struct em_hw * hw,uint32_t reg_addr,uint16_t * phy_data)5136 em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data)
5137 {
5138 	uint32_t ret_val;
5139 	uint16_t swfw;
5140 	DEBUGFUNC("em_read_phy_reg");
5141 
5142 	if (hw->mac_type == em_pchlan ||
5143 		hw->mac_type == em_pch2lan ||
5144 		hw->mac_type == em_pch_lpt ||
5145 		hw->mac_type == em_pch_spt ||
5146 		hw->mac_type == em_pch_cnp ||
5147 		hw->mac_type == em_pch_tgp ||
5148 		hw->mac_type == em_pch_adp)
5149 		return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE));
5150 
5151 	if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575) ||
5152 	    (hw->mac_type == em_82576)) &&
5153 	    (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
5154 		swfw = E1000_SWFW_PHY1_SM;
5155 	} else {
5156 		swfw = E1000_SWFW_PHY0_SM;
5157 	}
5158 	if (em_swfw_sync_acquire(hw, swfw))
5159 		return -E1000_ERR_SWFW_SYNC;
5160 
5161 	if ((hw->phy_type == em_phy_igp ||
5162 	    hw->phy_type == em_phy_igp_3 ||
5163 	    hw->phy_type == em_phy_igp_2) &&
5164 	    (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
5165 		ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
5166 		    (uint16_t) reg_addr);
5167 		if (ret_val) {
5168 			em_swfw_sync_release(hw, swfw);
5169 			return ret_val;
5170 		}
5171 	} else if (hw->phy_type == em_phy_gg82563) {
5172 		if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
5173 		    (hw->mac_type == em_80003es2lan)) {
5174 			/* Select Configuration Page */
5175 			if ((reg_addr & MAX_PHY_REG_ADDRESS) <
5176 			    GG82563_MIN_ALT_REG) {
5177 				ret_val = em_write_phy_reg_ex(hw,
5178 				    GG82563_PHY_PAGE_SELECT,
5179 				    (uint16_t) ((uint16_t) reg_addr >>
5180 				    GG82563_PAGE_SHIFT));
5181 			} else {
5182 				/*
5183 				 * Use Alternative Page Select register to
5184 				 * access registers 30 and 31
5185 				 */
5186 				ret_val = em_write_phy_reg_ex(hw,
5187 				    GG82563_PHY_PAGE_SELECT_ALT,
5188 				    (uint16_t) ((uint16_t) reg_addr >>
5189 				    GG82563_PAGE_SHIFT));
5190 			}
5191 
5192 			if (ret_val) {
5193 				em_swfw_sync_release(hw, swfw);
5194 				return ret_val;
5195 			}
5196 		}
5197 	} else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) {
5198 		if (reg_addr > MAX_PHY_MULTI_PAGE_REG) {
5199 			ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT,
5200 			    (uint16_t) ((uint16_t) reg_addr >>
5201 			    PHY_PAGE_SHIFT));
5202 			if (ret_val)
5203 				return ret_val;
5204 		}
5205 	}
5206 	ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
5207 	    phy_data);
5208 
5209 	em_swfw_sync_release(hw, swfw);
5210 	return ret_val;
5211 }
5212 
5213 STATIC int32_t
em_read_phy_reg_ex(struct em_hw * hw,uint32_t reg_addr,uint16_t * phy_data)5214 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data)
5215 {
5216 	uint32_t i;
5217 	uint32_t mdic = 0;
5218 	DEBUGFUNC("em_read_phy_reg_ex");
5219 
5220 	/* SGMII active is only set on some specific chips */
5221 	if (hw->sgmii_active && !em_sgmii_uses_mdio_82575(hw)) {
5222 		if (reg_addr > E1000_MAX_SGMII_PHY_REG_ADDR) {
5223 			DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
5224 			return -E1000_ERR_PARAM;
5225 		}
5226 		return em_read_phy_reg_i2c(hw, reg_addr, phy_data);
5227 	}
5228 	if (reg_addr > MAX_PHY_REG_ADDRESS) {
5229 		DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
5230 		return -E1000_ERR_PARAM;
5231 	}
5232 	if (hw->mac_type == em_icp_xxxx) {
5233 		*phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num,
5234 		    reg_addr);
5235 		return E1000_SUCCESS;
5236 	}
5237 	if (hw->mac_type > em_82543) {
5238 		/*
5239 		 * Set up Op-code, Phy Address, and register address in the
5240 		 * MDI Control register.  The MAC will take care of
5241 		 * interfacing with the PHY to retrieve the desired data.
5242 		 */
5243 		mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
5244 		    (hw->phy_addr << E1000_MDIC_PHY_SHIFT) |
5245 		    (E1000_MDIC_OP_READ));
5246 
5247 		E1000_WRITE_REG(hw, MDIC, mdic);
5248 
5249 		/*
5250 		 * Poll the ready bit to see if the MDI read completed
5251 		 * Increasing the time out as testing showed failures with
5252 		 * the lower time out (from FreeBSD driver)
5253 		 */
5254 		for (i = 0; i < 1960; i++) {
5255 			usec_delay(50);
5256 			mdic = E1000_READ_REG(hw, MDIC);
5257 			if (mdic & E1000_MDIC_READY)
5258 				break;
5259 		}
5260 		if (!(mdic & E1000_MDIC_READY)) {
5261 			DEBUGOUT("MDI Read did not complete\n");
5262 			return -E1000_ERR_PHY;
5263 		}
5264 		if (mdic & E1000_MDIC_ERROR) {
5265 			DEBUGOUT("MDI Error\n");
5266 			return -E1000_ERR_PHY;
5267 		}
5268 		*phy_data = (uint16_t) mdic;
5269 
5270 		if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt ||
5271 		    hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp ||
5272 		    hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp)
5273 			usec_delay(100);
5274 	} else {
5275 		/*
5276 		 * We must first send a preamble through the MDIO pin to
5277 		 * signal the beginning of an MII instruction.  This is done
5278 		 * by sending 32 consecutive "1" bits.
5279 		 */
5280 		em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
5281 		/*
5282 		 * Now combine the next few fields that are required for a
5283 		 * read operation.  We use this method instead of calling the
5284 		 * em_shift_out_mdi_bits routine five different times. The
5285 		 * format of a MII read instruction consists of a shift out
5286 		 * of 14 bits and is defined as follows: <Preamble><SOF><Op
5287 		 * Code><Phy Addr><Reg Addr> followed by a shift in of 18
5288 		 * bits.  This first two bits shifted in are TurnAround bits
5289 		 * used to avoid contention on the MDIO pin when a READ
5290 		 * operation is performed.  These two bits are thrown away
5291 		 * followed by a shift in of 16 bits which contains the
5292 		 * desired data.
5293 		 */
5294 		mdic = ((reg_addr) | (hw->phy_addr << 5) |
5295 		    (PHY_OP_READ << 10) | (PHY_SOF << 12));
5296 
5297 		em_shift_out_mdi_bits(hw, mdic, 14);
5298 		/*
5299 		 * Now that we've shifted out the read command to the MII, we
5300 		 * need to "shift in" the 16-bit value (18 total bits) of the
5301 		 * requested PHY register address.
5302 		 */
5303 		*phy_data = em_shift_in_mdi_bits(hw);
5304 	}
5305 	return E1000_SUCCESS;
5306 }
5307 
5308 /******************************************************************************
5309  * Writes a value to a PHY register
5310  *
5311  * hw - Struct containing variables accessed by shared code
5312  * reg_addr - address of the PHY register to write
5313  * data - data to write to the PHY
5314  *****************************************************************************/
5315 int32_t
em_write_phy_reg(struct em_hw * hw,uint32_t reg_addr,uint16_t phy_data)5316 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data)
5317 {
5318 	uint32_t ret_val;
5319 	DEBUGFUNC("em_write_phy_reg");
5320 
5321 	if (hw->mac_type == em_pchlan ||
5322 		hw->mac_type == em_pch2lan ||
5323 		hw->mac_type == em_pch_lpt ||
5324 		hw->mac_type == em_pch_spt ||
5325 		hw->mac_type == em_pch_cnp ||
5326 		hw->mac_type == em_pch_tgp ||
5327 		hw->mac_type == em_pch_adp)
5328 		return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE));
5329 
5330 	if (em_swfw_sync_acquire(hw, hw->swfw))
5331 		return -E1000_ERR_SWFW_SYNC;
5332 
5333 	if ((hw->phy_type == em_phy_igp ||
5334 	    hw->phy_type == em_phy_igp_3 ||
5335 	    hw->phy_type == em_phy_igp_2) &&
5336 	    (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
5337 		ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
5338 		    (uint16_t) reg_addr);
5339 		if (ret_val) {
5340 			em_swfw_sync_release(hw, hw->swfw);
5341 			return ret_val;
5342 		}
5343 	} else if (hw->phy_type == em_phy_gg82563) {
5344 		if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
5345 		    (hw->mac_type == em_80003es2lan)) {
5346 			/* Select Configuration Page */
5347 			if ((reg_addr & MAX_PHY_REG_ADDRESS) <
5348 			    GG82563_MIN_ALT_REG) {
5349 				ret_val = em_write_phy_reg_ex(hw,
5350 				    GG82563_PHY_PAGE_SELECT,
5351 				    (uint16_t) ((uint16_t) reg_addr >>
5352 				    GG82563_PAGE_SHIFT));
5353 			} else {
5354 				/*
5355 				 * Use Alternative Page Select register to
5356 				 * access registers 30 and 31
5357 				 */
5358 				ret_val = em_write_phy_reg_ex(hw,
5359 				    GG82563_PHY_PAGE_SELECT_ALT,
5360 				    (uint16_t) ((uint16_t) reg_addr >>
5361 				    GG82563_PAGE_SHIFT));
5362 			}
5363 
5364 			if (ret_val) {
5365 				em_swfw_sync_release(hw, hw->swfw);
5366 				return ret_val;
5367 			}
5368 		}
5369 	} else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) {
5370 		if (reg_addr > MAX_PHY_MULTI_PAGE_REG) {
5371 			ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT,
5372 			    (uint16_t) ((uint16_t) reg_addr >>
5373 			    PHY_PAGE_SHIFT));
5374 			if (ret_val)
5375 				return ret_val;
5376 		}
5377 	}
5378 	ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
5379 	    phy_data);
5380 
5381 	em_swfw_sync_release(hw, hw->swfw);
5382 	return ret_val;
5383 }
5384 
5385 STATIC int32_t
em_write_phy_reg_ex(struct em_hw * hw,uint32_t reg_addr,uint16_t phy_data)5386 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data)
5387 {
5388 	uint32_t i;
5389 	uint32_t mdic = 0;
5390 	DEBUGFUNC("em_write_phy_reg_ex");
5391 
5392 	/* SGMII active is only set on some specific chips */
5393 	if (hw->sgmii_active && !em_sgmii_uses_mdio_82575(hw)) {
5394 		if (reg_addr > E1000_MAX_SGMII_PHY_REG_ADDR) {
5395 			DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
5396 			return -E1000_ERR_PARAM;
5397 		}
5398 		return em_write_phy_reg_i2c(hw, reg_addr, phy_data);
5399 	}
5400 	if (reg_addr > MAX_PHY_REG_ADDRESS) {
5401 		DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
5402 		return -E1000_ERR_PARAM;
5403 	}
5404 	if (hw->mac_type == em_icp_xxxx) {
5405 		gcu_miibus_writereg(hw, hw->icp_xxxx_port_num,
5406 		    reg_addr, phy_data);
5407 		return E1000_SUCCESS;
5408 	}
5409 	if (hw->mac_type > em_82543) {
5410 		/*
5411 		 * Set up Op-code, Phy Address, register address, and data
5412 		 * intended for the PHY register in the MDI Control register.
5413 		 * The MAC will take care of interfacing with the PHY to send
5414 		 * the desired data.
5415 		 */
5416 		mdic = (((uint32_t) phy_data) |
5417 			(reg_addr << E1000_MDIC_REG_SHIFT) |
5418 			(hw->phy_addr << E1000_MDIC_PHY_SHIFT) |
5419 			(E1000_MDIC_OP_WRITE));
5420 
5421 		E1000_WRITE_REG(hw, MDIC, mdic);
5422 
5423 		/* Poll the ready bit to see if the MDI read completed */
5424 		for (i = 0; i < 641; i++) {
5425 			usec_delay(5);
5426 			mdic = E1000_READ_REG(hw, MDIC);
5427 			if (mdic & E1000_MDIC_READY)
5428 				break;
5429 		}
5430 		if (!(mdic & E1000_MDIC_READY)) {
5431 			DEBUGOUT("MDI Write did not complete\n");
5432 			return -E1000_ERR_PHY;
5433 		}
5434 
5435 		if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt ||
5436 		    hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp ||
5437 		    hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp)
5438 			usec_delay(100);
5439 	} else {
5440 		/*
5441 		 * We'll need to use the SW defined pins to shift the write
5442 		 * command out to the PHY. We first send a preamble to the
5443 		 * PHY to signal the beginning of the MII instruction.  This
5444 		 * is done by sending 32 consecutive "1" bits.
5445 		 */
5446 		em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
5447 		/*
5448 		 * Now combine the remaining required fields that will
5449 		 * indicate a write operation. We use this method instead of
5450 		 * calling the em_shift_out_mdi_bits routine for each field
5451 		 * in the command. The format of a MII write instruction is
5452 		 * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg
5453 		 * Addr><Turnaround><Data>.
5454 		 */
5455 		mdic = ((PHY_TURNAROUND) | (reg_addr << 2) |
5456 		    (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) |
5457 		    (PHY_SOF << 14));
5458 		mdic <<= 16;
5459 		mdic |= (uint32_t) phy_data;
5460 
5461 		em_shift_out_mdi_bits(hw, mdic, 32);
5462 	}
5463 
5464 	return E1000_SUCCESS;
5465 }
5466 
5467 STATIC int32_t
em_read_kmrn_reg(struct em_hw * hw,uint32_t reg_addr,uint16_t * data)5468 em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data)
5469 {
5470 	uint32_t reg_val;
5471 	DEBUGFUNC("em_read_kmrn_reg");
5472 
5473 	if (em_swfw_sync_acquire(hw, hw->swfw))
5474 		return -E1000_ERR_SWFW_SYNC;
5475 
5476 	/* Write register address */
5477 	reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
5478 	    E1000_KUMCTRLSTA_OFFSET) |
5479 	    E1000_KUMCTRLSTA_REN;
5480 
5481 	E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
5482 	usec_delay(2);
5483 
5484 	/* Read the data returned */
5485 	reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
5486 	*data = (uint16_t) reg_val;
5487 
5488 	em_swfw_sync_release(hw, hw->swfw);
5489 	return E1000_SUCCESS;
5490 }
5491 
5492 STATIC int32_t
em_write_kmrn_reg(struct em_hw * hw,uint32_t reg_addr,uint16_t data)5493 em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data)
5494 {
5495 	uint32_t reg_val;
5496 	DEBUGFUNC("em_write_kmrn_reg");
5497 
5498 	if (em_swfw_sync_acquire(hw, hw->swfw))
5499 		return -E1000_ERR_SWFW_SYNC;
5500 
5501 	reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
5502 	    E1000_KUMCTRLSTA_OFFSET) | data;
5503 
5504 	E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
5505 	usec_delay(2);
5506 
5507 	em_swfw_sync_release(hw, hw->swfw);
5508 	return E1000_SUCCESS;
5509 }
5510 
5511 /**
5512  *  em_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
5513  *  @hw: pointer to the HW structure
5514  *
5515  *  Called to determine if the I2C pins are being used for I2C or as an
5516  *  external MDIO interface since the two options are mutually exclusive.
5517  **/
5518 int
em_sgmii_uses_mdio_82575(struct em_hw * hw)5519 em_sgmii_uses_mdio_82575(struct em_hw *hw)
5520 {
5521 	uint32_t reg = 0;
5522 	int ext_mdio = 0;
5523 
5524 	DEBUGFUNC("em_sgmii_uses_mdio_82575");
5525 
5526 	switch (hw->mac_type) {
5527 	case em_82575:
5528 	case em_82576:
5529 		reg = E1000_READ_REG(hw, MDIC);
5530 		ext_mdio = !!(reg & E1000_MDIC_DEST);
5531 		break;
5532 	case em_82580:
5533 	case em_i350:
5534 	case em_i210:
5535 		reg = E1000_READ_REG(hw, MDICNFG);
5536 		ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
5537 		break;
5538 	default:
5539 		break;
5540 	}
5541 	return ext_mdio;
5542 }
5543 
5544 /**
5545  *  em_read_phy_reg_i2c - Read PHY register using i2c
5546  *  @hw: pointer to the HW structure
5547  *  @offset: register offset to be read
5548  *  @data: pointer to the read data
5549  *
5550  *  Reads the PHY register at offset using the i2c interface and stores the
5551  *  retrieved information in data.
5552  **/
5553 int32_t
em_read_phy_reg_i2c(struct em_hw * hw,uint32_t offset,uint16_t * data)5554 em_read_phy_reg_i2c(struct em_hw *hw, uint32_t offset, uint16_t *data)
5555 {
5556 	uint32_t i, i2ccmd = 0;
5557 
5558 	DEBUGFUNC("em_read_phy_reg_i2c");
5559 
5560 	/* Set up Op-code, Phy Address, and register address in the I2CCMD
5561 	 * register.  The MAC will take care of interfacing with the
5562 	 * PHY to retrieve the desired data.
5563 	 */
5564 	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
5565 		  (hw->phy_addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
5566 		  (E1000_I2CCMD_OPCODE_READ));
5567 
5568 	E1000_WRITE_REG(hw, I2CCMD, i2ccmd);
5569 
5570 	/* Poll the ready bit to see if the I2C read completed */
5571 	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
5572 		usec_delay(50);
5573 		i2ccmd = E1000_READ_REG(hw, I2CCMD);
5574 		if (i2ccmd & E1000_I2CCMD_READY)
5575 			break;
5576 	}
5577 	if (!(i2ccmd & E1000_I2CCMD_READY)) {
5578 		DEBUGOUT("I2CCMD Read did not complete\n");
5579 		return -E1000_ERR_PHY;
5580 	}
5581 	if (i2ccmd & E1000_I2CCMD_ERROR) {
5582 		DEBUGOUT("I2CCMD Error bit set\n");
5583 		return -E1000_ERR_PHY;
5584 	}
5585 
5586 	/* Need to byte-swap the 16-bit value. */
5587 	*data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
5588 
5589 	return E1000_SUCCESS;
5590 }
5591 
5592 /**
5593  *  em_write_phy_reg_i2c - Write PHY register using i2c
5594  *  @hw: pointer to the HW structure
5595  *  @offset: register offset to write to
5596  *  @data: data to write at register offset
5597  *
5598  *  Writes the data to PHY register at the offset using the i2c interface.
5599  **/
5600 int32_t
em_write_phy_reg_i2c(struct em_hw * hw,uint32_t offset,uint16_t data)5601 em_write_phy_reg_i2c(struct em_hw *hw, uint32_t offset, uint16_t data)
5602 {
5603 	uint32_t i, i2ccmd = 0;
5604 	uint16_t phy_data_swapped;
5605 
5606 	DEBUGFUNC("em_write_phy_reg_i2c");
5607 
5608 	/* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/
5609 	if ((hw->phy_addr == 0) || (hw->phy_addr > 7)) {
5610 		DEBUGOUT1("PHY I2C Address %d is out of range.\n",
5611 			  hw->phy_addr);
5612 		return -E1000_ERR_CONFIG;
5613 	}
5614 
5615 	/* Swap the data bytes for the I2C interface */
5616 	phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
5617 
5618 	/* Set up Op-code, Phy Address, and register address in the I2CCMD
5619 	 * register.  The MAC will take care of interfacing with the
5620 	 * PHY to retrieve the desired data.
5621 	 */
5622 	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
5623 		  (hw->phy_addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
5624 		  E1000_I2CCMD_OPCODE_WRITE |
5625 		  phy_data_swapped);
5626 
5627 	E1000_WRITE_REG(hw, I2CCMD, i2ccmd);
5628 
5629 	/* Poll the ready bit to see if the I2C read completed */
5630 	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
5631 		usec_delay(50);
5632 		i2ccmd = E1000_READ_REG(hw, I2CCMD);
5633 		if (i2ccmd & E1000_I2CCMD_READY)
5634 			break;
5635 	}
5636 	if (!(i2ccmd & E1000_I2CCMD_READY)) {
5637 		DEBUGOUT("I2CCMD Write did not complete\n");
5638 		return -E1000_ERR_PHY;
5639 	}
5640 	if (i2ccmd & E1000_I2CCMD_ERROR) {
5641 		DEBUGOUT("I2CCMD Error bit set\n");
5642 		return -E1000_ERR_PHY;
5643 	}
5644 
5645 	return E1000_SUCCESS;
5646 }
5647 
5648 /**
5649  *  em_read_sfp_data_byte - Reads SFP module data.
5650  *  @hw: pointer to the HW structure
5651  *  @offset: byte location offset to be read
5652  *  @data: read data buffer pointer
5653  *
5654  *  Reads one byte from SFP module data stored
5655  *  in SFP resided EEPROM memory or SFP diagnostic area.
5656  *  Function should be called with
5657  *  E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
5658  *  E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
5659  *  access
5660  **/
5661 int32_t
em_read_sfp_data_byte(struct em_hw * hw,uint16_t offset,uint8_t * data)5662 em_read_sfp_data_byte(struct em_hw *hw, uint16_t offset, uint8_t *data)
5663 {
5664 	uint32_t i = 0;
5665 	uint32_t i2ccmd = 0;
5666 	uint32_t data_local = 0;
5667 
5668 	DEBUGFUNC("em_read_sfp_data_byte");
5669 
5670 	if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
5671 		DEBUGOUT("I2CCMD command address exceeds upper limit\n");
5672 		return -E1000_ERR_PHY;
5673 	}
5674 
5675 	/* Set up Op-code, EEPROM Address,in the I2CCMD
5676 	 * register. The MAC will take care of interfacing with the
5677 	 * EEPROM to retrieve the desired data.
5678 	 */
5679 	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
5680 		  E1000_I2CCMD_OPCODE_READ);
5681 
5682 	E1000_WRITE_REG(hw, I2CCMD, i2ccmd);
5683 
5684 	/* Poll the ready bit to see if the I2C read completed */
5685 	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
5686 		usec_delay(50);
5687 		data_local = E1000_READ_REG(hw, I2CCMD);
5688 		if (data_local & E1000_I2CCMD_READY)
5689 			break;
5690 	}
5691 	if (!(data_local & E1000_I2CCMD_READY)) {
5692 		DEBUGOUT("I2CCMD Read did not complete\n");
5693 		return -E1000_ERR_PHY;
5694 	}
5695 	if (data_local & E1000_I2CCMD_ERROR) {
5696 		DEBUGOUT("I2CCMD Error bit set\n");
5697 		return -E1000_ERR_PHY;
5698 	}
5699 	*data = (uint8_t) data_local & 0xFF;
5700 
5701 	return E1000_SUCCESS;
5702 }
5703 
5704 /******************************************************************************
5705  * Returns the PHY to the power-on reset state
5706  *
5707  * hw - Struct containing variables accessed by shared code
5708  *****************************************************************************/
5709 int32_t
em_phy_hw_reset(struct em_hw * hw)5710 em_phy_hw_reset(struct em_hw *hw)
5711 {
5712 	uint32_t ctrl, ctrl_ext;
5713 	uint32_t led_ctrl;
5714 	int32_t  ret_val;
5715 	DEBUGFUNC("em_phy_hw_reset");
5716 	/*
5717 	 * In the case of the phy reset being blocked, it's not an error, we
5718 	 * simply return success without performing the reset.
5719 	 */
5720 	ret_val = em_check_phy_reset_block(hw);
5721 	if (ret_val)
5722 		return E1000_SUCCESS;
5723 
5724 	DEBUGOUT("Resetting Phy...\n");
5725 
5726 	if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) {
5727 		if (em_swfw_sync_acquire(hw, hw->swfw)) {
5728 			DEBUGOUT("Unable to acquire swfw sync\n");
5729 			return -E1000_ERR_SWFW_SYNC;
5730 		}
5731 		/*
5732 		 * Read the device control register and assert the
5733 		 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For
5734 		 * pre-em_82571 hardware, we delay for 10ms between the
5735 		 * assert and deassert.  For em_82571 hardware and later, we
5736 		 * instead delay for 50us between and 10ms after the
5737 		 * deassertion.
5738 		 */
5739 		ctrl = E1000_READ_REG(hw, CTRL);
5740 		E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
5741 		E1000_WRITE_FLUSH(hw);
5742 
5743 		if (hw->mac_type < em_82571)
5744 			msec_delay(10);
5745 		else
5746 			usec_delay(100);
5747 
5748 		E1000_WRITE_REG(hw, CTRL, ctrl);
5749 		E1000_WRITE_FLUSH(hw);
5750 
5751 		if (hw->mac_type >= em_82571)
5752 			msec_delay_irq(10);
5753 		em_swfw_sync_release(hw, hw->swfw);
5754 		/*
5755 		 * the M88E1141_E_PHY_ID might need reset here, but nothing
5756 		 * proves it
5757 		 */
5758 	} else {
5759 		/*
5760 		 * Read the Extended Device Control Register, assert the
5761 		 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it
5762 		 * out of reset.
5763 		 */
5764 		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5765 		ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
5766 		ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
5767 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5768 		E1000_WRITE_FLUSH(hw);
5769 		msec_delay(10);
5770 		ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
5771 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5772 		E1000_WRITE_FLUSH(hw);
5773 	}
5774 	usec_delay(150);
5775 
5776 	if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
5777 		/* Configure activity LED after PHY reset */
5778 		led_ctrl = E1000_READ_REG(hw, LEDCTL);
5779 		led_ctrl &= IGP_ACTIVITY_LED_MASK;
5780 		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
5781 		E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
5782 	}
5783 	/* Wait for FW to finish PHY configuration. */
5784 	ret_val = em_get_phy_cfg_done(hw);
5785 	if (ret_val != E1000_SUCCESS)
5786 		return ret_val;
5787 	em_release_software_semaphore(hw);
5788 
5789 	if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3))
5790 		ret_val = em_init_lcd_from_nvm(hw);
5791 
5792 	return ret_val;
5793 }
5794 
5795 /*****************************************************************************
5796  *  SW-based LCD Configuration.
5797  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
5798  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
5799  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
5800  *****************************************************************************/
5801 int32_t
em_oem_bits_config_pchlan(struct em_hw * hw,boolean_t d0_state)5802 em_oem_bits_config_pchlan(struct em_hw *hw, boolean_t d0_state)
5803 {
5804 	int32_t  ret_val = E1000_SUCCESS;
5805 	uint32_t mac_reg;
5806 	uint16_t oem_reg;
5807 	uint16_t swfw = E1000_SWFW_PHY0_SM;
5808 
5809 	if (hw->mac_type < em_pchlan)
5810 		return ret_val;
5811 
5812 	ret_val = em_swfw_sync_acquire(hw, swfw);
5813 	if (ret_val)
5814 		return ret_val;
5815 
5816 	if (hw->mac_type == em_pchlan) {
5817 		mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL);
5818 		if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
5819 			goto out;
5820 	}
5821 
5822 	mac_reg = E1000_READ_REG(hw, FEXTNVM);
5823 	if (!(mac_reg & FEXTNVM_SW_CONFIG_ICH8M))
5824 		goto out;
5825 
5826 	mac_reg = E1000_READ_REG(hw, PHY_CTRL);
5827 
5828 	ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg);
5829 	if (ret_val)
5830 		goto out;
5831 
5832 	oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
5833 
5834 	if (d0_state) {
5835 		if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
5836 			oem_reg |= HV_OEM_BITS_GBE_DIS;
5837 
5838 		if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
5839 			oem_reg |= HV_OEM_BITS_LPLU;
5840 		/* Restart auto-neg to activate the bits */
5841 		if (!em_check_phy_reset_block(hw))
5842 			oem_reg |= HV_OEM_BITS_RESTART_AN;
5843 
5844 	} else {
5845 		if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
5846 		    E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
5847 			oem_reg |= HV_OEM_BITS_GBE_DIS;
5848 
5849 		if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
5850 		    E1000_PHY_CTRL_NOND0A_LPLU))
5851 			oem_reg |= HV_OEM_BITS_LPLU;
5852 	}
5853 
5854 	ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg);
5855 
5856 out:
5857 	em_swfw_sync_release(hw, swfw);
5858 
5859 	return ret_val;
5860 }
5861 
5862 
5863 /******************************************************************************
5864  * Resets the PHY
5865  *
5866  * hw - Struct containing variables accessed by shared code
5867  *
5868  * Sets bit 15 of the MII Control register
5869  *****************************************************************************/
5870 int32_t
em_phy_reset(struct em_hw * hw)5871 em_phy_reset(struct em_hw *hw)
5872 {
5873 	int32_t  ret_val;
5874 	uint16_t phy_data;
5875 	DEBUGFUNC("em_phy_reset");
5876 	/*
5877 	 * In the case of the phy reset being blocked, it's not an error, we
5878 	 * simply return success without performing the reset.
5879 	 */
5880 	ret_val = em_check_phy_reset_block(hw);
5881 	if (ret_val)
5882 		return E1000_SUCCESS;
5883 
5884 	switch (hw->phy_type) {
5885 	case em_phy_igp:
5886 	case em_phy_igp_2:
5887 	case em_phy_igp_3:
5888 	case em_phy_ife:
5889 		ret_val = em_phy_hw_reset(hw);
5890 		if (ret_val)
5891 			return ret_val;
5892 		break;
5893 	default:
5894 		ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
5895 		if (ret_val)
5896 			return ret_val;
5897 
5898 		phy_data |= MII_CR_RESET;
5899 		ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
5900 		if (ret_val)
5901 			return ret_val;
5902 
5903 		usec_delay(1);
5904 		break;
5905 	}
5906 
5907 	/* Allow time for h/w to get to a quiescent state after reset */
5908 	msec_delay(10);
5909 
5910 	if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2)
5911 		em_phy_init_script(hw);
5912 
5913 	if (hw->mac_type == em_pchlan) {
5914 		ret_val = em_hv_phy_workarounds_ich8lan(hw);
5915 		if (ret_val)
5916 			return ret_val;
5917 	} else if (hw->mac_type == em_pch2lan) {
5918 		ret_val = em_lv_phy_workarounds_ich8lan(hw);
5919 		if (ret_val)
5920 			return ret_val;
5921 	}
5922 
5923 	if (hw->mac_type >= em_pchlan) {
5924 		ret_val = em_oem_bits_config_pchlan(hw, TRUE);
5925 		if (ret_val)
5926 			return ret_val;
5927 	}
5928 
5929 	/* Ungate automatic PHY configuration on non-managed 82579 */
5930 	if ((hw->mac_type == em_pch2lan) &&
5931 	    !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) {
5932 		msec_delay(10);
5933 		em_gate_hw_phy_config_ich8lan(hw, FALSE);
5934 	}
5935 
5936 	if (hw->phy_id == M88E1512_E_PHY_ID) {
5937 		ret_val = em_initialize_M88E1512_phy(hw);
5938 		if (ret_val)
5939 			return ret_val;
5940 	}
5941 
5942 	return E1000_SUCCESS;
5943 }
5944 
5945 /******************************************************************************
5946  * Work-around for 82566 Kumeran PCS lock loss:
5947  * On link status change (i.e. PCI reset, speed change) and link is up and
5948  * speed is gigabit-
5949  * 0) if workaround is optionally disabled do nothing
5950  * 1) wait 1ms for Kumeran link to come up
5951  * 2) check Kumeran Diagnostic register PCS lock loss bit
5952  * 3) if not set the link is locked (all is good), otherwise...
5953  * 4) reset the PHY
5954  * 5) repeat up to 10 times
5955  * Note: this is only called for IGP3 copper when speed is 1gb.
5956  *
5957  * hw - struct containing variables accessed by shared code
5958  *****************************************************************************/
5959 STATIC int32_t
em_kumeran_lock_loss_workaround(struct em_hw * hw)5960 em_kumeran_lock_loss_workaround(struct em_hw *hw)
5961 {
5962 	int32_t  ret_val;
5963 	int32_t  reg;
5964 	int32_t  cnt;
5965 	uint16_t phy_data;
5966 	if (hw->kmrn_lock_loss_workaround_disabled)
5967 		return E1000_SUCCESS;
5968 	/*
5969 	 * Make sure link is up before proceeding.  If not just return.
5970 	 * Attempting this while link is negotiating fouled up link stability
5971 	 */
5972 	ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
5973 	ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
5974 
5975 	if (phy_data & MII_SR_LINK_STATUS) {
5976 		for (cnt = 0; cnt < 10; cnt++) {
5977 			/* read once to clear */
5978 			ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG,
5979 			    &phy_data);
5980 			if (ret_val)
5981 				return ret_val;
5982 			/* and again to get new status */
5983 			ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
5984 			if (ret_val)
5985 				return ret_val;
5986 
5987 			/* check for PCS lock */
5988 			if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5989 				return E1000_SUCCESS;
5990 
5991 			/* Issue PHY reset */
5992 			em_phy_hw_reset(hw);
5993 			msec_delay_irq(5);
5994 		}
5995 		/* Disable GigE link negotiation */
5996 		reg = E1000_READ_REG(hw, PHY_CTRL);
5997 		E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE
5998 		    | E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5999 
6000 		/* unable to acquire PCS lock */
6001 		return E1000_ERR_PHY;
6002 	}
6003 	return E1000_SUCCESS;
6004 }
6005 
6006 /******************************************************************************
6007  * Reads and matches the expected PHY address for known PHY IDs
6008  *
6009  * hw - Struct containing variables accessed by shared code
6010  *****************************************************************************/
6011 STATIC int32_t
em_match_gig_phy(struct em_hw * hw)6012 em_match_gig_phy(struct em_hw *hw)
6013 {
6014 	int32_t   phy_init_status, ret_val;
6015 	uint16_t  phy_id_high, phy_id_low;
6016 	boolean_t match = FALSE;
6017 	DEBUGFUNC("em_match_gig_phy");
6018 
6019 	ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high);
6020 	if (ret_val)
6021 		return ret_val;
6022 
6023 	hw->phy_id = (uint32_t) (phy_id_high << 16);
6024 	usec_delay(20);
6025 	ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low);
6026 	if (ret_val)
6027 		return ret_val;
6028 
6029 	hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
6030 	hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
6031 
6032 	switch (hw->mac_type) {
6033 	case em_82543:
6034 		if (hw->phy_id == M88E1000_E_PHY_ID)
6035 			match = TRUE;
6036 		break;
6037 	case em_82544:
6038 		if (hw->phy_id == M88E1000_I_PHY_ID)
6039 			match = TRUE;
6040 		break;
6041 	case em_82540:
6042 	case em_82545:
6043 	case em_82545_rev_3:
6044 	case em_82546:
6045 	case em_82546_rev_3:
6046 		if (hw->phy_id == M88E1011_I_PHY_ID)
6047 			match = TRUE;
6048 		break;
6049 	case em_82541:
6050 	case em_82541_rev_2:
6051 	case em_82547:
6052 	case em_82547_rev_2:
6053 		if (hw->phy_id == IGP01E1000_I_PHY_ID)
6054 			match = TRUE;
6055 		break;
6056 	case em_82573:
6057 		if (hw->phy_id == M88E1111_I_PHY_ID)
6058 			match = TRUE;
6059 		break;
6060 	case em_82574:
6061 		if (hw->phy_id == BME1000_E_PHY_ID)
6062 			match = TRUE;
6063 		break;
6064 	case em_82575:
6065 	case em_82576:
6066 		if (hw->phy_id == M88E1000_E_PHY_ID)
6067 			match = TRUE;
6068 		if (hw->phy_id == IGP01E1000_I_PHY_ID)
6069 			match = TRUE;
6070 		if (hw->phy_id == IGP03E1000_E_PHY_ID)
6071 			match = TRUE;
6072 		break;
6073 	case em_82580:
6074 	case em_i210:
6075 	case em_i350:
6076 		if (hw->phy_id == I82580_I_PHY_ID ||
6077 		    hw->phy_id == I210_I_PHY_ID ||
6078 		    hw->phy_id == I347AT4_E_PHY_ID ||
6079 		    hw->phy_id == I350_I_PHY_ID ||
6080 		    hw->phy_id == M88E1111_I_PHY_ID ||
6081 		    hw->phy_id == M88E1112_E_PHY_ID ||
6082 		    hw->phy_id == M88E1543_E_PHY_ID ||
6083 		    hw->phy_id == M88E1512_E_PHY_ID) {
6084 			uint32_t mdic;
6085 
6086 			mdic = EM_READ_REG(hw, E1000_MDICNFG);
6087 			if (mdic & E1000_MDICNFG_EXT_MDIO) {
6088 				mdic &= E1000_MDICNFG_PHY_MASK;
6089 				hw->phy_addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
6090 				DEBUGOUT1("MDICNFG PHY ADDR %d",
6091 				    mdic >> E1000_MDICNFG_PHY_SHIFT);
6092 			}
6093 			match = TRUE;
6094 		}
6095 		break;
6096 	case em_80003es2lan:
6097 		if (hw->phy_id == GG82563_E_PHY_ID)
6098 			match = TRUE;
6099 		break;
6100 	case em_ich8lan:
6101 	case em_ich9lan:
6102 	case em_ich10lan:
6103 	case em_pchlan:
6104 	case em_pch2lan:
6105 		if (hw->phy_id == IGP03E1000_E_PHY_ID)
6106 			match = TRUE;
6107 		if (hw->phy_id == IFE_E_PHY_ID)
6108 			match = TRUE;
6109 		if (hw->phy_id == IFE_PLUS_E_PHY_ID)
6110 			match = TRUE;
6111 		if (hw->phy_id == IFE_C_E_PHY_ID)
6112 			match = TRUE;
6113 		if (hw->phy_id == BME1000_E_PHY_ID)
6114 			match = TRUE;
6115 		if (hw->phy_id == I82577_E_PHY_ID)
6116 			match = TRUE;
6117 		if (hw->phy_id == I82578_E_PHY_ID)
6118 			match = TRUE;
6119 		if (hw->phy_id == I82579_E_PHY_ID)
6120 			match = TRUE;
6121 		break;
6122 	case em_pch_lpt:
6123 	case em_pch_spt:
6124 	case em_pch_cnp:
6125 	case em_pch_tgp:
6126 	case em_pch_adp:
6127 		if (hw->phy_id == I217_E_PHY_ID)
6128 			match = TRUE;
6129 		break;
6130 	case em_icp_xxxx:
6131 		if (hw->phy_id == M88E1141_E_PHY_ID)
6132 			match = TRUE;
6133 		if (hw->phy_id == RTL8211_E_PHY_ID)
6134 			match = TRUE;
6135 		break;
6136 	default:
6137 		DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
6138 		return -E1000_ERR_CONFIG;
6139 	}
6140 	phy_init_status = em_set_phy_type(hw);
6141 
6142 	if ((match) && (phy_init_status == E1000_SUCCESS)) {
6143 		DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
6144 		return E1000_SUCCESS;
6145 	}
6146 	DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
6147 	return -E1000_ERR_PHY;
6148 }
6149 
6150 /******************************************************************************
6151  * Probes the expected PHY address for known PHY IDs
6152  *
6153  * hw - Struct containing variables accessed by shared code
6154  *****************************************************************************/
6155 STATIC int32_t
em_detect_gig_phy(struct em_hw * hw)6156 em_detect_gig_phy(struct em_hw *hw)
6157 {
6158 	int32_t ret_val, i;
6159 	DEBUGFUNC("em_detect_gig_phy");
6160 
6161 	if (hw->phy_id != 0)
6162 		return E1000_SUCCESS;
6163 
6164 	/* default phy address, most phys reside here, but not all (ICH10) */
6165 	if (hw->mac_type != em_icp_xxxx)
6166 		hw->phy_addr = 1;
6167 	else
6168 		hw->phy_addr = 0; /* There is a phy at phy_addr 0 on EP80579 */
6169 
6170 	/*
6171 	 * The 82571 firmware may still be configuring the PHY.  In this
6172 	 * case, we cannot access the PHY until the configuration is done.
6173 	 * So we explicitly set the PHY values.
6174 	 */
6175 	if (hw->mac_type == em_82571 ||
6176 	    hw->mac_type == em_82572) {
6177 		hw->phy_id = IGP01E1000_I_PHY_ID;
6178 		hw->phy_type = em_phy_igp_2;
6179 		return E1000_SUCCESS;
6180 	}
6181 
6182 	/*
6183 	 * Some of the fiber cards dont have a phy, so we must exit cleanly
6184 	 * here
6185 	 */
6186 	if ((hw->media_type == em_media_type_fiber) &&
6187 	    (hw->mac_type == em_82542_rev2_0 ||
6188 	    hw->mac_type == em_82542_rev2_1 ||
6189 	    hw->mac_type == em_82543 ||
6190 	    hw->mac_type == em_82573 ||
6191 	    hw->mac_type == em_82574 ||
6192 	    hw->mac_type == em_80003es2lan)) {
6193 		hw->phy_type = em_phy_undefined;
6194 		return E1000_SUCCESS;
6195 	}
6196 
6197 	if ((hw->media_type == em_media_type_internal_serdes ||
6198 	    hw->media_type == em_media_type_fiber) &&
6199 	    hw->mac_type >= em_82575) {
6200 		hw->phy_type = em_phy_undefined;
6201 		return E1000_SUCCESS;
6202 	}
6203 
6204 	/*
6205 	 * Up to 82543 (incl), we need reset the phy, or it might not get
6206 	 * detected
6207 	 */
6208 	if (hw->mac_type <= em_82543) {
6209 		ret_val = em_phy_hw_reset(hw);
6210 		if (ret_val)
6211 			return ret_val;
6212 	}
6213 	/*
6214 	 * ESB-2 PHY reads require em_phy_gg82563 to be set because of a
6215 	 * work- around that forces PHY page 0 to be set or the reads fail.
6216 	 * The rest of the code in this routine uses em_read_phy_reg to read
6217 	 * the PHY ID. So for ESB-2 we need to have this set so our reads
6218 	 * won't fail.  If the attached PHY is not a em_phy_gg82563, the
6219 	 * routines below will figure this out as well.
6220 	 */
6221 	if (hw->mac_type == em_80003es2lan)
6222 		hw->phy_type = em_phy_gg82563;
6223 
6224 	/* Power on SGMII phy if it is disabled */
6225 	if (hw->mac_type == em_82580 || hw->mac_type == em_i210 ||
6226 	    hw->mac_type == em_i350) {
6227 		uint32_t ctrl_ext = EM_READ_REG(hw, E1000_CTRL_EXT);
6228 		EM_WRITE_REG(hw, E1000_CTRL_EXT,
6229 		    ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
6230 		E1000_WRITE_FLUSH(hw);
6231 		msec_delay(300);
6232 	}
6233 
6234 	/* Read the PHY ID Registers to identify which PHY is onboard. */
6235 	for (i = 1; i < 8; i++) {
6236 		/*
6237 		 * hw->phy_addr may be modified down in the call stack,
6238 		 * we can't use it as loop variable.
6239 		 */
6240 		hw->phy_addr = i;
6241 		ret_val = em_match_gig_phy(hw);
6242 		if (ret_val == E1000_SUCCESS)
6243 			return E1000_SUCCESS;
6244 	}
6245 	return -E1000_ERR_PHY;
6246 }
6247 
6248 /******************************************************************************
6249  * Resets the PHY's DSP
6250  *
6251  * hw - Struct containing variables accessed by shared code
6252  *****************************************************************************/
6253 static int32_t
em_phy_reset_dsp(struct em_hw * hw)6254 em_phy_reset_dsp(struct em_hw *hw)
6255 {
6256 	int32_t ret_val;
6257 	DEBUGFUNC("em_phy_reset_dsp");
6258 
6259 	do {
6260 		if (hw->phy_type != em_phy_gg82563) {
6261 			ret_val = em_write_phy_reg(hw, 29, 0x001d);
6262 			if (ret_val)
6263 				break;
6264 		}
6265 		ret_val = em_write_phy_reg(hw, 30, 0x00c1);
6266 		if (ret_val)
6267 			break;
6268 		ret_val = em_write_phy_reg(hw, 30, 0x0000);
6269 		if (ret_val)
6270 			break;
6271 		ret_val = E1000_SUCCESS;
6272 	} while (0);
6273 
6274 	return ret_val;
6275 }
6276 
6277 /******************************************************************************
6278  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
6279  * is configured.  Additionally, if this is ICH8, the flash controller GbE
6280  * registers must be mapped, or this will crash.
6281  *
6282  * hw - Struct containing variables accessed by shared code
6283  *****************************************************************************/
6284 int32_t
em_init_eeprom_params(struct em_hw * hw)6285 em_init_eeprom_params(struct em_hw *hw)
6286 {
6287 	struct em_eeprom_info *eeprom = &hw->eeprom;
6288 	uint32_t eecd = E1000_READ_REG(hw, EECD);
6289 	int32_t  ret_val = E1000_SUCCESS;
6290 	uint16_t eeprom_size;
6291 	DEBUGFUNC("em_init_eeprom_params");
6292 
6293 	switch (hw->mac_type) {
6294 	case em_82542_rev2_0:
6295 	case em_82542_rev2_1:
6296 	case em_82543:
6297 	case em_82544:
6298 		eeprom->type = em_eeprom_microwire;
6299 		eeprom->word_size = 64;
6300 		eeprom->opcode_bits = 3;
6301 		eeprom->address_bits = 6;
6302 		eeprom->delay_usec = 50;
6303 		eeprom->use_eerd = FALSE;
6304 		eeprom->use_eewr = FALSE;
6305 		break;
6306 	case em_82540:
6307 	case em_82545:
6308 	case em_82545_rev_3:
6309 	case em_icp_xxxx:
6310 	case em_82546:
6311 	case em_82546_rev_3:
6312 		eeprom->type = em_eeprom_microwire;
6313 		eeprom->opcode_bits = 3;
6314 		eeprom->delay_usec = 50;
6315 		if (eecd & E1000_EECD_SIZE) {
6316 			eeprom->word_size = 256;
6317 			eeprom->address_bits = 8;
6318 		} else {
6319 			eeprom->word_size = 64;
6320 			eeprom->address_bits = 6;
6321 		}
6322 		eeprom->use_eerd = FALSE;
6323 		eeprom->use_eewr = FALSE;
6324 		break;
6325 	case em_82541:
6326 	case em_82541_rev_2:
6327 	case em_82547:
6328 	case em_82547_rev_2:
6329 		if (eecd & E1000_EECD_TYPE) {
6330 			eeprom->type = em_eeprom_spi;
6331 			eeprom->opcode_bits = 8;
6332 			eeprom->delay_usec = 1;
6333 			if (eecd & E1000_EECD_ADDR_BITS) {
6334 				eeprom->page_size = 32;
6335 				eeprom->address_bits = 16;
6336 			} else {
6337 				eeprom->page_size = 8;
6338 				eeprom->address_bits = 8;
6339 			}
6340 		} else {
6341 			eeprom->type = em_eeprom_microwire;
6342 			eeprom->opcode_bits = 3;
6343 			eeprom->delay_usec = 50;
6344 			if (eecd & E1000_EECD_ADDR_BITS) {
6345 				eeprom->word_size = 256;
6346 				eeprom->address_bits = 8;
6347 			} else {
6348 				eeprom->word_size = 64;
6349 				eeprom->address_bits = 6;
6350 			}
6351 		}
6352 		eeprom->use_eerd = FALSE;
6353 		eeprom->use_eewr = FALSE;
6354 		break;
6355 	case em_82571:
6356 	case em_82572:
6357 		eeprom->type = em_eeprom_spi;
6358 		eeprom->opcode_bits = 8;
6359 		eeprom->delay_usec = 1;
6360 		if (eecd & E1000_EECD_ADDR_BITS) {
6361 			eeprom->page_size = 32;
6362 			eeprom->address_bits = 16;
6363 		} else {
6364 			eeprom->page_size = 8;
6365 			eeprom->address_bits = 8;
6366 		}
6367 		eeprom->use_eerd = FALSE;
6368 		eeprom->use_eewr = FALSE;
6369 		break;
6370 	case em_82573:
6371 	case em_82574:
6372 	case em_82575:
6373 	case em_82576:
6374 	case em_82580:
6375 	case em_i210:
6376 	case em_i350:
6377 		eeprom->type = em_eeprom_spi;
6378 		eeprom->opcode_bits = 8;
6379 		eeprom->delay_usec = 1;
6380 		if (eecd & E1000_EECD_ADDR_BITS) {
6381 			eeprom->page_size = 32;
6382 			eeprom->address_bits = 16;
6383 		} else {
6384 			eeprom->page_size = 8;
6385 			eeprom->address_bits = 8;
6386 		}
6387 		eeprom->use_eerd = TRUE;
6388 		eeprom->use_eewr = TRUE;
6389 		if (em_is_onboard_nvm_eeprom(hw) == FALSE) {
6390 			eeprom->type = em_eeprom_flash;
6391 			eeprom->word_size = 2048;
6392 			/*
6393 			 * Ensure that the Autonomous FLASH update bit is
6394 			 * cleared due to Flash update issue on parts which
6395 			 * use a FLASH for NVM.
6396 			 */
6397 			eecd &= ~E1000_EECD_AUPDEN;
6398 			E1000_WRITE_REG(hw, EECD, eecd);
6399 		}
6400 		if (em_get_flash_presence_i210(hw) == FALSE) {
6401 			eeprom->type = em_eeprom_invm;
6402 			eeprom->word_size = INVM_SIZE;
6403 			eeprom->use_eerd = FALSE;
6404 			eeprom->use_eewr = FALSE;
6405 		}
6406 		break;
6407 	case em_80003es2lan:
6408 		eeprom->type = em_eeprom_spi;
6409 		eeprom->opcode_bits = 8;
6410 		eeprom->delay_usec = 1;
6411 		if (eecd & E1000_EECD_ADDR_BITS) {
6412 			eeprom->page_size = 32;
6413 			eeprom->address_bits = 16;
6414 		} else {
6415 			eeprom->page_size = 8;
6416 			eeprom->address_bits = 8;
6417 		}
6418 		eeprom->use_eerd = TRUE;
6419 		eeprom->use_eewr = FALSE;
6420 		break;
6421 	case em_ich8lan:
6422 	case em_ich9lan:
6423 	case em_ich10lan:
6424 	case em_pchlan:
6425 	case em_pch2lan:
6426 	case em_pch_lpt:
6427 		{
6428 			int32_t		i = 0;
6429 			uint32_t	flash_size =
6430 			    E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
6431 			eeprom->type = em_eeprom_ich8;
6432 			eeprom->use_eerd = FALSE;
6433 			eeprom->use_eewr = FALSE;
6434 			eeprom->word_size = E1000_SHADOW_RAM_WORDS;
6435 			/*
6436 			 * Zero the shadow RAM structure. But don't load it
6437 			 * from NVM so as to save time for driver init
6438 			 */
6439 			if (hw->eeprom_shadow_ram != NULL) {
6440 				for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
6441 					hw->eeprom_shadow_ram[i].modified =
6442 					    FALSE;
6443 					hw->eeprom_shadow_ram[i].eeprom_word =
6444 					    0xFFFF;
6445 				}
6446 			}
6447 			hw->flash_base_addr = (flash_size &
6448 			    ICH_GFPREG_BASE_MASK) * ICH_FLASH_SECTOR_SIZE;
6449 
6450 			hw->flash_bank_size = ((flash_size >> 16) &
6451 			    ICH_GFPREG_BASE_MASK) + 1;
6452 			hw->flash_bank_size -= (flash_size &
6453 			    ICH_GFPREG_BASE_MASK);
6454 
6455 			hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
6456 
6457 			hw->flash_bank_size /= 2 * sizeof(uint16_t);
6458 
6459 			break;
6460 		}
6461 	case em_pch_spt:
6462 	case em_pch_cnp:
6463 	case em_pch_tgp:
6464 	case em_pch_adp:
6465 		{
6466 			int32_t         i = 0;
6467 			uint32_t        flash_size = EM_READ_REG(hw, 0xc /* STRAP */);
6468 
6469 			eeprom->type = em_eeprom_ich8;
6470 			eeprom->use_eerd = FALSE;
6471 			eeprom->use_eewr = FALSE;
6472 			eeprom->word_size = E1000_SHADOW_RAM_WORDS;
6473 			/*
6474 			 * Zero the shadow RAM structure. But don't load it
6475 			 * from NVM so as to save time for driver init
6476 			 */
6477 			if (hw->eeprom_shadow_ram != NULL) {
6478 				for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
6479 					hw->eeprom_shadow_ram[i].modified =
6480 					    FALSE;
6481 					hw->eeprom_shadow_ram[i].eeprom_word =
6482 					    0xFFFF;
6483 				}
6484 			}
6485 			hw->flash_base_addr = 0;
6486 			flash_size = ((flash_size >> 1) & 0x1f) + 1;
6487 			flash_size *= 4096;
6488 			hw->flash_bank_size = flash_size / 4;
6489 		}
6490 		break;
6491 	default:
6492 		break;
6493 	}
6494 
6495 	if (eeprom->type == em_eeprom_spi) {
6496 		/*
6497 		 * eeprom_size will be an enum [0..8] that maps to eeprom
6498 		 * sizes 128B to 32KB (incremented by powers of 2).
6499 		 */
6500 		if (hw->mac_type <= em_82547_rev_2) {
6501 			/* Set to default value for initial eeprom read. */
6502 			eeprom->word_size = 64;
6503 			ret_val = em_read_eeprom(hw, EEPROM_CFG, 1,
6504 			    &eeprom_size);
6505 			if (ret_val)
6506 				return ret_val;
6507 			eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >>
6508 			    EEPROM_SIZE_SHIFT;
6509 			/*
6510 			 * 256B eeprom size was not supported in earlier
6511 			 * hardware, so we bump eeprom_size up one to ensure
6512 			 * that "1" (which maps to 256B) is never the result
6513 			 * used in the shifting logic below.
6514 			 */
6515 			if (eeprom_size)
6516 				eeprom_size++;
6517 		} else {
6518 			eeprom_size = (uint16_t) (
6519 			    (eecd & E1000_EECD_SIZE_EX_MASK) >>
6520 			    E1000_EECD_SIZE_EX_SHIFT);
6521 		}
6522 
6523 		/* EEPROM access above 16k is unsupported */
6524 		if (eeprom_size + EEPROM_WORD_SIZE_SHIFT >
6525 		    EEPROM_WORD_SIZE_SHIFT_MAX) {
6526 			eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX;
6527 		} else {
6528 			eeprom->word_size = 1 <<
6529 			    (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
6530 		}
6531 	}
6532 	return ret_val;
6533 }
6534 
6535 /******************************************************************************
6536  * Raises the EEPROM's clock input.
6537  *
6538  * hw - Struct containing variables accessed by shared code
6539  * eecd - EECD's current value
6540  *****************************************************************************/
6541 static void
em_raise_ee_clk(struct em_hw * hw,uint32_t * eecd)6542 em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd)
6543 {
6544 	/*
6545 	 * Raise the clock input to the EEPROM (by setting the SK bit), and
6546 	 * then wait <delay> microseconds.
6547 	 */
6548 	*eecd = *eecd | E1000_EECD_SK;
6549 	E1000_WRITE_REG(hw, EECD, *eecd);
6550 	E1000_WRITE_FLUSH(hw);
6551 	usec_delay(hw->eeprom.delay_usec);
6552 }
6553 
6554 /******************************************************************************
6555  * Lowers the EEPROM's clock input.
6556  *
6557  * hw - Struct containing variables accessed by shared code
6558  * eecd - EECD's current value
6559  *****************************************************************************/
6560 static void
em_lower_ee_clk(struct em_hw * hw,uint32_t * eecd)6561 em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd)
6562 {
6563 	/*
6564 	 * Lower the clock input to the EEPROM (by clearing the SK bit), and
6565 	 * then wait 50 microseconds.
6566 	 */
6567 	*eecd = *eecd & ~E1000_EECD_SK;
6568 	E1000_WRITE_REG(hw, EECD, *eecd);
6569 	E1000_WRITE_FLUSH(hw);
6570 	usec_delay(hw->eeprom.delay_usec);
6571 }
6572 
6573 /******************************************************************************
6574  * Shift data bits out to the EEPROM.
6575  *
6576  * hw - Struct containing variables accessed by shared code
6577  * data - data to send to the EEPROM
6578  * count - number of bits to shift out
6579  *****************************************************************************/
6580 static void
em_shift_out_ee_bits(struct em_hw * hw,uint16_t data,uint16_t count)6581 em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count)
6582 {
6583 	struct em_eeprom_info *eeprom = &hw->eeprom;
6584 	uint32_t eecd;
6585 	uint32_t mask;
6586 	/*
6587 	 * We need to shift "count" bits out to the EEPROM. So, value in the
6588 	 * "data" parameter will be shifted out to the EEPROM one bit at a
6589 	 * time. In order to do this, "data" must be broken down into bits.
6590 	 */
6591 	mask = 0x01 << (count - 1);
6592 	eecd = E1000_READ_REG(hw, EECD);
6593 	if (eeprom->type == em_eeprom_microwire) {
6594 		eecd &= ~E1000_EECD_DO;
6595 	} else if (eeprom->type == em_eeprom_spi) {
6596 		eecd |= E1000_EECD_DO;
6597 	}
6598 	do {
6599 		/*
6600 		 * A "1" is shifted out to the EEPROM by setting bit "DI" to
6601 		 * a "1", and then raising and then lowering the clock (the
6602 		 * SK bit controls the clock input to the EEPROM).  A "0" is
6603 		 * shifted out to the EEPROM by setting "DI" to "0" and then
6604 		 * raising and then lowering the clock.
6605 		 */
6606 		eecd &= ~E1000_EECD_DI;
6607 
6608 		if (data & mask)
6609 			eecd |= E1000_EECD_DI;
6610 
6611 		E1000_WRITE_REG(hw, EECD, eecd);
6612 		E1000_WRITE_FLUSH(hw);
6613 
6614 		usec_delay(eeprom->delay_usec);
6615 
6616 		em_raise_ee_clk(hw, &eecd);
6617 		em_lower_ee_clk(hw, &eecd);
6618 
6619 		mask = mask >> 1;
6620 
6621 	} while (mask);
6622 
6623 	/* We leave the "DI" bit set to "0" when we leave this routine. */
6624 	eecd &= ~E1000_EECD_DI;
6625 	E1000_WRITE_REG(hw, EECD, eecd);
6626 }
6627 
6628 /******************************************************************************
6629  * Shift data bits in from the EEPROM
6630  *
6631  * hw - Struct containing variables accessed by shared code
6632  *****************************************************************************/
6633 static uint16_t
em_shift_in_ee_bits(struct em_hw * hw,uint16_t count)6634 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count)
6635 {
6636 	uint32_t eecd;
6637 	uint32_t i;
6638 	uint16_t data;
6639 	/*
6640 	 * In order to read a register from the EEPROM, we need to shift
6641 	 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
6642 	 * the clock input to the EEPROM (setting the SK bit), and then
6643 	 * reading the value of the "DO" bit.  During this "shifting in"
6644 	 * process the "DI" bit should always be clear.
6645 	 */
6646 
6647 	eecd = E1000_READ_REG(hw, EECD);
6648 
6649 	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
6650 	data = 0;
6651 
6652 	for (i = 0; i < count; i++) {
6653 		data = data << 1;
6654 		em_raise_ee_clk(hw, &eecd);
6655 
6656 		eecd = E1000_READ_REG(hw, EECD);
6657 
6658 		eecd &= ~(E1000_EECD_DI);
6659 		if (eecd & E1000_EECD_DO)
6660 			data |= 1;
6661 
6662 		em_lower_ee_clk(hw, &eecd);
6663 	}
6664 
6665 	return data;
6666 }
6667 /******************************************************************************
6668  * Prepares EEPROM for access
6669  *
6670  * hw - Struct containing variables accessed by shared code
6671  *
6672  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
6673  * function should be called before issuing a command to the EEPROM.
6674  *****************************************************************************/
6675 static int32_t
em_acquire_eeprom(struct em_hw * hw)6676 em_acquire_eeprom(struct em_hw *hw)
6677 {
6678 	struct em_eeprom_info *eeprom = &hw->eeprom;
6679 	uint32_t eecd, i = 0;
6680 	DEBUGFUNC("em_acquire_eeprom");
6681 
6682 	if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
6683 		return -E1000_ERR_SWFW_SYNC;
6684 	eecd = E1000_READ_REG(hw, EECD);
6685 
6686 	if ((hw->mac_type != em_82573) && (hw->mac_type != em_82574)) {
6687 		/* Request EEPROM Access */
6688 		if (hw->mac_type > em_82544) {
6689 			eecd |= E1000_EECD_REQ;
6690 			E1000_WRITE_REG(hw, EECD, eecd);
6691 			eecd = E1000_READ_REG(hw, EECD);
6692 			while ((!(eecd & E1000_EECD_GNT)) &&
6693 			    (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
6694 				i++;
6695 				usec_delay(5);
6696 				eecd = E1000_READ_REG(hw, EECD);
6697 			}
6698 			if (!(eecd & E1000_EECD_GNT)) {
6699 				eecd &= ~E1000_EECD_REQ;
6700 				E1000_WRITE_REG(hw, EECD, eecd);
6701 				DEBUGOUT("Could not acquire EEPROM grant\n");
6702 				em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
6703 				return -E1000_ERR_EEPROM;
6704 			}
6705 		}
6706 	}
6707 
6708 	/* Setup EEPROM for Read/Write */
6709 	if (eeprom->type == em_eeprom_microwire) {
6710 		/* Clear SK and DI */
6711 		eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
6712 		E1000_WRITE_REG(hw, EECD, eecd);
6713 
6714 		/* Set CS */
6715 		eecd |= E1000_EECD_CS;
6716 		E1000_WRITE_REG(hw, EECD, eecd);
6717 	} else if (eeprom->type == em_eeprom_spi) {
6718 		/* Clear SK and CS */
6719 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
6720 		E1000_WRITE_REG(hw, EECD, eecd);
6721 		usec_delay(1);
6722 	}
6723 	return E1000_SUCCESS;
6724 }
6725 
6726 /******************************************************************************
6727  * Returns EEPROM to a "standby" state
6728  *
6729  * hw - Struct containing variables accessed by shared code
6730  *****************************************************************************/
6731 static void
em_standby_eeprom(struct em_hw * hw)6732 em_standby_eeprom(struct em_hw *hw)
6733 {
6734 	struct em_eeprom_info *eeprom = &hw->eeprom;
6735 	uint32_t eecd;
6736 	eecd = E1000_READ_REG(hw, EECD);
6737 
6738 	if (eeprom->type == em_eeprom_microwire) {
6739 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
6740 		E1000_WRITE_REG(hw, EECD, eecd);
6741 		E1000_WRITE_FLUSH(hw);
6742 		usec_delay(eeprom->delay_usec);
6743 
6744 		/* Clock high */
6745 		eecd |= E1000_EECD_SK;
6746 		E1000_WRITE_REG(hw, EECD, eecd);
6747 		E1000_WRITE_FLUSH(hw);
6748 		usec_delay(eeprom->delay_usec);
6749 
6750 		/* Select EEPROM */
6751 		eecd |= E1000_EECD_CS;
6752 		E1000_WRITE_REG(hw, EECD, eecd);
6753 		E1000_WRITE_FLUSH(hw);
6754 		usec_delay(eeprom->delay_usec);
6755 
6756 		/* Clock low */
6757 		eecd &= ~E1000_EECD_SK;
6758 		E1000_WRITE_REG(hw, EECD, eecd);
6759 		E1000_WRITE_FLUSH(hw);
6760 		usec_delay(eeprom->delay_usec);
6761 	} else if (eeprom->type == em_eeprom_spi) {
6762 		/* Toggle CS to flush commands */
6763 		eecd |= E1000_EECD_CS;
6764 		E1000_WRITE_REG(hw, EECD, eecd);
6765 		E1000_WRITE_FLUSH(hw);
6766 		usec_delay(eeprom->delay_usec);
6767 		eecd &= ~E1000_EECD_CS;
6768 		E1000_WRITE_REG(hw, EECD, eecd);
6769 		E1000_WRITE_FLUSH(hw);
6770 		usec_delay(eeprom->delay_usec);
6771 	}
6772 }
6773 
6774 /******************************************************************************
6775  * Terminates a command by inverting the EEPROM's chip select pin
6776  *
6777  * hw - Struct containing variables accessed by shared code
6778  *****************************************************************************/
6779 static void
em_release_eeprom(struct em_hw * hw)6780 em_release_eeprom(struct em_hw *hw)
6781 {
6782 	uint32_t eecd;
6783 	DEBUGFUNC("em_release_eeprom");
6784 
6785 	eecd = E1000_READ_REG(hw, EECD);
6786 
6787 	if (hw->eeprom.type == em_eeprom_spi) {
6788 		eecd |= E1000_EECD_CS;	/* Pull CS high */
6789 		eecd &= ~E1000_EECD_SK;	/* Lower SCK */
6790 
6791 		E1000_WRITE_REG(hw, EECD, eecd);
6792 
6793 		usec_delay(hw->eeprom.delay_usec);
6794 	} else if (hw->eeprom.type == em_eeprom_microwire) {
6795 		/* cleanup eeprom */
6796 
6797 		/* CS on Microwire is active-high */
6798 		eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
6799 
6800 		E1000_WRITE_REG(hw, EECD, eecd);
6801 
6802 		/* Rising edge of clock */
6803 		eecd |= E1000_EECD_SK;
6804 		E1000_WRITE_REG(hw, EECD, eecd);
6805 		E1000_WRITE_FLUSH(hw);
6806 		usec_delay(hw->eeprom.delay_usec);
6807 
6808 		/* Falling edge of clock */
6809 		eecd &= ~E1000_EECD_SK;
6810 		E1000_WRITE_REG(hw, EECD, eecd);
6811 		E1000_WRITE_FLUSH(hw);
6812 		usec_delay(hw->eeprom.delay_usec);
6813 	}
6814 	/* Stop requesting EEPROM access */
6815 	if (hw->mac_type > em_82544) {
6816 		eecd &= ~E1000_EECD_REQ;
6817 		E1000_WRITE_REG(hw, EECD, eecd);
6818 	}
6819 	em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
6820 }
6821 
6822 /******************************************************************************
6823  * Reads a 16 bit word from the EEPROM.
6824  *
6825  * hw - Struct containing variables accessed by shared code
6826  *****************************************************************************/
6827 STATIC int32_t
em_spi_eeprom_ready(struct em_hw * hw)6828 em_spi_eeprom_ready(struct em_hw *hw)
6829 {
6830 	uint16_t retry_count = 0;
6831 	uint8_t  spi_stat_reg;
6832 	DEBUGFUNC("em_spi_eeprom_ready");
6833 	/*
6834 	 * Read "Status Register" repeatedly until the LSB is cleared.  The
6835 	 * EEPROM will signal that the command has been completed by clearing
6836 	 * bit 0 of the internal status register.  If it's not cleared within
6837 	 * 5 milliseconds, then error out.
6838 	 */
6839 	retry_count = 0;
6840 	do {
6841 		em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
6842 		    hw->eeprom.opcode_bits);
6843 		spi_stat_reg = (uint8_t) em_shift_in_ee_bits(hw, 8);
6844 		if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
6845 			break;
6846 
6847 		usec_delay(5);
6848 		retry_count += 5;
6849 
6850 		em_standby_eeprom(hw);
6851 	} while (retry_count < EEPROM_MAX_RETRY_SPI);
6852 	/*
6853 	 * ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
6854 	 * only 0-5mSec on 5V devices)
6855 	 */
6856 	if (retry_count >= EEPROM_MAX_RETRY_SPI) {
6857 		DEBUGOUT("SPI EEPROM Status error\n");
6858 		return -E1000_ERR_EEPROM;
6859 	}
6860 	return E1000_SUCCESS;
6861 }
6862 
6863 /******************************************************************************
6864  * Reads a 16 bit word from the EEPROM.
6865  *
6866  * hw - Struct containing variables accessed by shared code
6867  * offset - offset of  word in the EEPROM to read
6868  * data - word read from the EEPROM
6869  * words - number of words to read
6870  *****************************************************************************/
6871 int32_t
em_read_eeprom(struct em_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)6872 em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words,
6873     uint16_t *data)
6874 {
6875 	struct em_eeprom_info *eeprom = &hw->eeprom;
6876 	uint32_t i = 0;
6877 	DEBUGFUNC("em_read_eeprom");
6878 
6879 	/* If eeprom is not yet detected, do so now */
6880 	if (eeprom->word_size == 0)
6881 		em_init_eeprom_params(hw);
6882 	/*
6883 	 * A check for invalid values:  offset too large, too many words, and
6884 	 * not enough words.
6885 	 */
6886 	if ((offset >= eeprom->word_size) ||
6887 	    (words > eeprom->word_size - offset) ||
6888 	    (words == 0)) {
6889 		DEBUGOUT2("\"words\" parameter out of bounds. Words = %d,"
6890 		    " size = %d\n", offset, eeprom->word_size);
6891 		return -E1000_ERR_EEPROM;
6892 	}
6893 	/*
6894 	 * EEPROM's that don't use EERD to read require us to bit-bang the
6895 	 * SPI directly. In this case, we need to acquire the EEPROM so that
6896 	 * FW or other port software does not interrupt.
6897 	 */
6898 	if (em_is_onboard_nvm_eeprom(hw) == TRUE &&
6899 	    em_get_flash_presence_i210(hw) == TRUE &&
6900 	    hw->eeprom.use_eerd == FALSE) {
6901 		/* Prepare the EEPROM for bit-bang reading */
6902 		if (em_acquire_eeprom(hw) != E1000_SUCCESS)
6903 			return -E1000_ERR_EEPROM;
6904 	}
6905 	/* Eerd register EEPROM access requires no eeprom acquire/release */
6906 	if (eeprom->use_eerd == TRUE)
6907 		return em_read_eeprom_eerd(hw, offset, words, data);
6908 
6909 	/* ICH EEPROM access is done via the ICH flash controller */
6910 	if (eeprom->type == em_eeprom_ich8)
6911 		return em_read_eeprom_ich8(hw, offset, words, data);
6912 
6913 	/* Some i210/i211 have a special OTP chip */
6914 	if (eeprom->type == em_eeprom_invm)
6915 		return em_read_invm_i210(hw, offset, words, data);
6916 
6917 	/*
6918 	 * Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
6919 	 * acquired the EEPROM at this point, so any returns should release it
6920 	 */
6921 	if (eeprom->type == em_eeprom_spi) {
6922 		uint16_t word_in;
6923 		uint8_t  read_opcode = EEPROM_READ_OPCODE_SPI;
6924 		if (em_spi_eeprom_ready(hw)) {
6925 			em_release_eeprom(hw);
6926 			return -E1000_ERR_EEPROM;
6927 		}
6928 		em_standby_eeprom(hw);
6929 		/*
6930 		 * Some SPI eeproms use the 8th address bit embedded in the
6931 		 * opcode
6932 		 */
6933 		if ((eeprom->address_bits == 8) && (offset >= 128))
6934 			read_opcode |= EEPROM_A8_OPCODE_SPI;
6935 
6936 		/* Send the READ command (opcode + addr)  */
6937 		em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
6938 		em_shift_out_ee_bits(hw, (uint16_t) (offset * 2),
6939 		    eeprom->address_bits);
6940 		/*
6941 		 * Read the data.  The address of the eeprom internally
6942 		 * increments with each byte (spi) being read, saving on the
6943 		 * overhead of eeprom setup and tear-down.  The address
6944 		 * counter will roll over if reading beyond the size of the
6945 		 * eeprom, thus allowing the entire memory to be read
6946 		 * starting from any offset.
6947 		 */
6948 		for (i = 0; i < words; i++) {
6949 			word_in = em_shift_in_ee_bits(hw, 16);
6950 			data[i] = (word_in >> 8) | (word_in << 8);
6951 		}
6952 	} else if (eeprom->type == em_eeprom_microwire) {
6953 		for (i = 0; i < words; i++) {
6954 			/* Send the READ command (opcode + addr)  */
6955 			em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
6956 			    eeprom->opcode_bits);
6957 			em_shift_out_ee_bits(hw, (uint16_t) (offset + i),
6958 			    eeprom->address_bits);
6959 			/*
6960 			 * Read the data.  For microwire, each word requires
6961 			 * the overhead of eeprom setup and tear-down.
6962 			 */
6963 			data[i] = em_shift_in_ee_bits(hw, 16);
6964 			em_standby_eeprom(hw);
6965 		}
6966 	}
6967 	/* End this read operation */
6968 	em_release_eeprom(hw);
6969 
6970 	return E1000_SUCCESS;
6971 }
6972 
6973 /******************************************************************************
6974  * Reads a 16 bit word from the EEPROM using the EERD register.
6975  *
6976  * hw - Struct containing variables accessed by shared code
6977  * offset - offset of  word in the EEPROM to read
6978  * data - word read from the EEPROM
6979  * words - number of words to read
6980  *****************************************************************************/
6981 STATIC int32_t
em_read_eeprom_eerd(struct em_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)6982 em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words,
6983     uint16_t *data)
6984 {
6985 	uint32_t i, eerd = 0;
6986 	int32_t  error = 0;
6987 	for (i = 0; i < words; i++) {
6988 		eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) +
6989 		    E1000_EEPROM_RW_REG_START;
6990 
6991 		E1000_WRITE_REG(hw, EERD, eerd);
6992 		error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
6993 
6994 		if (error) {
6995 			break;
6996 		}
6997 		data[i] = (E1000_READ_REG(hw, EERD) >>
6998 		    E1000_EEPROM_RW_REG_DATA);
6999 
7000 	}
7001 
7002 	return error;
7003 }
7004 
7005 /******************************************************************************
7006  * Writes a 16 bit word from the EEPROM using the EEWR register.
7007  *
7008  * hw - Struct containing variables accessed by shared code
7009  * offset - offset of  word in the EEPROM to read
7010  * data - word read from the EEPROM
7011  * words - number of words to read
7012  *****************************************************************************/
7013 STATIC int32_t
em_write_eeprom_eewr(struct em_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)7014 em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words,
7015     uint16_t *data)
7016 {
7017 	uint32_t register_value = 0;
7018 	uint32_t i = 0;
7019 	int32_t  error = 0;
7020 	if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
7021 		return -E1000_ERR_SWFW_SYNC;
7022 
7023 	for (i = 0; i < words; i++) {
7024 		register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
7025 		    ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) |
7026 		    E1000_EEPROM_RW_REG_START;
7027 
7028 		error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
7029 		if (error) {
7030 			break;
7031 		}
7032 		E1000_WRITE_REG(hw, EEWR, register_value);
7033 
7034 		error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
7035 
7036 		if (error) {
7037 			break;
7038 		}
7039 	}
7040 
7041 	em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
7042 	return error;
7043 }
7044 
7045 /******************************************************************************
7046  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
7047  *
7048  * hw - Struct containing variables accessed by shared code
7049  *****************************************************************************/
7050 STATIC int32_t
em_poll_eerd_eewr_done(struct em_hw * hw,int eerd)7051 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd)
7052 {
7053 	uint32_t attempts = 100000;
7054 	uint32_t i, reg = 0;
7055 	int32_t  done = E1000_ERR_EEPROM;
7056 	for (i = 0; i < attempts; i++) {
7057 		if (eerd == E1000_EEPROM_POLL_READ)
7058 			reg = E1000_READ_REG(hw, EERD);
7059 		else
7060 			reg = E1000_READ_REG(hw, EEWR);
7061 
7062 		if (reg & E1000_EEPROM_RW_REG_DONE) {
7063 			done = E1000_SUCCESS;
7064 			break;
7065 		}
7066 		usec_delay(5);
7067 	}
7068 
7069 	return done;
7070 }
7071 
7072 /******************************************************************************
7073  * Description:     Determines if the onboard NVM is FLASH or EEPROM.
7074  *
7075  * hw - Struct containing variables accessed by shared code
7076  *****************************************************************************/
7077 STATIC boolean_t
em_is_onboard_nvm_eeprom(struct em_hw * hw)7078 em_is_onboard_nvm_eeprom(struct em_hw *hw)
7079 {
7080 	uint32_t eecd = 0;
7081 	DEBUGFUNC("em_is_onboard_nvm_eeprom");
7082 
7083 	if (IS_ICH8(hw->mac_type))
7084 		return FALSE;
7085 
7086 	if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
7087 		eecd = E1000_READ_REG(hw, EECD);
7088 
7089 		/* Isolate bits 15 & 16 */
7090 		eecd = ((eecd >> 15) & 0x03);
7091 
7092 		/* If both bits are set, device is Flash type */
7093 		if (eecd == 0x03) {
7094 			return FALSE;
7095 		}
7096 	}
7097 	return TRUE;
7098 }
7099 
7100 /******************************************************************************
7101  * Check if flash device is detected.
7102  *
7103  * hw - Struct containing variables accessed by shared code
7104  *****************************************************************************/
7105 boolean_t
em_get_flash_presence_i210(struct em_hw * hw)7106 em_get_flash_presence_i210(struct em_hw *hw)
7107 {
7108 	uint32_t eecd;
7109 	DEBUGFUNC("em_get_flash_presence_i210");
7110 
7111 	if (hw->mac_type != em_i210)
7112 		return TRUE;
7113 
7114 	eecd = E1000_READ_REG(hw, EECD);
7115 
7116 	if (eecd & E1000_EECD_FLUPD)
7117 		return TRUE;
7118 
7119 	return FALSE;
7120 }
7121 
7122 /******************************************************************************
7123  * Verifies that the EEPROM has a valid checksum
7124  *
7125  * hw - Struct containing variables accessed by shared code
7126  *
7127  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
7128  * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
7129  * valid.
7130  *****************************************************************************/
7131 int32_t
em_validate_eeprom_checksum(struct em_hw * hw)7132 em_validate_eeprom_checksum(struct em_hw *hw)
7133 {
7134 	uint16_t checksum = 0;
7135 	uint16_t i, eeprom_data;
7136 	uint16_t checksum_reg;
7137 	DEBUGFUNC("em_validate_eeprom_checksum");
7138 
7139 	checksum_reg = hw->mac_type != em_icp_xxxx ?
7140 	    EEPROM_CHECKSUM_REG :
7141 	    EEPROM_CHECKSUM_REG_ICP_xxxx;
7142 
7143 	if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) &&
7144 	    (em_is_onboard_nvm_eeprom(hw) == FALSE)) {
7145 		/*
7146 		 * Check bit 4 of word 10h.  If it is 0, firmware is done
7147 		 * updating 10h-12h.  Checksum may need to be fixed.
7148 		 */
7149 		em_read_eeprom(hw, 0x10, 1, &eeprom_data);
7150 		if ((eeprom_data & 0x10) == 0) {
7151 			/*
7152 			 * Read 0x23 and check bit 15.  This bit is a 1 when
7153 			 * the checksum has already been fixed.  If the
7154 			 * checksum is still wrong and this bit is a 1, we
7155 			 * need to return bad checksum.  Otherwise, we need
7156 			 * to set this bit to a 1 and update the checksum.
7157 			 */
7158 			em_read_eeprom(hw, 0x23, 1, &eeprom_data);
7159 			if ((eeprom_data & 0x8000) == 0) {
7160 				eeprom_data |= 0x8000;
7161 				em_write_eeprom(hw, 0x23, 1, &eeprom_data);
7162 				em_update_eeprom_checksum(hw);
7163 			}
7164 		}
7165 	}
7166 	if (IS_ICH8(hw->mac_type)) {
7167 		uint16_t word;
7168 		uint16_t valid_csum_mask;
7169 
7170 		/*
7171 		 * Drivers must allocate the shadow ram structure for the
7172 		 * EEPROM checksum to be updated.  Otherwise, this bit as
7173 		 * well as the checksum must both be set correctly for this
7174 		 * validation to pass.
7175 		 */
7176 		switch (hw->mac_type) {
7177 		case em_pch_lpt:
7178 		case em_pch_spt:
7179 		case em_pch_cnp:
7180 		case em_pch_tgp:
7181 		case em_pch_adp:
7182 			word = EEPROM_COMPAT;
7183 			valid_csum_mask = EEPROM_COMPAT_VALID_CSUM;
7184 			break;
7185 		default:
7186 			word = EEPROM_FUTURE_INIT_WORD1;
7187 			valid_csum_mask = EEPROM_FUTURE_INIT_WORD1_VALID_CSUM;
7188 			break;
7189 		}
7190 		em_read_eeprom(hw, word, 1, &eeprom_data);
7191 		if ((eeprom_data & valid_csum_mask) == 0) {
7192 			eeprom_data |= valid_csum_mask;
7193 			em_write_eeprom(hw, word, 1, &eeprom_data);
7194 			em_update_eeprom_checksum(hw);
7195 		}
7196 	}
7197 	for (i = 0; i < (checksum_reg + 1); i++) {
7198 		if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
7199 			DEBUGOUT("EEPROM Read Error\n");
7200 			return -E1000_ERR_EEPROM;
7201 		}
7202 		checksum += eeprom_data;
7203 	}
7204 
7205 	if (checksum == (uint16_t) EEPROM_SUM)
7206 		return E1000_SUCCESS;
7207 	else {
7208 		DEBUGOUT("EEPROM Checksum Invalid\n");
7209 		return -E1000_ERR_EEPROM;
7210 	}
7211 }
7212 
7213 /******************************************************************************
7214  * Calculates the EEPROM checksum and writes it to the EEPROM
7215  *
7216  * hw - Struct containing variables accessed by shared code
7217  *
7218  * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
7219  * Writes the difference to word offset 63 of the EEPROM.
7220  *****************************************************************************/
7221 int32_t
em_update_eeprom_checksum(struct em_hw * hw)7222 em_update_eeprom_checksum(struct em_hw *hw)
7223 {
7224 	uint32_t ctrl_ext;
7225 	uint16_t checksum = 0;
7226 	uint16_t i, eeprom_data;
7227 	DEBUGFUNC("em_update_eeprom_checksum");
7228 
7229 	for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
7230 		if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
7231 			DEBUGOUT("EEPROM Read Error\n");
7232 			return -E1000_ERR_EEPROM;
7233 		}
7234 		checksum += eeprom_data;
7235 	}
7236 	checksum = (uint16_t) EEPROM_SUM - checksum;
7237 	if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
7238 		DEBUGOUT("EEPROM Write Error\n");
7239 		return -E1000_ERR_EEPROM;
7240 	} else if (hw->eeprom.type == em_eeprom_flash) {
7241 		em_commit_shadow_ram(hw);
7242 	} else if (hw->eeprom.type == em_eeprom_ich8) {
7243 		em_commit_shadow_ram(hw);
7244 		/*
7245 		 * Reload the EEPROM, or else modifications will not appear
7246 		 * until after next adapter reset.
7247 		 */
7248 		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
7249 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;
7250 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
7251 		msec_delay(10);
7252 	}
7253 	return E1000_SUCCESS;
7254 }
7255 
7256 /******************************************************************************
7257  * Parent function for writing words to the different EEPROM types.
7258  *
7259  * hw - Struct containing variables accessed by shared code
7260  * offset - offset within the EEPROM to be written to
7261  * words - number of words to write
7262  * data - 16 bit word to be written to the EEPROM
7263  *
7264  * If em_update_eeprom_checksum is not called after this function, the
7265  * EEPROM will most likely contain an invalid checksum.
7266  *****************************************************************************/
7267 int32_t
em_write_eeprom(struct em_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)7268 em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words,
7269     uint16_t *data)
7270 {
7271 	struct em_eeprom_info *eeprom = &hw->eeprom;
7272 	int32_t status = 0;
7273 	DEBUGFUNC("em_write_eeprom");
7274 
7275 	/* If eeprom is not yet detected, do so now */
7276 	if (eeprom->word_size == 0)
7277 		em_init_eeprom_params(hw);
7278 	/*
7279 	 * A check for invalid values:  offset too large, too many words, and
7280 	 * not enough words.
7281 	 */
7282 	if ((offset >= eeprom->word_size) ||
7283 	    (words > eeprom->word_size - offset) ||
7284 	    (words == 0)) {
7285 		DEBUGOUT("\"words\" parameter out of bounds\n");
7286 		return -E1000_ERR_EEPROM;
7287 	}
7288 	/* 82573/4 writes only through eewr */
7289 	if (eeprom->use_eewr == TRUE)
7290 		return em_write_eeprom_eewr(hw, offset, words, data);
7291 
7292 	if (eeprom->type == em_eeprom_ich8)
7293 		return em_write_eeprom_ich8(hw, offset, words, data);
7294 
7295 	/* Prepare the EEPROM for writing  */
7296 	if (em_acquire_eeprom(hw) != E1000_SUCCESS)
7297 		return -E1000_ERR_EEPROM;
7298 
7299 	if (eeprom->type == em_eeprom_microwire) {
7300 		status = em_write_eeprom_microwire(hw, offset, words, data);
7301 	} else {
7302 		status = em_write_eeprom_spi(hw, offset, words, data);
7303 		msec_delay(10);
7304 	}
7305 
7306 	/* Done with writing */
7307 	em_release_eeprom(hw);
7308 
7309 	return status;
7310 }
7311 
7312 /******************************************************************************
7313  * Writes a 16 bit word to a given offset in an SPI EEPROM.
7314  *
7315  * hw - Struct containing variables accessed by shared code
7316  * offset - offset within the EEPROM to be written to
7317  * words - number of words to write
7318  * data - pointer to array of 8 bit words to be written to the EEPROM
7319  *
7320  *****************************************************************************/
7321 STATIC int32_t
em_write_eeprom_spi(struct em_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)7322 em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words,
7323     uint16_t *data)
7324 {
7325 	struct em_eeprom_info *eeprom = &hw->eeprom;
7326 	uint16_t widx = 0;
7327 	DEBUGFUNC("em_write_eeprom_spi");
7328 
7329 	while (widx < words) {
7330 		uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
7331 		if (em_spi_eeprom_ready(hw))
7332 			return -E1000_ERR_EEPROM;
7333 
7334 		em_standby_eeprom(hw);
7335 
7336 		/* Send the WRITE ENABLE command (8 bit opcode )  */
7337 		em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
7338 		    eeprom->opcode_bits);
7339 
7340 		em_standby_eeprom(hw);
7341 		/*
7342 		 * Some SPI eeproms use the 8th address bit embedded in the
7343 		 * opcode
7344 		 */
7345 		if ((eeprom->address_bits == 8) && (offset >= 128))
7346 			write_opcode |= EEPROM_A8_OPCODE_SPI;
7347 
7348 		/* Send the Write command (8-bit opcode + addr) */
7349 		em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
7350 
7351 		em_shift_out_ee_bits(hw, (uint16_t) ((offset + widx) * 2),
7352 		    eeprom->address_bits);
7353 
7354 		/* Send the data */
7355 		/*
7356 		 * Loop to allow for up to whole page write (32 bytes) of
7357 		 * eeprom
7358 		 */
7359 		while (widx < words) {
7360 			uint16_t word_out = data[widx];
7361 			word_out = (word_out >> 8) | (word_out << 8);
7362 			em_shift_out_ee_bits(hw, word_out, 16);
7363 			widx++;
7364 			/*
7365 			 * Some larger eeprom sizes are capable of a 32-byte
7366 			 * PAGE WRITE operation, while the smaller eeproms
7367 			 * are capable of an 8-byte PAGE WRITE operation.
7368 			 * Break the inner loop to pass new address
7369 			 */
7370 			if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
7371 				em_standby_eeprom(hw);
7372 				break;
7373 			}
7374 		}
7375 	}
7376 
7377 	return E1000_SUCCESS;
7378 }
7379 
7380 /******************************************************************************
7381  * Writes a 16 bit word to a given offset in a Microwire EEPROM.
7382  *
7383  * hw - Struct containing variables accessed by shared code
7384  * offset - offset within the EEPROM to be written to
7385  * words - number of words to write
7386  * data - pointer to array of 16 bit words to be written to the EEPROM
7387  *
7388  *****************************************************************************/
7389 STATIC int32_t
em_write_eeprom_microwire(struct em_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)7390 em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words,
7391     uint16_t *data)
7392 {
7393 	struct em_eeprom_info *eeprom = &hw->eeprom;
7394 	uint32_t eecd;
7395 	uint16_t words_written = 0;
7396 	uint16_t i = 0;
7397 	DEBUGFUNC("em_write_eeprom_microwire");
7398 	/*
7399 	 * Send the write enable command to the EEPROM (3-bit opcode plus
7400 	 * 6/8-bit dummy address beginning with 11).  It's less work to
7401 	 * include the 11 of the dummy address as part of the opcode than it
7402 	 * is to shift it over the correct number of bits for the address.
7403 	 * This puts the EEPROM into write/erase mode.
7404 	 */
7405 	em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
7406 	    (uint16_t) (eeprom->opcode_bits + 2));
7407 
7408 	em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2));
7409 
7410 	/* Prepare the EEPROM */
7411 	em_standby_eeprom(hw);
7412 
7413 	while (words_written < words) {
7414 		/* Send the Write command (3-bit opcode + addr) */
7415 		em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
7416 		    eeprom->opcode_bits);
7417 
7418 		em_shift_out_ee_bits(hw, (uint16_t) (offset + words_written),
7419 		    eeprom->address_bits);
7420 
7421 		/* Send the data */
7422 		em_shift_out_ee_bits(hw, data[words_written], 16);
7423 		/*
7424 		 * Toggle the CS line.  This in effect tells the EEPROM to
7425 		 * execute the previous command.
7426 		 */
7427 		em_standby_eeprom(hw);
7428 		/*
7429 		 * Read DO repeatedly until it is high (equal to '1').  The
7430 		 * EEPROM will signal that the command has been completed by
7431 		 * raising the DO signal. If DO does not go high in 10
7432 		 * milliseconds, then error out.
7433 		 */
7434 		for (i = 0; i < 200; i++) {
7435 			eecd = E1000_READ_REG(hw, EECD);
7436 			if (eecd & E1000_EECD_DO)
7437 				break;
7438 			usec_delay(50);
7439 		}
7440 		if (i == 200) {
7441 			DEBUGOUT("EEPROM Write did not complete\n");
7442 			return -E1000_ERR_EEPROM;
7443 		}
7444 		/* Recover from write */
7445 		em_standby_eeprom(hw);
7446 
7447 		words_written++;
7448 	}
7449 	/*
7450 	 * Send the write disable command to the EEPROM (3-bit opcode plus
7451 	 * 6/8-bit dummy address beginning with 10).  It's less work to
7452 	 * include the 10 of the dummy address as part of the opcode than it
7453 	 * is to shift it over the correct number of bits for the address.
7454 	 * This takes the EEPROM out of write/erase mode.
7455 	 */
7456 	em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
7457 	    (uint16_t) (eeprom->opcode_bits + 2));
7458 
7459 	em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2));
7460 
7461 	return E1000_SUCCESS;
7462 }
7463 
7464 /******************************************************************************
7465  * Flushes the cached eeprom to NVM. This is done by saving the modified values
7466  * in the eeprom cache and the non modified values in the currently active bank
7467  * to the new bank.
7468  *
7469  * hw - Struct containing variables accessed by shared code
7470  * offset - offset of  word in the EEPROM to read
7471  * data - word read from the EEPROM
7472  * words - number of words to read
7473  *****************************************************************************/
7474 STATIC int32_t
em_commit_shadow_ram(struct em_hw * hw)7475 em_commit_shadow_ram(struct em_hw *hw)
7476 {
7477 	uint32_t  attempts = 100000;
7478 	uint32_t  eecd = 0;
7479 	uint32_t  flop = 0;
7480 	uint32_t  i = 0;
7481 	int32_t   error = E1000_SUCCESS;
7482 	uint32_t  old_bank_offset = 0;
7483 	uint32_t  new_bank_offset = 0;
7484 	uint8_t   low_byte = 0;
7485 	uint8_t   high_byte = 0;
7486 	boolean_t sector_write_failed = FALSE;
7487 	if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
7488 		/*
7489 		 * The flop register will be used to determine if flash type
7490 		 * is STM
7491 		 */
7492 		flop = E1000_READ_REG(hw, FLOP);
7493 		for (i = 0; i < attempts; i++) {
7494 			eecd = E1000_READ_REG(hw, EECD);
7495 			if ((eecd & E1000_EECD_FLUPD) == 0) {
7496 				break;
7497 			}
7498 			usec_delay(5);
7499 		}
7500 
7501 		if (i == attempts) {
7502 			return -E1000_ERR_EEPROM;
7503 		}
7504 		/*
7505 		 * If STM opcode located in bits 15:8 of flop, reset firmware
7506 		 */
7507 		if ((flop & 0xFF00) == E1000_STM_OPCODE) {
7508 			E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
7509 		}
7510 		/* Perform the flash update */
7511 		E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
7512 
7513 		for (i = 0; i < attempts; i++) {
7514 			eecd = E1000_READ_REG(hw, EECD);
7515 			if ((eecd & E1000_EECD_FLUPD) == 0) {
7516 				break;
7517 			}
7518 			usec_delay(5);
7519 		}
7520 
7521 		if (i == attempts) {
7522 			return -E1000_ERR_EEPROM;
7523 		}
7524 	}
7525 	if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) &&
7526 	    hw->eeprom_shadow_ram != NULL) {
7527 		/*
7528 		 * We're writing to the opposite bank so if we're on bank 1,
7529 		 * write to bank 0 etc.  We also need to erase the segment
7530 		 * that is going to be written
7531 		 */
7532 		if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
7533 			new_bank_offset = hw->flash_bank_size * 2;
7534 			old_bank_offset = 0;
7535 			em_erase_ich8_4k_segment(hw, 1);
7536 		} else {
7537 			old_bank_offset = hw->flash_bank_size * 2;
7538 			new_bank_offset = 0;
7539 			em_erase_ich8_4k_segment(hw, 0);
7540 		}
7541 
7542 		sector_write_failed = FALSE;
7543 		/*
7544 		 * Loop for every byte in the shadow RAM, which is in units
7545 		 * of words.
7546 		 */
7547 		for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
7548 			/*
7549 			 * Determine whether to write the value stored in the
7550 			 * other NVM bank or a modified value stored in the
7551 			 * shadow RAM
7552 			 */
7553 			if (hw->eeprom_shadow_ram[i].modified == TRUE) {
7554 				low_byte = (uint8_t)
7555 				    hw->eeprom_shadow_ram[i].eeprom_word;
7556 				usec_delay(100);
7557 				error = em_verify_write_ich8_byte(hw,
7558 				    (i << 1) + new_bank_offset, low_byte);
7559 
7560 				if (error != E1000_SUCCESS)
7561 					sector_write_failed = TRUE;
7562 				else {
7563 					high_byte = (uint8_t)
7564 					    (hw->eeprom_shadow_ram
7565 					    [i].eeprom_word >> 8);
7566 					usec_delay(100);
7567 				}
7568 			} else {
7569 				em_read_ich8_byte(hw, (i << 1) +
7570 				    old_bank_offset, &low_byte);
7571 				usec_delay(100);
7572 				error = em_verify_write_ich8_byte(hw,
7573 				      (i << 1) + new_bank_offset, low_byte);
7574 
7575 				if (error != E1000_SUCCESS)
7576 					sector_write_failed = TRUE;
7577 				else {
7578 					em_read_ich8_byte(hw, (i << 1) +
7579 					    old_bank_offset + 1, &high_byte);
7580 					usec_delay(100);
7581 				}
7582 			}
7583 			/*
7584 			 * If the write of the low byte was successful, go
7585 			 * ahread and write the high byte while checking to
7586 			 * make sure that if it is the signature byte, then
7587 			 * it is handled properly
7588 			 */
7589 			if (sector_write_failed == FALSE) {
7590 				/*
7591 				 * If the word is 0x13, then make sure the
7592 				 * signature bits (15:14) are 11b until the
7593 				 * commit has completed. This will allow us
7594 				 * to write 10b which indicates the signature
7595 				 * is valid.  We want to do this after the
7596 				 * write has completed so that we don't mark
7597 				 * the segment valid while the write is still
7598 				 * in progress
7599 				 */
7600 				if (i == E1000_ICH_NVM_SIG_WORD)
7601 					high_byte = E1000_ICH_NVM_VALID_SIG_MASK |
7602 					    high_byte;
7603 
7604 				error = em_verify_write_ich8_byte(hw, (i << 1)
7605 				    + new_bank_offset + 1, high_byte);
7606 				if (error != E1000_SUCCESS)
7607 					sector_write_failed = TRUE;
7608 
7609 			} else {
7610 				/*
7611 				 * If the write failed then break from the
7612 				 * loop and return an error
7613 				 */
7614 				break;
7615 			}
7616 		}
7617 		/*
7618 		 * Don't bother writing the segment valid bits if sector
7619 		 * programming failed.
7620 		 */
7621 		if (sector_write_failed == FALSE) {
7622 			/*
7623 			 * Finally validate the new segment by setting bit
7624 			 * 15:14 to 10b in word 0x13 , this can be done
7625 			 * without an erase as well since these bits are 11
7626 			 * to start with and we need to change bit 14 to 0b
7627 			 */
7628 			em_read_ich8_byte(hw, E1000_ICH_NVM_SIG_WORD * 2 + 1 +
7629 			    new_bank_offset, &high_byte);
7630 			high_byte &= 0xBF;
7631 			error = em_verify_write_ich8_byte(hw,
7632 			    E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
7633 			    high_byte);
7634 			/*
7635 			 * And invalidate the previously valid segment by
7636 			 * setting its signature word (0x13) high_byte to 0b.
7637 			 * This can be done without an erase because flash
7638 			 * erase sets all bits to 1's. We can write 1's to
7639 			 * 0's without an erase
7640 			 */
7641 			if (error == E1000_SUCCESS) {
7642 				error = em_verify_write_ich8_byte(hw,
7643 				    E1000_ICH_NVM_SIG_WORD * 2 + 1 +
7644 				    old_bank_offset, 0);
7645 			}
7646 			/* Clear the now not used entry in the cache */
7647 			for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
7648 				hw->eeprom_shadow_ram[i].modified = FALSE;
7649 				hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
7650 			}
7651 		}
7652 	}
7653 	return error;
7654 }
7655 
7656 /******************************************************************************
7657  * Reads the adapter's part number from the EEPROM
7658  *
7659  * hw - Struct containing variables accessed by shared code
7660  * part_num - Adapter's part number
7661  *****************************************************************************/
7662 int32_t
em_read_part_num(struct em_hw * hw,uint32_t * part_num)7663 em_read_part_num(struct em_hw *hw, uint32_t *part_num)
7664 {
7665 	uint16_t offset = EEPROM_PBA_BYTE_1;
7666 	uint16_t eeprom_data;
7667 	DEBUGFUNC("em_read_part_num");
7668 
7669 	/* Get word 0 from EEPROM */
7670 	if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
7671 		DEBUGOUT("EEPROM Read Error\n");
7672 		return -E1000_ERR_EEPROM;
7673 	}
7674 	/* Save word 0 in upper half of part_num */
7675 	*part_num = (uint32_t)eeprom_data << 16;
7676 
7677 	/* Get word 1 from EEPROM */
7678 	if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
7679 		DEBUGOUT("EEPROM Read Error\n");
7680 		return -E1000_ERR_EEPROM;
7681 	}
7682 	/* Save word 1 in lower half of part_num */
7683 	*part_num |= eeprom_data;
7684 
7685 	return E1000_SUCCESS;
7686 }
7687 
7688 /******************************************************************************
7689  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
7690  * second function of dual function devices
7691  *
7692  * hw - Struct containing variables accessed by shared code
7693  *****************************************************************************/
7694 int32_t
em_read_mac_addr(struct em_hw * hw)7695 em_read_mac_addr(struct em_hw *hw)
7696 {
7697 	uint16_t offset;
7698 	uint16_t eeprom_data, i;
7699 	uint16_t ia_base_addr = 0;
7700 	DEBUGFUNC("em_read_mac_addr");
7701 
7702 	if (hw->mac_type == em_icp_xxxx) {
7703 		ia_base_addr = (uint16_t)
7704 		EEPROM_IA_START_ICP_xxxx(hw->icp_xxxx_port_num);
7705 	} else if (hw->mac_type == em_82580 || hw->mac_type == em_i350) {
7706 		ia_base_addr = NVM_82580_LAN_FUNC_OFFSET(hw->bus_func);
7707 	}
7708 	for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
7709 		offset = i >> 1;
7710 		if (em_read_eeprom(hw, offset + ia_base_addr, 1, &eeprom_data)
7711 		    < 0) {
7712 			DEBUGOUT("EEPROM Read Error\n");
7713 			return -E1000_ERR_EEPROM;
7714 		}
7715 		hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
7716 		hw->perm_mac_addr[i + 1] = (uint8_t) (eeprom_data >> 8);
7717 	}
7718 
7719 	switch (hw->mac_type) {
7720 	default:
7721 		break;
7722 	case em_82546:
7723 	case em_82546_rev_3:
7724 	case em_82571:
7725 	case em_82575:
7726 	case em_82576:
7727 	case em_80003es2lan:
7728 		if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
7729 			hw->perm_mac_addr[5] ^= 0x01;
7730 		break;
7731 	}
7732 
7733 	for (i = 0; i < NODE_ADDRESS_SIZE; i++)
7734 		hw->mac_addr[i] = hw->perm_mac_addr[i];
7735 	return E1000_SUCCESS;
7736 }
7737 
7738 /******************************************************************************
7739  * Explicitly disables jumbo frames and resets some PHY registers back to hw-
7740  * defaults. This is necessary in case the ethernet cable was inserted AFTER
7741  * the firmware initialized the PHY. Otherwise it is left in a state where
7742  * it is possible to transmit but not receive packets. Observed on I217-LM and
7743  * fixed in FreeBSD's sys/dev/e1000/e1000_ich8lan.c.
7744  *
7745  * hw - Struct containing variables accessed by shared code
7746  *****************************************************************************/
7747 STATIC int32_t
em_phy_no_cable_workaround(struct em_hw * hw)7748 em_phy_no_cable_workaround(struct em_hw *hw) {
7749 	int32_t ret_val, dft_ret_val;
7750 	uint32_t mac_reg;
7751 	uint16_t data, phy_reg;
7752 
7753 	/* disable Rx path while enabling workaround */
7754 	em_read_phy_reg(hw, I2_DFT_CTRL, &phy_reg);
7755 	ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg | (1 << 14));
7756 	if (ret_val)
7757 		return ret_val;
7758 
7759 	/* Write MAC register values back to h/w defaults */
7760 	mac_reg = E1000_READ_REG(hw, FFLT_DBG);
7761 	mac_reg &= ~(0xF << 14);
7762 	E1000_WRITE_REG(hw, FFLT_DBG, mac_reg);
7763 
7764 	mac_reg = E1000_READ_REG(hw, RCTL);
7765 	mac_reg &= ~E1000_RCTL_SECRC;
7766 	E1000_WRITE_REG(hw, RCTL, mac_reg);
7767 
7768 	ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, &data);
7769 	if (ret_val)
7770 		goto out;
7771 	ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL,
7772 	    data & ~(1 << 0));
7773 	if (ret_val)
7774 		goto out;
7775 
7776 	ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, &data);
7777 	if (ret_val)
7778 		goto out;
7779 
7780 	data &= ~(0xF << 8);
7781 	data |= (0xB << 8);
7782 	ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, data);
7783 	if (ret_val)
7784 		goto out;
7785 
7786 	/* Write PHY register values back to h/w defaults */
7787 	em_read_phy_reg(hw, I2_SMBUS_CTRL, &data);
7788 	data &= ~(0x7F << 5);
7789 	ret_val = em_write_phy_reg(hw, I2_SMBUS_CTRL, data);
7790 	if (ret_val)
7791 		goto out;
7792 
7793 	em_read_phy_reg(hw, I2_MODE_CTRL, &data);
7794 	data |= (1 << 13);
7795 	ret_val = em_write_phy_reg(hw, I2_MODE_CTRL, data);
7796 	if (ret_val)
7797 		goto out;
7798 
7799 	/*
7800 	 * 776.20 and 776.23 are not documented in
7801 	 * i217-ethernet-controller-datasheet.pdf...
7802 	 */
7803 	em_read_phy_reg(hw, PHY_REG(776, 20), &data);
7804 	data &= ~(0x3FF << 2);
7805 	data |= (0x8 << 2);
7806 	ret_val = em_write_phy_reg(hw, PHY_REG(776, 20), data);
7807 	if (ret_val)
7808 		goto out;
7809 
7810 	ret_val = em_write_phy_reg(hw, PHY_REG(776, 23), 0x7E00);
7811 	if (ret_val)
7812 		goto out;
7813 
7814 	em_read_phy_reg(hw, I2_PCIE_POWER_CTRL, &data);
7815 	ret_val = em_write_phy_reg(hw, I2_PCIE_POWER_CTRL, data & ~(1 << 10));
7816 	if (ret_val)
7817 		goto out;
7818 
7819 out:
7820 	/* re-enable Rx path after enabling workaround */
7821 	dft_ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg & ~(1 << 14));
7822 	if (ret_val)
7823 		return ret_val;
7824 	else
7825 		return dft_ret_val;
7826 }
7827 
7828 /******************************************************************************
7829  * Initializes receive address filters.
7830  *
7831  * hw - Struct containing variables accessed by shared code
7832  *
7833  * Places the MAC address in receive address register 0 and clears the rest
7834  * of the receive address registers. Clears the multicast table. Assumes
7835  * the receiver is in reset when the routine is called.
7836  *****************************************************************************/
7837 STATIC void
em_init_rx_addrs(struct em_hw * hw)7838 em_init_rx_addrs(struct em_hw *hw)
7839 {
7840 	uint32_t i;
7841 	uint32_t rar_num;
7842 	DEBUGFUNC("em_init_rx_addrs");
7843 
7844 	if (hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt ||
7845 	    hw->mac_type == em_pch_cnp || hw->mac_type == em_pch_tgp ||
7846 	    hw->mac_type == em_pch_adp || hw->mac_type == em_pch2lan)
7847 		if (em_phy_no_cable_workaround(hw))
7848 			printf(" ...failed to apply em_phy_no_cable_"
7849 			    "workaround.\n");
7850 
7851 	/* Setup the receive address. */
7852 	DEBUGOUT("Programming MAC Address into RAR[0]\n");
7853 
7854 	em_rar_set(hw, hw->mac_addr, 0);
7855 
7856 	rar_num = E1000_RAR_ENTRIES;
7857 	/*
7858 	 * Reserve a spot for the Locally Administered Address to work around
7859 	 * an 82571 issue in which a reset on one port will reload the MAC on
7860 	 * the other port.
7861 	 */
7862 	if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE))
7863 		rar_num -= 1;
7864 	if (IS_ICH8(hw->mac_type))
7865 		rar_num = E1000_RAR_ENTRIES_ICH8LAN;
7866 	if (hw->mac_type == em_ich8lan)
7867 		rar_num -= 1;
7868 	if (hw->mac_type == em_82580)
7869 		rar_num = E1000_RAR_ENTRIES_82580;
7870 	if (hw->mac_type == em_i210)
7871 		rar_num = E1000_RAR_ENTRIES_82575;
7872 	if (hw->mac_type == em_i350)
7873 		rar_num = E1000_RAR_ENTRIES_I350;
7874 
7875 	/* Zero out the other 15 receive addresses. */
7876 	DEBUGOUT("Clearing RAR[1-15]\n");
7877 	for (i = 1; i < rar_num; i++) {
7878 		E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
7879 		E1000_WRITE_FLUSH(hw);
7880 		E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
7881 		E1000_WRITE_FLUSH(hw);
7882 	}
7883 }
7884 
7885 /******************************************************************************
7886  * Updates the MAC's list of multicast addresses.
7887  *
7888  * hw - Struct containing variables accessed by shared code
7889  * mc_addr_list - the list of new multicast addresses
7890  * mc_addr_count - number of addresses
7891  * pad - number of bytes between addresses in the list
7892  *
7893  * The given list replaces any existing list and hashes the addresses into the
7894  * multicast table.
7895  *****************************************************************************/
7896 void
em_mc_addr_list_update(struct em_hw * hw,uint8_t * mc_addr_list,uint32_t mc_addr_count,uint32_t pad)7897 em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list,
7898     uint32_t mc_addr_count, uint32_t pad)
7899 {
7900 	uint32_t hash_value;
7901 	uint32_t i;
7902 	uint32_t num_mta_entry;
7903 	DEBUGFUNC("em_mc_addr_list_update");
7904 	/*
7905 	 * Set the new number of MC addresses that we are being requested to
7906 	 * use.
7907 	 */
7908 	hw->num_mc_addrs = mc_addr_count;
7909 
7910 	/* Clear the MTA */
7911 	DEBUGOUT(" Clearing MTA\n");
7912 	num_mta_entry = E1000_NUM_MTA_REGISTERS;
7913 	if (IS_ICH8(hw->mac_type))
7914 		num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
7915 
7916 	for (i = 0; i < num_mta_entry; i++) {
7917 		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
7918 		E1000_WRITE_FLUSH(hw);
7919 	}
7920 
7921 	/* Add the new addresses */
7922 	for (i = 0; i < mc_addr_count; i++) {
7923 		DEBUGOUT(" Adding the multicast addresses:\n");
7924 		DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
7925 		    mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
7926 		    mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
7927 		    mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
7928 		    mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
7929 		    mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
7930 		    mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
7931 
7932 		hash_value = em_hash_mc_addr(hw, mc_addr_list +
7933 		    (i * (ETH_LENGTH_OF_ADDRESS + pad)));
7934 
7935 		DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
7936 		em_mta_set(hw, hash_value);
7937 	}
7938 	DEBUGOUT("MC Update Complete\n");
7939 }
7940 
7941 /******************************************************************************
7942  * Hashes an address to determine its location in the multicast table
7943  *
7944  * hw - Struct containing variables accessed by shared code
7945  * mc_addr - the multicast address to hash
7946  *****************************************************************************/
7947 uint32_t
em_hash_mc_addr(struct em_hw * hw,uint8_t * mc_addr)7948 em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr)
7949 {
7950 	uint32_t hash_value = 0;
7951 	/*
7952 	 * The portion of the address that is used for the hash table is
7953 	 * determined by the mc_filter_type setting.
7954 	 */
7955 	switch (hw->mc_filter_type) {
7956 		/*
7957 		 * [0] [1] [2] [3] [4] [5] 01  AA  00  12  34  56 LSB
7958 		 * MSB
7959 		 */
7960 	case 0:
7961 		if (IS_ICH8(hw->mac_type)) {
7962 			/* [47:38] i.e. 0x158 for above example address */
7963 			hash_value = ((mc_addr[4] >> 6) |
7964 			    (((uint16_t) mc_addr[5]) << 2));
7965 		} else {
7966 			/* [47:36] i.e. 0x563 for above example address */
7967 			hash_value = ((mc_addr[4] >> 4) |
7968 			    (((uint16_t) mc_addr[5]) << 4));
7969 		}
7970 		break;
7971 	case 1:
7972 		if (IS_ICH8(hw->mac_type)) {
7973 			/* [46:37] i.e. 0x2B1 for above example address */
7974 			hash_value = ((mc_addr[4] >> 5) |
7975 			    (((uint16_t) mc_addr[5]) << 3));
7976 		} else {
7977 			/* [46:35] i.e. 0xAC6 for above example address */
7978 			hash_value = ((mc_addr[4] >> 3) |
7979 			    (((uint16_t) mc_addr[5]) << 5));
7980 		}
7981 		break;
7982 	case 2:
7983 		if (IS_ICH8(hw->mac_type)) {
7984 			/* [45:36] i.e. 0x163 for above example address */
7985 			hash_value = ((mc_addr[4] >> 4) |
7986 			    (((uint16_t) mc_addr[5]) << 4));
7987 		} else {
7988 			/* [45:34] i.e. 0x5D8 for above example address */
7989 			hash_value = ((mc_addr[4] >> 2) |
7990 			    (((uint16_t) mc_addr[5]) << 6));
7991 		}
7992 		break;
7993 	case 3:
7994 		if (IS_ICH8(hw->mac_type)) {
7995 			/* [43:34] i.e. 0x18D for above example address */
7996 			hash_value = ((mc_addr[4] >> 2) |
7997 			    (((uint16_t) mc_addr[5]) << 6));
7998 		} else {
7999 			/* [43:32] i.e. 0x634 for above example address */
8000 			hash_value = ((mc_addr[4]) |
8001 			    (((uint16_t) mc_addr[5]) << 8));
8002 		}
8003 		break;
8004 	}
8005 
8006 	hash_value &= 0xFFF;
8007 	if (IS_ICH8(hw->mac_type))
8008 		hash_value &= 0x3FF;
8009 
8010 	return hash_value;
8011 }
8012 
8013 /******************************************************************************
8014  * Sets the bit in the multicast table corresponding to the hash value.
8015  *
8016  * hw - Struct containing variables accessed by shared code
8017  * hash_value - Multicast address hash value
8018  *****************************************************************************/
8019 void
em_mta_set(struct em_hw * hw,uint32_t hash_value)8020 em_mta_set(struct em_hw *hw, uint32_t hash_value)
8021 {
8022 	uint32_t hash_bit, hash_reg;
8023 	uint32_t mta;
8024 	uint32_t temp;
8025 	/*
8026 	 * The MTA is a register array of 128 32-bit registers. It is treated
8027 	 * like an array of 4096 bits.  We want to set bit
8028 	 * BitArray[hash_value]. So we figure out what register the bit is
8029 	 * in, read it, OR in the new bit, then write back the new value.
8030 	 * The register is determined by the upper 7 bits of the hash value
8031 	 * and the bit within that register are determined by the lower 5
8032 	 * bits of the value.
8033 	 */
8034 	hash_reg = (hash_value >> 5) & 0x7F;
8035 	if (IS_ICH8(hw->mac_type))
8036 		hash_reg &= 0x1F;
8037 
8038 	hash_bit = hash_value & 0x1F;
8039 
8040 	mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
8041 
8042 	mta |= (1 << hash_bit);
8043 	/*
8044 	 * If we are on an 82544 and we are trying to write an odd offset in
8045 	 * the MTA, save off the previous entry before writing and restore
8046 	 * the old value after writing.
8047 	 */
8048 	if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) {
8049 		temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
8050 		E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
8051 		E1000_WRITE_FLUSH(hw);
8052 		E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
8053 		E1000_WRITE_FLUSH(hw);
8054 	} else {
8055 		E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
8056 		E1000_WRITE_FLUSH(hw);
8057 	}
8058 }
8059 
8060 /******************************************************************************
8061  * Puts an ethernet address into a receive address register.
8062  *
8063  * hw - Struct containing variables accessed by shared code
8064  * addr - Address to put into receive address register
8065  * index - Receive address register to write
8066  *****************************************************************************/
8067 void
em_rar_set(struct em_hw * hw,uint8_t * addr,uint32_t index)8068 em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index)
8069 {
8070 	uint32_t rar_low, rar_high;
8071 	/*
8072 	 * HW expects these in little endian so we reverse the byte order
8073 	 * from network order (big endian) to little endian
8074 	 */
8075 	rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) |
8076 	    ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
8077 	rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
8078 	/*
8079 	 * Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
8080 	 * unit hang.
8081 	 *
8082 	 * Description: If there are any Rx frames queued up or otherwise
8083 	 * present in the HW before RSS is enabled, and then we enable RSS,
8084 	 * the HW Rx unit will hang.  To work around this issue, we have to
8085 	 * disable receives and flush out all Rx frames before we enable RSS.
8086 	 * To do so, we modify we redirect all Rx traffic to manageability
8087 	 * and then reset the HW. This flushes away Rx frames, and (since the
8088 	 * redirections to manageability persists across resets) keeps new
8089 	 * ones from coming in while we work.  Then, we clear the Address
8090 	 * Valid AV bit for all MAC addresses and undo the re-direction to
8091 	 * manageability. Now, frames are coming in again, but the MAC won't
8092 	 * accept them, so far so good.  We now proceed to initialize RSS (if
8093 	 * necessary) and configure the Rx unit.  Last, we re-enable the AV
8094 	 * bits and continue on our merry way.
8095 	 */
8096 	switch (hw->mac_type) {
8097 	case em_82571:
8098 	case em_82572:
8099 	case em_80003es2lan:
8100 		if (hw->leave_av_bit_off == TRUE)
8101 			break;
8102 	default:
8103 		/* Indicate to hardware the Address is Valid. */
8104 		rar_high |= E1000_RAH_AV;
8105 		break;
8106 	}
8107 
8108 	E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
8109 	E1000_WRITE_FLUSH(hw);
8110 	E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
8111 	E1000_WRITE_FLUSH(hw);
8112 }
8113 
8114 /******************************************************************************
8115  * Clears the VLAN filer table
8116  *
8117  * hw - Struct containing variables accessed by shared code
8118  *****************************************************************************/
8119 STATIC void
em_clear_vfta(struct em_hw * hw)8120 em_clear_vfta(struct em_hw *hw)
8121 {
8122 	uint32_t offset;
8123 	uint32_t vfta_value = 0;
8124 	uint32_t vfta_offset = 0;
8125 	uint32_t vfta_bit_in_reg = 0;
8126 	if (IS_ICH8(hw->mac_type))
8127 		return;
8128 
8129 	if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
8130 		if (hw->mng_cookie.vlan_id != 0) {
8131 			/*
8132 			 * The VFTA is a 4096b bit-field, each identifying a
8133 			 * single VLAN ID.  The following operations
8134 			 * determine which 32b entry (i.e. offset) into the
8135 			 * array we want to set the VLAN ID (i.e. bit) of the
8136 			 * manageability unit.
8137 			 */
8138 			vfta_offset = (hw->mng_cookie.vlan_id >>
8139 			    E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
8140 
8141 			vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
8142 			    E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
8143 		}
8144 	}
8145 	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
8146 		/*
8147 		 * If the offset we want to clear is the same offset of the
8148 		 * manageability VLAN ID, then clear all bits except that of
8149 		 * the manageability unit
8150 		 */
8151 		vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
8152 		E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
8153 		E1000_WRITE_FLUSH(hw);
8154 	}
8155 }
8156 
8157 /*
8158  * Due to hw errata, if the host tries to configure the VFTA register
8159  * while performing queries from the BMC or DMA, then the VFTA in some
8160  * cases won't be written.
8161  */
8162 void
em_clear_vfta_i350(struct em_hw * hw)8163 em_clear_vfta_i350(struct em_hw *hw)
8164 {
8165 	uint32_t offset;
8166 	int i;
8167 
8168 	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
8169 		for (i = 0; i < 10; i++)
8170 			E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
8171 		E1000_WRITE_FLUSH(hw);
8172 	}
8173 }
8174 
8175 STATIC int32_t
em_id_led_init(struct em_hw * hw)8176 em_id_led_init(struct em_hw *hw)
8177 {
8178 	uint32_t       ledctl;
8179 	const uint32_t ledctl_mask = 0x000000FF;
8180 	const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
8181 	const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
8182 	uint16_t       eeprom_data, i, temp;
8183 	const uint16_t led_mask = 0x0F;
8184 	DEBUGFUNC("em_id_led_init");
8185 
8186 	if (hw->mac_type < em_82540 || hw->mac_type == em_icp_xxxx) {
8187 		/* Nothing to do */
8188 		return E1000_SUCCESS;
8189 	}
8190 	ledctl = E1000_READ_REG(hw, LEDCTL);
8191 	hw->ledctl_default = ledctl;
8192 	hw->ledctl_mode1 = hw->ledctl_default;
8193 	hw->ledctl_mode2 = hw->ledctl_default;
8194 
8195 	if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
8196 		DEBUGOUT("EEPROM Read Error\n");
8197 		return -E1000_ERR_EEPROM;
8198 	}
8199 	if ((hw->mac_type == em_82573) &&
8200 	    (eeprom_data == ID_LED_RESERVED_82573))
8201 		eeprom_data = ID_LED_DEFAULT_82573;
8202 	else if ((eeprom_data == ID_LED_RESERVED_0000) ||
8203 	    (eeprom_data == ID_LED_RESERVED_FFFF)) {
8204 		if (hw->mac_type == em_ich8lan ||
8205 		    hw->mac_type == em_ich9lan ||
8206 		    hw->mac_type == em_ich10lan) // XXX
8207 			eeprom_data = ID_LED_DEFAULT_ICH8LAN;
8208 		else
8209 			eeprom_data = ID_LED_DEFAULT;
8210 	}
8211 	for (i = 0; i < 4; i++) {
8212 		temp = (eeprom_data >> (i << 2)) & led_mask;
8213 		switch (temp) {
8214 		case ID_LED_ON1_DEF2:
8215 		case ID_LED_ON1_ON2:
8216 		case ID_LED_ON1_OFF2:
8217 			hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
8218 			hw->ledctl_mode1 |= ledctl_on << (i << 3);
8219 			break;
8220 		case ID_LED_OFF1_DEF2:
8221 		case ID_LED_OFF1_ON2:
8222 		case ID_LED_OFF1_OFF2:
8223 			hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
8224 			hw->ledctl_mode1 |= ledctl_off << (i << 3);
8225 			break;
8226 		default:
8227 			/* Do nothing */
8228 			break;
8229 		}
8230 		switch (temp) {
8231 		case ID_LED_DEF1_ON2:
8232 		case ID_LED_ON1_ON2:
8233 		case ID_LED_OFF1_ON2:
8234 			hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
8235 			hw->ledctl_mode2 |= ledctl_on << (i << 3);
8236 			break;
8237 		case ID_LED_DEF1_OFF2:
8238 		case ID_LED_ON1_OFF2:
8239 		case ID_LED_OFF1_OFF2:
8240 			hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
8241 			hw->ledctl_mode2 |= ledctl_off << (i << 3);
8242 			break;
8243 		default:
8244 			/* Do nothing */
8245 			break;
8246 		}
8247 	}
8248 	return E1000_SUCCESS;
8249 }
8250 
8251 /******************************************************************************
8252  * Clears all hardware statistics counters.
8253  *
8254  * hw - Struct containing variables accessed by shared code
8255  *****************************************************************************/
8256 void
em_clear_hw_cntrs(struct em_hw * hw)8257 em_clear_hw_cntrs(struct em_hw *hw)
8258 {
8259 	volatile uint32_t temp;
8260 	temp = E1000_READ_REG(hw, CRCERRS);
8261 	temp = E1000_READ_REG(hw, SYMERRS);
8262 	temp = E1000_READ_REG(hw, MPC);
8263 	temp = E1000_READ_REG(hw, SCC);
8264 	temp = E1000_READ_REG(hw, ECOL);
8265 	temp = E1000_READ_REG(hw, MCC);
8266 	temp = E1000_READ_REG(hw, LATECOL);
8267 	temp = E1000_READ_REG(hw, COLC);
8268 	temp = E1000_READ_REG(hw, DC);
8269 	temp = E1000_READ_REG(hw, SEC);
8270 	temp = E1000_READ_REG(hw, RLEC);
8271 	temp = E1000_READ_REG(hw, XONRXC);
8272 	temp = E1000_READ_REG(hw, XONTXC);
8273 	temp = E1000_READ_REG(hw, XOFFRXC);
8274 	temp = E1000_READ_REG(hw, XOFFTXC);
8275 	temp = E1000_READ_REG(hw, FCRUC);
8276 
8277 	if (!IS_ICH8(hw->mac_type)) {
8278 		temp = E1000_READ_REG(hw, PRC64);
8279 		temp = E1000_READ_REG(hw, PRC127);
8280 		temp = E1000_READ_REG(hw, PRC255);
8281 		temp = E1000_READ_REG(hw, PRC511);
8282 		temp = E1000_READ_REG(hw, PRC1023);
8283 		temp = E1000_READ_REG(hw, PRC1522);
8284 	}
8285 	temp = E1000_READ_REG(hw, GPRC);
8286 	temp = E1000_READ_REG(hw, BPRC);
8287 	temp = E1000_READ_REG(hw, MPRC);
8288 	temp = E1000_READ_REG(hw, GPTC);
8289 	temp = E1000_READ_REG(hw, GORCL);
8290 	temp = E1000_READ_REG(hw, GORCH);
8291 	temp = E1000_READ_REG(hw, GOTCL);
8292 	temp = E1000_READ_REG(hw, GOTCH);
8293 	temp = E1000_READ_REG(hw, RNBC);
8294 	temp = E1000_READ_REG(hw, RUC);
8295 	temp = E1000_READ_REG(hw, RFC);
8296 	temp = E1000_READ_REG(hw, ROC);
8297 	temp = E1000_READ_REG(hw, RJC);
8298 	temp = E1000_READ_REG(hw, TORL);
8299 	temp = E1000_READ_REG(hw, TORH);
8300 	temp = E1000_READ_REG(hw, TOTL);
8301 	temp = E1000_READ_REG(hw, TOTH);
8302 	temp = E1000_READ_REG(hw, TPR);
8303 	temp = E1000_READ_REG(hw, TPT);
8304 
8305 	if (!IS_ICH8(hw->mac_type)) {
8306 		temp = E1000_READ_REG(hw, PTC64);
8307 		temp = E1000_READ_REG(hw, PTC127);
8308 		temp = E1000_READ_REG(hw, PTC255);
8309 		temp = E1000_READ_REG(hw, PTC511);
8310 		temp = E1000_READ_REG(hw, PTC1023);
8311 		temp = E1000_READ_REG(hw, PTC1522);
8312 	}
8313 	temp = E1000_READ_REG(hw, MPTC);
8314 	temp = E1000_READ_REG(hw, BPTC);
8315 
8316 	if (hw->mac_type < em_82543)
8317 		return;
8318 
8319 	temp = E1000_READ_REG(hw, ALGNERRC);
8320 	temp = E1000_READ_REG(hw, RXERRC);
8321 	temp = E1000_READ_REG(hw, TNCRS);
8322 	temp = E1000_READ_REG(hw, CEXTERR);
8323 	temp = E1000_READ_REG(hw, TSCTC);
8324 	temp = E1000_READ_REG(hw, TSCTFC);
8325 
8326 	if (hw->mac_type <= em_82544
8327 	    || hw->mac_type == em_icp_xxxx)
8328 		return;
8329 
8330 	temp = E1000_READ_REG(hw, MGTPRC);
8331 	temp = E1000_READ_REG(hw, MGTPDC);
8332 	temp = E1000_READ_REG(hw, MGTPTC);
8333 
8334 	if (hw->mac_type <= em_82547_rev_2)
8335 		return;
8336 
8337 	temp = E1000_READ_REG(hw, IAC);
8338 	temp = E1000_READ_REG(hw, ICRXOC);
8339 
8340 	if (hw->phy_type == em_phy_82577 ||
8341 	    hw->phy_type == em_phy_82578 ||
8342 	    hw->phy_type == em_phy_82579 ||
8343 	    hw->phy_type == em_phy_i217) {
8344 		uint16_t phy_data;
8345 
8346 		em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
8347 		em_read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
8348 		em_read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
8349 		em_read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
8350 		em_read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
8351 		em_read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
8352 		em_read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
8353 		em_read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
8354 		em_read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
8355 		em_read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
8356 		em_read_phy_reg(hw, HV_DC_UPPER, &phy_data);
8357 		em_read_phy_reg(hw, HV_DC_LOWER, &phy_data);
8358 		em_read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
8359 		em_read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
8360 	}
8361 
8362 	if (hw->mac_type == em_ich8lan ||
8363 	    hw->mac_type == em_ich9lan ||
8364 	    hw->mac_type == em_ich10lan ||
8365 	    hw->mac_type == em_pchlan ||
8366 	    (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt &&
8367 	     hw->mac_type != em_pch_spt && hw->mac_type != em_pch_cnp &&
8368 	     hw->mac_type != em_pch_tgp && hw->mac_type != em_pch_adp))
8369 		return;
8370 
8371 	temp = E1000_READ_REG(hw, ICRXPTC);
8372 	temp = E1000_READ_REG(hw, ICRXATC);
8373 	temp = E1000_READ_REG(hw, ICTXPTC);
8374 	temp = E1000_READ_REG(hw, ICTXATC);
8375 	temp = E1000_READ_REG(hw, ICTXQEC);
8376 	temp = E1000_READ_REG(hw, ICTXQMTC);
8377 	temp = E1000_READ_REG(hw, ICRXDMTC);
8378 }
8379 
8380 /******************************************************************************
8381  * Gets the current PCI bus type, speed, and width of the hardware
8382  *
8383  * hw - Struct containing variables accessed by shared code
8384  *****************************************************************************/
8385 void
em_get_bus_info(struct em_hw * hw)8386 em_get_bus_info(struct em_hw *hw)
8387 {
8388 	int32_t  ret_val;
8389 	uint16_t pci_ex_link_status;
8390 	uint32_t status;
8391 	switch (hw->mac_type) {
8392 	case em_82542_rev2_0:
8393 	case em_82542_rev2_1:
8394 		hw->bus_type = em_bus_type_unknown;
8395 		hw->bus_speed = em_bus_speed_unknown;
8396 		hw->bus_width = em_bus_width_unknown;
8397 		break;
8398 	case em_icp_xxxx:
8399 		hw->bus_type = em_bus_type_cpp;
8400 		hw->bus_speed = em_bus_speed_unknown;
8401 		hw->bus_width = em_bus_width_unknown;
8402 		break;
8403 	case em_82571:
8404 	case em_82572:
8405 	case em_82573:
8406 	case em_82574:
8407 	case em_82575:
8408 	case em_82576:
8409 	case em_82580:
8410 	case em_80003es2lan:
8411 	case em_i210:
8412 	case em_i350:
8413 		hw->bus_type = em_bus_type_pci_express;
8414 		hw->bus_speed = em_bus_speed_2500;
8415 		ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS,
8416 		    &pci_ex_link_status);
8417 		if (ret_val)
8418 			hw->bus_width = em_bus_width_unknown;
8419 		else
8420 			hw->bus_width = (pci_ex_link_status &
8421 			    PCI_EX_LINK_WIDTH_MASK) >> PCI_EX_LINK_WIDTH_SHIFT;
8422 		break;
8423 	case em_ich8lan:
8424 	case em_ich9lan:
8425 	case em_ich10lan:
8426 	case em_pchlan:
8427 	case em_pch2lan:
8428 	case em_pch_lpt:
8429 	case em_pch_spt:
8430 	case em_pch_cnp:
8431 	case em_pch_tgp:
8432 	case em_pch_adp:
8433 		hw->bus_type = em_bus_type_pci_express;
8434 		hw->bus_speed = em_bus_speed_2500;
8435 		hw->bus_width = em_bus_width_pciex_1;
8436 		break;
8437 	default:
8438 		status = E1000_READ_REG(hw, STATUS);
8439 		hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
8440 		    em_bus_type_pcix : em_bus_type_pci;
8441 
8442 		if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
8443 			hw->bus_speed = (hw->bus_type == em_bus_type_pci) ?
8444 			    em_bus_speed_66 : em_bus_speed_120;
8445 		} else if (hw->bus_type == em_bus_type_pci) {
8446 			hw->bus_speed = (status & E1000_STATUS_PCI66) ?
8447 			    em_bus_speed_66 : em_bus_speed_33;
8448 		} else {
8449 			switch (status & E1000_STATUS_PCIX_SPEED) {
8450 			case E1000_STATUS_PCIX_SPEED_66:
8451 				hw->bus_speed = em_bus_speed_66;
8452 				break;
8453 			case E1000_STATUS_PCIX_SPEED_100:
8454 				hw->bus_speed = em_bus_speed_100;
8455 				break;
8456 			case E1000_STATUS_PCIX_SPEED_133:
8457 				hw->bus_speed = em_bus_speed_133;
8458 				break;
8459 			default:
8460 				hw->bus_speed = em_bus_speed_reserved;
8461 				break;
8462 			}
8463 		}
8464 		hw->bus_width = (status & E1000_STATUS_BUS64) ?
8465 		    em_bus_width_64 : em_bus_width_32;
8466 		break;
8467 	}
8468 }
8469 
8470 /******************************************************************************
8471  * Writes a value to one of the devices registers using port I/O (as opposed to
8472  * memory mapped I/O). Only 82544 and newer devices support port I/O.
8473  *
8474  * hw - Struct containing variables accessed by shared code
8475  * offset - offset to write to
8476  * value - value to write
8477  *****************************************************************************/
8478 STATIC void
em_write_reg_io(struct em_hw * hw,uint32_t offset,uint32_t value)8479 em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value)
8480 {
8481 	unsigned long io_addr = hw->io_base;
8482 	unsigned long io_data = hw->io_base + 4;
8483 	em_io_write(hw, io_addr, offset);
8484 	em_io_write(hw, io_data, value);
8485 }
8486 
8487 /******************************************************************************
8488  * Estimates the cable length.
8489  *
8490  * hw - Struct containing variables accessed by shared code
8491  * min_length - The estimated minimum length
8492  * max_length - The estimated maximum length
8493  *
8494  * returns: - E1000_ERR_XXX
8495  *            E1000_SUCCESS
8496  *
8497  * This function always returns a ranged length (minimum & maximum).
8498  * So for M88 phy's, this function interprets the one value returned from the
8499  * register to the minimum and maximum range.
8500  * For IGP phy's, the function calculates the range by the AGC registers.
8501  *****************************************************************************/
8502 STATIC int32_t
em_get_cable_length(struct em_hw * hw,uint16_t * min_length,uint16_t * max_length)8503 em_get_cable_length(struct em_hw *hw, uint16_t *min_length,
8504     uint16_t *max_length)
8505 {
8506 	int32_t  ret_val;
8507 	uint16_t agc_value = 0;
8508 	uint16_t i, phy_data;
8509 	uint16_t cable_length;
8510 	DEBUGFUNC("em_get_cable_length");
8511 
8512 	*min_length = *max_length = 0;
8513 
8514 	/* Use old method for Phy older than IGP */
8515 	if (hw->phy_type == em_phy_m88 ||
8516 	    hw->phy_type == em_phy_oem ||
8517 	    hw->phy_type == em_phy_82578) {
8518 
8519 		ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
8520 		    &phy_data);
8521 		if (ret_val)
8522 			return ret_val;
8523 		cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
8524 		    M88E1000_PSSR_CABLE_LENGTH_SHIFT;
8525 
8526 		/* Convert the enum value to ranged values */
8527 		switch (cable_length) {
8528 		case em_cable_length_50:
8529 			*min_length = 0;
8530 			*max_length = em_igp_cable_length_50;
8531 			break;
8532 		case em_cable_length_50_80:
8533 			*min_length = em_igp_cable_length_50;
8534 			*max_length = em_igp_cable_length_80;
8535 			break;
8536 		case em_cable_length_80_110:
8537 			*min_length = em_igp_cable_length_80;
8538 			*max_length = em_igp_cable_length_110;
8539 			break;
8540 		case em_cable_length_110_140:
8541 			*min_length = em_igp_cable_length_110;
8542 			*max_length = em_igp_cable_length_140;
8543 			break;
8544 		case em_cable_length_140:
8545 			*min_length = em_igp_cable_length_140;
8546 			*max_length = em_igp_cable_length_170;
8547 			break;
8548 		default:
8549 			return -E1000_ERR_PHY;
8550 			break;
8551 		}
8552 	} else if (hw->phy_type == em_phy_rtl8211) {
8553 		/* no cable length info on RTL8211, fake */
8554 		*min_length = 0;
8555 		*max_length = em_igp_cable_length_50;
8556 	} else if (hw->phy_type == em_phy_gg82563) {
8557 		ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
8558 		    &phy_data);
8559 		if (ret_val)
8560 			return ret_val;
8561 		cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
8562 
8563 		switch (cable_length) {
8564 		case em_gg_cable_length_60:
8565 			*min_length = 0;
8566 			*max_length = em_igp_cable_length_60;
8567 			break;
8568 		case em_gg_cable_length_60_115:
8569 			*min_length = em_igp_cable_length_60;
8570 			*max_length = em_igp_cable_length_115;
8571 			break;
8572 		case em_gg_cable_length_115_150:
8573 			*min_length = em_igp_cable_length_115;
8574 			*max_length = em_igp_cable_length_150;
8575 			break;
8576 		case em_gg_cable_length_150:
8577 			*min_length = em_igp_cable_length_150;
8578 			*max_length = em_igp_cable_length_180;
8579 			break;
8580 		default:
8581 			return -E1000_ERR_PHY;
8582 			break;
8583 		}
8584 	} else if (hw->phy_type == em_phy_igp) {	/* For IGP PHY */
8585 		uint16_t        cur_agc_value;
8586 		uint16_t        min_agc_value =
8587 		    IGP01E1000_AGC_LENGTH_TABLE_SIZE;
8588 		uint16_t        agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
8589 		    {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B,
8590 		    IGP01E1000_PHY_AGC_C, IGP01E1000_PHY_AGC_D};
8591 
8592 		/* Read the AGC registers for all channels */
8593 		for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
8594 			ret_val = em_read_phy_reg(hw, agc_reg_array[i],
8595 			    &phy_data);
8596 			if (ret_val)
8597 				return ret_val;
8598 
8599 			cur_agc_value = phy_data >>
8600 			    IGP01E1000_AGC_LENGTH_SHIFT;
8601 
8602 			/* Value bound check. */
8603 			if ((cur_agc_value >=
8604 			    IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
8605 			    (cur_agc_value == 0))
8606 				return -E1000_ERR_PHY;
8607 
8608 			agc_value += cur_agc_value;
8609 
8610 			/* Update minimal AGC value. */
8611 			if (min_agc_value > cur_agc_value)
8612 				min_agc_value = cur_agc_value;
8613 		}
8614 
8615 		/* Remove the minimal AGC result for length < 50m */
8616 		if (agc_value < IGP01E1000_PHY_CHANNEL_NUM *
8617 		    em_igp_cable_length_50) {
8618 			agc_value -= min_agc_value;
8619 
8620 			/*
8621 			 * Get the average length of the remaining 3 channels
8622 			 */
8623 			agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
8624 		} else {
8625 			/* Get the average length of all the 4 channels. */
8626 			agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
8627 		}
8628 
8629 		/* Set the range of the calculated length. */
8630 		*min_length = ((em_igp_cable_length_table[agc_value] -
8631 		    IGP01E1000_AGC_RANGE) > 0) ?
8632 		    (em_igp_cable_length_table[agc_value] -
8633 		    IGP01E1000_AGC_RANGE) : 0;
8634 		*max_length = em_igp_cable_length_table[agc_value] +
8635 		    IGP01E1000_AGC_RANGE;
8636 	} else if (hw->phy_type == em_phy_igp_2 ||
8637 	    hw->phy_type == em_phy_igp_3) {
8638 		uint16_t cur_agc_index, max_agc_index = 0;
8639 		uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
8640 		uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
8641 		    {IGP02E1000_PHY_AGC_A, IGP02E1000_PHY_AGC_B,
8642 		    IGP02E1000_PHY_AGC_C, IGP02E1000_PHY_AGC_D};
8643 		/* Read the AGC registers for all channels */
8644 		for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
8645 			ret_val = em_read_phy_reg(hw, agc_reg_array[i],
8646 			    &phy_data);
8647 			if (ret_val)
8648 				return ret_val;
8649 			/*
8650 			 * Getting bits 15:9, which represent the combination
8651 			 * of course and fine gain values.  The result is a
8652 			 * number that can be put into the lookup table to
8653 			 * obtain the approximate cable length.
8654 			 */
8655 			cur_agc_index = (phy_data >>
8656 			    IGP02E1000_AGC_LENGTH_SHIFT) &
8657 			    IGP02E1000_AGC_LENGTH_MASK;
8658 
8659 			/* Array index bound check. */
8660 			if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE)
8661 			    || (cur_agc_index == 0))
8662 				return -E1000_ERR_PHY;
8663 
8664 			/* Remove min & max AGC values from calculation. */
8665 			if (em_igp_2_cable_length_table[min_agc_index] >
8666 			    em_igp_2_cable_length_table[cur_agc_index])
8667 				min_agc_index = cur_agc_index;
8668 			if (em_igp_2_cable_length_table[max_agc_index] <
8669 			    em_igp_2_cable_length_table[cur_agc_index])
8670 				max_agc_index = cur_agc_index;
8671 
8672 			agc_value += em_igp_2_cable_length_table
8673 			    [cur_agc_index];
8674 		}
8675 
8676 		agc_value -= (em_igp_2_cable_length_table[min_agc_index] +
8677 		    em_igp_2_cable_length_table[max_agc_index]);
8678 		agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
8679 		/*
8680 		 * Calculate cable length with the error range of +/- 10
8681 		 * meters.
8682 		 */
8683 		*min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
8684 		    (agc_value - IGP02E1000_AGC_RANGE) : 0;
8685 		*max_length = agc_value + IGP02E1000_AGC_RANGE;
8686 	}
8687 	return E1000_SUCCESS;
8688 }
8689 
8690 /******************************************************************************
8691  * Check if Downshift occurred
8692  *
8693  * hw - Struct containing variables accessed by shared code
8694  * downshift - output parameter : 0 - No Downshift occurred.
8695  *                                1 - Downshift occurred.
8696  *
8697  * returns: - E1000_ERR_XXX
8698  *            E1000_SUCCESS
8699  *
8700  * For phy's older then IGP, this function reads the Downshift bit in the Phy
8701  * Specific Status register.  For IGP phy's, it reads the Downgrade bit in the
8702  * Link Health register.  In IGP this bit is latched high, so the driver must
8703  * read it immediately after link is established.
8704  *****************************************************************************/
8705 STATIC int32_t
em_check_downshift(struct em_hw * hw)8706 em_check_downshift(struct em_hw *hw)
8707 {
8708 	int32_t  ret_val;
8709 	uint16_t phy_data;
8710 	DEBUGFUNC("em_check_downshift");
8711 
8712 	if (hw->phy_type == em_phy_igp ||
8713 	    hw->phy_type == em_phy_igp_3 ||
8714 	    hw->phy_type == em_phy_igp_2) {
8715 		ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
8716 		    &phy_data);
8717 		if (ret_val)
8718 			return ret_val;
8719 
8720 		hw->speed_downgraded = (phy_data &
8721 		    IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
8722 	} else if ((hw->phy_type == em_phy_m88) ||
8723 	    (hw->phy_type == em_phy_gg82563) ||
8724 	    (hw->phy_type == em_phy_oem) ||
8725 	    (hw->phy_type == em_phy_82578)) {
8726 		ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
8727 		    &phy_data);
8728 		if (ret_val)
8729 			return ret_val;
8730 
8731 		hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
8732 		    M88E1000_PSSR_DOWNSHIFT_SHIFT;
8733 	} else if (hw->phy_type == em_phy_ife) {
8734 		/* em_phy_ife supports 10/100 speed only */
8735 		hw->speed_downgraded = FALSE;
8736 	}
8737 	return E1000_SUCCESS;
8738 }
8739 
8740 /*****************************************************************************
8741  *
8742  * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
8743  * gigabit link is achieved to improve link quality.
8744  *
8745  * hw: Struct containing variables accessed by shared code
8746  *
8747  * returns: - E1000_ERR_PHY if fail to read/write the PHY
8748  *            E1000_SUCCESS at any other case.
8749  *
8750  ****************************************************************************/
8751 STATIC int32_t
em_config_dsp_after_link_change(struct em_hw * hw,boolean_t link_up)8752 em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up)
8753 {
8754 	int32_t  ret_val;
8755 	uint16_t phy_data, phy_saved_data, speed, duplex, i;
8756 	uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
8757 	    {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B,
8758 	    IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D};
8759 	uint16_t min_length, max_length;
8760 	DEBUGFUNC("em_config_dsp_after_link_change");
8761 
8762 	if (hw->phy_type != em_phy_igp)
8763 		return E1000_SUCCESS;
8764 
8765 	if (link_up) {
8766 		ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
8767 		if (ret_val) {
8768 			DEBUGOUT("Error getting link speed and duplex\n");
8769 			return ret_val;
8770 		}
8771 		if (speed == SPEED_1000) {
8772 
8773 			ret_val = em_get_cable_length(hw, &min_length, &max_length);
8774 			if (ret_val)
8775 				return ret_val;
8776 
8777 			if ((hw->dsp_config_state == em_dsp_config_enabled) &&
8778 			    min_length >= em_igp_cable_length_50) {
8779 
8780 				for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM;
8781 				    i++) {
8782 					ret_val = em_read_phy_reg(hw,
8783 					    dsp_reg_array[i], &phy_data);
8784 					if (ret_val)
8785 						return ret_val;
8786 
8787 					phy_data &=
8788 					    ~IGP01E1000_PHY_EDAC_MU_INDEX;
8789 
8790 					ret_val = em_write_phy_reg(hw,
8791 					    dsp_reg_array[i], phy_data);
8792 					if (ret_val)
8793 						return ret_val;
8794 				}
8795 				hw->dsp_config_state = em_dsp_config_activated;
8796 			}
8797 			if ((hw->ffe_config_state == em_ffe_config_enabled) &&
8798 			    (min_length < em_igp_cable_length_50)) {
8799 
8800 				uint16_t ffe_idle_err_timeout =
8801 				    FFE_IDLE_ERR_COUNT_TIMEOUT_20;
8802 				uint32_t idle_errs = 0;
8803 				/* clear previous idle error counts */
8804 				ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
8805 				    &phy_data);
8806 				if (ret_val)
8807 					return ret_val;
8808 
8809 				for (i = 0; i < ffe_idle_err_timeout; i++) {
8810 					usec_delay(1000);
8811 					ret_val = em_read_phy_reg(hw,
8812 					    PHY_1000T_STATUS, &phy_data);
8813 					if (ret_val)
8814 						return ret_val;
8815 
8816 					idle_errs += (phy_data &
8817 					    SR_1000T_IDLE_ERROR_CNT);
8818 					if (idle_errs >
8819 					    SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
8820 						hw->ffe_config_state =
8821 						    em_ffe_config_active;
8822 
8823 						ret_val = em_write_phy_reg(hw,
8824 						    IGP01E1000_PHY_DSP_FFE,
8825 						    IGP01E1000_PHY_DSP_FFE_CM_CP);
8826 						if (ret_val)
8827 							return ret_val;
8828 						break;
8829 					}
8830 					if (idle_errs)
8831 						ffe_idle_err_timeout =
8832 						    FFE_IDLE_ERR_COUNT_TIMEOUT_100;
8833 				}
8834 			}
8835 		}
8836 	} else {
8837 		if (hw->dsp_config_state == em_dsp_config_activated) {
8838 			/*
8839 			 * Save off the current value of register 0x2F5B to
8840 			 * be restored at the end of the routines.
8841 			 */
8842 			ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
8843 
8844 			if (ret_val)
8845 				return ret_val;
8846 
8847 			/* Disable the PHY transmitter */
8848 			ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
8849 
8850 			if (ret_val)
8851 				return ret_val;
8852 
8853 			msec_delay_irq(20);
8854 
8855 			ret_val = em_write_phy_reg(hw, 0x0000,
8856 			    IGP01E1000_IEEE_FORCE_GIGA);
8857 			if (ret_val)
8858 				return ret_val;
8859 			for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
8860 				ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
8861 				    &phy_data);
8862 				if (ret_val)
8863 					return ret_val;
8864 
8865 				phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
8866 				phy_data |=
8867 				    IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
8868 
8869 				ret_val = em_write_phy_reg(hw,
8870 				    dsp_reg_array[i], phy_data);
8871 				if (ret_val)
8872 					return ret_val;
8873 			}
8874 
8875 			ret_val = em_write_phy_reg(hw, 0x0000,
8876 			    IGP01E1000_IEEE_RESTART_AUTONEG);
8877 			if (ret_val)
8878 				return ret_val;
8879 
8880 			msec_delay_irq(20);
8881 
8882 			/* Now enable the transmitter */
8883 			ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
8884 
8885 			if (ret_val)
8886 				return ret_val;
8887 
8888 			hw->dsp_config_state = em_dsp_config_enabled;
8889 		}
8890 		if (hw->ffe_config_state == em_ffe_config_active) {
8891 			/*
8892 			 * Save off the current value of register 0x2F5B to
8893 			 * be restored at the end of the routines.
8894 			 */
8895 			ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
8896 
8897 			if (ret_val)
8898 				return ret_val;
8899 
8900 			/* Disable the PHY transmitter */
8901 			ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
8902 
8903 			if (ret_val)
8904 				return ret_val;
8905 
8906 			msec_delay_irq(20);
8907 
8908 			ret_val = em_write_phy_reg(hw, 0x0000,
8909 			    IGP01E1000_IEEE_FORCE_GIGA);
8910 			if (ret_val)
8911 				return ret_val;
8912 			ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
8913 			    IGP01E1000_PHY_DSP_FFE_DEFAULT);
8914 			if (ret_val)
8915 				return ret_val;
8916 
8917 			ret_val = em_write_phy_reg(hw, 0x0000,
8918 			    IGP01E1000_IEEE_RESTART_AUTONEG);
8919 			if (ret_val)
8920 				return ret_val;
8921 
8922 			msec_delay_irq(20);
8923 
8924 			/* Now enable the transmitter */
8925 			ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
8926 
8927 			if (ret_val)
8928 				return ret_val;
8929 
8930 			hw->ffe_config_state = em_ffe_config_enabled;
8931 		}
8932 	}
8933 	return E1000_SUCCESS;
8934 }
8935 
8936 /*****************************************************************************
8937  * Set PHY to class A mode
8938  * Assumes the following operations will follow to enable the new class mode.
8939  *  1. Do a PHY soft reset
8940  *  2. Restart auto-negotiation or force link.
8941  *
8942  * hw - Struct containing variables accessed by shared code
8943  ****************************************************************************/
8944 static int32_t
em_set_phy_mode(struct em_hw * hw)8945 em_set_phy_mode(struct em_hw *hw)
8946 {
8947 	int32_t  ret_val;
8948 	uint16_t eeprom_data;
8949 	DEBUGFUNC("em_set_phy_mode");
8950 
8951 	if ((hw->mac_type == em_82545_rev_3) &&
8952 	    (hw->media_type == em_media_type_copper)) {
8953 		ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
8954 		    &eeprom_data);
8955 		if (ret_val) {
8956 			return ret_val;
8957 		}
8958 		if ((eeprom_data != EEPROM_RESERVED_WORD) &&
8959 		    (eeprom_data & EEPROM_PHY_CLASS_A)) {
8960 			ret_val = em_write_phy_reg(hw,
8961 			    M88E1000_PHY_PAGE_SELECT, 0x000B);
8962 			if (ret_val)
8963 				return ret_val;
8964 			ret_val = em_write_phy_reg(hw,
8965 			    M88E1000_PHY_GEN_CONTROL, 0x8104);
8966 			if (ret_val)
8967 				return ret_val;
8968 
8969 			hw->phy_reset_disable = FALSE;
8970 		}
8971 	}
8972 	return E1000_SUCCESS;
8973 }
8974 
8975 /*****************************************************************************
8976  *
8977  * This function sets the lplu state according to the active flag.  When
8978  * activating lplu this function also disables smart speed and vise versa.
8979  * lplu will not be activated unless the device autonegotiation advertisement
8980  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
8981  * hw: Struct containing variables accessed by shared code
8982  * active - true to enable lplu false to disable lplu.
8983  *
8984  * returns: - E1000_ERR_PHY if fail to read/write the PHY
8985  *            E1000_SUCCESS at any other case.
8986  *
8987  ****************************************************************************/
8988 STATIC int32_t
em_set_d3_lplu_state(struct em_hw * hw,boolean_t active)8989 em_set_d3_lplu_state(struct em_hw *hw, boolean_t active)
8990 {
8991 	uint32_t phy_ctrl = 0;
8992 	int32_t  ret_val;
8993 	uint16_t phy_data;
8994 	DEBUGFUNC("em_set_d3_lplu_state");
8995 
8996 	if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2
8997 	    && hw->phy_type != em_phy_igp_3)
8998 		return E1000_SUCCESS;
8999 	/*
9000 	 * During driver activity LPLU should not be used or it will attain
9001 	 * link from the lowest speeds starting from 10Mbps. The capability
9002 	 * is used for Dx transitions and states
9003 	 */
9004 	if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) {
9005 		ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
9006 		if (ret_val)
9007 			return ret_val;
9008 	} else if (IS_ICH8(hw->mac_type)) {
9009 		/*
9010 		 * MAC writes into PHY register based on the state transition
9011 		 * and start auto-negotiation. SW driver can overwrite the
9012 		 * settings in CSR PHY power control E1000_PHY_CTRL register.
9013 		 */
9014 		phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
9015 	} else {
9016 		ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
9017 		    &phy_data);
9018 		if (ret_val)
9019 			return ret_val;
9020 	}
9021 
9022 	if (!active) {
9023 		if (hw->mac_type == em_82541_rev_2 ||
9024 		    hw->mac_type == em_82547_rev_2) {
9025 			phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
9026 			ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
9027 			    phy_data);
9028 			if (ret_val)
9029 				return ret_val;
9030 		} else {
9031 			if (IS_ICH8(hw->mac_type)) {
9032 				phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
9033 				E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
9034 			} else {
9035 				phy_data &= ~IGP02E1000_PM_D3_LPLU;
9036 				ret_val = em_write_phy_reg(hw,
9037 				    IGP02E1000_PHY_POWER_MGMT, phy_data);
9038 				if (ret_val)
9039 					return ret_val;
9040 			}
9041 		}
9042 		/*
9043 		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
9044 		 * during Dx states where the power conservation is most
9045 		 * important.  During driver activity we should enable
9046 		 * SmartSpeed, so performance is maintained.
9047 		 */
9048 		if (hw->smart_speed == em_smart_speed_on) {
9049 			ret_val = em_read_phy_reg(hw,
9050 			    IGP01E1000_PHY_PORT_CONFIG, &phy_data);
9051 			if (ret_val)
9052 				return ret_val;
9053 
9054 			phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
9055 			ret_val = em_write_phy_reg(hw,
9056 			    IGP01E1000_PHY_PORT_CONFIG, phy_data);
9057 			if (ret_val)
9058 				return ret_val;
9059 		} else if (hw->smart_speed == em_smart_speed_off) {
9060 			ret_val = em_read_phy_reg(hw,
9061 			    IGP01E1000_PHY_PORT_CONFIG, &phy_data);
9062 			if (ret_val)
9063 				return ret_val;
9064 
9065 			phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
9066 			ret_val = em_write_phy_reg(hw,
9067 			    IGP01E1000_PHY_PORT_CONFIG, phy_data);
9068 			if (ret_val)
9069 				return ret_val;
9070 		}
9071 	} else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
9072 	    || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
9073 	    (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
9074 
9075 		if (hw->mac_type == em_82541_rev_2 ||
9076 		    hw->mac_type == em_82547_rev_2) {
9077 			phy_data |= IGP01E1000_GMII_FLEX_SPD;
9078 			ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
9079 			    phy_data);
9080 			if (ret_val)
9081 				return ret_val;
9082 		} else {
9083 			if (IS_ICH8(hw->mac_type)) {
9084 				phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
9085 				E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
9086 			} else {
9087 				phy_data |= IGP02E1000_PM_D3_LPLU;
9088 				ret_val = em_write_phy_reg(hw,
9089 				    IGP02E1000_PHY_POWER_MGMT, phy_data);
9090 				if (ret_val)
9091 					return ret_val;
9092 			}
9093 		}
9094 
9095 		/* When LPLU is enabled we should disable SmartSpeed */
9096 		ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
9097 		    &phy_data);
9098 		if (ret_val)
9099 			return ret_val;
9100 
9101 		phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
9102 		ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
9103 		    phy_data);
9104 		if (ret_val)
9105 			return ret_val;
9106 
9107 	}
9108 	return E1000_SUCCESS;
9109 }
9110 
9111 /*****************************************************************************
9112  *
9113  * This function sets the lplu d0 state according to the active flag.  When
9114  * activating lplu this function also disables smart speed and vise versa.
9115  * lplu will not be activated unless the device autonegotiation advertisement
9116  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
9117  * hw: Struct containing variables accessed by shared code
9118  * active - true to enable lplu false to disable lplu.
9119  *
9120  * returns: - E1000_ERR_PHY if fail to read/write the PHY
9121  *            E1000_SUCCESS at any other case.
9122  *
9123  ****************************************************************************/
9124 STATIC int32_t
em_set_d0_lplu_state(struct em_hw * hw,boolean_t active)9125 em_set_d0_lplu_state(struct em_hw *hw, boolean_t active)
9126 {
9127 	uint32_t phy_ctrl = 0;
9128 	int32_t  ret_val;
9129 	uint16_t phy_data;
9130 	DEBUGFUNC("em_set_d0_lplu_state");
9131 
9132 	if (hw->mac_type <= em_82547_rev_2)
9133 		return E1000_SUCCESS;
9134 
9135 	if (IS_ICH8(hw->mac_type)) {
9136 		phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
9137 	} else {
9138 		ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
9139 		    &phy_data);
9140 		if (ret_val)
9141 			return ret_val;
9142 	}
9143 
9144 	if (!active) {
9145 		if (IS_ICH8(hw->mac_type)) {
9146 			phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
9147 			E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
9148 		} else {
9149 			phy_data &= ~IGP02E1000_PM_D0_LPLU;
9150 			ret_val = em_write_phy_reg(hw,
9151 			    IGP02E1000_PHY_POWER_MGMT, phy_data);
9152 			if (ret_val)
9153 				return ret_val;
9154 		}
9155 		/*
9156 		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
9157 		 * during Dx states where the power conservation is most
9158 		 * important.  During driver activity we should enable
9159 		 * SmartSpeed, so performance is maintained.
9160 		 */
9161 		if (hw->smart_speed == em_smart_speed_on) {
9162 			ret_val = em_read_phy_reg(hw,
9163 			    IGP01E1000_PHY_PORT_CONFIG, &phy_data);
9164 			if (ret_val)
9165 				return ret_val;
9166 
9167 			phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
9168 			ret_val = em_write_phy_reg(hw,
9169 			    IGP01E1000_PHY_PORT_CONFIG, phy_data);
9170 			if (ret_val)
9171 				return ret_val;
9172 		} else if (hw->smart_speed == em_smart_speed_off) {
9173 			ret_val = em_read_phy_reg(hw,
9174 			    IGP01E1000_PHY_PORT_CONFIG, &phy_data);
9175 			if (ret_val)
9176 				return ret_val;
9177 
9178 			phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
9179 			ret_val = em_write_phy_reg(hw,
9180 			    IGP01E1000_PHY_PORT_CONFIG, phy_data);
9181 			if (ret_val)
9182 				return ret_val;
9183 		}
9184 	} else {
9185 		if (IS_ICH8(hw->mac_type)) {
9186 			phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
9187 			E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
9188 		} else {
9189 			phy_data |= IGP02E1000_PM_D0_LPLU;
9190 			ret_val = em_write_phy_reg(hw,
9191 			    IGP02E1000_PHY_POWER_MGMT, phy_data);
9192 			if (ret_val)
9193 				return ret_val;
9194 		}
9195 
9196 		/* When LPLU is enabled we should disable SmartSpeed */
9197 		ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
9198 		    &phy_data);
9199 		if (ret_val)
9200 			return ret_val;
9201 
9202 		phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
9203 		ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
9204 		    phy_data);
9205 		if (ret_val)
9206 			return ret_val;
9207 
9208 	}
9209 	return E1000_SUCCESS;
9210 }
9211 
9212 /***************************************************************************
9213  *  Set Low Power Link Up state
9214  *
9215  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
9216  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
9217  *  the phy speed. This function will manually set the LPLU bit and restart
9218  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
9219  *  since it configures the same bit.
9220  ***************************************************************************/
9221 int32_t
em_set_lplu_state_pchlan(struct em_hw * hw,boolean_t active)9222 em_set_lplu_state_pchlan(struct em_hw *hw, boolean_t active)
9223 {
9224 	int32_t ret_val = E1000_SUCCESS;
9225 	uint16_t oem_reg;
9226 
9227 	DEBUGFUNC("e1000_set_lplu_state_pchlan");
9228 
9229 	ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg);
9230 	if (ret_val)
9231 		goto out;
9232 
9233 	if (active)
9234 		oem_reg |= HV_OEM_BITS_LPLU;
9235 	else
9236 		oem_reg &= ~HV_OEM_BITS_LPLU;
9237 
9238 	oem_reg |= HV_OEM_BITS_RESTART_AN;
9239 	ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg);
9240 
9241 out:
9242 	return ret_val;
9243 }
9244 
9245 /******************************************************************************
9246  * Change VCO speed register to improve Bit Error Rate performance of SERDES.
9247  *
9248  * hw - Struct containing variables accessed by shared code
9249  *****************************************************************************/
9250 static int32_t
em_set_vco_speed(struct em_hw * hw)9251 em_set_vco_speed(struct em_hw *hw)
9252 {
9253 	int32_t  ret_val;
9254 	uint16_t default_page = 0;
9255 	uint16_t phy_data;
9256 	DEBUGFUNC("em_set_vco_speed");
9257 
9258 	switch (hw->mac_type) {
9259 	case em_82545_rev_3:
9260 	case em_82546_rev_3:
9261 		break;
9262 	default:
9263 		return E1000_SUCCESS;
9264 	}
9265 
9266 	/* Set PHY register 30, page 5, bit 8 to 0 */
9267 
9268 	ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
9269 	if (ret_val)
9270 		return ret_val;
9271 
9272 	ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
9273 	if (ret_val)
9274 		return ret_val;
9275 
9276 	ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
9277 	if (ret_val)
9278 		return ret_val;
9279 
9280 	phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
9281 	ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
9282 	if (ret_val)
9283 		return ret_val;
9284 
9285 	/* Set PHY register 30, page 4, bit 11 to 1 */
9286 
9287 	ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
9288 	if (ret_val)
9289 		return ret_val;
9290 
9291 	ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
9292 	if (ret_val)
9293 		return ret_val;
9294 
9295 	phy_data |= M88E1000_PHY_VCO_REG_BIT11;
9296 	ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
9297 	if (ret_val)
9298 		return ret_val;
9299 
9300 	ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
9301 	if (ret_val)
9302 		return ret_val;
9303 
9304 	return E1000_SUCCESS;
9305 }
9306 
9307 /*****************************************************************************
9308  * This function reads the cookie from ARC ram.
9309  *
9310  * returns: - E1000_SUCCESS .
9311  ****************************************************************************/
9312 STATIC int32_t
em_host_if_read_cookie(struct em_hw * hw,uint8_t * buffer)9313 em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer)
9314 {
9315 	uint8_t  i;
9316 	uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
9317 	uint8_t  length = E1000_MNG_DHCP_COOKIE_LENGTH;
9318 	length = (length >> 2);
9319 	offset = (offset >> 2);
9320 
9321 	for (i = 0; i < length; i++) {
9322 		*((uint32_t *) buffer + i) =
9323 		    E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
9324 	}
9325 	return E1000_SUCCESS;
9326 }
9327 
9328 /*****************************************************************************
9329  * This function checks whether the HOST IF is enabled for command operation
9330  * and also checks whether the previous command is completed.
9331  * It busy waits in case of previous command is not completed.
9332  *
9333  * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
9334  *            timeout
9335  *          - E1000_SUCCESS for success.
9336  ****************************************************************************/
9337 STATIC int32_t
em_mng_enable_host_if(struct em_hw * hw)9338 em_mng_enable_host_if(struct em_hw *hw)
9339 {
9340 	uint32_t hicr;
9341 	uint8_t  i;
9342 	/* Check that the host interface is enabled. */
9343 	hicr = E1000_READ_REG(hw, HICR);
9344 	if ((hicr & E1000_HICR_EN) == 0) {
9345 		DEBUGOUT("E1000_HOST_EN bit disabled.\n");
9346 		return -E1000_ERR_HOST_INTERFACE_COMMAND;
9347 	}
9348 	/* check the previous command is completed */
9349 	for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
9350 		hicr = E1000_READ_REG(hw, HICR);
9351 		if (!(hicr & E1000_HICR_C))
9352 			break;
9353 		msec_delay_irq(1);
9354 	}
9355 
9356 	if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
9357 		DEBUGOUT("Previous command timeout failed .\n");
9358 		return -E1000_ERR_HOST_INTERFACE_COMMAND;
9359 	}
9360 	return E1000_SUCCESS;
9361 }
9362 
9363 /*****************************************************************************
9364  * This function checks the mode of the firmware.
9365  *
9366  * returns  - TRUE when the mode is IAMT or FALSE.
9367  ****************************************************************************/
9368 boolean_t
em_check_mng_mode(struct em_hw * hw)9369 em_check_mng_mode(struct em_hw *hw)
9370 {
9371 	uint32_t fwsm;
9372 	fwsm = E1000_READ_REG(hw, FWSM);
9373 
9374 	if (IS_ICH8(hw->mac_type)) {
9375 		if ((fwsm & E1000_FWSM_MODE_MASK) ==
9376 		    (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
9377 			return TRUE;
9378 	} else if ((fwsm & E1000_FWSM_MODE_MASK) ==
9379 	    (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
9380 		return TRUE;
9381 
9382 	return FALSE;
9383 }
9384 
9385 /*****************************************************************************
9386  * This function calculates the checksum.
9387  *
9388  * returns  - checksum of buffer contents.
9389  ****************************************************************************/
9390 STATIC uint8_t
em_calculate_mng_checksum(char * buffer,uint32_t length)9391 em_calculate_mng_checksum(char *buffer, uint32_t length)
9392 {
9393 	uint8_t  sum = 0;
9394 	uint32_t i;
9395 	if (!buffer)
9396 		return 0;
9397 
9398 	for (i = 0; i < length; i++)
9399 		sum += buffer[i];
9400 
9401 	return (uint8_t) (0 - sum);
9402 }
9403 
9404 /*****************************************************************************
9405  * This function checks whether tx pkt filtering needs to be enabled or not.
9406  *
9407  * returns  - TRUE for packet filtering or FALSE.
9408  ****************************************************************************/
9409 boolean_t
em_enable_tx_pkt_filtering(struct em_hw * hw)9410 em_enable_tx_pkt_filtering(struct em_hw *hw)
9411 {
9412 	/* called in init as well as watchdog timer functions */
9413 	int32_t   ret_val, checksum;
9414 	boolean_t tx_filter = FALSE;
9415 	struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
9416 	uint8_t   *buffer = (uint8_t *) & (hw->mng_cookie);
9417 	if (em_check_mng_mode(hw)) {
9418 		ret_val = em_mng_enable_host_if(hw);
9419 		if (ret_val == E1000_SUCCESS) {
9420 			ret_val = em_host_if_read_cookie(hw, buffer);
9421 			if (ret_val == E1000_SUCCESS) {
9422 				checksum = hdr->checksum;
9423 				hdr->checksum = 0;
9424 				if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
9425 				    checksum == em_calculate_mng_checksum(
9426 				    (char *) buffer,
9427 				    E1000_MNG_DHCP_COOKIE_LENGTH)) {
9428 					if (hdr->status &
9429 					    E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
9430 						tx_filter = TRUE;
9431 				} else
9432 					tx_filter = TRUE;
9433 			} else
9434 				tx_filter = TRUE;
9435 		}
9436 	}
9437 	hw->tx_pkt_filtering = tx_filter;
9438 	return tx_filter;
9439 }
9440 
9441 static int32_t
em_polarity_reversal_workaround(struct em_hw * hw)9442 em_polarity_reversal_workaround(struct em_hw *hw)
9443 {
9444 	int32_t  ret_val;
9445 	uint16_t mii_status_reg;
9446 	uint16_t i;
9447 	/* Polarity reversal workaround for forced 10F/10H links. */
9448 
9449 	/* Disable the transmitter on the PHY */
9450 	ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
9451 	if (ret_val)
9452 		return ret_val;
9453 	ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
9454 	if (ret_val)
9455 		return ret_val;
9456 
9457 	ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
9458 	if (ret_val)
9459 		return ret_val;
9460 
9461 	/* This loop will early-out if the NO link condition has been met. */
9462 	for (i = PHY_FORCE_TIME; i > 0; i--) {
9463 		/*
9464 		 * Read the MII Status Register and wait for Link Status bit
9465 		 * to be clear.
9466 		 */
9467 
9468 		ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
9469 		if (ret_val)
9470 			return ret_val;
9471 
9472 		ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
9473 		if (ret_val)
9474 			return ret_val;
9475 
9476 		if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
9477 			break;
9478 		msec_delay_irq(100);
9479 	}
9480 
9481 	/* Recommended delay time after link has been lost */
9482 	msec_delay_irq(1000);
9483 
9484 	/* Now we will re-enable the transmitter on the PHY */
9485 
9486 	ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
9487 	if (ret_val)
9488 		return ret_val;
9489 	msec_delay_irq(50);
9490 	ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
9491 	if (ret_val)
9492 		return ret_val;
9493 	msec_delay_irq(50);
9494 	ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
9495 	if (ret_val)
9496 		return ret_val;
9497 	msec_delay_irq(50);
9498 	ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
9499 	if (ret_val)
9500 		return ret_val;
9501 
9502 	ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
9503 	if (ret_val)
9504 		return ret_val;
9505 
9506 	/* This loop will early-out if the link condition has been met. */
9507 	for (i = PHY_FORCE_TIME; i > 0; i--) {
9508 		/*
9509 		 * Read the MII Status Register and wait for Link Status bit
9510 		 * to be set.
9511 		 */
9512 
9513 		ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
9514 		if (ret_val)
9515 			return ret_val;
9516 
9517 		ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
9518 		if (ret_val)
9519 			return ret_val;
9520 
9521 		if (mii_status_reg & MII_SR_LINK_STATUS)
9522 			break;
9523 		msec_delay_irq(100);
9524 	}
9525 	return E1000_SUCCESS;
9526 }
9527 
9528 /******************************************************************************
9529  *
9530  * Disables PCI-Express master access.
9531  *
9532  * hw: Struct containing variables accessed by shared code
9533  *
9534  * returns: - none.
9535  *
9536  *****************************************************************************/
9537 STATIC void
em_set_pci_express_master_disable(struct em_hw * hw)9538 em_set_pci_express_master_disable(struct em_hw *hw)
9539 {
9540 	uint32_t ctrl;
9541 	DEBUGFUNC("em_set_pci_express_master_disable");
9542 
9543 	if (hw->bus_type != em_bus_type_pci_express)
9544 		return;
9545 
9546 	ctrl = E1000_READ_REG(hw, CTRL);
9547 	ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
9548 	E1000_WRITE_REG(hw, CTRL, ctrl);
9549 }
9550 
9551 /******************************************************************************
9552  *
9553  * Disables PCI-Express master access and verifies there are no pending
9554  * requests
9555  *
9556  * hw: Struct containing variables accessed by shared code
9557  *
9558  * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
9559  *            caused the master requests to be disabled.
9560  *            E1000_SUCCESS master requests disabled.
9561  *
9562  ******************************************************************************/
9563 int32_t
em_disable_pciex_master(struct em_hw * hw)9564 em_disable_pciex_master(struct em_hw *hw)
9565 {
9566 	int32_t timeout = MASTER_DISABLE_TIMEOUT;	/* 80ms */
9567 	DEBUGFUNC("em_disable_pciex_master");
9568 
9569 	if (hw->bus_type != em_bus_type_pci_express)
9570 		return E1000_SUCCESS;
9571 
9572 	em_set_pci_express_master_disable(hw);
9573 
9574 	while (timeout) {
9575 		if (!(E1000_READ_REG(hw, STATUS) &
9576 		    E1000_STATUS_GIO_MASTER_ENABLE))
9577 			break;
9578 		else
9579 			usec_delay(100);
9580 		timeout--;
9581 	}
9582 
9583 	if (!timeout) {
9584 		DEBUGOUT("Master requests are pending.\n");
9585 		return -E1000_ERR_MASTER_REQUESTS_PENDING;
9586 	}
9587 	return E1000_SUCCESS;
9588 }
9589 
9590 /******************************************************************************
9591  *
9592  * Check for EEPROM Auto Read bit done.
9593  *
9594  * hw: Struct containing variables accessed by shared code
9595  *
9596  * returns: - E1000_ERR_RESET if fail to reset MAC
9597  *            E1000_SUCCESS at any other case.
9598  *
9599  ******************************************************************************/
9600 STATIC int32_t
em_get_auto_rd_done(struct em_hw * hw)9601 em_get_auto_rd_done(struct em_hw *hw)
9602 {
9603 	int32_t timeout = AUTO_READ_DONE_TIMEOUT;
9604 	DEBUGFUNC("em_get_auto_rd_done");
9605 
9606 	switch (hw->mac_type) {
9607 	default:
9608 		msec_delay(5);
9609 		break;
9610 	case em_82571:
9611 	case em_82572:
9612 	case em_82573:
9613 	case em_82574:
9614 	case em_82575:
9615 	case em_82576:
9616 	case em_82580:
9617 	case em_80003es2lan:
9618 	case em_i210:
9619 	case em_i350:
9620 	case em_ich8lan:
9621 	case em_ich9lan:
9622 	case em_ich10lan:
9623 	case em_pchlan:
9624 	case em_pch2lan:
9625 	case em_pch_lpt:
9626 	case em_pch_spt:
9627 	case em_pch_cnp:
9628 	case em_pch_tgp:
9629 	case em_pch_adp:
9630 		while (timeout) {
9631 			if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
9632 				break;
9633 			else
9634 				msec_delay(1);
9635 			timeout--;
9636 		}
9637 
9638 		if (!timeout) {
9639 			DEBUGOUT("Auto read by HW from EEPROM has not"
9640 			    " completed.\n");
9641 			return -E1000_ERR_RESET;
9642 		}
9643 		break;
9644 	}
9645 	/*
9646 	 * PHY configuration from NVM just starts after EECD_AUTO_RD sets to
9647 	 * high. Need to wait for PHY configuration completion before
9648 	 * accessing NVM and PHY.
9649 	 */
9650 	if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574))
9651 		msec_delay(25);
9652 
9653 	return E1000_SUCCESS;
9654 }
9655 
9656 /***************************************************************************
9657  * Checks if the PHY configuration is done
9658  *
9659  * hw: Struct containing variables accessed by shared code
9660  *
9661  * returns: - E1000_ERR_RESET if fail to reset MAC
9662  *            E1000_SUCCESS at any other case.
9663  *
9664  ***************************************************************************/
9665 STATIC int32_t
em_get_phy_cfg_done(struct em_hw * hw)9666 em_get_phy_cfg_done(struct em_hw *hw)
9667 {
9668 	int32_t  timeout = PHY_CFG_TIMEOUT;
9669 	uint32_t cfg_mask = E1000_NVM_CFG_DONE_PORT_0;
9670 	DEBUGFUNC("em_get_phy_cfg_done");
9671 
9672 	switch (hw->mac_type) {
9673 	default:
9674 		msec_delay_irq(10);
9675 		break;
9676 	case em_80003es2lan:
9677 	case em_82575:
9678 	case em_82576:
9679 	case em_82580:
9680 	case em_i350:
9681 		switch (hw->bus_func) {
9682 		case 1:
9683 			cfg_mask = E1000_NVM_CFG_DONE_PORT_1;
9684 			break;
9685 		case 2:
9686 			cfg_mask = E1000_NVM_CFG_DONE_PORT_2;
9687 			break;
9688 		case 3:
9689 			cfg_mask = E1000_NVM_CFG_DONE_PORT_3;
9690 			break;
9691 		}
9692 		/* FALLTHROUGH */
9693 	case em_82571:
9694 	case em_82572:
9695 		while (timeout) {
9696 			if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
9697 				break;
9698 			else
9699 				msec_delay(1);
9700 			timeout--;
9701 		}
9702 		if (!timeout) {
9703 			DEBUGOUT("MNG configuration cycle has not completed."
9704 			    "\n");
9705 		}
9706 		break;
9707 	}
9708 
9709 	return E1000_SUCCESS;
9710 }
9711 
9712 /***************************************************************************
9713  *
9714  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
9715  * adapter or Eeprom access.
9716  *
9717  * hw: Struct containing variables accessed by shared code
9718  *
9719  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
9720  *            E1000_SUCCESS at any other case.
9721  *
9722  ***************************************************************************/
9723 STATIC int32_t
em_get_hw_eeprom_semaphore(struct em_hw * hw)9724 em_get_hw_eeprom_semaphore(struct em_hw *hw)
9725 {
9726 	int32_t  timeout;
9727 	uint32_t swsm;
9728 	DEBUGFUNC("em_get_hw_eeprom_semaphore");
9729 
9730 	if (!hw->eeprom_semaphore_present)
9731 		return E1000_SUCCESS;
9732 
9733 	if (hw->mac_type == em_80003es2lan) {
9734 		/* Get the SW semaphore. */
9735 		if (em_get_software_semaphore(hw) != E1000_SUCCESS)
9736 			return -E1000_ERR_EEPROM;
9737 	}
9738 	/* Get the FW semaphore. */
9739 	timeout = hw->eeprom.word_size + 1;
9740 	while (timeout) {
9741 		swsm = E1000_READ_REG(hw, SWSM);
9742 		swsm |= E1000_SWSM_SWESMBI;
9743 		E1000_WRITE_REG(hw, SWSM, swsm);
9744 		/* if we managed to set the bit we got the semaphore. */
9745 		swsm = E1000_READ_REG(hw, SWSM);
9746 		if (swsm & E1000_SWSM_SWESMBI)
9747 			break;
9748 
9749 		usec_delay(50);
9750 		timeout--;
9751 	}
9752 
9753 	if (!timeout) {
9754 		/* Release semaphores */
9755 		em_put_hw_eeprom_semaphore(hw);
9756 		DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set."
9757 		    "\n");
9758 		return -E1000_ERR_EEPROM;
9759 	}
9760 	return E1000_SUCCESS;
9761 }
9762 
9763 /***************************************************************************
9764  * This function clears HW semaphore bits.
9765  *
9766  * hw: Struct containing variables accessed by shared code
9767  *
9768  * returns: - None.
9769  *
9770  ***************************************************************************/
9771 STATIC void
em_put_hw_eeprom_semaphore(struct em_hw * hw)9772 em_put_hw_eeprom_semaphore(struct em_hw *hw)
9773 {
9774 	uint32_t swsm;
9775 	DEBUGFUNC("em_put_hw_eeprom_semaphore");
9776 
9777 	if (!hw->eeprom_semaphore_present)
9778 		return;
9779 
9780 	swsm = E1000_READ_REG(hw, SWSM);
9781 	if (hw->mac_type == em_80003es2lan) {
9782 		/* Release both semaphores. */
9783 		swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
9784 	} else
9785 		swsm &= ~(E1000_SWSM_SWESMBI);
9786 	E1000_WRITE_REG(hw, SWSM, swsm);
9787 }
9788 
9789 /***************************************************************************
9790  *
9791  * Obtaining software semaphore bit (SMBI) before resetting PHY.
9792  *
9793  * hw: Struct containing variables accessed by shared code
9794  *
9795  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
9796  *            E1000_SUCCESS at any other case.
9797  *
9798  ***************************************************************************/
9799 STATIC int32_t
em_get_software_semaphore(struct em_hw * hw)9800 em_get_software_semaphore(struct em_hw *hw)
9801 {
9802 	int32_t  timeout = hw->eeprom.word_size + 1;
9803 	uint32_t swsm;
9804 	DEBUGFUNC("em_get_software_semaphore");
9805 
9806 	if (hw->mac_type != em_80003es2lan)
9807 		return E1000_SUCCESS;
9808 
9809 	while (timeout) {
9810 		swsm = E1000_READ_REG(hw, SWSM);
9811 		/*
9812 		 * If SMBI bit cleared, it is now set and we hold the
9813 		 * semaphore
9814 		 */
9815 		if (!(swsm & E1000_SWSM_SMBI))
9816 			break;
9817 		msec_delay_irq(1);
9818 		timeout--;
9819 	}
9820 
9821 	if (!timeout) {
9822 		DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
9823 		return -E1000_ERR_RESET;
9824 	}
9825 	return E1000_SUCCESS;
9826 }
9827 
9828 /***************************************************************************
9829  *
9830  * Release semaphore bit (SMBI).
9831  *
9832  * hw: Struct containing variables accessed by shared code
9833  *
9834  ***************************************************************************/
9835 STATIC void
em_release_software_semaphore(struct em_hw * hw)9836 em_release_software_semaphore(struct em_hw *hw)
9837 {
9838 	uint32_t swsm;
9839 	DEBUGFUNC("em_release_software_semaphore");
9840 
9841 	if (hw->mac_type != em_80003es2lan)
9842 		return;
9843 
9844 	swsm = E1000_READ_REG(hw, SWSM);
9845 	/* Release the SW semaphores. */
9846 	swsm &= ~E1000_SWSM_SMBI;
9847 	E1000_WRITE_REG(hw, SWSM, swsm);
9848 }
9849 
9850 /******************************************************************************
9851  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
9852  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
9853  * the caller to figure out how to deal with it.
9854  *
9855  * hw - Struct containing variables accessed by shared code
9856  *
9857  * returns: - E1000_BLK_PHY_RESET
9858  *            E1000_SUCCESS
9859  *
9860  *****************************************************************************/
9861 int32_t
em_check_phy_reset_block(struct em_hw * hw)9862 em_check_phy_reset_block(struct em_hw *hw)
9863 {
9864 	uint32_t manc = 0;
9865 	uint32_t fwsm = 0;
9866 	DEBUGFUNC("em_check_phy_reset_block\n");
9867 
9868 	if (IS_ICH8(hw->mac_type)) {
9869 		int i = 0;
9870 		int blocked = 0;
9871 		do {
9872 			fwsm = E1000_READ_REG(hw, FWSM);
9873 			if (!(fwsm & E1000_FWSM_RSPCIPHY)) {
9874 				blocked = 1;
9875 				msec_delay(10);
9876 				continue;
9877 			}
9878 			blocked = 0;
9879 		} while (blocked && (i++ < 30));
9880 		return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
9881 	}
9882 	if (hw->mac_type > em_82547_rev_2)
9883 		manc = E1000_READ_REG(hw, MANC);
9884 	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
9885 	    E1000_BLK_PHY_RESET : E1000_SUCCESS;
9886 }
9887 
9888 /******************************************************************************
9889  * Configure PCI-Ex no-snoop
9890  *
9891  * hw - Struct containing variables accessed by shared code.
9892  * no_snoop - Bitmap of no-snoop events.
9893  *
9894  * returns: E1000_SUCCESS
9895  *
9896  *****************************************************************************/
9897 STATIC int32_t
em_set_pci_ex_no_snoop(struct em_hw * hw,uint32_t no_snoop)9898 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop)
9899 {
9900 	uint32_t gcr_reg = 0;
9901 	DEBUGFUNC("em_set_pci_ex_no_snoop");
9902 
9903 	if (hw->bus_type == em_bus_type_unknown)
9904 		em_get_bus_info(hw);
9905 
9906 	if (hw->bus_type != em_bus_type_pci_express)
9907 		return E1000_SUCCESS;
9908 
9909 	if (no_snoop) {
9910 		gcr_reg = E1000_READ_REG(hw, GCR);
9911 		gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
9912 		gcr_reg |= no_snoop;
9913 		E1000_WRITE_REG(hw, GCR, gcr_reg);
9914 	}
9915 	if (IS_ICH8(hw->mac_type)) {
9916 		uint32_t ctrl_ext;
9917 		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
9918 		ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
9919 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
9920 	}
9921 	return E1000_SUCCESS;
9922 }
9923 
9924 /***************************************************************************
9925  *
9926  * Get software semaphore FLAG bit (SWFLAG).
9927  * SWFLAG is used to synchronize the access to all shared resource between
9928  * SW, FW and HW.
9929  *
9930  * hw: Struct containing variables accessed by shared code
9931  *
9932  ***************************************************************************/
9933 STATIC int32_t
em_get_software_flag(struct em_hw * hw)9934 em_get_software_flag(struct em_hw *hw)
9935 {
9936 	int32_t  timeout = PHY_CFG_TIMEOUT;
9937 	uint32_t extcnf_ctrl;
9938 	DEBUGFUNC("em_get_software_flag");
9939 
9940 	if (IS_ICH8(hw->mac_type)) {
9941 		if (hw->sw_flag) {
9942 			hw->sw_flag++;
9943 			return E1000_SUCCESS;
9944 		}
9945 		while (timeout) {
9946 			extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
9947 			if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
9948 				break;
9949 			msec_delay_irq(1);
9950 			timeout--;
9951 		}
9952 		if (!timeout) {
9953 			printf("%s: SW has already locked the resource?\n",
9954 			    __func__);
9955 			return -E1000_ERR_CONFIG;
9956 		}
9957 		timeout = SW_FLAG_TIMEOUT;
9958 		extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
9959 		E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
9960 
9961 		while (timeout) {
9962 			extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
9963 			if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
9964 				break;
9965 			msec_delay_irq(1);
9966 			timeout--;
9967 		}
9968 
9969 		if (!timeout) {
9970 			printf("Failed to acquire the semaphore, FW or HW "
9971 			    "has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
9972 			    E1000_READ_REG(hw, FWSM), extcnf_ctrl);
9973 			extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
9974 			E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
9975 			return -E1000_ERR_CONFIG;
9976 		}
9977 	}
9978 	hw->sw_flag++;
9979 	return E1000_SUCCESS;
9980 }
9981 
9982 /***************************************************************************
9983  *
9984  * Release software semaphore FLAG bit (SWFLAG).
9985  * SWFLAG is used to synchronize the access to all shared resource between
9986  * SW, FW and HW.
9987  *
9988  * hw: Struct containing variables accessed by shared code
9989  *
9990  ***************************************************************************/
9991 STATIC void
em_release_software_flag(struct em_hw * hw)9992 em_release_software_flag(struct em_hw *hw)
9993 {
9994 	uint32_t extcnf_ctrl;
9995 	DEBUGFUNC("em_release_software_flag");
9996 
9997 	if (IS_ICH8(hw->mac_type)) {
9998 		KASSERT(hw->sw_flag > 0);
9999 		if (--hw->sw_flag > 0)
10000 			return;
10001 		extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
10002 		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
10003 		E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
10004 	}
10005 	return;
10006 }
10007 
10008 /**
10009  *  em_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
10010  *  @hw: pointer to the HW structure
10011  *  @bank:  pointer to the variable that returns the active bank
10012  *
10013  *  Reads signature byte from the NVM using the flash access registers.
10014  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
10015  **/
10016 int32_t
em_valid_nvm_bank_detect_ich8lan(struct em_hw * hw,uint32_t * bank)10017 em_valid_nvm_bank_detect_ich8lan(struct em_hw *hw, uint32_t *bank)
10018 {
10019 	uint32_t eecd;
10020 	uint32_t bank1_offset = hw->flash_bank_size * sizeof(uint16_t);
10021 	uint32_t act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
10022 	uint32_t nvm_dword = 0;
10023 	uint8_t sig_byte = 0;
10024 	int32_t ret_val;
10025 
10026 	DEBUGFUNC("em_valid_nvm_bank_detect_ich8lan");
10027 
10028 	switch (hw->mac_type) {
10029 	case em_pch_spt:
10030 	case em_pch_cnp:
10031 	case em_pch_tgp:
10032 	case em_pch_adp:
10033 		bank1_offset = hw->flash_bank_size * 2;
10034 		act_offset = E1000_ICH_NVM_SIG_WORD * 2;
10035 
10036 		/* set bank to 0 in case flash read fails. */
10037 		*bank = 0;
10038 
10039 		/* Check bank 0 */
10040 		ret_val = em_read_ich8_dword(hw, act_offset, &nvm_dword);
10041 		if (ret_val)
10042 			return ret_val;
10043 		sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8);
10044 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
10045 		    E1000_ICH_NVM_SIG_VALUE) {
10046 			*bank = 0;
10047 			return 0;
10048 		}
10049 
10050 		/* Check bank 1 */
10051 		ret_val = em_read_ich8_dword(hw, act_offset + bank1_offset,
10052 		    &nvm_dword);
10053 		if (ret_val)
10054 			return ret_val;
10055 		sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8);
10056 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
10057 		    E1000_ICH_NVM_SIG_VALUE) {
10058 			*bank = 1;
10059 			return 0;
10060 		}
10061 
10062 		DEBUGOUT("ERROR: No valid NVM bank present\n");
10063 		return -1;
10064 	case em_ich8lan:
10065 	case em_ich9lan:
10066 		eecd = E1000_READ_REG(hw, EECD);
10067 		if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
10068 		    E1000_EECD_SEC1VAL_VALID_MASK) {
10069 			if (eecd & E1000_EECD_SEC1VAL)
10070 				*bank = 1;
10071 			else
10072 				*bank = 0;
10073 
10074 			return E1000_SUCCESS;
10075 		}
10076 		DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
10077 		/* fall-thru */
10078 	default:
10079 		/* set bank to 0 in case flash read fails */
10080 		*bank = 0;
10081 
10082 		/* Check bank 0 */
10083 		ret_val = em_read_ich8_byte(hw, act_offset,
10084 							&sig_byte);
10085 		if (ret_val)
10086 			return ret_val;
10087 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
10088 		    E1000_ICH_NVM_SIG_VALUE) {
10089 			*bank = 0;
10090 			return E1000_SUCCESS;
10091 		}
10092 
10093 		/* Check bank 1 */
10094 		ret_val = em_read_ich8_byte(hw, act_offset +
10095 							bank1_offset,
10096 							&sig_byte);
10097 		if (ret_val)
10098 			return ret_val;
10099 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
10100 		    E1000_ICH_NVM_SIG_VALUE) {
10101 			*bank = 1;
10102 			return E1000_SUCCESS;
10103 		}
10104 
10105 		DEBUGOUT("ERROR: No valid NVM bank present\n");
10106 		return -1;
10107 	}
10108 }
10109 
10110 STATIC int32_t
em_read_eeprom_spt(struct em_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)10111 em_read_eeprom_spt(struct em_hw *hw, uint16_t offset, uint16_t words,
10112     uint16_t *data)
10113 {
10114 	int32_t  error = E1000_SUCCESS;
10115 	uint32_t flash_bank = 0;
10116 	uint32_t act_offset = 0;
10117 	uint32_t bank_offset = 0;
10118 	uint32_t dword = 0;
10119 	uint16_t i = 0, add;
10120 
10121 	/*
10122 	 * We need to know which is the valid flash bank.  In the event that
10123 	 * we didn't allocate eeprom_shadow_ram, we may not be managing
10124 	 * flash_bank.  So it cannot be trusted and needs to be updated with
10125 	 * each read.
10126 	 */
10127 
10128 	if (hw->mac_type < em_pch_spt)
10129 		return -E1000_ERR_EEPROM;
10130 
10131 	error = em_get_software_flag(hw);
10132 	if (error != E1000_SUCCESS)
10133 		return error;
10134 
10135 	error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank);
10136 	if (error != E1000_SUCCESS) {
10137 		DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
10138 		flash_bank = 0;
10139 	}
10140 
10141 	/*
10142 	 * Adjust offset appropriately if we're on bank 1 - adjust for word
10143 	 * size
10144 	 */
10145 	bank_offset = flash_bank * (hw->flash_bank_size * 2);
10146 
10147 	for (i = add = 0; i < words; i += add) {
10148 		if ((offset + i) % 2) {
10149 			add = 1;
10150 			if (hw->eeprom_shadow_ram != NULL
10151 			    && hw->eeprom_shadow_ram[offset + i].modified) {
10152 				data[i] =
10153 				    hw->eeprom_shadow_ram[offset+i].eeprom_word;
10154 				continue;
10155 			}
10156 			act_offset = bank_offset + (offset + i - 1) * 2;
10157 		} else {
10158 			add = 2;
10159 			if (hw->eeprom_shadow_ram != NULL
10160 			    && hw->eeprom_shadow_ram[offset+i].modified
10161 			    && hw->eeprom_shadow_ram[offset+i+1].modified) {
10162 				data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
10163 				data[i+1] = hw->eeprom_shadow_ram[offset+i+1].eeprom_word;
10164 				continue;
10165 			}
10166 			act_offset = bank_offset + (offset + i) * 2;
10167 		}
10168 		error = em_read_ich8_dword(hw, act_offset, &dword);
10169 		if (error != E1000_SUCCESS)
10170 			break;
10171 		if (hw->eeprom_shadow_ram != NULL
10172 		    && hw->eeprom_shadow_ram[offset+i].modified) {
10173 			data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
10174 		} else {
10175 			if (add == 1)
10176 				data[i] = dword >> 16;
10177 			else
10178 				data[i] = dword & 0xFFFFUL;
10179 		}
10180 		if (add == 1 || words-i == 1)
10181 			continue;
10182 		if (hw->eeprom_shadow_ram != NULL
10183 		    && hw->eeprom_shadow_ram[offset+i+1].modified) {
10184 			data[i+1] =
10185 			    hw->eeprom_shadow_ram[offset+i+1].eeprom_word;
10186 		} else {
10187 			data[i+1] = dword >> 16;
10188 		}
10189 	}
10190 
10191 	em_release_software_flag(hw);
10192 
10193 	return error;
10194 }
10195 
10196 /******************************************************************************
10197  * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
10198  * register.
10199  *
10200  * hw - Struct containing variables accessed by shared code
10201  * offset - offset of word in the EEPROM to read
10202  * data - word read from the EEPROM
10203  * words - number of words to read
10204  *****************************************************************************/
10205 STATIC int32_t
em_read_eeprom_ich8(struct em_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)10206 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words,
10207     uint16_t *data)
10208 {
10209 	int32_t  error = E1000_SUCCESS;
10210 	uint32_t flash_bank = 0;
10211 	uint32_t act_offset = 0;
10212 	uint32_t bank_offset = 0;
10213 	uint16_t word = 0;
10214 	uint16_t i = 0;
10215 	/*
10216 	 * We need to know which is the valid flash bank.  In the event that
10217 	 * we didn't allocate eeprom_shadow_ram, we may not be managing
10218 	 * flash_bank.  So it cannot be trusted and needs to be updated with
10219 	 * each read.
10220 	 */
10221 
10222 	if (hw->mac_type >= em_pch_spt)
10223 		return em_read_eeprom_spt(hw, offset, words, data);
10224 
10225 	error = em_get_software_flag(hw);
10226 	if (error != E1000_SUCCESS)
10227 		return error;
10228 
10229 	error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank);
10230 	if (error != E1000_SUCCESS) {
10231 		DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
10232 		flash_bank = 0;
10233 	}
10234 
10235 	/*
10236 	 * Adjust offset appropriately if we're on bank 1 - adjust for word
10237 	 * size
10238 	 */
10239 	bank_offset = flash_bank * (hw->flash_bank_size * 2);
10240 
10241 	for (i = 0; i < words; i++) {
10242 		if (hw->eeprom_shadow_ram != NULL &&
10243 		    hw->eeprom_shadow_ram[offset + i].modified == TRUE) {
10244 			data[i] =
10245 			    hw->eeprom_shadow_ram[offset + i].eeprom_word;
10246 		} else {
10247 			/* The NVM part needs a byte offset, hence * 2 */
10248 			act_offset = bank_offset + ((offset + i) * 2);
10249 			error = em_read_ich8_word(hw, act_offset, &word);
10250 			if (error != E1000_SUCCESS)
10251 				break;
10252 			data[i] = word;
10253 		}
10254 	}
10255 
10256 	em_release_software_flag(hw);
10257 
10258 	return error;
10259 }
10260 
10261 /******************************************************************************
10262  * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
10263  * register.  Actually, writes are written to the shadow ram cache in the hw
10264  * structure hw->em_shadow_ram.  em_commit_shadow_ram flushes this to
10265  * the NVM, which occurs when the NVM checksum is updated.
10266  *
10267  * hw - Struct containing variables accessed by shared code
10268  * offset - offset of word in the EEPROM to write
10269  * words - number of words to write
10270  * data - words to write to the EEPROM
10271  *****************************************************************************/
10272 STATIC int32_t
em_write_eeprom_ich8(struct em_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)10273 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words,
10274     uint16_t *data)
10275 {
10276 	uint32_t i = 0;
10277 	int32_t  error = E1000_SUCCESS;
10278 	error = em_get_software_flag(hw);
10279 	if (error != E1000_SUCCESS)
10280 		return error;
10281 	/*
10282 	 * A driver can write to the NVM only if it has eeprom_shadow_ram
10283 	 * allocated.  Subsequent reads to the modified words are read from
10284 	 * this cached structure as well.  Writes will only go into this
10285 	 * cached structure unless it's followed by a call to
10286 	 * em_update_eeprom_checksum() where it will commit the changes and
10287 	 * clear the "modified" field.
10288 	 */
10289 	if (hw->eeprom_shadow_ram != NULL) {
10290 		for (i = 0; i < words; i++) {
10291 			if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
10292 				hw->eeprom_shadow_ram[offset + i].modified =
10293 				    TRUE;
10294 				hw->eeprom_shadow_ram[offset + i].eeprom_word =
10295 				    data[i];
10296 			} else {
10297 				error = -E1000_ERR_EEPROM;
10298 				break;
10299 			}
10300 		}
10301 	} else {
10302 		/*
10303 		 * Drivers have the option to not allocate eeprom_shadow_ram
10304 		 * as long as they don't perform any NVM writes.  An attempt
10305 		 * in doing so will result in this error.
10306 		 */
10307 		error = -E1000_ERR_EEPROM;
10308 	}
10309 
10310 	em_release_software_flag(hw);
10311 
10312 	return error;
10313 }
10314 
10315 /******************************************************************************
10316  * This function does initial flash setup so that a new read/write/erase cycle
10317  * can be started.
10318  *
10319  * hw - The pointer to the hw structure
10320  ****************************************************************************/
10321 STATIC int32_t
em_ich8_cycle_init(struct em_hw * hw)10322 em_ich8_cycle_init(struct em_hw *hw)
10323 {
10324 	union ich8_hws_flash_status hsfsts;
10325 	int32_t error = E1000_ERR_EEPROM;
10326 	int32_t i = 0;
10327 	DEBUGFUNC("em_ich8_cycle_init");
10328 
10329 	if (hw->mac_type >= em_pch_spt)
10330 		hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw,
10331 		    ICH_FLASH_HSFSTS) & 0xFFFFUL;
10332 	else
10333 		hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,
10334 		    ICH_FLASH_HSFSTS);
10335 
10336 	/* May be check the Flash Des Valid bit in Hw status */
10337 	if (hsfsts.hsf_status.fldesvalid == 0) {
10338 		DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be"
10339 		    " used.");
10340 		return error;
10341 	}
10342 	/* Clear FCERR in Hw status by writing 1 */
10343 	/* Clear DAEL in Hw status by writing a 1 */
10344 	hsfsts.hsf_status.flcerr = 1;
10345 	hsfsts.hsf_status.dael = 1;
10346 	if (hw->mac_type >= em_pch_spt)
10347 		E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS,
10348 		    hsfsts.regval & 0xFFFFUL);
10349 	else
10350 		E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
10351 		    hsfsts.regval);
10352 	/*
10353 	 * Either we should have a hardware SPI cycle in progress bit to
10354 	 * check against, in order to start a new cycle or FDONE bit should
10355 	 * be changed in the hardware so that it is 1 after hardware reset,
10356 	 * which can then be used as an indication whether a cycle is in
10357 	 * progress or has been completed .. we should also have some
10358 	 * software semaphore mechanism to guard FDONE or the cycle in
10359 	 * progress bit so that two threads access to those bits can be
10360 	 * sequentiallized or a way so that 2 threads dont start the cycle at
10361 	 * the same time
10362 	 */
10363 
10364 	if (hsfsts.hsf_status.flcinprog == 0) {
10365 		/*
10366 		 * There is no cycle running at present, so we can start a
10367 		 * cycle
10368 		 */
10369 		/* Begin by setting Flash Cycle Done. */
10370 		hsfsts.hsf_status.flcdone = 1;
10371 		if (hw->mac_type >= em_pch_spt)
10372 			E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS,
10373 			    hsfsts.regval & 0xFFFFUL);
10374 		else
10375 			E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
10376 			    hsfsts.regval);
10377 		error = E1000_SUCCESS;
10378 	} else {
10379 		/*
10380 		 * otherwise poll for sometime so the current cycle has a
10381 		 * chance to end before giving up.
10382 		 */
10383 		for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
10384 			if (hw->mac_type >= em_pch_spt)
10385 				hsfsts.regval = E1000_READ_ICH_FLASH_REG32(
10386 				    hw, ICH_FLASH_HSFSTS) & 0xFFFFUL;
10387 			else
10388 				hsfsts.regval = E1000_READ_ICH_FLASH_REG16(
10389 				    hw, ICH_FLASH_HSFSTS);
10390 			if (hsfsts.hsf_status.flcinprog == 0) {
10391 				error = E1000_SUCCESS;
10392 				break;
10393 			}
10394 			usec_delay(1);
10395 		}
10396 		if (error == E1000_SUCCESS) {
10397 			/*
10398 			 * Successful in waiting for previous cycle to
10399 			 * timeout, now set the Flash Cycle Done.
10400 			 */
10401 			hsfsts.hsf_status.flcdone = 1;
10402 			if (hw->mac_type >= em_pch_spt)
10403 				E1000_WRITE_ICH_FLASH_REG32(hw,
10404 				    ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFFUL);
10405 			else
10406 				E1000_WRITE_ICH_FLASH_REG16(hw,
10407 				    ICH_FLASH_HSFSTS, hsfsts.regval);
10408 		} else {
10409 			DEBUGOUT("Flash controller busy, cannot get access");
10410 		}
10411 	}
10412 	return error;
10413 }
10414 
10415 /******************************************************************************
10416  * This function starts a flash cycle and waits for its completion
10417  *
10418  * hw - The pointer to the hw structure
10419  *****************************************************************************/
10420 STATIC int32_t
em_ich8_flash_cycle(struct em_hw * hw,uint32_t timeout)10421 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout)
10422 {
10423 	union ich8_hws_flash_ctrl hsflctl;
10424 	union ich8_hws_flash_status hsfsts;
10425 	int32_t  error = E1000_ERR_EEPROM;
10426 	uint32_t i = 0;
10427 
10428 	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
10429 	if (hw->mac_type >= em_pch_spt)
10430 		hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw,
10431 		    ICH_FLASH_HSFSTS) >> 16;
10432 	else
10433 		hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw,
10434 		    ICH_FLASH_HSFCTL);
10435 	hsflctl.hsf_ctrl.flcgo = 1;
10436 
10437 	if (hw->mac_type >= em_pch_spt)
10438 		E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS,
10439 		    (uint32_t)hsflctl.regval << 16);
10440 	else
10441 		E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
10442 		    hsflctl.regval);
10443 
10444 	/* wait till FDONE bit is set to 1 */
10445 	do {
10446 		if (hw->mac_type >= em_pch_spt)
10447 			hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw,
10448 			    ICH_FLASH_HSFSTS) & 0xFFFFUL;
10449 		else
10450 			hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,
10451 			    ICH_FLASH_HSFSTS);
10452 		if (hsfsts.hsf_status.flcdone == 1)
10453 			break;
10454 		usec_delay(1);
10455 		i++;
10456 	} while (i < timeout);
10457 	if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
10458 		error = E1000_SUCCESS;
10459 	}
10460 	return error;
10461 }
10462 
10463 /******************************************************************************
10464  * Reads a byte or word from the NVM using the ICH8 flash access registers.
10465  *
10466  * hw - The pointer to the hw structure
10467  * index - The index of the byte or word to read.
10468  * size - Size of data to read, 1=byte 2=word
10469  * data - Pointer to the word to store the value read.
10470  *****************************************************************************/
10471 STATIC int32_t
em_read_ich8_data(struct em_hw * hw,uint32_t index,uint32_t size,uint16_t * data)10472 em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size,
10473     uint16_t *data)
10474 {
10475 	union ich8_hws_flash_status hsfsts;
10476 	union ich8_hws_flash_ctrl hsflctl;
10477 	uint32_t flash_linear_address;
10478 	uint32_t flash_data = 0;
10479 	int32_t  error = -E1000_ERR_EEPROM;
10480 	int32_t  count = 0;
10481 	DEBUGFUNC("em_read_ich8_data");
10482 
10483 	if (size < 1 || size > 2 || data == 0x0 ||
10484 	    index > ICH_FLASH_LINEAR_ADDR_MASK)
10485 		return error;
10486 
10487 	flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
10488 	    hw->flash_base_addr;
10489 
10490 	do {
10491 		usec_delay(1);
10492 		/* Steps */
10493 		error = em_ich8_cycle_init(hw);
10494 		if (error != E1000_SUCCESS)
10495 			break;
10496 
10497 		hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw,
10498 		    ICH_FLASH_HSFCTL);
10499 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
10500 		hsflctl.hsf_ctrl.fldbcount = size - 1;
10501 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
10502 		E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
10503 		    hsflctl.regval);
10504 		/*
10505 		 * Write the last 24 bits of index into Flash Linear address
10506 		 * field in Flash Address
10507 		 */
10508 		/* TODO: TBD maybe check the index against the size of flash */
10509 
10510 		E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR,
10511 		    flash_linear_address);
10512 
10513 		error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
10514 		/*
10515 		 * Check if FCERR is set to 1, if set to 1, clear it and try
10516 		 * the whole sequence a few more times, else read in (shift
10517 		 * in) the Flash Data0, the order is least significant byte
10518 		 * first msb to lsb
10519 		 */
10520 		if (error == E1000_SUCCESS) {
10521 			flash_data = E1000_READ_ICH_FLASH_REG(hw,
10522 			    ICH_FLASH_FDATA0);
10523 			if (size == 1) {
10524 				*data = (uint8_t) (flash_data & 0x000000FF);
10525 			} else if (size == 2) {
10526 				*data = (uint16_t) (flash_data & 0x0000FFFF);
10527 			}
10528 			break;
10529 		} else {
10530 			/*
10531 			 * If we've gotten here, then things are probably
10532 			 * completely hosed, but if the error condition is
10533 			 * detected, it won't hurt to give it another
10534 			 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
10535 			 */
10536 			hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,
10537 			    ICH_FLASH_HSFSTS);
10538 			if (hsfsts.hsf_status.flcerr == 1) {
10539 				/* Repeat for some time before giving up. */
10540 				continue;
10541 			} else if (hsfsts.hsf_status.flcdone == 0) {
10542 				DEBUGOUT("Timeout error - flash cycle did not"
10543 				    " complete.");
10544 				break;
10545 			}
10546 		}
10547 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
10548 
10549 	return error;
10550 }
10551 
10552 STATIC int32_t
em_read_ich8_data32(struct em_hw * hw,uint32_t offset,uint32_t * data)10553 em_read_ich8_data32(struct em_hw *hw, uint32_t offset, uint32_t *data)
10554 {
10555 	union ich8_hws_flash_status hsfsts;
10556 	union ich8_hws_flash_ctrl hsflctl;
10557 	uint32_t flash_linear_address;
10558 	int32_t  error = -E1000_ERR_EEPROM;
10559 	uint32_t  count = 0;
10560 	DEBUGFUNC("em_read_ich8_data32");
10561 
10562 	if (hw->mac_type < em_pch_spt)
10563 		return error;
10564 	if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
10565 		return error;
10566 	flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
10567 	    hw->flash_base_addr;
10568 
10569 	do {
10570 		usec_delay(1);
10571 		/* Steps */
10572 		error = em_ich8_cycle_init(hw);
10573 		if (error != E1000_SUCCESS)
10574 			break;
10575 
10576 		/* 32 bit accesses in SPT. */
10577 		hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw,
10578 		    ICH_FLASH_HSFSTS) >> 16;
10579 
10580 		hsflctl.hsf_ctrl.fldbcount = sizeof(uint32_t) - 1;
10581 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
10582 
10583 		E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS,
10584 		    (uint32_t)hsflctl.regval << 16);
10585 		/*
10586 		 * Write the last 24 bits of offset into Flash Linear address
10587 		 * field in Flash Address
10588 		 */
10589 		/* TODO: TBD maybe check the offset against the size of flash */
10590 
10591 		E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR,
10592 		    flash_linear_address);
10593 
10594 		error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
10595 		/*
10596 		 * Check if FCERR is set to 1, if set to 1, clear it and try
10597 		 * the whole sequence a few more times, else read in (shift
10598 		 * in) the Flash Data0, the order is least significant byte
10599 		 * first msb to lsb
10600 		 */
10601 		if (error == E1000_SUCCESS) {
10602 			(*data) = (uint32_t)E1000_READ_ICH_FLASH_REG32(hw,
10603 			    ICH_FLASH_FDATA0);
10604 			break;
10605 		} else {
10606 			/*
10607 			 * If we've gotten here, then things are probably
10608 			 * completely hosed, but if the error condition is
10609 			 * detected, it won't hurt to give it another
10610 			 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
10611 			 */
10612 			hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,
10613 			    ICH_FLASH_HSFSTS);
10614 			if (hsfsts.hsf_status.flcerr == 1) {
10615 				/* Repeat for some time before giving up. */
10616 				continue;
10617 			} else if (hsfsts.hsf_status.flcdone == 0) {
10618 				DEBUGOUT("Timeout error - flash cycle did not"
10619 				    " complete.");
10620 				break;
10621 			}
10622 		}
10623 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
10624 
10625 	return error;
10626 }
10627 
10628 
10629 /******************************************************************************
10630  * Writes One /two bytes to the NVM using the ICH8 flash access registers.
10631  *
10632  * hw - The pointer to the hw structure
10633  * index - The index of the byte/word to write.
10634  * size - Size of data to read, 1=byte 2=word
10635  * data - The byte(s) to write to the NVM.
10636  *****************************************************************************/
10637 STATIC int32_t
em_write_ich8_data(struct em_hw * hw,uint32_t index,uint32_t size,uint16_t data)10638 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size,
10639     uint16_t data)
10640 {
10641 	union ich8_hws_flash_status hsfsts;
10642 	union ich8_hws_flash_ctrl hsflctl;
10643 	uint32_t flash_linear_address;
10644 	uint32_t flash_data = 0;
10645 	int32_t  error = -E1000_ERR_EEPROM;
10646 	int32_t  count = 0;
10647 	DEBUGFUNC("em_write_ich8_data");
10648 
10649 	if (hw->mac_type >= em_pch_spt)
10650 		return -E1000_ERR_EEPROM;
10651 	if (size < 1 || size > 2 || data > size * 0xff ||
10652 	    index > ICH_FLASH_LINEAR_ADDR_MASK)
10653 		return error;
10654 
10655 	flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
10656 	    hw->flash_base_addr;
10657 
10658 	do {
10659 		usec_delay(1);
10660 		/* Steps */
10661 		error = em_ich8_cycle_init(hw);
10662 		if (error != E1000_SUCCESS)
10663 			break;
10664 
10665 		hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw,
10666 		    ICH_FLASH_HSFCTL);
10667 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
10668 		hsflctl.hsf_ctrl.fldbcount = size - 1;
10669 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
10670 		E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
10671 		    hsflctl.regval);
10672 		/*
10673 		 * Write the last 24 bits of index into Flash Linear address
10674 		 * field in Flash Address
10675 		 */
10676 		E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR,
10677 		    flash_linear_address);
10678 
10679 		if (size == 1)
10680 			flash_data = (uint32_t) data & 0x00FF;
10681 		else
10682 			flash_data = (uint32_t) data;
10683 
10684 		E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FDATA0, flash_data);
10685 		/*
10686 		 * check if FCERR is set to 1 , if set to 1, clear it and try
10687 		 * the whole sequence a few more times else done
10688 		 */
10689 		error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
10690 		if (error == E1000_SUCCESS) {
10691 			break;
10692 		} else {
10693 			/*
10694 			 * If we're here, then things are most likely
10695 			 * completely hosed, but if the error condition is
10696 			 * detected, it won't hurt to give it another
10697 			 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
10698 			 */
10699 			hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,
10700 			    ICH_FLASH_HSFSTS);
10701 			if (hsfsts.hsf_status.flcerr == 1) {
10702 				/* Repeat for some time before giving up. */
10703 				continue;
10704 			} else if (hsfsts.hsf_status.flcdone == 0) {
10705 				DEBUGOUT("Timeout error - flash cycle did not"
10706 				    " complete.");
10707 				break;
10708 			}
10709 		}
10710 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
10711 
10712 	return error;
10713 }
10714 
10715 /******************************************************************************
10716  * Reads a single byte from the NVM using the ICH8 flash access registers.
10717  *
10718  * hw - pointer to em_hw structure
10719  * index - The index of the byte to read.
10720  * data - Pointer to a byte to store the value read.
10721  *****************************************************************************/
10722 STATIC int32_t
em_read_ich8_byte(struct em_hw * hw,uint32_t index,uint8_t * data)10723 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data)
10724 {
10725 	int32_t  status = E1000_SUCCESS;
10726 	uint16_t word = 0;
10727 
10728 	if (hw->mac_type >= em_pch_spt)
10729 		return -E1000_ERR_EEPROM;
10730 	else
10731 		status = em_read_ich8_data(hw, index, 1, &word);
10732 	if (status == E1000_SUCCESS) {
10733 		*data = (uint8_t) word;
10734 	}
10735 	return status;
10736 }
10737 
10738 /******************************************************************************
10739  * Writes a single byte to the NVM using the ICH8 flash access registers.
10740  * Performs verification by reading back the value and then going through
10741  * a retry algorithm before giving up.
10742  *
10743  * hw - pointer to em_hw structure
10744  * index - The index of the byte to write.
10745  * byte - The byte to write to the NVM.
10746  *****************************************************************************/
10747 STATIC int32_t
em_verify_write_ich8_byte(struct em_hw * hw,uint32_t index,uint8_t byte)10748 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte)
10749 {
10750 	int32_t error = E1000_SUCCESS;
10751 	int32_t program_retries = 0;
10752 	DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
10753 
10754 	error = em_write_ich8_byte(hw, index, byte);
10755 
10756 	if (error != E1000_SUCCESS) {
10757 		for (program_retries = 0; program_retries < 100;
10758 		    program_retries++) {
10759 			DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n",
10760 			    byte, index);
10761 			error = em_write_ich8_byte(hw, index, byte);
10762 			usec_delay(100);
10763 			if (error == E1000_SUCCESS)
10764 				break;
10765 		}
10766 	}
10767 	if (program_retries == 100)
10768 		error = E1000_ERR_EEPROM;
10769 
10770 	return error;
10771 }
10772 
10773 /******************************************************************************
10774  * Writes a single byte to the NVM using the ICH8 flash access registers.
10775  *
10776  * hw - pointer to em_hw structure
10777  * index - The index of the byte to read.
10778  * data - The byte to write to the NVM.
10779  *****************************************************************************/
10780 STATIC int32_t
em_write_ich8_byte(struct em_hw * hw,uint32_t index,uint8_t data)10781 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data)
10782 {
10783 	int32_t  status = E1000_SUCCESS;
10784 	uint16_t word = (uint16_t) data;
10785 	status = em_write_ich8_data(hw, index, 1, word);
10786 
10787 	return status;
10788 }
10789 
10790 /******************************************************************************
10791  * Reads a dword from the NVM using the ICH8 flash access registers.
10792  *
10793  * hw - pointer to em_hw structure
10794  * index - The starting BYTE index of the word to read.
10795  * data - Pointer to a word to store the value read.
10796  *****************************************************************************/
10797 STATIC int32_t
em_read_ich8_dword(struct em_hw * hw,uint32_t index,uint32_t * data)10798 em_read_ich8_dword(struct em_hw *hw, uint32_t index, uint32_t *data)
10799 {
10800 	int32_t status = E1000_SUCCESS;
10801 	status = em_read_ich8_data32(hw, index, data);
10802 	return status;
10803 }
10804 
10805 /******************************************************************************
10806  * Reads a word from the NVM using the ICH8 flash access registers.
10807  *
10808  * hw - pointer to em_hw structure
10809  * index - The starting byte index of the word to read.
10810  * data - Pointer to a word to store the value read.
10811  *****************************************************************************/
10812 STATIC int32_t
em_read_ich8_word(struct em_hw * hw,uint32_t index,uint16_t * data)10813 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data)
10814 {
10815 	int32_t status = E1000_SUCCESS;
10816 	status = em_read_ich8_data(hw, index, 2, data);
10817 	return status;
10818 }
10819 
10820 /******************************************************************************
10821  * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
10822  * based.
10823  *
10824  * hw - pointer to em_hw structure
10825  * bank - 0 for first bank, 1 for second bank
10826  *
10827  * Note that this function may actually erase as much as 8 or 64 KBytes.  The
10828  * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
10829  * bank size may be 4, 8 or 64 KBytes
10830  *****************************************************************************/
10831 int32_t
em_erase_ich8_4k_segment(struct em_hw * hw,uint32_t bank)10832 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank)
10833 {
10834 	union ich8_hws_flash_status hsfsts;
10835 	union ich8_hws_flash_ctrl hsflctl;
10836 	uint32_t flash_linear_address;
10837 	int32_t  count = 0;
10838 	int32_t  error = E1000_ERR_EEPROM;
10839 	int32_t  iteration;
10840 	int32_t  sub_sector_size = 0;
10841 	int32_t  bank_size;
10842 	int32_t  j = 0;
10843 	int32_t  error_flag = 0;
10844 	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
10845 	/*
10846 	 * Determine HW Sector size: Read BERASE bits of Hw flash Status
10847 	 * register
10848 	 */
10849 	/*
10850 	 * 00: The Hw sector is 256 bytes, hence we need to erase 16
10851 	 * consecutive sectors.  The start index for the nth Hw sector can be
10852 	 * calculated as bank * 4096 + n * 256 01: The Hw sector is 4K bytes,
10853 	 * hence we need to erase 1 sector. The start index for the nth Hw
10854 	 * sector can be calculated as bank * 4096 10: The HW sector is 8K
10855 	 * bytes 11: The Hw sector size is 64K bytes
10856 	 */
10857 	if (hsfsts.hsf_status.berasesz == 0x0) {
10858 		/* Hw sector size 256 */
10859 		sub_sector_size = ICH_FLASH_SEG_SIZE_256;
10860 		bank_size = ICH_FLASH_SECTOR_SIZE;
10861 		iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
10862 	} else if (hsfsts.hsf_status.berasesz == 0x1) {
10863 		bank_size = ICH_FLASH_SEG_SIZE_4K;
10864 		iteration = 1;
10865 	} else if (hsfsts.hsf_status.berasesz == 0x2) {
10866 		if (hw->mac_type == em_ich9lan) {
10867 			uint32_t gfpreg, sector_base_addr, sector_end_addr;
10868 			gfpreg = E1000_READ_ICH_FLASH_REG(hw,
10869 			    ICH_FLASH_GFPREG);
10870 			/*
10871 		         * sector_X_addr is a "sector"-aligned address (4096 bytes)
10872 		         * Add 1 to sector_end_addr since this sector is included in
10873 		         * the overall size.
10874 		         */
10875 			sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK;
10876 			sector_end_addr =
10877 			    ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1;
10878 
10879 			/*
10880 		         * find total size of the NVM, then cut in half since the total
10881 		         * size represents two separate NVM banks.
10882 		         */
10883 			bank_size = (sector_end_addr - sector_base_addr)
10884 			    << ICH_FLASH_SECT_ADDR_SHIFT;
10885 			bank_size /= 2;
10886 			/* Word align */
10887 			bank_size =
10888 			    (bank_size / sizeof(uint16_t)) * sizeof(uint16_t);
10889 
10890 			sub_sector_size = ICH_FLASH_SEG_SIZE_8K;
10891 			iteration = bank_size / ICH_FLASH_SEG_SIZE_8K;
10892 		} else {
10893 			return error;
10894 		}
10895 	} else if (hsfsts.hsf_status.berasesz == 0x3) {
10896 		bank_size = ICH_FLASH_SEG_SIZE_64K;
10897 		iteration = 1;
10898 	} else {
10899 		return error;
10900 	}
10901 
10902 	for (j = 0; j < iteration; j++) {
10903 		do {
10904 			count++;
10905 			/* Steps */
10906 			error = em_ich8_cycle_init(hw);
10907 			if (error != E1000_SUCCESS) {
10908 				error_flag = 1;
10909 				break;
10910 			}
10911 			/*
10912 			 * Write a value 11 (block Erase) in Flash Cycle
10913 			 * field in Hw flash Control
10914 			 */
10915 			hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw,
10916 			    ICH_FLASH_HSFCTL);
10917 			hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
10918 			E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
10919 			    hsflctl.regval);
10920 			/*
10921 			 * Write the last 24 bits of an index within the
10922 			 * block into Flash Linear address field in Flash
10923 			 * Address.  This probably needs to be calculated
10924 			 * here based off the on-chip erase sector size and
10925 			 * the software bank size (4, 8 or 64 KBytes)
10926 			 */
10927 			flash_linear_address =
10928 			    bank * bank_size + j * sub_sector_size;
10929 			flash_linear_address += hw->flash_base_addr;
10930 			flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
10931 
10932 			E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR,
10933 			    flash_linear_address);
10934 
10935 			error =
10936 			    em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
10937 			/*
10938 			 * Check if FCERR is set to 1.  If 1, clear it and
10939 			 * try the whole sequence a few more times else Done
10940 			 */
10941 			if (error == E1000_SUCCESS) {
10942 				break;
10943 			} else {
10944 				hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,
10945 				    ICH_FLASH_HSFSTS);
10946 				if (hsfsts.hsf_status.flcerr == 1) {
10947 					/*
10948 					 * repeat for some time before giving
10949 					 * up
10950 					 */
10951 					continue;
10952 				} else if (hsfsts.hsf_status.flcdone == 0) {
10953 					error_flag = 1;
10954 					break;
10955 				}
10956 			}
10957 		} while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
10958 		if (error_flag == 1)
10959 			break;
10960 	}
10961 	if (error_flag != 1)
10962 		error = E1000_SUCCESS;
10963 	return error;
10964 }
10965 
10966 /******************************************************************************
10967  * Reads 16-bit words from the OTP. Return error when the word is not
10968  * stored in OTP.
10969  *
10970  * hw - Struct containing variables accessed by shared code
10971  * offset - offset of word in the OTP to read
10972  * data - word read from the OTP
10973  * words - number of words to read
10974  *****************************************************************************/
10975 STATIC int32_t
em_read_invm_i210(struct em_hw * hw,uint16_t offset,uint16_t words,uint16_t * data)10976 em_read_invm_i210(struct em_hw *hw, uint16_t offset, uint16_t words,
10977     uint16_t *data)
10978 {
10979 	int32_t  ret_val = E1000_SUCCESS;
10980 
10981 	switch (offset)
10982 	{
10983 	case EEPROM_MAC_ADDR_WORD0:
10984 	case EEPROM_MAC_ADDR_WORD1:
10985 	case EEPROM_MAC_ADDR_WORD2:
10986 		/* Generate random MAC address if there's none. */
10987 		ret_val = em_read_invm_word_i210(hw, offset, data);
10988 		if (ret_val != E1000_SUCCESS) {
10989 			DEBUGOUT("MAC Addr not found in iNVM\n");
10990 			*data = 0xFFFF;
10991 			ret_val = E1000_SUCCESS;
10992 		}
10993 		break;
10994 	case EEPROM_INIT_CONTROL2_REG:
10995 		ret_val = em_read_invm_word_i210(hw, offset, data);
10996 		if (ret_val != E1000_SUCCESS) {
10997 			*data = NVM_INIT_CTRL_2_DEFAULT_I211;
10998 			ret_val = E1000_SUCCESS;
10999 		}
11000 		break;
11001 	case EEPROM_INIT_CONTROL4_REG:
11002 		ret_val = em_read_invm_word_i210(hw, offset, data);
11003 		if (ret_val != E1000_SUCCESS) {
11004 			*data = NVM_INIT_CTRL_4_DEFAULT_I211;
11005 			ret_val = E1000_SUCCESS;
11006 		}
11007 		break;
11008 	case EEPROM_LED_1_CFG:
11009 		ret_val = em_read_invm_word_i210(hw, offset, data);
11010 		if (ret_val != E1000_SUCCESS) {
11011 			*data = NVM_LED_1_CFG_DEFAULT_I211;
11012 			ret_val = E1000_SUCCESS;
11013 		}
11014 		break;
11015 	case EEPROM_LED_0_2_CFG:
11016 		ret_val = em_read_invm_word_i210(hw, offset, data);
11017 		if (ret_val != E1000_SUCCESS) {
11018 			*data = NVM_LED_0_2_CFG_DEFAULT_I211;
11019 			ret_val = E1000_SUCCESS;
11020 		}
11021 		break;
11022 	case EEPROM_ID_LED_SETTINGS:
11023 		ret_val = em_read_invm_word_i210(hw, offset, data);
11024 		if (ret_val != E1000_SUCCESS) {
11025 			*data = ID_LED_RESERVED_FFFF;
11026 			ret_val = E1000_SUCCESS;
11027 		}
11028 		break;
11029 	default:
11030 		DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset);
11031 		*data = NVM_RESERVED_WORD;
11032 		break;
11033 	}
11034 
11035 	return ret_val;
11036 }
11037 
11038 /******************************************************************************
11039  * Reads 16-bit words from the OTP. Return error when the word is not
11040  * stored in OTP.
11041  *
11042  * hw - Struct containing variables accessed by shared code
11043  * offset - offset of word in the OTP to read
11044  * data - word read from the OTP
11045  *****************************************************************************/
11046 STATIC int32_t
em_read_invm_word_i210(struct em_hw * hw,uint16_t address,uint16_t * data)11047 em_read_invm_word_i210(struct em_hw *hw, uint16_t address, uint16_t *data)
11048 {
11049 	int32_t  error = -E1000_NOT_IMPLEMENTED;
11050 	uint32_t invm_dword;
11051 	uint16_t i;
11052 	uint8_t record_type, word_address;
11053 
11054 	for (i = 0; i < INVM_SIZE; i++) {
11055 		invm_dword = EM_READ_REG(hw, E1000_INVM_DATA_REG(i));
11056 		/* Get record type */
11057 		record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
11058 		if (record_type == INVM_UNINITIALIZED_STRUCTURE)
11059 			break;
11060 		if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE)
11061 			i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
11062 		if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE)
11063 			i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
11064 		if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) {
11065 			word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
11066 			if (word_address == address) {
11067 				*data = INVM_DWORD_TO_WORD_DATA(invm_dword);
11068 				error = E1000_SUCCESS;
11069 				break;
11070 			}
11071 		}
11072 	}
11073 
11074 	return error;
11075 }
11076 
11077 STATIC int32_t
em_init_lcd_from_nvm_config_region(struct em_hw * hw,uint32_t cnf_base_addr,uint32_t cnf_size)11078 em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr,
11079     uint32_t cnf_size)
11080 {
11081 	uint32_t ret_val = E1000_SUCCESS;
11082 	uint16_t word_addr, reg_data, reg_addr;
11083 	uint16_t i;
11084 	/* cnf_base_addr is in DWORD */
11085 	word_addr = (uint16_t) (cnf_base_addr << 1);
11086 
11087 	/* cnf_size is returned in size of dwords */
11088 	for (i = 0; i < cnf_size; i++) {
11089 		ret_val =
11090 		    em_read_eeprom(hw, (word_addr + i * 2), 1, &reg_data);
11091 		if (ret_val)
11092 			return ret_val;
11093 
11094 		ret_val =
11095 		    em_read_eeprom(hw, (word_addr + i * 2 + 1), 1, &reg_addr);
11096 		if (ret_val)
11097 			return ret_val;
11098 
11099 		ret_val = em_get_software_flag(hw);
11100 		if (ret_val != E1000_SUCCESS)
11101 			return ret_val;
11102 
11103 		ret_val =
11104 		    em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data);
11105 
11106 		em_release_software_flag(hw);
11107 	}
11108 
11109 	return ret_val;
11110 }
11111 
11112 /******************************************************************************
11113  * This function initializes the PHY from the NVM on ICH8 platforms. This
11114  * is needed due to an issue where the NVM configuration is not properly
11115  * autoloaded after power transitions. Therefore, after each PHY reset, we
11116  * will load the configuration data out of the NVM manually.
11117  *
11118  * hw: Struct containing variables accessed by shared code
11119  *****************************************************************************/
11120 STATIC int32_t
em_init_lcd_from_nvm(struct em_hw * hw)11121 em_init_lcd_from_nvm(struct em_hw *hw)
11122 {
11123 	uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask;
11124 	if (hw->phy_type != em_phy_igp_3)
11125 		return E1000_SUCCESS;
11126 
11127 	/* Check if SW needs configure the PHY */
11128 	if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT ||
11129 	    hw->device_id == E1000_DEV_ID_ICH8_IGP_M ||
11130 	    hw->mac_type == em_pchlan ||
11131 	    hw->mac_type == em_pch2lan ||
11132 	    hw->mac_type == em_pch_lpt ||
11133 	    hw->mac_type == em_pch_spt ||
11134 	    hw->mac_type == em_pch_cnp ||
11135 	    hw->mac_type == em_pch_tgp ||
11136 	    hw->mac_type == em_pch_adp)
11137 		sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M;
11138 	else
11139 		sw_cfg_mask = FEXTNVM_SW_CONFIG;
11140 
11141 	reg_data = E1000_READ_REG(hw, FEXTNVM);
11142 	if (!(reg_data & sw_cfg_mask))
11143 		return E1000_SUCCESS;
11144 
11145 	/* Wait for basic configuration completes before proceeding */
11146 	loop = 0;
11147 	do {
11148 		reg_data =
11149 		    E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
11150 		usec_delay(100);
11151 		loop++;
11152 	} while ((!reg_data) && (loop < 50));
11153 
11154 	/* Clear the Init Done bit for the next init event */
11155 	reg_data = E1000_READ_REG(hw, STATUS);
11156 	reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
11157 	E1000_WRITE_REG(hw, STATUS, reg_data);
11158 	/*
11159 	 * Make sure HW does not configure LCD from PHY extended
11160 	 * configuration before SW configuration
11161 	 */
11162 	reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
11163 	if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
11164 		reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
11165 		cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
11166 		cnf_size >>= 16;
11167 		if (cnf_size) {
11168 			reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
11169 			cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
11170 			/* cnf_base_addr is in DWORD */
11171 			cnf_base_addr >>= 16;
11172 
11173 			/* Configure LCD from extended configuration region. */
11174 			ret_val = em_init_lcd_from_nvm_config_region(hw,
11175 			    cnf_base_addr, cnf_size);
11176 			if (ret_val)
11177 				return ret_val;
11178 		}
11179 	}
11180 	return E1000_SUCCESS;
11181 }
11182 
11183 /******************************************************************************
11184  *  em_set_pciex_completion_timeout - set pci-e completion timeout
11185  *
11186  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
11187  *  however the hardware default for these parts is 500us to 1ms which is less
11188  *  than the 10ms recommended by the pci-e spec.  To address this we need to
11189  *  increase the value to either 10ms to 200ms for capability version 1 config,
11190  *  or 16ms to 55ms for version 2.
11191  *
11192  *  * hw - pointer to em_hw structure
11193  *****************************************************************************/
11194 int32_t
em_set_pciex_completion_timeout(struct em_hw * hw)11195 em_set_pciex_completion_timeout(struct em_hw *hw)
11196 {
11197 	uint32_t gcr = E1000_READ_REG(hw, GCR);
11198 	int32_t ret_val = E1000_SUCCESS;
11199 
11200 	/* Only take action if timeout value is not set by system BIOS */
11201 	if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
11202 		goto out;
11203 
11204 	DEBUGOUT("PCIe completion timeout not set by system BIOS.");
11205 
11206 	/*
11207 	 * If capabilities version is type 1 we can write the
11208 	 * timeout of 10ms to 200ms through the GCR register
11209 	 */
11210 
11211 	if (!(gcr & E1000_GCR_CAP_VER2)) {
11212 		gcr |= E1000_GCR_CMPL_TMOUT_10ms;
11213 		DEBUGOUT("PCIe capability version 1 detected, setting \
11214 		    completion timeout to 10ms.");
11215 		goto out;
11216 	}
11217 
11218 	/*
11219 	 * For version 2 capabilities we need to write the config space
11220 	 * directly in order to set the completion timeout value for
11221 	 * 16ms to 55ms
11222 	 *
11223 	 * XXX: Implement em_*_pcie_cap_reg() first.
11224 	 */
11225 #if 0
11226 	ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
11227 	    &pciex_devctl2);
11228 
11229 	if (ret_val)
11230 		goto out;
11231 
11232 	pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
11233 
11234 	ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
11235 	    &pciex_devctl2);
11236 #endif
11237 
11238 out:
11239 
11240 	/* Disable completion timeout resend */
11241 	gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
11242 
11243 	DEBUGOUT("PCIe completion timeout resend disabled.");
11244 
11245 	E1000_WRITE_REG(hw, GCR, gcr);
11246 	return ret_val;
11247 }
11248 
11249 /***************************************************************************
11250  *  Set slow MDIO access mode
11251  ***************************************************************************/
11252 static int32_t
em_set_mdio_slow_mode_hv(struct em_hw * hw)11253 em_set_mdio_slow_mode_hv(struct em_hw *hw)
11254 {
11255 	int32_t ret_val;
11256 	uint16_t data;
11257 	DEBUGFUNC("em_set_mdio_slow_mode_hv");
11258 
11259 	ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL, &data);
11260 	if (ret_val)
11261 		return ret_val;
11262 
11263 	data |= HV_KMRN_MDIO_SLOW;
11264 
11265 	ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL, data);
11266 
11267 	return ret_val;
11268 }
11269 
11270 /***************************************************************************
11271  *  A series of Phy workarounds to be done after every PHY reset.
11272  ***************************************************************************/
11273 int32_t
em_hv_phy_workarounds_ich8lan(struct em_hw * hw)11274 em_hv_phy_workarounds_ich8lan(struct em_hw *hw)
11275 {
11276 	int32_t ret_val = E1000_SUCCESS;
11277 	uint16_t phy_data;
11278 	uint16_t swfw;
11279 	DEBUGFUNC("em_hv_phy_workarounds_ich8lan");
11280 
11281 	if (hw->mac_type != em_pchlan)
11282 		goto out;
11283 
11284 	swfw = E1000_SWFW_PHY0_SM;
11285 
11286 	/* Set MDIO slow mode before any other MDIO access */
11287 	if (hw->phy_type == em_phy_82577 ||
11288 	    hw->phy_type == em_phy_82578) {
11289 		ret_val = em_set_mdio_slow_mode_hv(hw);
11290 		if (ret_val)
11291 			goto out;
11292 	}
11293 
11294 	/* Hanksville M Phy init for IEEE. */
11295 	if ((hw->revision_id == 2) &&
11296 	    (hw->phy_type == em_phy_82577) &&
11297 	    ((hw->phy_revision == 2) || (hw->phy_revision == 3))) {
11298 		em_write_phy_reg(hw, 0x10, 0x8823);
11299 		em_write_phy_reg(hw, 0x11, 0x0018);
11300 		em_write_phy_reg(hw, 0x10, 0x8824);
11301 		em_write_phy_reg(hw, 0x11, 0x0016);
11302 		em_write_phy_reg(hw, 0x10, 0x8825);
11303 		em_write_phy_reg(hw, 0x11, 0x001A);
11304 		em_write_phy_reg(hw, 0x10, 0x888C);
11305 		em_write_phy_reg(hw, 0x11, 0x0007);
11306 		em_write_phy_reg(hw, 0x10, 0x888D);
11307 		em_write_phy_reg(hw, 0x11, 0x0007);
11308 		em_write_phy_reg(hw, 0x10, 0x888E);
11309 		em_write_phy_reg(hw, 0x11, 0x0007);
11310 		em_write_phy_reg(hw, 0x10, 0x8827);
11311 		em_write_phy_reg(hw, 0x11, 0x0001);
11312 		em_write_phy_reg(hw, 0x10, 0x8835);
11313 		em_write_phy_reg(hw, 0x11, 0x0001);
11314 		em_write_phy_reg(hw, 0x10, 0x8834);
11315 		em_write_phy_reg(hw, 0x11, 0x0001);
11316 		em_write_phy_reg(hw, 0x10, 0x8833);
11317 		em_write_phy_reg(hw, 0x11, 0x0002);
11318 	}
11319 
11320 	if (((hw->phy_type == em_phy_82577) &&
11321 	     ((hw->phy_revision == 1) || (hw->phy_revision == 2))) ||
11322 	    ((hw->phy_type == em_phy_82578) && (hw->phy_revision == 1))) {
11323 		/* Disable generation of early preamble */
11324 		ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431);
11325 		if (ret_val)
11326 			goto out;
11327 
11328 		/* Preamble tuning for SSC */
11329 		ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204);
11330 		if (ret_val)
11331 			goto out;
11332 	}
11333 
11334 	if (hw->phy_type == em_phy_82578) {
11335 		/*
11336 		 * Return registers to default by doing a soft reset then
11337 		 * writing 0x3140 to the control register.
11338 		 */
11339 		if (hw->phy_revision < 2) {
11340 			em_phy_reset(hw);
11341 			ret_val = em_write_phy_reg(hw, PHY_CTRL, 0x3140);
11342 		}
11343 	}
11344 
11345 	if ((hw->revision_id == 2) &&
11346 	    (hw->phy_type == em_phy_82577) &&
11347 	    ((hw->phy_revision == 2) || (hw->phy_revision == 3))) {
11348 		/*
11349 		 * Workaround for OEM (GbE) not operating after reset -
11350 		 * restart AN (twice)
11351 		 */
11352 		ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400);
11353 		if (ret_val)
11354 			goto out;
11355 		ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400);
11356 		if (ret_val)
11357 			goto out;
11358 	}
11359 
11360 	/* Select page 0 */
11361 	ret_val = em_swfw_sync_acquire(hw, swfw);
11362 	if (ret_val)
11363 		goto out;
11364 
11365 	hw->phy_addr = 1;
11366 	ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
11367 	em_swfw_sync_release(hw, swfw);
11368 	if (ret_val)
11369 		goto out;
11370 
11371 	/* Workaround for link disconnects on a busy hub in half duplex */
11372 	ret_val = em_read_phy_reg(hw,
11373 	                                      PHY_REG(BM_PORT_CTRL_PAGE, 17),
11374 	                                      &phy_data);
11375 	if (ret_val)
11376 		goto release;
11377 	ret_val = em_write_phy_reg(hw,
11378 	                                       PHY_REG(BM_PORT_CTRL_PAGE, 17),
11379 	                                       phy_data & 0x00FF);
11380 release:
11381 out:
11382 	return ret_val;
11383 }
11384 
11385 
11386 /***************************************************************************
11387  *  Si workaround
11388  *
11389  *  This function works around a Si bug where the link partner can get
11390  *  a link up indication before the PHY does.  If small packets are sent
11391  *  by the link partner they can be placed in the packet buffer without
11392  *  being properly accounted for by the PHY and will stall preventing
11393  *  further packets from being received.  The workaround is to clear the
11394  *  packet buffer after the PHY detects link up.
11395  ***************************************************************************/
11396 int32_t
em_link_stall_workaround_hv(struct em_hw * hw)11397 em_link_stall_workaround_hv(struct em_hw *hw)
11398 {
11399 	int32_t ret_val = E1000_SUCCESS;
11400 	uint16_t phy_data;
11401 
11402 	if (hw->phy_type != em_phy_82578)
11403 		goto out;
11404 
11405 	/* Do not apply workaround if in PHY loopback bit 14 set */
11406 	em_read_phy_reg(hw, PHY_CTRL, &phy_data);
11407 	if (phy_data & E1000_PHY_CTRL_LOOPBACK)
11408 		goto out;
11409 
11410 	/* check if link is up and at 1Gbps */
11411 	ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data);
11412 	if (ret_val)
11413 		goto out;
11414 
11415 	phy_data &= BM_CS_STATUS_LINK_UP |
11416 		    BM_CS_STATUS_RESOLVED |
11417 		    BM_CS_STATUS_SPEED_MASK;
11418 
11419 	if (phy_data != (BM_CS_STATUS_LINK_UP |
11420 			 BM_CS_STATUS_RESOLVED |
11421 			 BM_CS_STATUS_SPEED_1000))
11422 		goto out;
11423 
11424 	msec_delay(200);
11425 
11426 	/* flush the packets in the fifo buffer */
11427 	ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL,
11428 	    HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED);
11429 	if (ret_val)
11430 		goto out;
11431 
11432 	ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL,
11433 	    HV_MUX_DATA_CTRL_GEN_TO_MAC);
11434 
11435 out:
11436 	return ret_val;
11437 }
11438 
11439 /****************************************************************************
11440  *  K1 Si workaround
11441  *
11442  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
11443  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig.
11444  *  If link is down, the function will restore the default K1 setting located
11445  *  in the NVM.
11446  ****************************************************************************/
11447 int32_t
em_k1_gig_workaround_hv(struct em_hw * hw,boolean_t link)11448 em_k1_gig_workaround_hv(struct em_hw *hw, boolean_t link)
11449 {
11450 	int32_t ret_val;
11451 	uint16_t phy_data;
11452 	boolean_t k1_enable;
11453 
11454 	DEBUGFUNC("em_k1_gig_workaround_hv");
11455 
11456 	if (hw->mac_type != em_pchlan)
11457 		return E1000_SUCCESS;
11458 
11459 	ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data);
11460 	if (ret_val)
11461 		return ret_val;
11462 
11463 	k1_enable = phy_data & E1000_NVM_K1_ENABLE ? TRUE : FALSE;
11464 
11465 	/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
11466 	if (link) {
11467 		if (hw->phy_type == em_phy_82578) {
11468 			ret_val = em_read_phy_reg(hw, BM_CS_STATUS,
11469 			    &phy_data);
11470 			if (ret_val)
11471 				return ret_val;
11472 
11473 			phy_data &= BM_CS_STATUS_LINK_UP |
11474 				    BM_CS_STATUS_RESOLVED |
11475 				    BM_CS_STATUS_SPEED_MASK;
11476 
11477 			if (phy_data == (BM_CS_STATUS_LINK_UP |
11478 					 BM_CS_STATUS_RESOLVED |
11479 					 BM_CS_STATUS_SPEED_1000))
11480 				k1_enable = FALSE;
11481 		}
11482 
11483 		if (hw->phy_type == em_phy_82577) {
11484 			ret_val = em_read_phy_reg(hw, HV_M_STATUS,
11485 			    &phy_data);
11486 			if (ret_val)
11487 				return ret_val;
11488 
11489 			phy_data &= HV_M_STATUS_LINK_UP |
11490 				    HV_M_STATUS_AUTONEG_COMPLETE |
11491 				    HV_M_STATUS_SPEED_MASK;
11492 
11493 			if (phy_data == (HV_M_STATUS_LINK_UP |
11494 					 HV_M_STATUS_AUTONEG_COMPLETE |
11495 					 HV_M_STATUS_SPEED_1000))
11496 				k1_enable = FALSE;
11497 		}
11498 
11499 		/* Link stall fix for link up */
11500 		ret_val = em_write_phy_reg(hw, PHY_REG(770, 19),
11501 		    0x0100);
11502 		if (ret_val)
11503 			return ret_val;
11504 
11505 	} else {
11506 		/* Link stall fix for link down */
11507 		ret_val = em_write_phy_reg(hw, PHY_REG(770, 19),
11508 		    0x4100);
11509 		if (ret_val)
11510 			return ret_val;
11511 	}
11512 
11513 	ret_val = em_configure_k1_ich8lan(hw, k1_enable);
11514 
11515 	return ret_val;
11516 }
11517 
11518 /* Workaround to set the K1 beacon duration for 82579 parts */
11519 int32_t
em_k1_workaround_lv(struct em_hw * hw)11520 em_k1_workaround_lv(struct em_hw *hw)
11521 {
11522 	int32_t ret_val;
11523 	uint16_t phy_data;
11524 	uint32_t mac_reg;
11525 
11526 	ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data);
11527 	if (ret_val)
11528 		return ret_val;
11529 
11530 	if ((phy_data & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
11531 	    == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
11532 		mac_reg = E1000_READ_REG(hw, FEXTNVM4);
11533 		mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
11534 
11535 		if (phy_data & HV_M_STATUS_SPEED_1000)
11536 			mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
11537 		else
11538 			mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
11539 
11540 		E1000_WRITE_REG(hw, FEXTNVM4, mac_reg);
11541 	}
11542 
11543 	return E1000_SUCCESS;
11544 }
11545 
11546 /**
11547  *  em_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
11548  *
11549  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
11550  *  preventing further DMA write requests.  Workaround the issue by disabling
11551  *  the de-assertion of the clock request when in 1Gbps mode.
11552  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
11553  *  speeds in order to avoid Tx hangs.
11554  **/
11555 int32_t
em_k1_workaround_lpt_lp(struct em_hw * hw,boolean_t link)11556 em_k1_workaround_lpt_lp(struct em_hw *hw, boolean_t link)
11557 {
11558 	uint32_t fextnvm6 = E1000_READ_REG(hw, FEXTNVM6);
11559 	uint32_t status = E1000_READ_REG(hw, STATUS);
11560 	int32_t ret_val = E1000_SUCCESS;
11561 	uint16_t reg;
11562 
11563 	if (link && (status & E1000_STATUS_SPEED_1000)) {
11564 		ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11565 		    &reg);
11566 		if (ret_val)
11567 			return ret_val;
11568 
11569 		ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11570 		    reg & ~E1000_KMRNCTRLSTA_K1_ENABLE);
11571 		if (ret_val)
11572 			return ret_val;
11573 
11574 		usec_delay(10);
11575 
11576 		E1000_WRITE_REG(hw, FEXTNVM6,
11577 				fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
11578 
11579 		ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11580 		    reg);
11581 	} else {
11582 		/* clear FEXTNVM6 bit 8 on link down or 10/100 */
11583 		fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
11584 
11585 		if (!link || ((status & E1000_STATUS_SPEED_100) &&
11586 			      (status & E1000_STATUS_FD)))
11587 			goto update_fextnvm6;
11588 
11589 		ret_val = em_read_phy_reg(hw, I217_INBAND_CTRL, &reg);
11590 		if (ret_val)
11591 			return ret_val;
11592 
11593 		/* Clear link status transmit timeout */
11594 		reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
11595 
11596 		if (status & E1000_STATUS_SPEED_100) {
11597 			/* Set inband Tx timeout to 5x10us for 100Half */
11598 			reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
11599 
11600 			/* Do not extend the K1 entry latency for 100Half */
11601 			fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
11602 		} else {
11603 			/* Set inband Tx timeout to 50x10us for 10Full/Half */
11604 			reg |= 50 <<
11605 			       I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
11606 
11607 			/* Extend the K1 entry latency for 10 Mbps */
11608 			fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
11609 		}
11610 
11611 		ret_val = em_write_phy_reg(hw, I217_INBAND_CTRL, reg);
11612 		if (ret_val)
11613 			return ret_val;
11614 
11615 update_fextnvm6:
11616 		E1000_WRITE_REG(hw, FEXTNVM6, fextnvm6);
11617 	}
11618 
11619 	return ret_val;
11620 
11621 }
11622 
11623 
11624 /***************************************************************************
11625  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
11626  *  @hw:   pointer to the HW structure
11627  *  @gate: boolean set to TRUE to gate, FALSE to ungate
11628  *
11629  *  Gate/ungate the automatic PHY configuration via hardware; perform
11630  *  the configuration via software instead.
11631  ***************************************************************************/
11632 void
em_gate_hw_phy_config_ich8lan(struct em_hw * hw,boolean_t gate)11633 em_gate_hw_phy_config_ich8lan(struct em_hw *hw, boolean_t gate)
11634 {
11635        uint32_t extcnf_ctrl;
11636 
11637        DEBUGFUNC("em_gate_hw_phy_config_ich8lan");
11638 
11639        if (hw->mac_type != em_pch2lan)
11640                return;
11641 
11642        extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
11643 
11644        if (gate)
11645                extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
11646        else
11647                extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
11648 
11649        E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
11650 }
11651 
11652 /***************************************************************************
11653  *  Configure K1 power state
11654  *
11655  *  Configure the K1 power state based on the provided parameter.
11656  *  Assumes semaphore already acquired.
11657  *
11658  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
11659  ***************************************************************************/
11660 int32_t
em_configure_k1_ich8lan(struct em_hw * hw,boolean_t k1_enable)11661 em_configure_k1_ich8lan(struct em_hw *hw, boolean_t k1_enable)
11662 {
11663 	int32_t ret_val = E1000_SUCCESS;
11664 	uint32_t ctrl_reg = 0;
11665 	uint32_t ctrl_ext = 0;
11666 	uint32_t reg = 0;
11667 	uint16_t kmrn_reg = 0;
11668 
11669 	ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11670 	    &kmrn_reg);
11671 	if (ret_val)
11672 		goto out;
11673 
11674 	if (k1_enable)
11675 		kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
11676 	else
11677 		kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
11678 
11679 	ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11680 	    kmrn_reg);
11681 	if (ret_val)
11682 		goto out;
11683 
11684 	usec_delay(20);
11685 	ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
11686 	ctrl_reg = E1000_READ_REG(hw, CTRL);
11687 
11688 	reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
11689 	reg |= E1000_CTRL_FRCSPD;
11690 	E1000_WRITE_REG(hw, CTRL, reg);
11691 
11692 	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
11693 	usec_delay(20);
11694 	E1000_WRITE_REG(hw, CTRL, ctrl_reg);
11695 	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
11696 	usec_delay(20);
11697 
11698 out:
11699 	return ret_val;
11700 }
11701 
11702 /***************************************************************************
11703  *  em_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
11704  *  done after every PHY reset.
11705  ***************************************************************************/
11706 int32_t
em_lv_phy_workarounds_ich8lan(struct em_hw * hw)11707 em_lv_phy_workarounds_ich8lan(struct em_hw *hw)
11708 {
11709        int32_t ret_val = E1000_SUCCESS;
11710        uint16_t swfw;
11711 
11712        DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
11713 
11714        if (hw->mac_type != em_pch2lan)
11715                goto out;
11716 
11717        /* Set MDIO slow mode before any other MDIO access */
11718        ret_val = em_set_mdio_slow_mode_hv(hw);
11719 
11720        swfw = E1000_SWFW_PHY0_SM;
11721        ret_val = em_swfw_sync_acquire(hw, swfw);
11722        if (ret_val)
11723                goto out;
11724        ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR,
11725                                               I82579_MSE_THRESHOLD);
11726        if (ret_val)
11727                goto release;
11728        /* set MSE higher to enable link to stay up when noise is high */
11729        ret_val = em_write_phy_reg(hw, I82579_EMI_DATA,
11730                                               0x0034);
11731        if (ret_val)
11732                goto release;
11733        ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR,
11734                                               I82579_MSE_LINK_DOWN);
11735        if (ret_val)
11736                goto release;
11737        /* drop link after 5 times MSE threshold was reached */
11738        ret_val = em_write_phy_reg(hw, I82579_EMI_DATA,
11739                                               0x0005);
11740 release:
11741        em_swfw_sync_release(hw, swfw);
11742 
11743 out:
11744        return ret_val;
11745 }
11746 
11747 int32_t
em_set_eee_i350(struct em_hw * hw)11748 em_set_eee_i350(struct em_hw *hw)
11749 {
11750 	int32_t ret_val = E1000_SUCCESS;
11751 	uint32_t ipcnfg, eeer;
11752 
11753 	if ((hw->mac_type < em_i350) ||
11754 	    (hw->media_type != em_media_type_copper))
11755 		goto out;
11756 	ipcnfg = EM_READ_REG(hw, E1000_IPCNFG);
11757 	eeer = EM_READ_REG(hw, E1000_EEER);
11758 
11759 	if (hw->eee_enable) {
11760 		ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
11761 		eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
11762 		    E1000_EEER_LPI_FC);
11763 	} else {
11764 		ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
11765 		eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
11766 		    E1000_EEER_LPI_FC);
11767 	}
11768 	EM_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
11769 	EM_WRITE_REG(hw, E1000_EEER, eeer);
11770 	EM_READ_REG(hw, E1000_IPCNFG);
11771 	EM_READ_REG(hw, E1000_EEER);
11772 out:
11773 	return ret_val;
11774 }
11775 
11776 /***************************************************************************
11777  *  em_set_eee_pchlan - Enable/disable EEE support
11778  *  @hw: pointer to the HW structure
11779  *
11780  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
11781  *  the LPI Control register will remain set only if/when link is up.
11782  ***************************************************************************/
11783 int32_t
em_set_eee_pchlan(struct em_hw * hw)11784 em_set_eee_pchlan(struct em_hw *hw)
11785 {
11786        int32_t ret_val = E1000_SUCCESS;
11787        uint16_t phy_reg;
11788 
11789        DEBUGFUNC("em_set_eee_pchlan");
11790 
11791        if (hw->phy_type != em_phy_82579 &&
11792 	   hw->phy_type != em_phy_i217)
11793                goto out;
11794 
11795        ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL, &phy_reg);
11796        if (ret_val)
11797                goto out;
11798 
11799        if (hw->eee_enable)
11800                phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
11801        else
11802                phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
11803 
11804        ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL, phy_reg);
11805 out:
11806        return ret_val;
11807 }
11808 
11809 /**
11810  *  em_initialize_M88E1512_phy - Initialize M88E1512 PHY
11811  *  @hw: pointer to the HW structure
11812  *
11813  *  Initialize Marvell 1512 to work correctly with Avoton.
11814  **/
11815 int32_t
em_initialize_M88E1512_phy(struct em_hw * hw)11816 em_initialize_M88E1512_phy(struct em_hw *hw)
11817 {
11818 	int32_t ret_val = E1000_SUCCESS;
11819 
11820 	DEBUGFUNC("e1000_initialize_M88E1512_phy");
11821 
11822 	/* Check if this is correct PHY. */
11823 	if (hw->phy_id != M88E1512_E_PHY_ID)
11824 		goto out;
11825 
11826 	/* Switch to PHY page 0xFF. */
11827 	ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FF);
11828 	if (ret_val)
11829 		goto out;
11830 
11831 	ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x214B);
11832 	if (ret_val)
11833 		goto out;
11834 
11835 	ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2144);
11836 	if (ret_val)
11837 		goto out;
11838 
11839 	ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x0C28);
11840 	if (ret_val)
11841 		goto out;
11842 
11843 	ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2146);
11844 	if (ret_val)
11845 		goto out;
11846 
11847 	ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xB233);
11848 	if (ret_val)
11849 		goto out;
11850 
11851 	ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x214D);
11852 	if (ret_val)
11853 		goto out;
11854 
11855 	ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xCC0C);
11856 	if (ret_val)
11857 		goto out;
11858 
11859 	ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2159);
11860 	if (ret_val)
11861 		goto out;
11862 
11863 	/* Switch to PHY page 0xFB. */
11864 	ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FB);
11865 	if (ret_val)
11866 		goto out;
11867 
11868 	ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_3, 0x000D);
11869 	if (ret_val)
11870 		goto out;
11871 
11872 	/* Switch to PHY page 0x12. */
11873 	ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x12);
11874 	if (ret_val)
11875 		goto out;
11876 
11877 	/* Change mode to SGMII-to-Copper */
11878 	ret_val = em_write_phy_reg(hw, M88E1512_MODE, 0x8001);
11879 	if (ret_val)
11880 		goto out;
11881 
11882 	/* Return the PHY to page 0. */
11883 	ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0);
11884 	if (ret_val)
11885 		goto out;
11886 
11887 	ret_val = em_phy_hw_reset(hw);
11888 	if (ret_val) {
11889 		DEBUGOUT("Error committing the PHY changes\n");
11890 		return ret_val;
11891 	}
11892 
11893 	msec_delay(1000);
11894 out:
11895 	return ret_val;
11896 }
11897 
11898 uint32_t
em_translate_82542_register(uint32_t reg)11899 em_translate_82542_register(uint32_t reg)
11900 {
11901 	/*
11902 	 * Some of the 82542 registers are located at different
11903 	 * offsets than they are in newer adapters.
11904 	 * Despite the difference in location, the registers
11905 	 * function in the same manner.
11906 	 */
11907 	switch (reg) {
11908 	case E1000_RA:
11909 		reg = 0x00040;
11910 		break;
11911 	case E1000_RDTR:
11912 		reg = 0x00108;
11913 		break;
11914 	case E1000_RDBAL(0):
11915 		reg = 0x00110;
11916 		break;
11917 	case E1000_RDBAH(0):
11918 		reg = 0x00114;
11919 		break;
11920 	case E1000_RDLEN(0):
11921 		reg = 0x00118;
11922 		break;
11923 	case E1000_RDH(0):
11924 		reg = 0x00120;
11925 		break;
11926 	case E1000_RDT(0):
11927 		reg = 0x00128;
11928 		break;
11929 	case E1000_RDBAL(1):
11930 		reg = 0x00138;
11931 		break;
11932 	case E1000_RDBAH(1):
11933 		reg = 0x0013C;
11934 		break;
11935 	case E1000_RDLEN(1):
11936 		reg = 0x00140;
11937 		break;
11938 	case E1000_RDH(1):
11939 		reg = 0x00148;
11940 		break;
11941 	case E1000_RDT(1):
11942 		reg = 0x00150;
11943 		break;
11944 	case E1000_FCRTH:
11945 		reg = 0x00160;
11946 		break;
11947 	case E1000_FCRTL:
11948 		reg = 0x00168;
11949 		break;
11950 	case E1000_MTA:
11951 		reg = 0x00200;
11952 		break;
11953 	case E1000_TDBAL(0):
11954 		reg = 0x00420;
11955 		break;
11956 	case E1000_TDBAH(0):
11957 		reg = 0x00424;
11958 		break;
11959 	case E1000_TDLEN(0):
11960 		reg = 0x00428;
11961 		break;
11962 	case E1000_TDH(0):
11963 		reg = 0x00430;
11964 		break;
11965 	case E1000_TDT(0):
11966 		reg = 0x00438;
11967 		break;
11968 	case E1000_TIDV:
11969 		reg = 0x00440;
11970 		break;
11971 	case E1000_VFTA:
11972 		reg = 0x00600;
11973 		break;
11974 	case E1000_TDFH:
11975 		reg = 0x08010;
11976 		break;
11977 	case E1000_TDFT:
11978 		reg = 0x08018;
11979 		break;
11980 	default:
11981 		break;
11982 	}
11983 
11984 	return (reg);
11985 }
11986