1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _HWMGR_H_ 24 #define _HWMGR_H_ 25 26 #include <linux/seq_file.h> 27 #include "amd_powerplay.h" 28 #include "hardwaremanager.h" 29 #include "hwmgr_ppt.h" 30 #include "ppatomctrl.h" 31 #include "hwmgr_ppt.h" 32 #include "power_state.h" 33 #include "smu_helper.h" 34 35 struct pp_hwmgr; 36 struct phm_fan_speed_info; 37 struct pp_atomctrl_voltage_table; 38 39 #define VOLTAGE_SCALE 4 40 #define VOLTAGE_VID_OFFSET_SCALE1 625 41 #define VOLTAGE_VID_OFFSET_SCALE2 100 42 43 enum DISPLAY_GAP { 44 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */ 45 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */ 46 DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */ 47 DISPLAY_GAP_IGNORE = 3 /* Do not wait. */ 48 }; 49 typedef enum DISPLAY_GAP DISPLAY_GAP; 50 51 struct vi_dpm_level { 52 bool enabled; 53 uint32_t value; 54 uint32_t param1; 55 }; 56 57 struct vi_dpm_table { 58 uint32_t count; 59 struct vi_dpm_level dpm_level[1]; 60 }; 61 62 #define PCIE_PERF_REQ_REMOVE_REGISTRY 0 63 #define PCIE_PERF_REQ_FORCE_LOWPOWER 1 64 #define PCIE_PERF_REQ_GEN1 2 65 #define PCIE_PERF_REQ_GEN2 3 66 #define PCIE_PERF_REQ_GEN3 4 67 68 enum PHM_BackEnd_Magic { 69 PHM_Dummy_Magic = 0xAA5555AA, 70 PHM_RV770_Magic = 0xDCBAABCD, 71 PHM_Kong_Magic = 0x239478DF, 72 PHM_NIslands_Magic = 0x736C494E, 73 PHM_Sumo_Magic = 0x8339FA11, 74 PHM_SIslands_Magic = 0x369431AC, 75 PHM_Trinity_Magic = 0x96751873, 76 PHM_CIslands_Magic = 0x38AC78B0, 77 PHM_Kv_Magic = 0xDCBBABC0, 78 PHM_VIslands_Magic = 0x20130307, 79 PHM_Cz_Magic = 0x67DCBA25, 80 PHM_Rv_Magic = 0x20161121 81 }; 82 83 struct phm_set_power_state_input { 84 const struct pp_hw_power_state *pcurrent_state; 85 const struct pp_hw_power_state *pnew_state; 86 }; 87 88 struct phm_clock_array { 89 uint32_t count; 90 uint32_t values[1]; 91 }; 92 93 struct phm_clock_voltage_dependency_record { 94 uint32_t clk; 95 uint32_t v; 96 }; 97 98 struct phm_vceclock_voltage_dependency_record { 99 uint32_t ecclk; 100 uint32_t evclk; 101 uint32_t v; 102 }; 103 104 struct phm_uvdclock_voltage_dependency_record { 105 uint32_t vclk; 106 uint32_t dclk; 107 uint32_t v; 108 }; 109 110 struct phm_samuclock_voltage_dependency_record { 111 uint32_t samclk; 112 uint32_t v; 113 }; 114 115 struct phm_acpclock_voltage_dependency_record { 116 uint32_t acpclk; 117 uint32_t v; 118 }; 119 120 struct phm_clock_voltage_dependency_table { 121 uint32_t count; /* Number of entries. */ 122 struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 123 }; 124 125 struct phm_phase_shedding_limits_record { 126 uint32_t Voltage; 127 uint32_t Sclk; 128 uint32_t Mclk; 129 }; 130 131 struct phm_uvd_clock_voltage_dependency_record { 132 uint32_t vclk; 133 uint32_t dclk; 134 uint32_t v; 135 }; 136 137 struct phm_uvd_clock_voltage_dependency_table { 138 uint8_t count; 139 struct phm_uvd_clock_voltage_dependency_record entries[1]; 140 }; 141 142 struct phm_acp_clock_voltage_dependency_record { 143 uint32_t acpclk; 144 uint32_t v; 145 }; 146 147 struct phm_acp_clock_voltage_dependency_table { 148 uint32_t count; 149 struct phm_acp_clock_voltage_dependency_record entries[1]; 150 }; 151 152 struct phm_vce_clock_voltage_dependency_record { 153 uint32_t ecclk; 154 uint32_t evclk; 155 uint32_t v; 156 }; 157 158 struct phm_phase_shedding_limits_table { 159 uint32_t count; 160 struct phm_phase_shedding_limits_record entries[1]; 161 }; 162 163 struct phm_vceclock_voltage_dependency_table { 164 uint8_t count; /* Number of entries. */ 165 struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 166 }; 167 168 struct phm_uvdclock_voltage_dependency_table { 169 uint8_t count; /* Number of entries. */ 170 struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 171 }; 172 173 struct phm_samuclock_voltage_dependency_table { 174 uint8_t count; /* Number of entries. */ 175 struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 176 }; 177 178 struct phm_acpclock_voltage_dependency_table { 179 uint32_t count; /* Number of entries. */ 180 struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 181 }; 182 183 struct phm_vce_clock_voltage_dependency_table { 184 uint8_t count; 185 struct phm_vce_clock_voltage_dependency_record entries[1]; 186 }; 187 188 struct pp_smumgr_func { 189 int (*smu_init)(struct pp_hwmgr *hwmgr); 190 int (*smu_fini)(struct pp_hwmgr *hwmgr); 191 int (*start_smu)(struct pp_hwmgr *hwmgr); 192 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr, 193 uint32_t firmware); 194 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr); 195 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr, 196 uint32_t firmware); 197 uint32_t (*get_argument)(struct pp_hwmgr *hwmgr); 198 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg); 199 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr, 200 uint16_t msg, uint32_t parameter); 201 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr, 202 void **table); 203 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr); 204 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type); 205 int (*process_firmware_header)(struct pp_hwmgr *hwmgr); 206 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr); 207 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr); 208 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr); 209 int (*init_smc_table)(struct pp_hwmgr *hwmgr); 210 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr); 211 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr); 212 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr); 213 uint32_t (*get_offsetof)(uint32_t type, uint32_t member); 214 uint32_t (*get_mac_definition)(uint32_t value); 215 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr); 216 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr); 217 int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting); 218 int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */ 219 int (*stop_smc)(struct pp_hwmgr *hwmgr); 220 }; 221 222 struct pp_hwmgr_func { 223 int (*backend_init)(struct pp_hwmgr *hw_mgr); 224 int (*backend_fini)(struct pp_hwmgr *hw_mgr); 225 int (*asic_setup)(struct pp_hwmgr *hw_mgr); 226 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr); 227 228 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr, 229 struct pp_power_state *prequest_ps, 230 const struct pp_power_state *pcurrent_ps); 231 232 int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr); 233 234 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr, 235 enum amd_dpm_forced_level level); 236 237 int (*dynamic_state_management_enable)( 238 struct pp_hwmgr *hw_mgr); 239 int (*dynamic_state_management_disable)( 240 struct pp_hwmgr *hw_mgr); 241 242 int (*patch_boot_state)(struct pp_hwmgr *hwmgr, 243 struct pp_hw_power_state *hw_ps); 244 245 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr, 246 unsigned long, struct pp_power_state *); 247 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr); 248 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr); 249 void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate); 250 void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate); 251 uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low); 252 uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low); 253 int (*power_state_set)(struct pp_hwmgr *hwmgr, 254 const void *state); 255 int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr); 256 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr); 257 int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr); 258 int (*display_config_changed)(struct pp_hwmgr *hwmgr); 259 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr); 260 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr, 261 const uint32_t *msg_id); 262 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm); 263 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm); 264 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr); 265 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info); 266 void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode); 267 uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr); 268 int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent); 269 int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed); 270 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent); 271 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed); 272 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr); 273 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr); 274 int (*register_irq_handlers)(struct pp_hwmgr *hwmgr); 275 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr); 276 int (*check_states_equal)(struct pp_hwmgr *hwmgr, 277 const struct pp_hw_power_state *pstate1, 278 const struct pp_hw_power_state *pstate2, 279 bool *equal); 280 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr); 281 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time, 282 bool cc6_disable, bool pstate_disable, 283 bool pstate_switch_disable); 284 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr, 285 struct amd_pp_simple_clock_info *info); 286 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *, 287 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *); 288 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr, 289 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info); 290 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks); 291 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr, 292 enum amd_pp_clock_type type, 293 struct pp_clock_levels_with_latency *clocks); 294 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr, 295 enum amd_pp_clock_type type, 296 struct pp_clock_levels_with_voltage *clocks); 297 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges); 298 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr, 299 struct pp_display_clock_request *clock); 300 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks); 301 int (*gfx_off_control)(struct pp_hwmgr *hwmgr, bool enable); 302 int (*power_off_asic)(struct pp_hwmgr *hwmgr); 303 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask); 304 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf); 305 int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable); 306 int (*get_sclk_od)(struct pp_hwmgr *hwmgr); 307 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); 308 int (*get_mclk_od)(struct pp_hwmgr *hwmgr); 309 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); 310 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size); 311 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable); 312 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr); 313 int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count); 314 int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock); 315 int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range); 316 int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr, 317 uint32_t virtual_addr_low, 318 uint32_t virtual_addr_hi, 319 uint32_t mc_addr_low, 320 uint32_t mc_addr_hi, 321 uint32_t size); 322 int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr, 323 struct PP_TemperatureRange *range); 324 int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf); 325 int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size); 326 int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr, 327 enum PP_OD_DPM_TABLE_COMMAND type, 328 long *input, uint32_t size); 329 int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n); 330 int (*powergate_mmhub)(struct pp_hwmgr *hwmgr); 331 int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr); 332 }; 333 334 struct pp_table_func { 335 int (*pptable_init)(struct pp_hwmgr *hw_mgr); 336 int (*pptable_fini)(struct pp_hwmgr *hw_mgr); 337 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr); 338 int (*pptable_get_vce_state_table_entry)( 339 struct pp_hwmgr *hwmgr, 340 unsigned long i, 341 struct amd_vce_state *vce_state, 342 void **clock_info, 343 unsigned long *flag); 344 }; 345 346 union phm_cac_leakage_record { 347 struct { 348 uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */ 349 uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */ 350 }; 351 struct { 352 uint16_t Vddc1; 353 uint16_t Vddc2; 354 uint16_t Vddc3; 355 }; 356 }; 357 358 struct phm_cac_leakage_table { 359 uint32_t count; 360 union phm_cac_leakage_record entries[1]; 361 }; 362 363 struct phm_samu_clock_voltage_dependency_record { 364 uint32_t samclk; 365 uint32_t v; 366 }; 367 368 369 struct phm_samu_clock_voltage_dependency_table { 370 uint8_t count; 371 struct phm_samu_clock_voltage_dependency_record entries[1]; 372 }; 373 374 struct phm_cac_tdp_table { 375 uint16_t usTDP; 376 uint16_t usConfigurableTDP; 377 uint16_t usTDC; 378 uint16_t usBatteryPowerLimit; 379 uint16_t usSmallPowerLimit; 380 uint16_t usLowCACLeakage; 381 uint16_t usHighCACLeakage; 382 uint16_t usMaximumPowerDeliveryLimit; 383 uint16_t usEDCLimit; 384 uint16_t usOperatingTempMinLimit; 385 uint16_t usOperatingTempMaxLimit; 386 uint16_t usOperatingTempStep; 387 uint16_t usOperatingTempHyst; 388 uint16_t usDefaultTargetOperatingTemp; 389 uint16_t usTargetOperatingTemp; 390 uint16_t usPowerTuneDataSetID; 391 uint16_t usSoftwareShutdownTemp; 392 uint16_t usClockStretchAmount; 393 uint16_t usTemperatureLimitHotspot; 394 uint16_t usTemperatureLimitLiquid1; 395 uint16_t usTemperatureLimitLiquid2; 396 uint16_t usTemperatureLimitVrVddc; 397 uint16_t usTemperatureLimitVrMvdd; 398 uint16_t usTemperatureLimitPlx; 399 uint8_t ucLiquid1_I2C_address; 400 uint8_t ucLiquid2_I2C_address; 401 uint8_t ucLiquid_I2C_Line; 402 uint8_t ucVr_I2C_address; 403 uint8_t ucVr_I2C_Line; 404 uint8_t ucPlx_I2C_address; 405 uint8_t ucPlx_I2C_Line; 406 uint32_t usBoostPowerLimit; 407 uint8_t ucCKS_LDO_REFSEL; 408 }; 409 410 struct phm_tdp_table { 411 uint16_t usTDP; 412 uint16_t usConfigurableTDP; 413 uint16_t usTDC; 414 uint16_t usBatteryPowerLimit; 415 uint16_t usSmallPowerLimit; 416 uint16_t usLowCACLeakage; 417 uint16_t usHighCACLeakage; 418 uint16_t usMaximumPowerDeliveryLimit; 419 uint16_t usEDCLimit; 420 uint16_t usOperatingTempMinLimit; 421 uint16_t usOperatingTempMaxLimit; 422 uint16_t usOperatingTempStep; 423 uint16_t usOperatingTempHyst; 424 uint16_t usDefaultTargetOperatingTemp; 425 uint16_t usTargetOperatingTemp; 426 uint16_t usPowerTuneDataSetID; 427 uint16_t usSoftwareShutdownTemp; 428 uint16_t usClockStretchAmount; 429 uint16_t usTemperatureLimitTedge; 430 uint16_t usTemperatureLimitHotspot; 431 uint16_t usTemperatureLimitLiquid1; 432 uint16_t usTemperatureLimitLiquid2; 433 uint16_t usTemperatureLimitHBM; 434 uint16_t usTemperatureLimitVrVddc; 435 uint16_t usTemperatureLimitVrMvdd; 436 uint16_t usTemperatureLimitPlx; 437 uint8_t ucLiquid1_I2C_address; 438 uint8_t ucLiquid2_I2C_address; 439 uint8_t ucLiquid_I2C_Line; 440 uint8_t ucVr_I2C_address; 441 uint8_t ucVr_I2C_Line; 442 uint8_t ucPlx_I2C_address; 443 uint8_t ucPlx_I2C_Line; 444 uint8_t ucLiquid_I2C_LineSDA; 445 uint8_t ucVr_I2C_LineSDA; 446 uint8_t ucPlx_I2C_LineSDA; 447 uint32_t usBoostPowerLimit; 448 uint16_t usBoostStartTemperature; 449 uint16_t usBoostStopTemperature; 450 uint32_t ulBoostClock; 451 }; 452 453 struct phm_ppm_table { 454 uint8_t ppm_design; 455 uint16_t cpu_core_number; 456 uint32_t platform_tdp; 457 uint32_t small_ac_platform_tdp; 458 uint32_t platform_tdc; 459 uint32_t small_ac_platform_tdc; 460 uint32_t apu_tdp; 461 uint32_t dgpu_tdp; 462 uint32_t dgpu_ulv_power; 463 uint32_t tj_max; 464 }; 465 466 struct phm_vq_budgeting_record { 467 uint32_t ulCUs; 468 uint32_t ulSustainableSOCPowerLimitLow; 469 uint32_t ulSustainableSOCPowerLimitHigh; 470 uint32_t ulMinSclkLow; 471 uint32_t ulMinSclkHigh; 472 uint8_t ucDispConfig; 473 uint32_t ulDClk; 474 uint32_t ulEClk; 475 uint32_t ulSustainableSclk; 476 uint32_t ulSustainableCUs; 477 }; 478 479 struct phm_vq_budgeting_table { 480 uint8_t numEntries; 481 struct phm_vq_budgeting_record entries[1]; 482 }; 483 484 struct phm_clock_and_voltage_limits { 485 uint32_t sclk; 486 uint32_t mclk; 487 uint32_t gfxclk; 488 uint16_t vddc; 489 uint16_t vddci; 490 uint16_t vddgfx; 491 uint16_t vddmem; 492 }; 493 494 /* Structure to hold PPTable information */ 495 496 struct phm_ppt_v1_information { 497 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk; 498 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk; 499 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk; 500 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk; 501 struct phm_clock_array *valid_sclk_values; 502 struct phm_clock_array *valid_mclk_values; 503 struct phm_clock_array *valid_socclk_values; 504 struct phm_clock_array *valid_dcefclk_values; 505 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; 506 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; 507 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl; 508 struct phm_ppm_table *ppm_parameter_table; 509 struct phm_cac_tdp_table *cac_dtp_table; 510 struct phm_tdp_table *tdp_table; 511 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table; 512 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 513 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table; 514 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table; 515 struct phm_ppt_v1_pcie_table *pcie_table; 516 struct phm_ppt_v1_gpio_table *gpio_table; 517 uint16_t us_ulv_voltage_offset; 518 uint16_t us_ulv_smnclk_did; 519 uint16_t us_ulv_mp1clk_did; 520 uint16_t us_ulv_gfxclk_bypass; 521 uint16_t us_gfxclk_slew_rate; 522 uint16_t us_min_gfxclk_freq_limit; 523 }; 524 525 struct phm_ppt_v2_information { 526 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk; 527 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk; 528 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk; 529 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk; 530 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk; 531 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk; 532 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk; 533 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table; 534 535 struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl; 536 537 struct phm_clock_array *valid_sclk_values; 538 struct phm_clock_array *valid_mclk_values; 539 struct phm_clock_array *valid_socclk_values; 540 struct phm_clock_array *valid_dcefclk_values; 541 542 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; 543 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; 544 545 struct phm_ppm_table *ppm_parameter_table; 546 struct phm_cac_tdp_table *cac_dtp_table; 547 struct phm_tdp_table *tdp_table; 548 549 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 550 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table; 551 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table; 552 struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table; 553 554 struct phm_ppt_v1_pcie_table *pcie_table; 555 556 uint16_t us_ulv_voltage_offset; 557 uint16_t us_ulv_smnclk_did; 558 uint16_t us_ulv_mp1clk_did; 559 uint16_t us_ulv_gfxclk_bypass; 560 uint16_t us_gfxclk_slew_rate; 561 uint16_t us_min_gfxclk_freq_limit; 562 563 uint8_t uc_gfx_dpm_voltage_mode; 564 uint8_t uc_soc_dpm_voltage_mode; 565 uint8_t uc_uclk_dpm_voltage_mode; 566 uint8_t uc_uvd_dpm_voltage_mode; 567 uint8_t uc_vce_dpm_voltage_mode; 568 uint8_t uc_mp0_dpm_voltage_mode; 569 uint8_t uc_dcef_dpm_voltage_mode; 570 }; 571 572 struct phm_ppt_v3_information 573 { 574 uint8_t uc_thermal_controller_type; 575 576 uint16_t us_small_power_limit1; 577 uint16_t us_small_power_limit2; 578 uint16_t us_boost_power_limit; 579 580 uint16_t us_od_turbo_power_limit; 581 uint16_t us_od_powersave_power_limit; 582 uint16_t us_software_shutdown_temp; 583 584 uint32_t *power_saving_clock_max; 585 uint32_t *power_saving_clock_min; 586 587 uint32_t *od_settings_max; 588 uint32_t *od_settings_min; 589 590 void *smc_pptable; 591 }; 592 593 struct phm_dynamic_state_info { 594 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk; 595 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk; 596 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk; 597 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk; 598 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl; 599 struct phm_clock_array *valid_sclk_values; 600 struct phm_clock_array *valid_mclk_values; 601 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; 602 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; 603 uint32_t mclk_sclk_ratio; 604 uint32_t sclk_mclk_delta; 605 uint32_t vddc_vddci_delta; 606 uint32_t min_vddc_for_pcie_gen2; 607 struct phm_cac_leakage_table *cac_leakage_table; 608 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table; 609 610 struct phm_vce_clock_voltage_dependency_table 611 *vce_clock_voltage_dependency_table; 612 struct phm_uvd_clock_voltage_dependency_table 613 *uvd_clock_voltage_dependency_table; 614 struct phm_acp_clock_voltage_dependency_table 615 *acp_clock_voltage_dependency_table; 616 struct phm_samu_clock_voltage_dependency_table 617 *samu_clock_voltage_dependency_table; 618 619 struct phm_ppm_table *ppm_parameter_table; 620 struct phm_cac_tdp_table *cac_dtp_table; 621 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk; 622 }; 623 624 struct pp_fan_info { 625 bool bNoFan; 626 uint8_t ucTachometerPulsesPerRevolution; 627 uint32_t ulMinRPM; 628 uint32_t ulMaxRPM; 629 }; 630 631 struct pp_advance_fan_control_parameters { 632 uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */ 633 uint16_t usTMed; /* The middle temperature where we change slopes. */ 634 uint16_t usTHigh; /* The high temperature for setting the second slope. */ 635 uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */ 636 uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */ 637 uint16_t usPWMHigh; /* The PWM value at THigh. */ 638 uint8_t ucTHyst; /* Temperature hysteresis. Integer. */ 639 uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */ 640 uint16_t usTMax; /* The max temperature */ 641 uint8_t ucFanControlMode; 642 uint16_t usFanPWMMinLimit; 643 uint16_t usFanPWMMaxLimit; 644 uint16_t usFanPWMStep; 645 uint16_t usDefaultMaxFanPWM; 646 uint16_t usFanOutputSensitivity; 647 uint16_t usDefaultFanOutputSensitivity; 648 uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */ 649 uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */ 650 uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */ 651 uint16_t usFanRPMStep; /* Step increments/decerements, in percent */ 652 uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */ 653 uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */ 654 uint16_t usFanCurrentLow; /* Low current */ 655 uint16_t usFanCurrentHigh; /* High current */ 656 uint16_t usFanRPMLow; /* Low RPM */ 657 uint16_t usFanRPMHigh; /* High RPM */ 658 uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */ 659 uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */ 660 uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */ 661 uint16_t usFanGainEdge; /* The following is added for Fiji */ 662 uint16_t usFanGainHotspot; 663 uint16_t usFanGainLiquid; 664 uint16_t usFanGainVrVddc; 665 uint16_t usFanGainVrMvdd; 666 uint16_t usFanGainPlx; 667 uint16_t usFanGainHbm; 668 uint8_t ucEnableZeroRPM; 669 uint8_t ucFanStopTemperature; 670 uint8_t ucFanStartTemperature; 671 uint32_t ulMaxFanSCLKAcousticLimit; /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */ 672 uint32_t ulTargetGfxClk; 673 uint16_t usZeroRPMStartTemperature; 674 uint16_t usZeroRPMStopTemperature; 675 }; 676 677 struct pp_thermal_controller_info { 678 uint8_t ucType; 679 uint8_t ucI2cLine; 680 uint8_t ucI2cAddress; 681 uint8_t use_hw_fan_control; 682 struct pp_fan_info fanInfo; 683 struct pp_advance_fan_control_parameters advanceFanControlParameters; 684 }; 685 686 struct phm_microcode_version_info { 687 uint32_t SMC; 688 uint32_t DMCU; 689 uint32_t MC; 690 uint32_t NB; 691 }; 692 693 enum PP_TABLE_VERSION { 694 PP_TABLE_V0 = 0, 695 PP_TABLE_V1, 696 PP_TABLE_V2, 697 PP_TABLE_MAX 698 }; 699 700 /** 701 * The main hardware manager structure. 702 */ 703 #define Workload_Policy_Max 5 704 705 struct pp_hwmgr { 706 void *adev; 707 uint32_t chip_family; 708 uint32_t chip_id; 709 uint32_t smu_version; 710 bool not_vf; 711 bool pm_en; 712 struct lock smu_lock; 713 714 uint32_t pp_table_version; 715 void *device; 716 struct pp_smumgr *smumgr; 717 const void *soft_pp_table; 718 uint32_t soft_pp_table_size; 719 void *hardcode_pp_table; 720 bool need_pp_table_upload; 721 722 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; 723 uint32_t num_vce_state_tables; 724 725 enum amd_dpm_forced_level dpm_level; 726 enum amd_dpm_forced_level saved_dpm_level; 727 enum amd_dpm_forced_level request_dpm_level; 728 uint32_t usec_timeout; 729 void *pptable; 730 struct phm_platform_descriptor platform_descriptor; 731 void *backend; 732 733 void *smu_backend; 734 const struct pp_smumgr_func *smumgr_funcs; 735 bool is_kicker; 736 bool reload_fw; 737 738 enum PP_DAL_POWERLEVEL dal_power_level; 739 struct phm_dynamic_state_info dyn_state; 740 const struct pp_hwmgr_func *hwmgr_func; 741 const struct pp_table_func *pptable_func; 742 743 struct pp_power_state *ps; 744 uint32_t num_ps; 745 struct pp_thermal_controller_info thermal_controller; 746 bool fan_ctrl_is_in_default_mode; 747 uint32_t fan_ctrl_default_mode; 748 bool fan_ctrl_enabled; 749 uint32_t tmin; 750 struct phm_microcode_version_info microcode_version_info; 751 uint32_t ps_size; 752 struct pp_power_state *current_ps; 753 struct pp_power_state *request_ps; 754 struct pp_power_state *boot_ps; 755 struct pp_power_state *uvd_ps; 756 const struct amd_pp_display_configuration *display_config; 757 uint32_t feature_mask; 758 bool avfs_supported; 759 /* UMD Pstate */ 760 bool en_umd_pstate; 761 uint32_t power_profile_mode; 762 uint32_t default_power_profile_mode; 763 uint32_t pstate_sclk; 764 uint32_t pstate_mclk; 765 bool od_enabled; 766 uint32_t power_limit; 767 uint32_t default_power_limit; 768 uint32_t workload_mask; 769 uint32_t workload_prority[Workload_Policy_Max]; 770 uint32_t workload_setting[Workload_Policy_Max]; 771 }; 772 773 int hwmgr_early_init(struct pp_hwmgr *hwmgr); 774 int hwmgr_sw_init(struct pp_hwmgr *hwmgr); 775 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr); 776 int hwmgr_hw_init(struct pp_hwmgr *hwmgr); 777 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr); 778 int hwmgr_suspend(struct pp_hwmgr *hwmgr); 779 int hwmgr_resume(struct pp_hwmgr *hwmgr); 780 781 int hwmgr_handle_task(struct pp_hwmgr *hwmgr, 782 enum amd_pp_task task_id, 783 enum amd_pm_state_type *user_state); 784 785 786 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU 787 788 789 #endif /* _HWMGR_H_ */ 790