1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
28
29 #include <linux/i2c.h>
30 #include <linux/pm_qos.h>
31 #include <linux/pwm.h>
32 #include <linux/sched/clock.h>
33
34 #include <drm/display/drm_dp_dual_mode_helper.h>
35 #include <drm/display/drm_dp_mst_helper.h>
36 #include <drm/display/drm_dp_tunnel.h>
37 #include <drm/display/drm_dsc.h>
38 #include <drm/drm_atomic.h>
39 #include <drm/drm_crtc.h>
40 #include <drm/drm_encoder.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_framebuffer.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
45 #include <drm/drm_vblank.h>
46 #include <drm/drm_vblank_work.h>
47 #include <drm/i915_hdcp_interface.h>
48 #include <media/cec-notifier.h>
49
50 #include "i915_vma.h"
51 #include "i915_vma_types.h"
52 #include "intel_bios.h"
53 #include "intel_display.h"
54 #include "intel_display_limits.h"
55 #include "intel_display_power.h"
56 #include "intel_dpll_mgr.h"
57 #include "intel_wm_types.h"
58
59 struct drm_printer;
60 struct __intel_global_objs_state;
61 struct intel_ddi_buf_trans;
62 struct intel_fbc;
63 struct intel_connector;
64 struct intel_tc_port;
65
66 /*
67 * Display related stuff
68 */
69
70 /* these are outputs from the chip - integrated only
71 external chips are via DVO or SDVO output */
72 enum intel_output_type {
73 INTEL_OUTPUT_UNUSED = 0,
74 INTEL_OUTPUT_ANALOG = 1,
75 INTEL_OUTPUT_DVO = 2,
76 INTEL_OUTPUT_SDVO = 3,
77 INTEL_OUTPUT_LVDS = 4,
78 INTEL_OUTPUT_TVOUT = 5,
79 INTEL_OUTPUT_HDMI = 6,
80 INTEL_OUTPUT_DP = 7,
81 INTEL_OUTPUT_EDP = 8,
82 INTEL_OUTPUT_DSI = 9,
83 INTEL_OUTPUT_DDI = 10,
84 INTEL_OUTPUT_DP_MST = 11,
85 };
86
87 enum hdmi_force_audio {
88 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
89 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
90 HDMI_AUDIO_AUTO, /* trust EDID */
91 HDMI_AUDIO_ON, /* force turn on HDMI audio */
92 };
93
94 /* "Broadcast RGB" property */
95 enum intel_broadcast_rgb {
96 INTEL_BROADCAST_RGB_AUTO,
97 INTEL_BROADCAST_RGB_FULL,
98 INTEL_BROADCAST_RGB_LIMITED,
99 };
100
101 struct intel_fb_view {
102 /*
103 * The remap information used in the remapped and rotated views to
104 * create the DMA scatter-gather list for each FB color plane. This sg
105 * list is created along with the view type (gtt.type) specific
106 * i915_vma object and contains the list of FB object pages (reordered
107 * in the rotated view) that are visible in the view.
108 * In the normal view the FB object's backing store sg list is used
109 * directly and hence the remap information here is not used.
110 */
111 struct i915_gtt_view gtt;
112
113 /*
114 * The GTT view (gtt.type) specific information for each FB color
115 * plane. In the normal GTT view all formats (up to 4 color planes),
116 * in the rotated and remapped GTT view all no-CCS formats (up to 2
117 * color planes) are supported.
118 *
119 * The view information shared by all FB color planes in the FB,
120 * like dst x/y and src/dst width, is stored separately in
121 * intel_plane_state.
122 */
123 struct i915_color_plane_view {
124 u32 offset;
125 unsigned int x, y;
126 /*
127 * Plane stride in:
128 * bytes for 0/180 degree rotation
129 * pixels for 90/270 degree rotation
130 */
131 unsigned int mapping_stride;
132 unsigned int scanout_stride;
133 } color_plane[4];
134 };
135
136 struct intel_framebuffer {
137 struct drm_framebuffer base;
138 struct intel_frontbuffer *frontbuffer;
139
140 /* Params to remap the FB pages and program the plane registers in each view. */
141 struct intel_fb_view normal_view;
142 union {
143 struct intel_fb_view rotated_view;
144 struct intel_fb_view remapped_view;
145 };
146
147 struct i915_address_space *dpt_vm;
148 };
149
150 enum intel_hotplug_state {
151 INTEL_HOTPLUG_UNCHANGED,
152 INTEL_HOTPLUG_CHANGED,
153 INTEL_HOTPLUG_RETRY,
154 };
155
156 struct intel_encoder {
157 struct drm_encoder base;
158
159 enum intel_output_type type;
160 enum port port;
161 u16 cloneable;
162 u8 pipe_mask;
163 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
164 struct intel_connector *connector);
165 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
166 struct intel_crtc_state *,
167 struct drm_connector_state *);
168 int (*compute_config)(struct intel_encoder *,
169 struct intel_crtc_state *,
170 struct drm_connector_state *);
171 int (*compute_config_late)(struct intel_encoder *,
172 struct intel_crtc_state *,
173 struct drm_connector_state *);
174 void (*pre_pll_enable)(struct intel_atomic_state *,
175 struct intel_encoder *,
176 const struct intel_crtc_state *,
177 const struct drm_connector_state *);
178 void (*pre_enable)(struct intel_atomic_state *,
179 struct intel_encoder *,
180 const struct intel_crtc_state *,
181 const struct drm_connector_state *);
182 void (*enable)(struct intel_atomic_state *,
183 struct intel_encoder *,
184 const struct intel_crtc_state *,
185 const struct drm_connector_state *);
186 void (*disable)(struct intel_atomic_state *,
187 struct intel_encoder *,
188 const struct intel_crtc_state *,
189 const struct drm_connector_state *);
190 void (*post_disable)(struct intel_atomic_state *,
191 struct intel_encoder *,
192 const struct intel_crtc_state *,
193 const struct drm_connector_state *);
194 void (*post_pll_disable)(struct intel_atomic_state *,
195 struct intel_encoder *,
196 const struct intel_crtc_state *,
197 const struct drm_connector_state *);
198 void (*update_pipe)(struct intel_atomic_state *,
199 struct intel_encoder *,
200 const struct intel_crtc_state *,
201 const struct drm_connector_state *);
202 void (*audio_enable)(struct intel_encoder *encoder,
203 const struct intel_crtc_state *crtc_state,
204 const struct drm_connector_state *conn_state);
205 void (*audio_disable)(struct intel_encoder *encoder,
206 const struct intel_crtc_state *old_crtc_state,
207 const struct drm_connector_state *old_conn_state);
208 /* Read out the current hw state of this connector, returning true if
209 * the encoder is active. If the encoder is enabled it also set the pipe
210 * it is connected to in the pipe parameter. */
211 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
212 /* Reconstructs the equivalent mode flags for the current hardware
213 * state. This must be called _after_ display->get_pipe_config has
214 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
215 * be set correctly before calling this function. */
216 void (*get_config)(struct intel_encoder *,
217 struct intel_crtc_state *pipe_config);
218
219 /*
220 * Optional hook called during init/resume to sync any state
221 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
222 */
223 void (*sync_state)(struct intel_encoder *encoder,
224 const struct intel_crtc_state *crtc_state);
225
226 /*
227 * Optional hook, returning true if this encoder allows a fastset
228 * during the initial commit, false otherwise.
229 */
230 bool (*initial_fastset_check)(struct intel_encoder *encoder,
231 struct intel_crtc_state *crtc_state);
232
233 /*
234 * Acquires the power domains needed for an active encoder during
235 * hardware state readout.
236 */
237 void (*get_power_domains)(struct intel_encoder *encoder,
238 struct intel_crtc_state *crtc_state);
239 /*
240 * Called during system suspend after all pending requests for the
241 * encoder are flushed (for example for DP AUX transactions) and
242 * device interrupts are disabled.
243 * All modeset locks are held while the hook is called.
244 */
245 void (*suspend)(struct intel_encoder *);
246 /*
247 * Called without the modeset locks held after the suspend() hook for
248 * all encoders have been called.
249 */
250 void (*suspend_complete)(struct intel_encoder *encoder);
251 /*
252 * Called during system reboot/shutdown after all the
253 * encoders have been disabled and suspended.
254 * All modeset locks are held while the hook is called.
255 */
256 void (*shutdown)(struct intel_encoder *encoder);
257 /*
258 * Called without the modeset locks held after the shutdown() hook for
259 * all encoders have been called.
260 */
261 void (*shutdown_complete)(struct intel_encoder *encoder);
262 /*
263 * Enable/disable the clock to the port.
264 */
265 void (*enable_clock)(struct intel_encoder *encoder,
266 const struct intel_crtc_state *crtc_state);
267 void (*disable_clock)(struct intel_encoder *encoder);
268 /*
269 * Returns whether the port clock is enabled or not.
270 */
271 bool (*is_clock_enabled)(struct intel_encoder *encoder);
272 /*
273 * Returns the PLL type the port uses.
274 */
275 enum icl_port_dpll_id (*port_pll_type)(struct intel_encoder *encoder,
276 const struct intel_crtc_state *crtc_state);
277 const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder,
278 const struct intel_crtc_state *crtc_state,
279 int *n_entries);
280 void (*set_signal_levels)(struct intel_encoder *encoder,
281 const struct intel_crtc_state *crtc_state);
282
283 enum hpd_pin hpd_pin;
284 enum intel_display_power_domain power_domain;
285
286 /* VBT information for this encoder (may be NULL for older platforms) */
287 const struct intel_bios_encoder_data *devdata;
288 };
289
290 struct intel_panel_bl_funcs {
291 /* Connector and platform specific backlight functions */
292 int (*setup)(struct intel_connector *connector, enum pipe pipe);
293 u32 (*get)(struct intel_connector *connector, enum pipe pipe);
294 void (*set)(const struct drm_connector_state *conn_state, u32 level);
295 void (*disable)(const struct drm_connector_state *conn_state, u32 level);
296 void (*enable)(const struct intel_crtc_state *crtc_state,
297 const struct drm_connector_state *conn_state, u32 level);
298 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
299 };
300
301 enum drrs_type {
302 DRRS_TYPE_NONE,
303 DRRS_TYPE_STATIC,
304 DRRS_TYPE_SEAMLESS,
305 };
306
307 struct intel_vbt_panel_data {
308 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
309 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
310
311 /* Feature bits */
312 int panel_type;
313 unsigned int lvds_dither:1;
314 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
315
316 bool vrr;
317
318 u8 seamless_drrs_min_refresh_rate;
319 enum drrs_type drrs_type;
320
321 struct {
322 int max_link_rate;
323 int rate;
324 int lanes;
325 int preemphasis;
326 int vswing;
327 int bpp;
328 struct edp_power_seq pps;
329 u8 drrs_msa_timing_delay;
330 bool low_vswing;
331 bool hobl;
332 } edp;
333
334 struct {
335 bool enable;
336 bool full_link;
337 bool require_aux_wakeup;
338 int idle_frames;
339 int tp1_wakeup_time_us;
340 int tp2_tp3_wakeup_time_us;
341 int psr2_tp2_tp3_wakeup_time_us;
342 } psr;
343
344 struct {
345 u16 pwm_freq_hz;
346 u16 brightness_precision_bits;
347 u16 hdr_dpcd_refresh_timeout;
348 bool present;
349 bool active_low_pwm;
350 u8 min_brightness; /* min_brightness/255 of max */
351 s8 controller; /* brightness controller number */
352 enum intel_backlight_type type;
353 } backlight;
354
355 /* MIPI DSI */
356 struct {
357 u16 panel_id;
358 struct mipi_config *config;
359 struct mipi_pps_data *pps;
360 u16 bl_ports;
361 u16 cabc_ports;
362 u8 seq_version;
363 u32 size;
364 u8 *data;
365 const u8 *sequence[MIPI_SEQ_MAX];
366 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
367 enum drm_panel_orientation orientation;
368 } dsi;
369 };
370
371 struct intel_panel {
372 /* Fixed EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
373 const struct drm_edid *fixed_edid;
374
375 struct list_head fixed_modes;
376
377 /* backlight */
378 struct {
379 bool present;
380 u32 level;
381 u32 min;
382 u32 max;
383 bool enabled;
384 bool combination_mode; /* gen 2/4 only */
385 bool active_low_pwm;
386 bool alternate_pwm_increment; /* lpt+ */
387
388 /* PWM chip */
389 u32 pwm_level_min;
390 u32 pwm_level_max;
391 bool pwm_enabled;
392 bool util_pin_active_low; /* bxt+ */
393 u8 controller; /* bxt+ only */
394 struct pwm_device *pwm;
395 struct pwm_state pwm_state;
396
397 /* DPCD backlight */
398 union {
399 struct {
400 struct drm_edp_backlight_info info;
401 } vesa;
402 struct {
403 bool sdr_uses_aux;
404 } intel;
405 } edp;
406
407 struct backlight_device *device;
408
409 const struct intel_panel_bl_funcs *funcs;
410 const struct intel_panel_bl_funcs *pwm_funcs;
411 void (*power)(struct intel_connector *, bool enable);
412 } backlight;
413
414 struct intel_vbt_panel_data vbt;
415 };
416
417 struct intel_digital_port;
418
419 enum check_link_response {
420 HDCP_LINK_PROTECTED = 0,
421 HDCP_TOPOLOGY_CHANGE,
422 HDCP_LINK_INTEGRITY_FAILURE,
423 HDCP_REAUTH_REQUEST
424 };
425
426 /*
427 * This structure serves as a translation layer between the generic HDCP code
428 * and the bus-specific code. What that means is that HDCP over HDMI differs
429 * from HDCP over DP, so to account for these differences, we need to
430 * communicate with the receiver through this shim.
431 *
432 * For completeness, the 2 buses differ in the following ways:
433 * - DP AUX vs. DDC
434 * HDCP registers on the receiver are set via DP AUX for DP, and
435 * they are set via DDC for HDMI.
436 * - Receiver register offsets
437 * The offsets of the registers are different for DP vs. HDMI
438 * - Receiver register masks/offsets
439 * For instance, the ready bit for the KSV fifo is in a different
440 * place on DP vs HDMI
441 * - Receiver register names
442 * Seriously. In the DP spec, the 16-bit register containing
443 * downstream information is called BINFO, on HDMI it's called
444 * BSTATUS. To confuse matters further, DP has a BSTATUS register
445 * with a completely different definition.
446 * - KSV FIFO
447 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
448 * be read 3 keys at a time
449 * - Aksv output
450 * Since Aksv is hidden in hardware, there's different procedures
451 * to send it over DP AUX vs DDC
452 */
453 struct intel_hdcp_shim {
454 /* Outputs the transmitter's An and Aksv values to the receiver. */
455 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
456
457 /* Reads the receiver's key selection vector */
458 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
459
460 /*
461 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
462 * definitions are the same in the respective specs, but the names are
463 * different. Call it BSTATUS since that's the name the HDMI spec
464 * uses and it was there first.
465 */
466 int (*read_bstatus)(struct intel_digital_port *dig_port,
467 u8 *bstatus);
468
469 /* Determines whether a repeater is present downstream */
470 int (*repeater_present)(struct intel_digital_port *dig_port,
471 bool *repeater_present);
472
473 /* Reads the receiver's Ri' value */
474 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
475
476 /* Determines if the receiver's KSV FIFO is ready for consumption */
477 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
478 bool *ksv_ready);
479
480 /* Reads the ksv fifo for num_downstream devices */
481 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
482 int num_downstream, u8 *ksv_fifo);
483
484 /* Reads a 32-bit part of V' from the receiver */
485 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
486 int i, u32 *part);
487
488 /* Enables HDCP signalling on the port */
489 int (*toggle_signalling)(struct intel_digital_port *dig_port,
490 enum transcoder cpu_transcoder,
491 bool enable);
492
493 /* Enable/Disable stream encryption on DP MST Transport Link */
494 int (*stream_encryption)(struct intel_connector *connector,
495 bool enable);
496
497 /* Ensures the link is still protected */
498 bool (*check_link)(struct intel_digital_port *dig_port,
499 struct intel_connector *connector);
500
501 /* Detects panel's hdcp capability. This is optional for HDMI. */
502 int (*hdcp_get_capability)(struct intel_digital_port *dig_port,
503 bool *hdcp_capable);
504
505 /* HDCP adaptation(DP/HDMI) required on the port */
506 enum hdcp_wired_protocol protocol;
507
508 /* Detects whether sink is HDCP2.2 capable */
509 int (*hdcp_2_2_get_capability)(struct intel_connector *connector,
510 bool *capable);
511
512 /* Write HDCP2.2 messages */
513 int (*write_2_2_msg)(struct intel_connector *connector,
514 void *buf, size_t size);
515
516 /* Read HDCP2.2 messages */
517 int (*read_2_2_msg)(struct intel_connector *connector,
518 u8 msg_id, void *buf, size_t size);
519
520 /*
521 * Implementation of DP HDCP2.2 Errata for the communication of stream
522 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
523 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
524 */
525 int (*config_stream_type)(struct intel_connector *connector,
526 bool is_repeater, u8 type);
527
528 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
529 int (*stream_2_2_encryption)(struct intel_connector *connector,
530 bool enable);
531
532 /* HDCP2.2 Link Integrity Check */
533 int (*check_2_2_link)(struct intel_digital_port *dig_port,
534 struct intel_connector *connector);
535
536 /* HDCP remote sink cap */
537 int (*get_remote_hdcp_capability)(struct intel_connector *connector,
538 bool *hdcp_capable, bool *hdcp2_capable);
539 };
540
541 struct intel_hdcp {
542 const struct intel_hdcp_shim *shim;
543 /* Mutex for hdcp state of the connector */
544 struct mutex mutex;
545 u64 value;
546 struct delayed_work check_work;
547 struct work_struct prop_work;
548
549 /* HDCP1.4 Encryption status */
550 bool hdcp_encrypted;
551
552 /* HDCP2.2 related definitions */
553 /* Flag indicates whether this connector supports HDCP2.2 or not. */
554 bool hdcp2_supported;
555
556 /* HDCP2.2 Encryption status */
557 bool hdcp2_encrypted;
558
559 /*
560 * Content Stream Type defined by content owner. TYPE0(0x0) content can
561 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
562 * content can flow only through a link protected by HDCP2.2.
563 */
564 u8 content_type;
565
566 bool is_paired;
567 bool is_repeater;
568
569 /*
570 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
571 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
572 * When it rolls over re-auth has to be triggered.
573 */
574 u32 seq_num_v;
575
576 /*
577 * Count of RepeaterAuth_Stream_Manage msg propagated.
578 * Initialized to 0 on AKE_INIT. Incremented after every successful
579 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
580 * over re-Auth has to be triggered.
581 */
582 u32 seq_num_m;
583
584 /*
585 * Work queue to signal the CP_IRQ. Used for the waiters to read the
586 * available information from HDCP DP sink.
587 */
588 wait_queue_head_t cp_irq_queue;
589 atomic_t cp_irq_count;
590 int cp_irq_count_cached;
591
592 /*
593 * HDCP register access for gen12+ need the transcoder associated.
594 * Transcoder attached to the connector could be changed at modeset.
595 * Hence caching the transcoder here.
596 */
597 enum transcoder cpu_transcoder;
598 /* Only used for DP MST stream encryption */
599 enum transcoder stream_transcoder;
600 };
601
602 struct intel_connector {
603 struct drm_connector base;
604 /*
605 * The fixed encoder this connector is connected to.
606 */
607 struct intel_encoder *encoder;
608
609 /* ACPI device id for ACPI and driver cooperation */
610 u32 acpi_device_id;
611
612 /* Reads out the current hw, returning true if the connector is enabled
613 * and active (i.e. dpms ON state). */
614 bool (*get_hw_state)(struct intel_connector *);
615
616 /*
617 * Optional hook called during init/resume to sync any state
618 * stored in the connector (eg. DSC state) wrt. the HW state.
619 */
620 void (*sync_state)(struct intel_connector *connector,
621 const struct intel_crtc_state *crtc_state);
622
623 /* Panel info for eDP and LVDS */
624 struct intel_panel panel;
625
626 /* Cached EDID for detect. */
627 const struct drm_edid *detect_edid;
628
629 /* Number of times hotplug detection was tried after an HPD interrupt */
630 int hotplug_retries;
631
632 /* since POLL and HPD connectors may use the same HPD line keep the native
633 state of connector->polled in case hotplug storm detection changes it */
634 u8 polled;
635
636 struct drm_dp_mst_port *port;
637
638 struct intel_dp *mst_port;
639
640 bool force_bigjoiner_enable;
641
642 struct {
643 struct drm_dp_aux *dsc_decompression_aux;
644 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
645 u8 fec_capability;
646
647 u8 dsc_hblank_expansion_quirk:1;
648 u8 dsc_decompression_enabled:1;
649 } dp;
650
651 /* Work struct to schedule a uevent on link train failure */
652 struct work_struct modeset_retry_work;
653
654 struct intel_hdcp hdcp;
655 };
656
657 struct intel_digital_connector_state {
658 struct drm_connector_state base;
659
660 enum hdmi_force_audio force_audio;
661 int broadcast_rgb;
662 };
663
664 #define to_intel_digital_connector_state(conn_state) \
665 container_of_const((conn_state), struct intel_digital_connector_state, base)
666
667 struct dpll {
668 /* given values */
669 int n;
670 int m1, m2;
671 int p1, p2;
672 /* derived values */
673 int dot;
674 int vco;
675 int m;
676 int p;
677 };
678
679 struct intel_atomic_state {
680 struct drm_atomic_state base;
681
682 intel_wakeref_t wakeref;
683
684 struct __intel_global_objs_state *global_objs;
685 int num_global_objs;
686
687 /* Internal commit, as opposed to userspace/client initiated one */
688 bool internal;
689
690 bool dpll_set, modeset;
691
692 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
693
694 struct intel_dp_tunnel_inherited_state *inherited_dp_tunnels;
695
696 /*
697 * Current watermarks can't be trusted during hardware readout, so
698 * don't bother calculating intermediate watermarks.
699 */
700 bool skip_intermediate_wm;
701
702 bool rps_interactive;
703 };
704
705 struct intel_plane_state {
706 struct drm_plane_state uapi;
707
708 /*
709 * actual hardware state, the state we program to the hardware.
710 * The following members are used to verify the hardware state:
711 * During initial hw readout, they need to be copied from uapi.
712 */
713 struct {
714 struct drm_crtc *crtc;
715 struct drm_framebuffer *fb;
716
717 u16 alpha;
718 u16 pixel_blend_mode;
719 unsigned int rotation;
720 enum drm_color_encoding color_encoding;
721 enum drm_color_range color_range;
722 enum drm_scaling_filter scaling_filter;
723 } hw;
724
725 struct i915_vma *ggtt_vma;
726 struct i915_vma *dpt_vma;
727 unsigned long flags;
728 #define PLANE_HAS_FENCE BIT(0)
729
730 struct intel_fb_view view;
731 u32 phys_dma_addr; /* for cursor_needs_physical */
732
733 /* Plane pxp decryption state */
734 bool decrypt;
735
736 /* Plane state to display black pixels when pxp is borked */
737 bool force_black;
738
739 /* plane control register */
740 u32 ctl;
741
742 /* plane color control register */
743 u32 color_ctl;
744
745 /* chroma upsampler control register */
746 u32 cus_ctl;
747
748 /*
749 * scaler_id
750 * = -1 : not using a scaler
751 * >= 0 : using a scalers
752 *
753 * plane requiring a scaler:
754 * - During check_plane, its bit is set in
755 * crtc_state->scaler_state.scaler_users by calling helper function
756 * update_scaler_plane.
757 * - scaler_id indicates the scaler it got assigned.
758 *
759 * plane doesn't require a scaler:
760 * - this can happen when scaling is no more required or plane simply
761 * got disabled.
762 * - During check_plane, corresponding bit is reset in
763 * crtc_state->scaler_state.scaler_users by calling helper function
764 * update_scaler_plane.
765 */
766 int scaler_id;
767
768 /*
769 * planar_linked_plane:
770 *
771 * ICL planar formats require 2 planes that are updated as pairs.
772 * This member is used to make sure the other plane is also updated
773 * when required, and for update_slave() to find the correct
774 * plane_state to pass as argument.
775 */
776 struct intel_plane *planar_linked_plane;
777
778 /*
779 * planar_slave:
780 * If set don't update use the linked plane's state for updating
781 * this plane during atomic commit with the update_slave() callback.
782 *
783 * It's also used by the watermark code to ignore wm calculations on
784 * this plane. They're calculated by the linked plane's wm code.
785 */
786 u32 planar_slave;
787
788 struct drm_intel_sprite_colorkey ckey;
789
790 struct drm_rect psr2_sel_fetch_area;
791
792 /* Clear Color Value */
793 u64 ccval;
794
795 const char *no_fbc_reason;
796 };
797
798 struct intel_initial_plane_config {
799 struct intel_framebuffer *fb;
800 struct intel_memory_region *mem;
801 resource_size_t phys_base;
802 struct i915_vma *vma;
803 unsigned int tiling;
804 int size;
805 u32 base;
806 u8 rotation;
807 };
808
809 struct intel_scaler {
810 int in_use;
811 u32 mode;
812 };
813
814 struct intel_crtc_scaler_state {
815 #define SKL_NUM_SCALERS 2
816 struct intel_scaler scalers[SKL_NUM_SCALERS];
817
818 /*
819 * scaler_users: keeps track of users requesting scalers on this crtc.
820 *
821 * If a bit is set, a user is using a scaler.
822 * Here user can be a plane or crtc as defined below:
823 * bits 0-30 - plane (bit position is index from drm_plane_index)
824 * bit 31 - crtc
825 *
826 * Instead of creating a new index to cover planes and crtc, using
827 * existing drm_plane_index for planes which is well less than 31
828 * planes and bit 31 for crtc. This should be fine to cover all
829 * our platforms.
830 *
831 * intel_atomic_setup_scalers will setup available scalers to users
832 * requesting scalers. It will gracefully fail if request exceeds
833 * avilability.
834 */
835 #define SKL_CRTC_INDEX 31
836 unsigned scaler_users;
837
838 /* scaler used by crtc for panel fitting purpose */
839 int scaler_id;
840 };
841
842 /* {crtc,crtc_state}->mode_flags */
843 /* Flag to get scanline using frame time stamps */
844 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
845 /* Flag to use the scanline counter instead of the pixel counter */
846 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
847 /*
848 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
849 * is operating in command mode.
850 * Flag to use TE from DSI0 instead of VBI in command mode
851 */
852 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
853 /* Flag to use TE from DSI1 instead of VBI in command mode */
854 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
855 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
856 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
857 /* Do tricks to make vblank timestamps sane with VRR? */
858 #define I915_MODE_FLAG_VRR (1<<6)
859
860 struct intel_wm_level {
861 bool enable;
862 u32 pri_val;
863 u32 spr_val;
864 u32 cur_val;
865 u32 fbc_val;
866 };
867
868 struct intel_pipe_wm {
869 struct intel_wm_level wm[5];
870 bool fbc_wm_enabled;
871 bool pipe_enabled;
872 bool sprites_enabled;
873 bool sprites_scaled;
874 };
875
876 struct skl_wm_level {
877 u16 min_ddb_alloc;
878 u16 blocks;
879 u8 lines;
880 bool enable;
881 bool ignore_lines;
882 bool can_sagv;
883 };
884
885 struct skl_plane_wm {
886 struct skl_wm_level wm[8];
887 struct skl_wm_level uv_wm[8];
888 struct skl_wm_level trans_wm;
889 struct {
890 struct skl_wm_level wm0;
891 struct skl_wm_level trans_wm;
892 } sagv;
893 bool is_planar;
894 };
895
896 struct skl_pipe_wm {
897 struct skl_plane_wm planes[I915_MAX_PLANES];
898 bool use_sagv_wm;
899 };
900
901 enum vlv_wm_level {
902 VLV_WM_LEVEL_PM2,
903 VLV_WM_LEVEL_PM5,
904 VLV_WM_LEVEL_DDR_DVFS,
905 NUM_VLV_WM_LEVELS,
906 };
907
908 struct vlv_wm_state {
909 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
910 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
911 u8 num_levels;
912 bool cxsr;
913 };
914
915 struct vlv_fifo_state {
916 u16 plane[I915_MAX_PLANES];
917 };
918
919 enum g4x_wm_level {
920 G4X_WM_LEVEL_NORMAL,
921 G4X_WM_LEVEL_SR,
922 G4X_WM_LEVEL_HPLL,
923 NUM_G4X_WM_LEVELS,
924 };
925
926 struct g4x_wm_state {
927 struct g4x_pipe_wm wm;
928 struct g4x_sr_wm sr;
929 struct g4x_sr_wm hpll;
930 bool cxsr;
931 bool hpll_en;
932 bool fbc_en;
933 };
934
935 struct intel_crtc_wm_state {
936 union {
937 /*
938 * raw:
939 * The "raw" watermark values produced by the formula
940 * given the plane's current state. They do not consider
941 * how much FIFO is actually allocated for each plane.
942 *
943 * optimal:
944 * The "optimal" watermark values given the current
945 * state of the planes and the amount of FIFO
946 * allocated to each, ignoring any previous state
947 * of the planes.
948 *
949 * intermediate:
950 * The "intermediate" watermark values when transitioning
951 * between the old and new "optimal" values. Used when
952 * the watermark registers are single buffered and hence
953 * their state changes asynchronously with regards to the
954 * actual plane registers. These are essentially the
955 * worst case combination of the old and new "optimal"
956 * watermarks, which are therefore safe to use when the
957 * plane is in either its old or new state.
958 */
959 struct {
960 struct intel_pipe_wm intermediate;
961 struct intel_pipe_wm optimal;
962 } ilk;
963
964 struct {
965 struct skl_pipe_wm raw;
966 /* gen9+ only needs 1-step wm programming */
967 struct skl_pipe_wm optimal;
968 struct skl_ddb_entry ddb;
969 /*
970 * pre-icl: for packed/planar CbCr
971 * icl+: for everything
972 */
973 struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
974 /* pre-icl: for planar Y */
975 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
976 } skl;
977
978 struct {
979 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
980 struct vlv_wm_state intermediate; /* inverted */
981 struct vlv_wm_state optimal; /* inverted */
982 struct vlv_fifo_state fifo_state;
983 } vlv;
984
985 struct {
986 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
987 struct g4x_wm_state intermediate;
988 struct g4x_wm_state optimal;
989 } g4x;
990 };
991
992 /*
993 * Platforms with two-step watermark programming will need to
994 * update watermark programming post-vblank to switch from the
995 * safe intermediate watermarks to the optimal final
996 * watermarks.
997 */
998 bool need_postvbl_update;
999 };
1000
1001 enum intel_output_format {
1002 INTEL_OUTPUT_FORMAT_RGB,
1003 INTEL_OUTPUT_FORMAT_YCBCR420,
1004 INTEL_OUTPUT_FORMAT_YCBCR444,
1005 };
1006
1007 /* Used by dp and fdi links */
1008 struct intel_link_m_n {
1009 u32 tu;
1010 u32 data_m;
1011 u32 data_n;
1012 u32 link_m;
1013 u32 link_n;
1014 };
1015
1016 struct intel_csc_matrix {
1017 u16 coeff[9];
1018 u16 preoff[3];
1019 u16 postoff[3];
1020 };
1021
1022 struct intel_crtc_state {
1023 /*
1024 * uapi (drm) state. This is the software state shown to userspace.
1025 * In particular, the following members are used for bookkeeping:
1026 * - crtc
1027 * - state
1028 * - *_changed
1029 * - event
1030 * - commit
1031 * - mode_blob
1032 */
1033 struct drm_crtc_state uapi;
1034
1035 /*
1036 * actual hardware state, the state we program to the hardware.
1037 * The following members are used to verify the hardware state:
1038 * - enable
1039 * - active
1040 * - mode / pipe_mode / adjusted_mode
1041 * - color property blobs.
1042 *
1043 * During initial hw readout, they need to be copied to uapi.
1044 *
1045 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
1046 * Use the pipe_mode for calculations like watermarks, pipe
1047 * scaler, and bandwidth.
1048 *
1049 * Use adjusted_mode for things that need to know the full
1050 * mode on the transcoder, which spans all pipes.
1051 */
1052 struct {
1053 bool active, enable;
1054 /* logical state of LUTs */
1055 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
1056 struct drm_display_mode mode, pipe_mode, adjusted_mode;
1057 enum drm_scaling_filter scaling_filter;
1058 } hw;
1059
1060 /* actual state of LUTs */
1061 struct drm_property_blob *pre_csc_lut, *post_csc_lut;
1062
1063 struct intel_csc_matrix csc, output_csc;
1064
1065 /**
1066 * quirks - bitfield with hw state readout quirks
1067 *
1068 * For various reasons the hw state readout code might not be able to
1069 * completely faithfully read out the current state. These cases are
1070 * tracked with quirk flags so that fastboot and state checker can act
1071 * accordingly.
1072 */
1073 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
1074 unsigned long quirks;
1075
1076 unsigned fb_bits; /* framebuffers to flip */
1077 bool update_pipe; /* can a fast modeset be performed? */
1078 bool update_m_n; /* update M/N seamlessly during fastset? */
1079 bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
1080 bool disable_cxsr;
1081 bool update_wm_pre, update_wm_post; /* watermarks are updated */
1082 bool fifo_changed; /* FIFO split is changed */
1083 bool preload_luts;
1084 bool inherited; /* state inherited from BIOS? */
1085
1086 /* Ask the hardware to actually async flip? */
1087 bool do_async_flip;
1088
1089 /* Pipe source size (ie. panel fitter input size)
1090 * All planes will be positioned inside this space,
1091 * and get clipped at the edges. */
1092 struct drm_rect pipe_src;
1093
1094 /*
1095 * Pipe pixel rate, adjusted for
1096 * panel fitter/pipe scaler downscaling.
1097 */
1098 unsigned int pixel_rate;
1099
1100 /* Whether to set up the PCH/FDI. Note that we never allow sharing
1101 * between pch encoders and cpu encoders. */
1102 bool has_pch_encoder;
1103
1104 /* Are we sending infoframes on the attached port */
1105 bool has_infoframe;
1106
1107 /* CPU Transcoder for the pipe. Currently this can only differ from the
1108 * pipe on Haswell and later (where we have a special eDP transcoder)
1109 * and Broxton (where we have special DSI transcoders). */
1110 enum transcoder cpu_transcoder;
1111
1112 /*
1113 * Use reduced/limited/broadcast rbg range, compressing from the full
1114 * range fed into the crtcs.
1115 */
1116 bool limited_color_range;
1117
1118 /* Bitmask of encoder types (enum intel_output_type)
1119 * driven by the pipe.
1120 */
1121 unsigned int output_types;
1122
1123 /* Whether we should send NULL infoframes. Required for audio. */
1124 bool has_hdmi_sink;
1125
1126 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
1127 * has_dp_encoder is set. */
1128 bool has_audio;
1129
1130 /*
1131 * Enable dithering, used when the selected pipe bpp doesn't match the
1132 * plane bpp.
1133 */
1134 bool dither;
1135
1136 /*
1137 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
1138 * compliance video pattern tests.
1139 * Disable dither only if it is a compliance test request for
1140 * 18bpp.
1141 */
1142 bool dither_force_disable;
1143
1144 /* Controls for the clock computation, to override various stages. */
1145 bool clock_set;
1146
1147 /* SDVO TV has a bunch of special case. To make multifunction encoders
1148 * work correctly, we need to track this at runtime.*/
1149 bool sdvo_tv_clock;
1150
1151 /*
1152 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
1153 * required. This is set in the 2nd loop of calling encoder's
1154 * ->compute_config if the first pick doesn't work out.
1155 */
1156 bool bw_constrained;
1157
1158 /* Settings for the intel dpll used on pretty much everything but
1159 * haswell. */
1160 struct dpll dpll;
1161
1162 /* Selected dpll when shared or NULL. */
1163 struct intel_shared_dpll *shared_dpll;
1164
1165 /* Actual register state of the dpll, for shared dpll cross-checking. */
1166 struct intel_dpll_hw_state dpll_hw_state;
1167
1168 /*
1169 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
1170 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
1171 */
1172 struct icl_port_dpll {
1173 struct intel_shared_dpll *pll;
1174 struct intel_dpll_hw_state hw_state;
1175 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
1176
1177 /* DSI PLL registers */
1178 struct {
1179 u32 ctrl, div;
1180 } dsi_pll;
1181
1182 int max_link_bpp_x16; /* in 1/16 bpp units */
1183 int pipe_bpp; /* in 1 bpp units */
1184 struct intel_link_m_n dp_m_n;
1185
1186 /* m2_n2 for eDP downclock */
1187 struct intel_link_m_n dp_m2_n2;
1188 bool has_drrs;
1189
1190 /* PSR is supported but might not be enabled due the lack of enabled planes */
1191 bool has_psr;
1192 bool has_psr2;
1193 bool enable_psr2_sel_fetch;
1194 bool enable_psr2_su_region_et;
1195 bool req_psr2_sdp_prior_scanline;
1196 bool has_panel_replay;
1197 bool wm_level_disabled;
1198 u32 dc3co_exitline;
1199 u16 su_y_granularity;
1200
1201 /*
1202 * Frequence the dpll for the port should run at. Differs from the
1203 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
1204 * already multiplied by pixel_multiplier.
1205 */
1206 int port_clock;
1207
1208 /* Used by SDVO (and if we ever fix it, HDMI). */
1209 unsigned pixel_multiplier;
1210
1211 /* I915_MODE_FLAG_* */
1212 u8 mode_flags;
1213
1214 u8 lane_count;
1215
1216 /*
1217 * Used by platforms having DP/HDMI PHY with programmable lane
1218 * latency optimization.
1219 */
1220 u8 lane_lat_optim_mask;
1221
1222 /* minimum acceptable voltage level */
1223 u8 min_voltage_level;
1224
1225 /* Panel fitter controls for gen2-gen4 + VLV */
1226 struct {
1227 u32 control;
1228 u32 pgm_ratios;
1229 u32 lvds_border_bits;
1230 } gmch_pfit;
1231
1232 /* Panel fitter placement and size for Ironlake+ */
1233 struct {
1234 struct drm_rect dst;
1235 bool enabled;
1236 bool force_thru;
1237 } pch_pfit;
1238
1239 /* FDI configuration, only valid if has_pch_encoder is set. */
1240 int fdi_lanes;
1241 struct intel_link_m_n fdi_m_n;
1242
1243 bool ips_enabled;
1244
1245 bool crc_enabled;
1246
1247 bool double_wide;
1248
1249 int pbn;
1250
1251 struct intel_crtc_scaler_state scaler_state;
1252
1253 /* w/a for waiting 2 vblanks during crtc enable */
1254 enum pipe hsw_workaround_pipe;
1255
1256 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1257 bool disable_lp_wm;
1258
1259 struct intel_crtc_wm_state wm;
1260
1261 int min_cdclk[I915_MAX_PLANES];
1262
1263 /* for packed/planar CbCr */
1264 u32 data_rate[I915_MAX_PLANES];
1265 /* for planar Y */
1266 u32 data_rate_y[I915_MAX_PLANES];
1267
1268 /* FIXME unify with data_rate[]? */
1269 u64 rel_data_rate[I915_MAX_PLANES];
1270 u64 rel_data_rate_y[I915_MAX_PLANES];
1271
1272 /* Gamma mode programmed on the pipe */
1273 u32 gamma_mode;
1274
1275 union {
1276 /* CSC mode programmed on the pipe */
1277 u32 csc_mode;
1278
1279 /* CHV CGM mode */
1280 u32 cgm_mode;
1281 };
1282
1283 /* bitmask of logically enabled planes (enum plane_id) */
1284 u8 enabled_planes;
1285
1286 /* bitmask of actually visible planes (enum plane_id) */
1287 u8 active_planes;
1288 u8 scaled_planes;
1289 u8 nv12_planes;
1290 u8 c8_planes;
1291
1292 /* bitmask of planes that will be updated during the commit */
1293 u8 update_planes;
1294
1295 /* bitmask of planes with async flip active */
1296 u8 async_flip_planes;
1297
1298 u8 framestart_delay; /* 1-4 */
1299 u8 msa_timing_delay; /* 0-3 */
1300
1301 struct {
1302 u32 enable;
1303 u32 gcp;
1304 union hdmi_infoframe avi;
1305 union hdmi_infoframe spd;
1306 union hdmi_infoframe hdmi;
1307 union hdmi_infoframe drm;
1308 struct drm_dp_vsc_sdp vsc;
1309 struct drm_dp_as_sdp as_sdp;
1310 } infoframes;
1311
1312 u8 eld[MAX_ELD_BYTES];
1313
1314 /* HDMI scrambling status */
1315 bool hdmi_scrambling;
1316
1317 /* HDMI High TMDS char rate ratio */
1318 bool hdmi_high_tmds_clock_ratio;
1319
1320 /*
1321 * Output format RGB/YCBCR etc., that is coming out
1322 * at the end of the pipe.
1323 */
1324 enum intel_output_format output_format;
1325
1326 /*
1327 * Sink output format RGB/YCBCR etc., that is going
1328 * into the sink.
1329 */
1330 enum intel_output_format sink_format;
1331
1332 /* enable pipe gamma? */
1333 bool gamma_enable;
1334
1335 /* enable pipe csc? */
1336 bool csc_enable;
1337
1338 /* enable vlv/chv wgc csc? */
1339 bool wgc_enable;
1340
1341 /* big joiner pipe bitmask */
1342 u8 bigjoiner_pipes;
1343
1344 /* Display Stream compression state */
1345 struct {
1346 bool compression_enable;
1347 bool dsc_split;
1348 /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
1349 u16 compressed_bpp_x16;
1350 u8 slice_count;
1351 struct drm_dsc_config config;
1352 } dsc;
1353
1354 /* DP tunnel used for BW allocation. */
1355 struct drm_dp_tunnel_ref dp_tunnel_ref;
1356
1357 /* HSW+ linetime watermarks */
1358 u16 linetime;
1359 u16 ips_linetime;
1360
1361 bool enhanced_framing;
1362
1363 /*
1364 * Forward Error Correction.
1365 *
1366 * Note: This will be false for 128b/132b, which will always have FEC
1367 * enabled automatically.
1368 */
1369 bool fec_enable;
1370
1371 bool sdp_split_enable;
1372
1373 /* Pointer to master transcoder in case of tiled displays */
1374 enum transcoder master_transcoder;
1375
1376 /* Bitmask to indicate slaves attached */
1377 u8 sync_mode_slaves_mask;
1378
1379 /* Only valid on TGL+ */
1380 enum transcoder mst_master_transcoder;
1381
1382 /* For DSB related info */
1383 struct intel_dsb *dsb;
1384
1385 u32 psr2_man_track_ctl;
1386
1387 u32 pipe_srcsz_early_tpt;
1388
1389 struct drm_rect psr2_su_area;
1390
1391 /* Variable Refresh Rate state */
1392 struct {
1393 bool enable, in_range;
1394 u8 pipeline_full;
1395 u16 flipline, vmin, vmax, guardband;
1396 u32 vsync_end, vsync_start;
1397 } vrr;
1398
1399 /* Stream Splitter for eDP MSO */
1400 struct {
1401 bool enable;
1402 u8 link_count;
1403 u8 pixel_overlap;
1404 } splitter;
1405
1406 /* for loading single buffered registers during vblank */
1407 struct drm_vblank_work vblank_work;
1408 };
1409
1410 enum intel_pipe_crc_source {
1411 INTEL_PIPE_CRC_SOURCE_NONE,
1412 INTEL_PIPE_CRC_SOURCE_PLANE1,
1413 INTEL_PIPE_CRC_SOURCE_PLANE2,
1414 INTEL_PIPE_CRC_SOURCE_PLANE3,
1415 INTEL_PIPE_CRC_SOURCE_PLANE4,
1416 INTEL_PIPE_CRC_SOURCE_PLANE5,
1417 INTEL_PIPE_CRC_SOURCE_PLANE6,
1418 INTEL_PIPE_CRC_SOURCE_PLANE7,
1419 INTEL_PIPE_CRC_SOURCE_PIPE,
1420 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1421 INTEL_PIPE_CRC_SOURCE_TV,
1422 INTEL_PIPE_CRC_SOURCE_DP_B,
1423 INTEL_PIPE_CRC_SOURCE_DP_C,
1424 INTEL_PIPE_CRC_SOURCE_DP_D,
1425 INTEL_PIPE_CRC_SOURCE_AUTO,
1426 INTEL_PIPE_CRC_SOURCE_MAX,
1427 };
1428
1429 enum drrs_refresh_rate {
1430 DRRS_REFRESH_RATE_HIGH,
1431 DRRS_REFRESH_RATE_LOW,
1432 };
1433
1434 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1435 struct intel_pipe_crc {
1436 spinlock_t lock;
1437 int skipped;
1438 enum intel_pipe_crc_source source;
1439 };
1440
1441 struct intel_crtc {
1442 struct drm_crtc base;
1443 enum pipe pipe;
1444 /*
1445 * Whether the crtc and the connected output pipeline is active. Implies
1446 * that crtc->enabled is set, i.e. the current mode configuration has
1447 * some outputs connected to this crtc.
1448 */
1449 bool active;
1450 u8 plane_ids_mask;
1451
1452 /* I915_MODE_FLAG_* */
1453 u8 mode_flags;
1454
1455 u16 vmax_vblank_start;
1456
1457 struct intel_display_power_domain_set enabled_power_domains;
1458 struct intel_display_power_domain_set hw_readout_power_domains;
1459 struct intel_overlay *overlay;
1460
1461 struct intel_crtc_state *config;
1462
1463 /* armed event for async flip */
1464 struct drm_pending_vblank_event *flip_done_event;
1465
1466 /* Access to these should be protected by dev_priv->irq_lock. */
1467 bool cpu_fifo_underrun_disabled;
1468 bool pch_fifo_underrun_disabled;
1469
1470 /* per-pipe watermark state */
1471 struct {
1472 /* watermarks currently being used */
1473 union {
1474 struct intel_pipe_wm ilk;
1475 struct vlv_wm_state vlv;
1476 struct g4x_wm_state g4x;
1477 } active;
1478 } wm;
1479
1480 struct {
1481 struct mutex mutex;
1482 struct delayed_work work;
1483 enum drrs_refresh_rate refresh_rate;
1484 unsigned int frontbuffer_bits;
1485 unsigned int busy_frontbuffer_bits;
1486 enum transcoder cpu_transcoder;
1487 struct intel_link_m_n m_n, m2_n2;
1488 } drrs;
1489
1490 int scanline_offset;
1491
1492 struct {
1493 unsigned start_vbl_count;
1494 ktime_t start_vbl_time;
1495 int min_vbl, max_vbl;
1496 int scanline_start;
1497 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1498 struct {
1499 u64 min;
1500 u64 max;
1501 u64 sum;
1502 unsigned int over;
1503 unsigned int times[17]; /* [1us, 16ms] */
1504 } vbl;
1505 #endif
1506 } debug;
1507
1508 /* scalers available on this crtc */
1509 int num_scalers;
1510
1511 /* for loading single buffered registers during vblank */
1512 struct pm_qos_request vblank_pm_qos;
1513
1514 #ifdef CONFIG_DEBUG_FS
1515 struct intel_pipe_crc pipe_crc;
1516 #endif
1517 };
1518
1519 struct intel_plane {
1520 struct drm_plane base;
1521 enum i9xx_plane_id i9xx_plane;
1522 enum plane_id id;
1523 enum pipe pipe;
1524 bool need_async_flip_disable_wa;
1525 u32 frontbuffer_bit;
1526
1527 struct {
1528 u32 base, cntl, size;
1529 } cursor;
1530
1531 struct intel_fbc *fbc;
1532
1533 /*
1534 * NOTE: Do not place new plane state fields here (e.g., when adding
1535 * new plane properties). New runtime state should now be placed in
1536 * the intel_plane_state structure and accessed via plane_state.
1537 */
1538
1539 int (*min_width)(const struct drm_framebuffer *fb,
1540 int color_plane,
1541 unsigned int rotation);
1542 int (*max_width)(const struct drm_framebuffer *fb,
1543 int color_plane,
1544 unsigned int rotation);
1545 int (*max_height)(const struct drm_framebuffer *fb,
1546 int color_plane,
1547 unsigned int rotation);
1548 unsigned int (*max_stride)(struct intel_plane *plane,
1549 u32 pixel_format, u64 modifier,
1550 unsigned int rotation);
1551 /* Write all non-self arming plane registers */
1552 void (*update_noarm)(struct intel_plane *plane,
1553 const struct intel_crtc_state *crtc_state,
1554 const struct intel_plane_state *plane_state);
1555 /* Write all self-arming plane registers */
1556 void (*update_arm)(struct intel_plane *plane,
1557 const struct intel_crtc_state *crtc_state,
1558 const struct intel_plane_state *plane_state);
1559 /* Disable the plane, must arm */
1560 void (*disable_arm)(struct intel_plane *plane,
1561 const struct intel_crtc_state *crtc_state);
1562 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1563 int (*check_plane)(struct intel_crtc_state *crtc_state,
1564 struct intel_plane_state *plane_state);
1565 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1566 const struct intel_plane_state *plane_state);
1567 void (*async_flip)(struct intel_plane *plane,
1568 const struct intel_crtc_state *crtc_state,
1569 const struct intel_plane_state *plane_state,
1570 bool async_flip);
1571 void (*enable_flip_done)(struct intel_plane *plane);
1572 void (*disable_flip_done)(struct intel_plane *plane);
1573 };
1574
1575 struct intel_watermark_params {
1576 u16 fifo_size;
1577 u16 max_wm;
1578 u8 default_wm;
1579 u8 guard_size;
1580 u8 cacheline_size;
1581 };
1582
1583 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1584 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1585 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1586 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1587 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1588
1589 #define to_intel_crtc_state(crtc_state) \
1590 container_of_const((crtc_state), struct intel_crtc_state, uapi)
1591 #define to_intel_plane_state(plane_state) \
1592 container_of_const((plane_state), struct intel_plane_state, uapi)
1593 #define to_intel_framebuffer(fb) \
1594 container_of_const((fb), struct intel_framebuffer, base)
1595
1596 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1597
1598 struct intel_hdmi {
1599 i915_reg_t hdmi_reg;
1600 struct {
1601 enum drm_dp_dual_mode_type type;
1602 int max_tmds_clock;
1603 } dp_dual_mode;
1604 struct intel_connector *attached_connector;
1605 struct cec_notifier *cec_notifier;
1606 };
1607
1608 struct intel_dp_mst_encoder;
1609
1610 struct intel_dp_compliance_data {
1611 unsigned long edid;
1612 u8 video_pattern;
1613 u16 hdisplay, vdisplay;
1614 u8 bpc;
1615 struct drm_dp_phy_test_params phytest;
1616 };
1617
1618 struct intel_dp_compliance {
1619 unsigned long test_type;
1620 struct intel_dp_compliance_data test_data;
1621 bool test_active;
1622 int test_link_rate;
1623 u8 test_lane_count;
1624 };
1625
1626 struct intel_dp_pcon_frl {
1627 bool is_trained;
1628 int trained_rate_gbps;
1629 };
1630
1631 struct intel_pps {
1632 int panel_power_up_delay;
1633 int panel_power_down_delay;
1634 int panel_power_cycle_delay;
1635 int backlight_on_delay;
1636 int backlight_off_delay;
1637 struct delayed_work panel_vdd_work;
1638 bool want_panel_vdd;
1639 bool initializing;
1640 unsigned long last_power_on;
1641 unsigned long last_backlight_off;
1642 ktime_t panel_power_off_time;
1643 intel_wakeref_t vdd_wakeref;
1644
1645 union {
1646 /*
1647 * Pipe whose power sequencer is currently locked into
1648 * this port. Only relevant on VLV/CHV.
1649 */
1650 enum pipe pps_pipe;
1651
1652 /*
1653 * Power sequencer index. Only relevant on BXT+.
1654 */
1655 int pps_idx;
1656 };
1657
1658 /*
1659 * Pipe currently driving the port. Used for preventing
1660 * the use of the PPS for any pipe currentrly driving
1661 * external DP as that will mess things up on VLV.
1662 */
1663 enum pipe active_pipe;
1664 /*
1665 * Set if the sequencer may be reset due to a power transition,
1666 * requiring a reinitialization. Only relevant on BXT+.
1667 */
1668 bool pps_reset;
1669 struct edp_power_seq pps_delays;
1670 struct edp_power_seq bios_pps_delays;
1671 };
1672
1673 struct intel_psr {
1674 /* Mutex for PSR state of the transcoder */
1675 struct mutex lock;
1676
1677 #define I915_PSR_DEBUG_MODE_MASK 0x0f
1678 #define I915_PSR_DEBUG_DEFAULT 0x00
1679 #define I915_PSR_DEBUG_DISABLE 0x01
1680 #define I915_PSR_DEBUG_ENABLE 0x02
1681 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
1682 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
1683 #define I915_PSR_DEBUG_IRQ 0x10
1684 #define I915_PSR_DEBUG_SU_REGION_ET_DISABLE 0x20
1685
1686 u32 debug;
1687 bool sink_support;
1688 bool source_support;
1689 bool enabled;
1690 bool paused;
1691 enum pipe pipe;
1692 enum transcoder transcoder;
1693 bool active;
1694 struct work_struct work;
1695 unsigned int busy_frontbuffer_bits;
1696 bool sink_psr2_support;
1697 bool link_standby;
1698 bool psr2_enabled;
1699 bool psr2_sel_fetch_enabled;
1700 bool psr2_sel_fetch_cff_enabled;
1701 bool req_psr2_sdp_prior_scanline;
1702 u8 sink_sync_latency;
1703
1704 struct {
1705 u8 io_wake_lines;
1706 u8 fast_wake_lines;
1707
1708 /* LNL and beyond */
1709 u8 check_entry_lines;
1710 u8 silence_period_sym_clocks;
1711 u8 lfps_half_cycle_num_of_syms;
1712 } alpm_parameters;
1713
1714 ktime_t last_entry_attempt;
1715 ktime_t last_exit;
1716 bool sink_not_reliable;
1717 bool irq_aux_error;
1718 u16 su_w_granularity;
1719 u16 su_y_granularity;
1720 bool source_panel_replay_support;
1721 bool sink_panel_replay_support;
1722 bool panel_replay_enabled;
1723 u32 dc3co_exitline;
1724 u32 dc3co_exit_delay;
1725 struct delayed_work dc3co_work;
1726 u8 entry_setup_frames;
1727 };
1728
1729 struct intel_dp {
1730 i915_reg_t output_reg;
1731 u32 DP;
1732 int link_rate;
1733 u8 lane_count;
1734 u8 sink_count;
1735 bool link_trained;
1736 bool reset_link_params;
1737 bool use_max_params;
1738 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1739 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1740 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1741 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1742 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1743 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1744 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1745 /* source rates */
1746 int num_source_rates;
1747 const int *source_rates;
1748 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1749 int num_sink_rates;
1750 int sink_rates[DP_MAX_SUPPORTED_RATES];
1751 bool use_rate_select;
1752 /* Max sink lane count as reported by DP_MAX_LANE_COUNT */
1753 int max_sink_lane_count;
1754 /* intersection of source and sink rates */
1755 int num_common_rates;
1756 int common_rates[DP_MAX_SUPPORTED_RATES];
1757 /* Max lane count for the current link */
1758 int max_link_lane_count;
1759 /* Max rate for the current link */
1760 int max_link_rate;
1761 int mso_link_count;
1762 int mso_pixel_overlap;
1763 /* sink or branch descriptor */
1764 struct drm_dp_desc desc;
1765 struct drm_dp_aux aux;
1766 u32 aux_busy_last_status;
1767 u8 train_set[4];
1768
1769 struct intel_pps pps;
1770
1771 bool is_mst;
1772 int active_mst_links;
1773 enum drm_dp_mst_mode mst_detect;
1774
1775 /* connector directly attached - won't be use for modeset in mst world */
1776 struct intel_connector *attached_connector;
1777
1778 struct drm_dp_tunnel *tunnel;
1779 bool tunnel_suspended:1;
1780
1781 /* mst connector list */
1782 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1783 struct drm_dp_mst_topology_mgr mst_mgr;
1784
1785 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1786 /*
1787 * This function returns the value we have to program the AUX_CTL
1788 * register with to kick off an AUX transaction.
1789 */
1790 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1791 u32 aux_clock_divider);
1792
1793 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1794 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1795
1796 /* This is called before a link training is starterd */
1797 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1798 const struct intel_crtc_state *crtc_state);
1799 void (*set_link_train)(struct intel_dp *intel_dp,
1800 const struct intel_crtc_state *crtc_state,
1801 u8 dp_train_pat);
1802 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1803 const struct intel_crtc_state *crtc_state);
1804
1805 u8 (*preemph_max)(struct intel_dp *intel_dp);
1806 u8 (*voltage_max)(struct intel_dp *intel_dp,
1807 const struct intel_crtc_state *crtc_state);
1808
1809 /* Displayport compliance testing */
1810 struct intel_dp_compliance compliance;
1811
1812 /* Downstream facing port caps */
1813 struct {
1814 int min_tmds_clock, max_tmds_clock;
1815 int max_dotclock;
1816 int pcon_max_frl_bw;
1817 u8 max_bpc;
1818 bool ycbcr_444_to_420;
1819 bool ycbcr420_passthrough;
1820 bool rgb_to_ycbcr;
1821 } dfp;
1822
1823 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1824 struct pm_qos_request pm_qos;
1825
1826 /* Display stream compression testing */
1827 bool force_dsc_en;
1828 int force_dsc_output_format;
1829 bool force_dsc_fractional_bpp_en;
1830 int force_dsc_bpc;
1831
1832 bool hobl_failed;
1833 bool hobl_active;
1834
1835 struct intel_dp_pcon_frl frl;
1836
1837 struct intel_psr psr;
1838
1839 /* When we last wrote the OUI for eDP */
1840 unsigned long last_oui_write;
1841
1842 bool colorimetry_support;
1843 };
1844
1845 enum lspcon_vendor {
1846 LSPCON_VENDOR_MCA,
1847 LSPCON_VENDOR_PARADE
1848 };
1849
1850 struct intel_lspcon {
1851 bool active;
1852 bool hdr_supported;
1853 enum drm_lspcon_mode mode;
1854 enum lspcon_vendor vendor;
1855 };
1856
1857 struct intel_digital_port {
1858 struct intel_encoder base;
1859 u32 saved_port_bits;
1860 struct intel_dp dp;
1861 struct intel_hdmi hdmi;
1862 struct intel_lspcon lspcon;
1863 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1864 bool release_cl2_override;
1865 u8 max_lanes;
1866 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1867 enum aux_ch aux_ch;
1868 enum intel_display_power_domain ddi_io_power_domain;
1869 intel_wakeref_t ddi_io_wakeref;
1870 intel_wakeref_t aux_wakeref;
1871
1872 struct intel_tc_port *tc;
1873
1874 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */
1875 struct mutex hdcp_mutex;
1876 /* the number of pipes using HDCP signalling out of this port */
1877 unsigned int num_hdcp_streams;
1878 /* port HDCP auth status */
1879 bool hdcp_auth_status;
1880 /* HDCP port data need to pass to security f/w */
1881 struct hdcp_port_data hdcp_port_data;
1882 /* Whether the MST topology supports HDCP Type 1 Content */
1883 bool hdcp_mst_type1_capable;
1884
1885 void (*write_infoframe)(struct intel_encoder *encoder,
1886 const struct intel_crtc_state *crtc_state,
1887 unsigned int type,
1888 const void *frame, ssize_t len);
1889 void (*read_infoframe)(struct intel_encoder *encoder,
1890 const struct intel_crtc_state *crtc_state,
1891 unsigned int type,
1892 void *frame, ssize_t len);
1893 void (*set_infoframes)(struct intel_encoder *encoder,
1894 bool enable,
1895 const struct intel_crtc_state *crtc_state,
1896 const struct drm_connector_state *conn_state);
1897 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1898 const struct intel_crtc_state *pipe_config);
1899 bool (*connected)(struct intel_encoder *encoder);
1900
1901 void (*lock)(struct intel_digital_port *dig_port);
1902 void (*unlock)(struct intel_digital_port *dig_port);
1903 };
1904
1905 struct intel_dp_mst_encoder {
1906 struct intel_encoder base;
1907 enum pipe pipe;
1908 struct intel_digital_port *primary;
1909 struct intel_connector *connector;
1910 };
1911
1912 static inline struct intel_encoder *
intel_attached_encoder(struct intel_connector * connector)1913 intel_attached_encoder(struct intel_connector *connector)
1914 {
1915 return connector->encoder;
1916 }
1917
intel_encoder_is_dig_port(struct intel_encoder * encoder)1918 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1919 {
1920 switch (encoder->type) {
1921 case INTEL_OUTPUT_DDI:
1922 case INTEL_OUTPUT_DP:
1923 case INTEL_OUTPUT_EDP:
1924 case INTEL_OUTPUT_HDMI:
1925 return true;
1926 default:
1927 return false;
1928 }
1929 }
1930
intel_encoder_is_mst(struct intel_encoder * encoder)1931 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1932 {
1933 return encoder->type == INTEL_OUTPUT_DP_MST;
1934 }
1935
1936 static inline struct intel_dp_mst_encoder *
enc_to_mst(struct intel_encoder * encoder)1937 enc_to_mst(struct intel_encoder *encoder)
1938 {
1939 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1940 base.base);
1941 }
1942
1943 static inline struct intel_digital_port *
enc_to_dig_port(struct intel_encoder * encoder)1944 enc_to_dig_port(struct intel_encoder *encoder)
1945 {
1946 struct intel_encoder *intel_encoder = encoder;
1947
1948 if (intel_encoder_is_dig_port(intel_encoder))
1949 return container_of(&encoder->base, struct intel_digital_port,
1950 base.base);
1951 else if (intel_encoder_is_mst(intel_encoder))
1952 return enc_to_mst(encoder)->primary;
1953 else
1954 return NULL;
1955 }
1956
1957 static inline struct intel_digital_port *
intel_attached_dig_port(struct intel_connector * connector)1958 intel_attached_dig_port(struct intel_connector *connector)
1959 {
1960 return enc_to_dig_port(intel_attached_encoder(connector));
1961 }
1962
1963 static inline struct intel_hdmi *
enc_to_intel_hdmi(struct intel_encoder * encoder)1964 enc_to_intel_hdmi(struct intel_encoder *encoder)
1965 {
1966 return &enc_to_dig_port(encoder)->hdmi;
1967 }
1968
1969 static inline struct intel_hdmi *
intel_attached_hdmi(struct intel_connector * connector)1970 intel_attached_hdmi(struct intel_connector *connector)
1971 {
1972 return enc_to_intel_hdmi(intel_attached_encoder(connector));
1973 }
1974
enc_to_intel_dp(struct intel_encoder * encoder)1975 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1976 {
1977 return &enc_to_dig_port(encoder)->dp;
1978 }
1979
intel_attached_dp(struct intel_connector * connector)1980 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1981 {
1982 return enc_to_intel_dp(intel_attached_encoder(connector));
1983 }
1984
intel_encoder_is_dp(struct intel_encoder * encoder)1985 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1986 {
1987 switch (encoder->type) {
1988 case INTEL_OUTPUT_DP:
1989 case INTEL_OUTPUT_EDP:
1990 return true;
1991 case INTEL_OUTPUT_DDI:
1992 /* Skip pure HDMI/DVI DDI encoders */
1993 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1994 default:
1995 return false;
1996 }
1997 }
1998
1999 static inline struct intel_lspcon *
enc_to_intel_lspcon(struct intel_encoder * encoder)2000 enc_to_intel_lspcon(struct intel_encoder *encoder)
2001 {
2002 return &enc_to_dig_port(encoder)->lspcon;
2003 }
2004
2005 static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp * intel_dp)2006 dp_to_dig_port(struct intel_dp *intel_dp)
2007 {
2008 return container_of(intel_dp, struct intel_digital_port, dp);
2009 }
2010
2011 static inline struct intel_lspcon *
dp_to_lspcon(struct intel_dp * intel_dp)2012 dp_to_lspcon(struct intel_dp *intel_dp)
2013 {
2014 return &dp_to_dig_port(intel_dp)->lspcon;
2015 }
2016
2017 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
2018
2019 static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi * intel_hdmi)2020 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
2021 {
2022 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
2023 }
2024
2025 static inline struct intel_plane_state *
intel_atomic_get_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2026 intel_atomic_get_plane_state(struct intel_atomic_state *state,
2027 struct intel_plane *plane)
2028 {
2029 struct drm_plane_state *ret =
2030 drm_atomic_get_plane_state(&state->base, &plane->base);
2031
2032 if (IS_ERR(ret))
2033 return ERR_CAST(ret);
2034
2035 return to_intel_plane_state(ret);
2036 }
2037
2038 static inline struct intel_plane_state *
intel_atomic_get_old_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2039 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
2040 struct intel_plane *plane)
2041 {
2042 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
2043 &plane->base));
2044 }
2045
2046 static inline struct intel_plane_state *
intel_atomic_get_new_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)2047 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
2048 struct intel_plane *plane)
2049 {
2050 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
2051 &plane->base));
2052 }
2053
2054 static inline struct intel_crtc_state *
intel_atomic_get_old_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)2055 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
2056 struct intel_crtc *crtc)
2057 {
2058 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
2059 &crtc->base));
2060 }
2061
2062 static inline struct intel_crtc_state *
intel_atomic_get_new_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)2063 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
2064 struct intel_crtc *crtc)
2065 {
2066 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
2067 &crtc->base));
2068 }
2069
2070 static inline struct intel_digital_connector_state *
intel_atomic_get_new_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)2071 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
2072 struct intel_connector *connector)
2073 {
2074 return to_intel_digital_connector_state(
2075 drm_atomic_get_new_connector_state(&state->base,
2076 &connector->base));
2077 }
2078
2079 static inline struct intel_digital_connector_state *
intel_atomic_get_old_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)2080 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
2081 struct intel_connector *connector)
2082 {
2083 return to_intel_digital_connector_state(
2084 drm_atomic_get_old_connector_state(&state->base,
2085 &connector->base));
2086 }
2087
2088 /* intel_display.c */
2089 static inline bool
intel_crtc_has_type(const struct intel_crtc_state * crtc_state,enum intel_output_type type)2090 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
2091 enum intel_output_type type)
2092 {
2093 return crtc_state->output_types & BIT(type);
2094 }
2095
2096 static inline bool
intel_crtc_has_dp_encoder(const struct intel_crtc_state * crtc_state)2097 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
2098 {
2099 return crtc_state->output_types &
2100 (BIT(INTEL_OUTPUT_DP) |
2101 BIT(INTEL_OUTPUT_DP_MST) |
2102 BIT(INTEL_OUTPUT_EDP));
2103 }
2104
2105 static inline bool
intel_crtc_needs_modeset(const struct intel_crtc_state * crtc_state)2106 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
2107 {
2108 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
2109 }
2110
2111 static inline bool
intel_crtc_needs_fastset(const struct intel_crtc_state * crtc_state)2112 intel_crtc_needs_fastset(const struct intel_crtc_state *crtc_state)
2113 {
2114 return crtc_state->update_pipe;
2115 }
2116
2117 static inline bool
intel_crtc_needs_color_update(const struct intel_crtc_state * crtc_state)2118 intel_crtc_needs_color_update(const struct intel_crtc_state *crtc_state)
2119 {
2120 return crtc_state->uapi.color_mgmt_changed ||
2121 intel_crtc_needs_fastset(crtc_state) ||
2122 intel_crtc_needs_modeset(crtc_state);
2123 }
2124
intel_plane_ggtt_offset(const struct intel_plane_state * plane_state)2125 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
2126 {
2127 return i915_ggtt_offset(plane_state->ggtt_vma);
2128 }
2129
2130 static inline struct intel_frontbuffer *
to_intel_frontbuffer(struct drm_framebuffer * fb)2131 to_intel_frontbuffer(struct drm_framebuffer *fb)
2132 {
2133 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
2134 }
2135
to_bpp_int(int bpp_x16)2136 static inline int to_bpp_int(int bpp_x16)
2137 {
2138 return bpp_x16 >> 4;
2139 }
2140
to_bpp_frac(int bpp_x16)2141 static inline int to_bpp_frac(int bpp_x16)
2142 {
2143 return bpp_x16 & 0xf;
2144 }
2145
2146 #define BPP_X16_FMT "%d.%04d"
2147 #define BPP_X16_ARGS(bpp_x16) to_bpp_int(bpp_x16), (to_bpp_frac(bpp_x16) * 625)
2148
to_bpp_int_roundup(int bpp_x16)2149 static inline int to_bpp_int_roundup(int bpp_x16)
2150 {
2151 return (bpp_x16 + 0xf) >> 4;
2152 }
2153
to_bpp_x16(int bpp)2154 static inline int to_bpp_x16(int bpp)
2155 {
2156 return bpp << 4;
2157 }
2158
2159 /*
2160 * Conversion functions/macros from various pointer types to struct
2161 * intel_display pointer.
2162 */
2163 #define __drm_device_to_intel_display(p) \
2164 (&to_i915(p)->display)
2165 #define __intel_connector_to_intel_display(p) \
2166 __drm_device_to_intel_display((p)->base.dev)
2167 #define __intel_crtc_to_intel_display(p) \
2168 __drm_device_to_intel_display((p)->base.dev)
2169 #define __intel_crtc_state_to_intel_display(p) \
2170 __drm_device_to_intel_display((p)->uapi.crtc->dev)
2171 #define __intel_digital_port_to_intel_display(p) \
2172 __drm_device_to_intel_display((p)->base.base.dev)
2173 #define __intel_dp_to_intel_display(p) \
2174 __drm_device_to_intel_display(dp_to_dig_port(p)->base.base.dev)
2175 #define __intel_encoder_to_intel_display(p) \
2176 __drm_device_to_intel_display((p)->base.dev)
2177 #define __intel_hdmi_to_intel_display(p) \
2178 __drm_device_to_intel_display(hdmi_to_dig_port(p)->base.base.dev)
2179
2180 /* Helper for generic association. Map types to conversion functions/macros. */
2181 #define __assoc(type, p) \
2182 struct type: __##type##_to_intel_display((struct type *)(p))
2183
2184 /* Convert various pointer types to struct intel_display pointer. */
2185 #define to_intel_display(p) \
2186 _Generic(*p, \
2187 __assoc(drm_device, p), \
2188 __assoc(intel_connector, p), \
2189 __assoc(intel_crtc, p), \
2190 __assoc(intel_crtc_state, p), \
2191 __assoc(intel_digital_port, p), \
2192 __assoc(intel_dp, p), \
2193 __assoc(intel_encoder, p), \
2194 __assoc(intel_hdmi, p))
2195
2196 #endif /* __INTEL_DISPLAY_TYPES_H__ */
2197