xref: /dragonfly/sys/dev/netif/iwn/if_iwn_chip_cfg.h (revision 05538f72)
1 /*-
2  * Copyright (c) 2013 Cedric GROSS <cg@cgross.info>
3  * Copyright (c) 2011 Intel Corporation
4  *
5  * Permission to use, copy, modify, and distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  *
17  * $FreeBSD$
18  */
19 
20 #ifndef	__IF_IWN_CHIP_CFG_H__
21 #define	__IF_IWN_CHIP_CFG_H__
22 
23 /* ==========================================================================
24  *                                  NIC PARAMETERS
25  *
26  * ==========================================================================
27  */
28 
29 /*
30  * Flags for managing calibration result. See calib_need
31  * in iwn_base_params struct
32  *
33  * These are bitmasks that determine which indexes in the calibcmd
34  * array are pushed up.
35  */
36 #define IWN_FLG_NEED_PHY_CALIB_DC		(1<<0)
37 #define IWN_FLG_NEED_PHY_CALIB_LO		(1<<1)
38 #define IWN_FLG_NEED_PHY_CALIB_TX_IQ		(1<<2)
39 #define IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC	(1<<3)
40 #define IWN_FLG_NEED_PHY_CALIB_BASE_BAND	(1<<4)
41 /*
42  * These aren't (yet) included in the calibcmd array, but
43  * are used as flags for which calibrations to use.
44  *
45  * XXX I think they should be named differently and
46  * stuffed in a different member in the config struct!
47  */
48 #define IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET	(1<<5)
49 #define IWN_FLG_NEED_PHY_CALIB_CRYSTAL		(1<<6)
50 #define IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2	(1<<7)
51 
52 /*
53  * Each chip has a different threshold for PLCP errors that should trigger a
54  * retune.
55  */
56 #define	IWN_PLCP_ERR_DEFAULT_THRESHOLD		50
57 #define	IWN_PLCP_ERR_LONG_THRESHOLD		100
58 #define	IWN_PLCP_ERR_EXT_LONG_THRESHOLD		200
59 
60 /*
61  * Define some parameters for managing different NIC.
62  * Refer to linux specific file like iwl-xxxx.c to determine correct value
63  * for NIC.
64  *
65  * @max_ll_items: max number of OTP blocks
66  * @shadow_ram_support: shadow support for OTP memory
67  * @shadow_reg_enable: HW shadhow register bit
68  * @no_idle_support: do not support idle mode
69  * @advanced_bt_coexist : Advanced BT management
70  * @bt_session_2 : NIC need a new struct for configure BT coexistence. Needed
71  *   only if advanced_bt_coexist is true
72  * @bt_sco_disable :
73  * @additional_nic_config: For 6005 series
74  * @iq_invert : ? But need it for N 2000 series
75  * @regulatory_bands : XXX
76  * @enhanced_TX_power : EEPROM Has advanced TX power options. Set 'True'
77  *    if update_enhanced_txpower = iwl_eeprom_enhanced_txpower.
78  *    See iwl-agn-devices.c file to determine that(enhanced_txpower)
79  * @need_temp_offset_calib : Need to compute some temp offset for calibration.
80  * @calib_need : Use IWN_FLG_NEED_PHY_CALIB_* flags to specify which
81  *    calibration data ucode need. See calib_init_cfg in iwl-xxxx.c
82  *    linux kernel file
83  * @support_hostap: Define IEEE80211_C_HOSTAP for ic_caps
84  * @no_multi_vaps: See iwn_vap_create
85  * @additional_gp_drv_bit : Specific bit to defined during nic_config
86  * @bt_mode: BT configuration mode
87  */
88 enum bt_mode_enum {
89 	IWN_BT_NONE,
90 	IWN_BT_SIMPLE,
91 	IWN_BT_ADVANCED
92 };
93 
94 struct iwn_base_params {
95 	uint32_t	pll_cfg_val;
96 	const uint16_t	max_ll_items;
97 #define IWN_OTP_MAX_LL_ITEMS_1000		(3)	/* OTP blocks for 1000 */
98 #define IWN_OTP_MAX_LL_ITEMS_6x00		(4)	/* OTP blocks for 6x00 */
99 #define IWN_OTP_MAX_LL_ITEMS_6x50		(7)	/* OTP blocks for 6x50 */
100 #define IWN_OTP_MAX_LL_ITEMS_2x00		(4)	/* OTP blocks for 2x00 */
101 	const bool	shadow_ram_support;
102 	const bool	shadow_reg_enable;
103 	const bool	bt_session_2;
104 	const bool	bt_sco_disable;
105 	const bool	additional_nic_config;
106 	const uint32_t	*regulatory_bands;
107 	const bool	enhanced_TX_power;
108 	const uint16_t	calib_need;
109 	const bool	support_hostap;
110 	const bool	no_multi_vaps;
111 	uint8_t	additional_gp_drv_bit;
112 	enum bt_mode_enum	bt_mode;
113 	uint32_t	plcp_err_threshold;
114 };
115 
116 static const struct iwn_base_params iwn5000_base_params = {
117 	.pll_cfg_val = IWN_ANA_PLL_INIT,	/* pll_cfg_val; */
118 	.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,	/* max_ll_items */
119 	.shadow_ram_support = false,	/* shadow_ram_support */
120 	.shadow_reg_enable = false,	/* shadow_reg_enable */
121 	.bt_session_2 = false,	/* bt_session_2 */
122 	.bt_sco_disable = true,	/* bt_sco_disable */
123 	.additional_nic_config = false,	/* additional_nic_config */
124 	.regulatory_bands = iwn5000_regulatory_bands,	/* regulatory_bands */
125 	.enhanced_TX_power = false,	/* enhanced_TX_power */
126 	.calib_need =
127 	    ( IWN_FLG_NEED_PHY_CALIB_LO
128 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC
129 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ
130 	    | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
131 	.support_hostap = false,	/* support_hostap */
132 	.no_multi_vaps = true,	/* no_multi_vaps */
133 	.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,	/* additional_gp_drv_bit */
134 	.bt_mode = IWN_BT_NONE,	/* bt_mode */
135 	.plcp_err_threshold = IWN_PLCP_ERR_LONG_THRESHOLD,
136 };
137 
138 /*
139  * 4965 support
140  */
141 static const struct iwn_base_params iwn4965_base_params = {
142 	.pll_cfg_val = 0,				/* pll_cfg_val; */
143 	.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,	/* max_ll_items - ignored for 4965 */
144 	.shadow_ram_support = true,	/* shadow_ram_support */
145 	.shadow_reg_enable = false,	/* shadow_reg_enable */
146 	.bt_session_2 = false,	/* bt_session_2 XXX unknown? */
147 	.bt_sco_disable = true,	/* bt_sco_disable XXX unknown? */
148 	.additional_nic_config = false,	/* additional_nic_config - not for 4965 */
149 	.regulatory_bands = iwn5000_regulatory_bands,	/* regulatory_bands */
150 	.enhanced_TX_power = false,	/* enhanced_TX_power - not for 4965 */
151 	.calib_need =
152 	    (IWN_FLG_NEED_PHY_CALIB_DC
153 	    | IWN_FLG_NEED_PHY_CALIB_LO
154 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC
155 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ
156 	    | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
157 	.support_hostap = false,	/* support_hostap - XXX should work on fixing! */
158 	.no_multi_vaps = true,	/* no_multi_vaps - XXX should work on fixing!  */
159 	.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,	/* additional_gp_drv_bit */
160 	.bt_mode = IWN_BT_SIMPLE,	/* bt_mode */
161 	.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
162 };
163 
164 
165 static const struct iwn_base_params iwn2000_base_params = {
166 	.pll_cfg_val = 0,
167 	.max_ll_items = IWN_OTP_MAX_LL_ITEMS_2x00,
168 	.shadow_ram_support = true,
169 	.shadow_reg_enable = false,
170 	.bt_session_2 = false,
171 	.bt_sco_disable = true,
172 	.additional_nic_config = false,
173 	.regulatory_bands = iwn2030_regulatory_bands,
174 	.enhanced_TX_power = true,
175 	.calib_need =
176 	    (IWN_FLG_NEED_PHY_CALIB_DC
177 	    | IWN_FLG_NEED_PHY_CALIB_LO
178 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ
179 	    | IWN_FLG_NEED_PHY_CALIB_BASE_BAND
180 	    | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2 ),
181 	.support_hostap = true,
182 	.no_multi_vaps = false,
183 	.additional_gp_drv_bit = IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT,
184 	.bt_mode = IWN_BT_NONE,
185 	.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
186 };
187 
188 static const struct iwn_base_params iwn2030_base_params = {
189 	.pll_cfg_val = 0,
190 	.max_ll_items = IWN_OTP_MAX_LL_ITEMS_2x00,
191 	.shadow_ram_support = true,
192 	.shadow_reg_enable = false,     /* XXX check? */
193 	.bt_session_2 = true,
194 	.bt_sco_disable = true,
195 	.additional_nic_config = false,
196 	.regulatory_bands = iwn2030_regulatory_bands,
197 	.enhanced_TX_power = true,
198 	.calib_need =
199 	    (IWN_FLG_NEED_PHY_CALIB_DC
200 	    | IWN_FLG_NEED_PHY_CALIB_LO
201 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ
202 	    | IWN_FLG_NEED_PHY_CALIB_BASE_BAND
203 	    | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2 ),
204 	.support_hostap = true,
205 	.no_multi_vaps = false,
206 	.additional_gp_drv_bit = IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT,
207 	.bt_mode = IWN_BT_ADVANCED,
208 	.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
209 };
210 
211 static const struct iwn_base_params iwn1000_base_params = {
212 	.pll_cfg_val = IWN_ANA_PLL_INIT,
213 	.max_ll_items = IWN_OTP_MAX_LL_ITEMS_1000,
214 	.shadow_ram_support = false,
215 	.shadow_reg_enable = false,	/* XXX check? */
216 	.bt_session_2 = false,
217 	.bt_sco_disable = false,
218 	.additional_nic_config = false,
219 	.regulatory_bands = iwn5000_regulatory_bands,
220 	.enhanced_TX_power = false,
221 	.calib_need =
222 	    ( IWN_FLG_NEED_PHY_CALIB_LO
223 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC
224 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ
225 	    | IWN_FLG_NEED_PHY_CALIB_BASE_BAND
226 	    ),
227 	.support_hostap = false,
228 	.no_multi_vaps = true,
229 	.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
230 	/* XXX 1000 - no BT */
231 	.bt_mode = IWN_BT_SIMPLE,
232 	.plcp_err_threshold = IWN_PLCP_ERR_EXT_LONG_THRESHOLD,
233 };
234 static const struct iwn_base_params iwn_6000_base_params = {
235 	.pll_cfg_val = 0,
236 	.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
237 	.shadow_ram_support = true,
238 	.shadow_reg_enable = true,
239 	.bt_session_2 = false,
240 	.bt_sco_disable = false,
241 	.additional_nic_config = false,
242 	.regulatory_bands = iwn6000_regulatory_bands,
243 	.enhanced_TX_power = true,
244 	.calib_need =
245 	    (IWN_FLG_NEED_PHY_CALIB_DC
246 	    | IWN_FLG_NEED_PHY_CALIB_LO
247 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ
248 	    | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
249 	.support_hostap = false,
250 	.no_multi_vaps = true,
251 	.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
252 	.bt_mode = IWN_BT_SIMPLE,
253 	.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
254 };
255 static const struct iwn_base_params iwn_6000i_base_params = {
256 	.pll_cfg_val = 0,
257 	.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
258 	.shadow_ram_support = true,
259 	.shadow_reg_enable = true,
260 	.bt_session_2 = false,
261 	.bt_sco_disable = true,
262 	.additional_nic_config = false,
263 	.regulatory_bands = iwn6000_regulatory_bands,
264 	.enhanced_TX_power = true,
265 	.calib_need =
266 	    (IWN_FLG_NEED_PHY_CALIB_DC
267 	    | IWN_FLG_NEED_PHY_CALIB_LO
268 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ
269 	    | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
270 	.support_hostap = false,
271 	.no_multi_vaps = true,
272 	.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
273 	.bt_mode = IWN_BT_SIMPLE,
274 	.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
275 };
276 static const struct iwn_base_params iwn_6000g2_base_params = {
277 	.pll_cfg_val = 0,
278 	.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
279 	.shadow_ram_support = true,
280 	.shadow_reg_enable = true,
281 	.bt_session_2 = false,
282 	.bt_sco_disable = true,
283 	.additional_nic_config = false,
284 	.regulatory_bands = iwn6000_regulatory_bands,
285 	.enhanced_TX_power = true,
286 	.calib_need =
287 	    (IWN_FLG_NEED_PHY_CALIB_DC
288 	    | IWN_FLG_NEED_PHY_CALIB_LO
289 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ
290 	    | IWN_FLG_NEED_PHY_CALIB_BASE_BAND
291 	    | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ),
292 	.support_hostap = false,
293 	.no_multi_vaps = true,
294 	.additional_gp_drv_bit = 0,
295 	.bt_mode = IWN_BT_SIMPLE,
296 	.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
297 };
298 
299 static const struct iwn_base_params iwn_6050_base_params = {
300 	.pll_cfg_val = 0,
301 	.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x50,
302 	.shadow_ram_support = true,
303 	.shadow_reg_enable = true,
304 	.bt_session_2 = false,
305 	.bt_sco_disable = true,
306 	.additional_nic_config = true,
307 	.regulatory_bands = iwn6000_regulatory_bands,
308 	.enhanced_TX_power = true,
309 	.calib_need =
310 	    (IWN_FLG_NEED_PHY_CALIB_LO
311 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ
312 	    | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
313 	.support_hostap = false,
314 	.no_multi_vaps = true,
315 	.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
316 	.bt_mode = IWN_BT_SIMPLE,
317 	.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
318 };
319 static const struct iwn_base_params iwn_6150_base_params = {
320 	.pll_cfg_val = 0,
321 	.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x50,
322 	.shadow_ram_support = true,
323 	.shadow_reg_enable = true,
324 	.bt_session_2 = false,
325 	.bt_sco_disable = true,
326 	.additional_nic_config = true,
327 	.regulatory_bands = iwn6000_regulatory_bands,
328 	.enhanced_TX_power = true,
329 	.calib_need =
330 	    (IWN_FLG_NEED_PHY_CALIB_LO
331 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ
332 	    | IWN_FLG_NEED_PHY_CALIB_BASE_BAND),
333 	.support_hostap = false,
334 	.no_multi_vaps = true,
335 	.additional_gp_drv_bit = IWN_GP_DRIVER_6050_1X2,
336 	.bt_mode = IWN_BT_SIMPLE,
337 	.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
338 };
339 
340 /* IWL_DEVICE_6035 & IWL_DEVICE_6030 */
341 static const struct iwn_base_params iwn_6000g2b_base_params = {
342 	.pll_cfg_val = 0,
343 	.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
344 	.shadow_ram_support = true,
345 	.shadow_reg_enable = true,
346 	.bt_session_2 = false,
347 	.bt_sco_disable = true,
348 	.additional_nic_config = false,
349 	.regulatory_bands = iwn6000_regulatory_bands,
350 	.enhanced_TX_power = true,
351 	.calib_need =
352 	    (IWN_FLG_NEED_PHY_CALIB_DC
353 	    | IWN_FLG_NEED_PHY_CALIB_LO
354 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ
355 	    | IWN_FLG_NEED_PHY_CALIB_BASE_BAND
356 	    | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ),
357 	.support_hostap = false,
358 	.no_multi_vaps = true,
359 	.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
360 	.bt_mode = IWN_BT_ADVANCED,
361 	.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
362 };
363 
364 /*
365  * 6235 series NICs.
366  */
367 static const struct iwn_base_params iwn_6235_base_params = {
368 	.pll_cfg_val = 0,
369 	.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
370 	.shadow_ram_support = true,
371 	.shadow_reg_enable = true,
372 	.bt_session_2 = false,
373 	.bt_sco_disable = true,
374 	.additional_nic_config = true,
375 	.regulatory_bands = iwn6000_regulatory_bands,
376 	.enhanced_TX_power = true,
377 	.calib_need =
378 	    (IWN_FLG_NEED_PHY_CALIB_DC
379 	    | IWN_FLG_NEED_PHY_CALIB_LO
380 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ
381 	    | IWN_FLG_NEED_PHY_CALIB_BASE_BAND
382 	    | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ),
383 	.support_hostap = false,
384 	.no_multi_vaps = true,
385 	/* XXX 1x2? This NIC is 2x2, right? */
386 	.additional_gp_drv_bit = IWN_GP_DRIVER_6050_1X2,
387 	.bt_mode = IWN_BT_ADVANCED,
388 	.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
389 };
390 
391 static const struct iwn_base_params iwn_5x50_base_params = {
392 	.pll_cfg_val = IWN_ANA_PLL_INIT,
393 	.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
394 	.shadow_ram_support = true,
395 	.shadow_reg_enable = false,
396 	.bt_session_2 = false,
397 	.bt_sco_disable = true,
398 	.additional_nic_config = false,
399 	.regulatory_bands = iwn5000_regulatory_bands,
400 	.enhanced_TX_power =false,
401 	.calib_need =
402 	    (IWN_FLG_NEED_PHY_CALIB_DC
403 	    | IWN_FLG_NEED_PHY_CALIB_LO
404 	    | IWN_FLG_NEED_PHY_CALIB_TX_IQ
405 	    | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
406 	.support_hostap = false,
407 	.no_multi_vaps = true,
408 	.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
409 	.bt_mode = IWN_BT_SIMPLE,
410 	.plcp_err_threshold = IWN_PLCP_ERR_LONG_THRESHOLD,
411 };
412 
413 #endif	/* __IF_IWN_CHIP_CFG_H__ */
414