xref: /dragonfly/sys/dev/netif/tx/if_tx.c (revision 05d02a38)
1 /*-
2  * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $
27  */
28 
29 /*
30  * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
31  *
32  * These cards are based on SMC83c17x (EPIC) chip and one of the various
33  * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
34  * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
35  * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
36  * supports fibre optics.
37  *
38  * Thanks are going to Steve Bauer and Jason Wright.
39  */
40 
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/sockio.h>
44 #include <sys/mbuf.h>
45 #include <sys/malloc.h>
46 #include <sys/kernel.h>
47 #include <sys/socket.h>
48 #include <sys/queue.h>
49 #include <sys/serialize.h>
50 #include <sys/bus.h>
51 #include <sys/rman.h>
52 #include <sys/interrupt.h>
53 
54 #include <net/if.h>
55 #include <net/ifq_var.h>
56 #include <net/if_arp.h>
57 #include <net/ethernet.h>
58 #include <net/if_dl.h>
59 #include <net/if_media.h>
60 
61 #include <net/bpf.h>
62 
63 #include <net/vlan/if_vlan_var.h>
64 
65 #include <vm/vm.h>		/* for vtophys */
66 #include <vm/pmap.h>		/* for vtophys */
67 
68 #include <bus/pci/pcireg.h>
69 #include <bus/pci/pcivar.h>
70 #include "pcidevs.h"
71 
72 #include <dev/netif/mii_layer/mii.h>
73 #include <dev/netif/mii_layer/miivar.h>
74 #include "miidevs.h"
75 #include <dev/netif/mii_layer/lxtphyreg.h>
76 
77 #include "miibus_if.h"
78 
79 #include <dev/netif/tx/if_txreg.h>
80 #include <dev/netif/tx/if_txvar.h>
81 
82 static int epic_ifioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
83 static void epic_intr(void *);
84 static void epic_tx_underrun(epic_softc_t *);
85 static int epic_common_attach(epic_softc_t *);
86 static void epic_ifstart(struct ifnet *, struct ifaltq_subque *);
87 static void epic_ifwatchdog(struct ifnet *);
88 static void epic_stats_update(void *);
89 static int epic_init(epic_softc_t *);
90 static void epic_stop(epic_softc_t *);
91 static void epic_rx_done(epic_softc_t *);
92 static void epic_tx_done(epic_softc_t *);
93 static int epic_init_rings(epic_softc_t *);
94 static void epic_free_rings(epic_softc_t *);
95 static void epic_stop_activity(epic_softc_t *);
96 static int epic_queue_last_packet(epic_softc_t *);
97 static void epic_start_activity(epic_softc_t *);
98 static void epic_set_rx_mode(epic_softc_t *);
99 static void epic_set_tx_mode(epic_softc_t *);
100 static void epic_set_mc_table(epic_softc_t *);
101 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
102 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
103 static u_int16_t epic_input_eepromw(epic_softc_t *);
104 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
105 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
106 static u_int8_t epic_read_eepromreg(epic_softc_t *);
107 
108 static int epic_read_phy_reg(epic_softc_t *, int, int);
109 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
110 
111 static int epic_miibus_readreg(device_t, int, int);
112 static int epic_miibus_writereg(device_t, int, int, int);
113 static void epic_miibus_statchg(device_t);
114 static void epic_miibus_mediainit(device_t);
115 
116 static int epic_ifmedia_upd(struct ifnet *);
117 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
118 
119 static int epic_probe(device_t);
120 static int epic_attach(device_t);
121 static void epic_shutdown(device_t);
122 static int epic_detach(device_t);
123 
124 static device_method_t epic_methods[] = {
125 	/* Device interface */
126 	DEVMETHOD(device_probe,		epic_probe),
127 	DEVMETHOD(device_attach,	epic_attach),
128 	DEVMETHOD(device_detach,	epic_detach),
129 	DEVMETHOD(device_shutdown,	epic_shutdown),
130 
131 	/* MII interface */
132 	DEVMETHOD(miibus_readreg,	epic_miibus_readreg),
133 	DEVMETHOD(miibus_writereg,	epic_miibus_writereg),
134 	DEVMETHOD(miibus_statchg,	epic_miibus_statchg),
135 	DEVMETHOD(miibus_mediainit,	epic_miibus_mediainit),
136 
137 	DEVMETHOD_END
138 };
139 
140 static driver_t epic_driver = {
141 	"tx",
142 	epic_methods,
143 	sizeof(epic_softc_t)
144 };
145 
146 static devclass_t epic_devclass;
147 
148 DECLARE_DUMMY_MODULE(if_tx);
149 MODULE_DEPEND(if_tx, miibus, 1, 1, 1);
150 DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, NULL, NULL);
151 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, NULL, NULL);
152 
153 static struct epic_type epic_devs[] = {
154 	{ PCI_VENDOR_SMC, PCI_PRODUCT_SMC_83C170,
155 		"SMC EtherPower II 10/100" },
156 	{ 0, 0, NULL }
157 };
158 
159 static int
epic_probe(device_t dev)160 epic_probe(device_t dev)
161 {
162 	struct epic_type *t;
163 	uint16_t vid, did;
164 
165 	vid = pci_get_vendor(dev);
166 	did = pci_get_device(dev);
167 	for (t = epic_devs; t->name != NULL; ++t) {
168 		if (vid == t->ven_id && did == t->dev_id) {
169 			device_set_desc(dev, t->name);
170 			return 0;
171 		}
172 	}
173 	return ENXIO;
174 }
175 
176 #if defined(EPIC_USEIOSPACE)
177 #define	EPIC_RES	SYS_RES_IOPORT
178 #define EPIC_RID	PCIR_BAR(0)
179 #else
180 #define	EPIC_RES	SYS_RES_MEMORY
181 #define EPIC_RID	PCIR_BAR(1)
182 #endif
183 
184 /*
185  * Attach routine: map registers, allocate softc, rings and descriptors.
186  * Reset to known state.
187  */
188 static int
epic_attach(device_t dev)189 epic_attach(device_t dev)
190 {
191 	struct ifnet *ifp;
192 	epic_softc_t *sc;
193 	int error;
194 	int i, rid, tmp;
195 
196 	sc = device_get_softc(dev);
197 
198 	/* Preinitialize softc structure */
199 	sc->dev = dev;
200 	callout_init(&sc->tx_stat_timer);
201 
202 	/* Fill ifnet structure */
203 	ifp = &sc->sc_if;
204 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
205 	ifp->if_softc = sc;
206 	ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
207 	ifp->if_ioctl = epic_ifioctl;
208 	ifp->if_start = epic_ifstart;
209 	ifp->if_watchdog = epic_ifwatchdog;
210 	ifp->if_init = (if_init_f_t*)epic_init;
211 	ifp->if_timer = 0;
212 	ifp->if_baudrate = 10000000;
213 	ifq_set_maxlen(&ifp->if_snd, TX_RING_SIZE - 1);
214 	ifq_set_ready(&ifp->if_snd);
215 
216 	pci_enable_busmaster(dev);
217 
218 	rid = EPIC_RID;
219 	sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE);
220 
221 	if (sc->res == NULL) {
222 		device_printf(dev, "couldn't map ports/memory\n");
223 		error = ENXIO;
224 		goto fail;
225 	}
226 
227 	sc->sc_st = rman_get_bustag(sc->res);
228 	sc->sc_sh = rman_get_bushandle(sc->res);
229 
230 	/* Allocate interrupt */
231 	rid = 0;
232 	sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
233 	    RF_SHAREABLE | RF_ACTIVE);
234 
235 	if (sc->irq == NULL) {
236 		device_printf(dev, "couldn't map interrupt\n");
237 		error = ENXIO;
238 		goto fail;
239 	}
240 
241 	/* Do OS independent part, including chip wakeup and reset */
242 	error = epic_common_attach(sc);
243 	if (error) {
244 		error = ENXIO;
245 		goto fail;
246 	}
247 
248 	/* Do ifmedia setup */
249 	if (mii_phy_probe(dev, &sc->miibus,
250 	    epic_ifmedia_upd, epic_ifmedia_sts)) {
251 		device_printf(dev, "ERROR! MII without any PHY!?\n");
252 		error = ENXIO;
253 		goto fail;
254 	}
255 
256 	/* board type and ... */
257 	kprintf(" type ");
258 	for(i=0x2c;i<0x32;i++) {
259 		tmp = epic_read_eeprom(sc, i);
260 		if (' ' == (u_int8_t)tmp) break;
261 		kprintf("%c", (u_int8_t)tmp);
262 		tmp >>= 8;
263 		if (' ' == (u_int8_t)tmp) break;
264 		kprintf("%c", (u_int8_t)tmp);
265 	}
266 	kprintf("\n");
267 
268 	/* Attach to OS's managers */
269 	ether_ifattach(ifp, sc->sc_macaddr, NULL);
270 	ifp->if_hdrlen = sizeof(struct ether_vlan_header);
271 
272 	ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->irq));
273 
274 	error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE,
275 			       epic_intr, sc, &sc->sc_ih,
276 			       ifp->if_serializer);
277 
278 	if (error) {
279 		device_printf(dev, "couldn't set up irq\n");
280 		ether_ifdetach(ifp);
281 		goto fail;
282 	}
283 
284 	return(0);
285 
286 fail:
287 	epic_detach(dev);
288 	return(error);
289 }
290 
291 /*
292  * Detach driver and free resources
293  */
294 static int
epic_detach(device_t dev)295 epic_detach(device_t dev)
296 {
297 	epic_softc_t *sc = device_get_softc(dev);
298 	struct ifnet *ifp = &sc->arpcom.ac_if;
299 
300 	if (device_is_attached(dev)) {
301 		lwkt_serialize_enter(ifp->if_serializer);
302 		epic_stop(sc);
303 		bus_teardown_intr(dev, sc->irq, sc->sc_ih);
304 		lwkt_serialize_exit(ifp->if_serializer);
305 
306 		ether_ifdetach(ifp);
307 	}
308 
309 	if (sc->miibus)
310 		device_delete_child(dev, sc->miibus);
311 	bus_generic_detach(dev);
312 
313 	if (sc->irq)
314 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
315 	if (sc->res)
316 		bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
317 
318 	if (sc->tx_flist)
319 		kfree(sc->tx_flist, M_DEVBUF);
320 	if (sc->tx_desc)
321 		kfree(sc->tx_desc, M_DEVBUF);
322 	if (sc->rx_desc)
323 		kfree(sc->rx_desc, M_DEVBUF);
324 
325 	return(0);
326 }
327 
328 #undef	EPIC_RES
329 #undef	EPIC_RID
330 
331 /*
332  * Stop all chip I/O so that the kernel's probe routines don't
333  * get confused by errant DMAs when rebooting.
334  */
335 static void
epic_shutdown(device_t dev)336 epic_shutdown(device_t dev)
337 {
338 	epic_softc_t *sc;
339 	struct ifnet *ifp;
340 
341 	sc = device_get_softc(dev);
342 	ifp = &sc->arpcom.ac_if;
343 	lwkt_serialize_enter(ifp->if_serializer);
344 	epic_stop(sc);
345 	lwkt_serialize_exit(ifp->if_serializer);
346 }
347 
348 /*
349  * This is if_ioctl handler.
350  */
351 static int
epic_ifioctl(struct ifnet * ifp,u_long command,caddr_t data,struct ucred * cr)352 epic_ifioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
353 {
354 	epic_softc_t *sc = ifp->if_softc;
355 	struct mii_data	*mii;
356 	struct ifreq *ifr = (struct ifreq *) data;
357 	int error = 0;
358 
359 	switch (command) {
360 	case SIOCSIFMTU:
361 		if (ifp->if_mtu == ifr->ifr_mtu)
362 			break;
363 
364 		/* XXX Though the datasheet doesn't imply any
365 		 * limitations on RX and TX sizes beside max 64Kb
366 		 * DMA transfer, seems we can't send more then 1600
367 		 * data bytes per ethernet packet. (Transmitter hangs
368 		 * up if more data is sent)
369 		 */
370 		if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
371 			ifp->if_mtu = ifr->ifr_mtu;
372 			epic_stop(sc);
373 			epic_init(sc);
374 		} else
375 			error = EINVAL;
376 		break;
377 
378 	case SIOCSIFFLAGS:
379 		/*
380 		 * If the interface is marked up and stopped, then start it.
381 		 * If it is marked down and running, then stop it.
382 		 */
383 		if (ifp->if_flags & IFF_UP) {
384 			if ((ifp->if_flags & IFF_RUNNING) == 0) {
385 				epic_init(sc);
386 				break;
387 			}
388 		} else {
389 			if (ifp->if_flags & IFF_RUNNING) {
390 				epic_stop(sc);
391 				break;
392 			}
393 		}
394 
395 		/* Handle IFF_PROMISC and IFF_ALLMULTI flags */
396 		epic_stop_activity(sc);
397 		epic_set_mc_table(sc);
398 		epic_set_rx_mode(sc);
399 		epic_start_activity(sc);
400 		break;
401 
402 	case SIOCADDMULTI:
403 	case SIOCDELMULTI:
404 		epic_set_mc_table(sc);
405 		error = 0;
406 		break;
407 
408 	case SIOCSIFMEDIA:
409 	case SIOCGIFMEDIA:
410 		mii = device_get_softc(sc->miibus);
411 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
412 		break;
413 
414 	default:
415 		error = ether_ioctl(ifp, command, data);
416 		break;
417 	}
418 	return error;
419 }
420 
421 /*
422  * OS-independed part of attach process. allocate memory for descriptors
423  * and frag lists, wake up chip, read MAC address and PHY identyfier.
424  * Return -1 on failure.
425  */
426 static int
epic_common_attach(epic_softc_t * sc)427 epic_common_attach(epic_softc_t *sc)
428 {
429 	uint16_t sub_vid;
430 	int i;
431 
432 	sc->tx_flist = kmalloc(sizeof(struct epic_frag_list)*TX_RING_SIZE,
433 	    M_DEVBUF, M_WAITOK | M_ZERO);
434 	sc->tx_desc = kmalloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE,
435 	    M_DEVBUF, M_WAITOK | M_ZERO);
436 	sc->rx_desc = kmalloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE,
437 	    M_DEVBUF, M_WAITOK | M_ZERO);
438 
439 	/* Bring the chip out of low-power mode. */
440 	CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
441 	DELAY(500);
442 
443 	/* Workaround for Application Note 7-15 */
444 	for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
445 
446 	/* Read mac address from EEPROM */
447 	for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
448 		((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
449 
450 	/* Set Non-Volatile Control Register from EEPROM */
451 	CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
452 
453 	/* Set defaults */
454 	sc->tx_threshold = TRANSMIT_THRESHOLD;
455 	sc->txcon = TXCON_DEFAULT;
456 	sc->miicfg = MIICFG_SMI_ENABLE;
457 	sc->phyid = EPIC_UNKN_PHY;
458 	sc->serinst = -1;
459 
460 	/* Fetch card id */
461 	sub_vid = pci_get_subvendor(sc->dev);
462 	sc->cardid = pci_get_subdevice(sc->dev);
463 
464 	if (sub_vid != PCI_VENDOR_SMC)
465 		device_printf(sc->dev, "unknown card vendor %04xh\n", sub_vid);
466 
467 	return 0;
468 }
469 
470 /*
471  * This is if_start handler. It takes mbufs from if_snd queue
472  * and queue them for transmit, one by one, until TX ring become full
473  * or queue become empty.
474  */
475 static void
epic_ifstart(struct ifnet * ifp,struct ifaltq_subque * ifsq)476 epic_ifstart(struct ifnet *ifp, struct ifaltq_subque *ifsq)
477 {
478 	epic_softc_t *sc = ifp->if_softc;
479 	struct epic_tx_buffer *buf;
480 	struct epic_tx_desc *desc;
481 	struct epic_frag_list *flist;
482 	struct mbuf *m0;
483 	struct mbuf *m;
484 	int i;
485 
486 	ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
487 
488 	while (sc->pending_txs < TX_RING_SIZE) {
489 		buf = sc->tx_buffer + sc->cur_tx;
490 		desc = sc->tx_desc + sc->cur_tx;
491 		flist = sc->tx_flist + sc->cur_tx;
492 
493 		/* Get next packet to send */
494 		m0 = ifq_dequeue(&ifp->if_snd);
495 
496 		/* If nothing to send, return */
497 		if (m0 == NULL)
498 			return;
499 
500 		/* Fill fragments list */
501 		for (m = m0, i = 0;
502 		    (NULL != m) && (i < EPIC_MAX_FRAGS);
503 		    m = m->m_next, i++) {
504 			flist->frag[i].fraglen = m->m_len;
505 			flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t));
506 		}
507 		flist->numfrags = i;
508 
509 		/* If packet was more than EPIC_MAX_FRAGS parts, */
510 		/* recopy packet to new allocated mbuf cluster */
511 		if (NULL != m) {
512 			m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
513 			if (NULL == m) {
514 				m_freem(m0);
515 				IFNET_STAT_INC(ifp, oerrors, 1);
516 				continue;
517 			}
518 
519 			m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
520 			flist->frag[0].fraglen =
521 			     m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
522 			m->m_pkthdr.rcvif = ifp;
523 
524 			flist->numfrags = 1;
525 			flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t));
526 			m_freem(m0);
527 			m0 = m;
528 		}
529 
530 		buf->mbuf = m0;
531 		sc->pending_txs++;
532 		sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
533 		desc->control = 0x01;
534 		desc->txlength =
535 		    max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
536 		desc->status = 0x8000;
537 		CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
538 
539 		/* Set watchdog timer */
540 		ifp->if_timer = 8;
541 
542 		BPF_MTAP(ifp, m0);
543 	}
544 
545 	ifq_set_oactive(&ifp->if_snd);
546 
547 	return;
548 
549 }
550 
551 /*
552  * Synopsis: Finish all received frames.
553  */
554 static void
epic_rx_done(epic_softc_t * sc)555 epic_rx_done(epic_softc_t *sc)
556 {
557 	u_int16_t len;
558 	struct ifnet *ifp = &sc->sc_if;
559 	struct epic_rx_buffer *buf;
560 	struct epic_rx_desc *desc;
561 	struct mbuf *m;
562 
563 	while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
564 		buf = sc->rx_buffer + sc->cur_rx;
565 		desc = sc->rx_desc + sc->cur_rx;
566 
567 		/* Switch to next descriptor */
568 		sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK;
569 
570 		/*
571 		 * Check for RX errors. This should only happen if
572 		 * SAVE_ERRORED_PACKETS is set. RX errors generate
573 		 * RXE interrupt usually.
574 		 */
575 		if ((desc->status & 1) == 0) {
576 			IFNET_STAT_INC(&sc->sc_if, ierrors, 1);
577 			desc->status = 0x8000;
578 			continue;
579 		}
580 
581 		/* Save packet length and mbuf contained packet */
582 		len = desc->rxlength - ETHER_CRC_LEN;
583 		m = buf->mbuf;
584 
585 		/* Try to get mbuf cluster */
586 		buf->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
587 		if (NULL == buf->mbuf) {
588 			buf->mbuf = m;
589 			desc->status = 0x8000;
590 			IFNET_STAT_INC(ifp, ierrors, 1);
591 			continue;
592 		}
593 
594 		/* Point to new mbuf, and give descriptor to chip */
595 		desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
596 		desc->status = 0x8000;
597 
598 		/* First mbuf in packet holds the ethernet and packet headers */
599 		m->m_pkthdr.rcvif = ifp;
600 		m->m_pkthdr.len = m->m_len = len;
601 
602 		/* Give mbuf to OS */
603 		ifp->if_input(ifp, m, NULL, -1);
604 
605 		/* Successfuly received frame */
606 		IFNET_STAT_INC(ifp, ipackets, 1);
607 	}
608 
609 	return;
610 }
611 
612 /*
613  * Synopsis: Do last phase of transmission. I.e. if desc is
614  * transmitted, decrease pending_txs counter, free mbuf contained
615  * packet, switch to next descriptor and repeat until no packets
616  * are pending or descriptor is not transmitted yet.
617  */
618 static void
epic_tx_done(epic_softc_t * sc)619 epic_tx_done(epic_softc_t *sc)
620 {
621 	struct epic_tx_buffer *buf;
622 	struct epic_tx_desc *desc;
623 	u_int16_t status;
624 
625 	while (sc->pending_txs > 0) {
626 		buf = sc->tx_buffer + sc->dirty_tx;
627 		desc = sc->tx_desc + sc->dirty_tx;
628 		status = desc->status;
629 
630 		/* If packet is not transmitted, thou followed */
631 		/* packets are not transmitted too */
632 		if (status & 0x8000) break;
633 
634 		/* Packet is transmitted. Switch to next and */
635 		/* free mbuf */
636 		sc->pending_txs--;
637 		sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
638 		m_freem(buf->mbuf);
639 		buf->mbuf = NULL;
640 
641 		/* Check for errors and collisions */
642 		if (status & 0x0001) IFNET_STAT_INC(&sc->sc_if, opackets, 1);
643 		else IFNET_STAT_INC(&sc->sc_if, oerrors, 1);
644 		IFNET_STAT_INC(&sc->sc_if, collisions, (status >> 8) & 0x1F);
645 #if defined(EPIC_DIAG)
646 		if ((status & 0x1001) == 0x1001) {
647 			if_printf(&sc->sc_if,
648 				  "Tx ERROR: excessive coll. number\n");
649 		}
650 #endif
651 	}
652 
653 	if (sc->pending_txs < TX_RING_SIZE)
654 		ifq_clr_oactive(&sc->sc_if.if_snd);
655 }
656 
657 /*
658  * Interrupt function
659  */
660 static void
epic_intr(void * arg)661 epic_intr(void *arg)
662 {
663     epic_softc_t * sc = (epic_softc_t *) arg;
664     int status, i = 4;
665 
666     while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
667 	CSR_WRITE_4(sc, INTSTAT, status);
668 
669 	if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
670 	    epic_rx_done(sc);
671 	    if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
672 #if defined(EPIC_DIAG)
673 		if (status & INTSTAT_OVW)
674 		    if_printf(&sc->sc_if, "RX buffer overflow\n");
675 		if (status & INTSTAT_RQE)
676 		    if_printf(&sc->sc_if, "RX FIFO overflow\n");
677 #endif
678 		if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
679 		    CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
680 		IFNET_STAT_INC(&sc->sc_if, ierrors, 1);
681 	    }
682 	}
683 
684 	if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
685 	    epic_tx_done(sc);
686 	    if (!ifq_is_empty(&sc->sc_if.if_snd))
687 		if_devstart(&sc->sc_if);
688 	}
689 
690 	/* Check for rare errors */
691 	if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
692 		      INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
693     	    if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
694 			  INTSTAT_APE|INTSTAT_DPE)) {
695 		if_printf(&sc->sc_if, "PCI fatal errors occurred: %s%s%s%s\n",
696 		    (status&INTSTAT_PMA)?"PMA ":"",
697 		    (status&INTSTAT_PTA)?"PTA ":"",
698 		    (status&INTSTAT_APE)?"APE ":"",
699 		    (status&INTSTAT_DPE)?"DPE":""
700 		);
701 
702 		epic_stop(sc);
703 		epic_init(sc);
704 
705 	    	break;
706 	    }
707 
708 	    if (status & INTSTAT_RXE) {
709 #if defined(EPIC_DIAG)
710 		if_printf(sc->sc_if, "CRC/Alignment error\n");
711 #endif
712 		IFNET_STAT_INC(&sc->sc_if, ierrors, 1);
713 	    }
714 
715 	    if (status & INTSTAT_TXU) {
716 		epic_tx_underrun(sc);
717 		IFNET_STAT_INC(&sc->sc_if, oerrors, 1);
718 	    }
719 	}
720     }
721 
722     /* If no packets are pending, then no timeouts */
723     if (sc->pending_txs == 0) sc->sc_if.if_timer = 0;
724 
725     return;
726 }
727 
728 /*
729  * Handle the TX underrun error: increase the TX threshold
730  * and restart the transmitter.
731  */
732 static void
epic_tx_underrun(epic_softc_t * sc)733 epic_tx_underrun(epic_softc_t *sc)
734 {
735 	if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
736 		sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
737 #if defined(EPIC_DIAG)
738 		if_printf(&sc->sc_if, "Tx UNDERRUN: early TX disabled\n");
739 #endif
740 	} else {
741 		sc->tx_threshold += 0x40;
742 #if defined(EPIC_DIAG)
743 		if_printf(&sc->sc_if, "Tx UNDERRUN: "
744 			  "TX threshold increased to %d\n", sc->tx_threshold);
745 #endif
746 	}
747 
748 	/* We must set TXUGO to reset the stuck transmitter */
749 	CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
750 
751 	/* Update the TX threshold */
752 	epic_stop_activity(sc);
753 	epic_set_tx_mode(sc);
754 	epic_start_activity(sc);
755 
756 	return;
757 }
758 
759 /*
760  * Synopsis: This one is called if packets wasn't transmitted
761  * during timeout. Try to deallocate transmitted packets, and
762  * if success continue to work.
763  */
764 static void
epic_ifwatchdog(struct ifnet * ifp)765 epic_ifwatchdog(struct ifnet *ifp)
766 {
767 	epic_softc_t *sc = ifp->if_softc;
768 
769 	if_printf(ifp, "device timeout %d packets\n", sc->pending_txs);
770 
771 	/* Try to finish queued packets */
772 	epic_tx_done(sc);
773 
774 	/* If not successful */
775 	if (sc->pending_txs > 0) {
776 
777 		IFNET_STAT_INC(ifp, oerrors, sc->pending_txs);
778 
779 		/* Reinitialize board */
780 		if_printf(ifp, "reinitialization\n");
781 		epic_stop(sc);
782 		epic_init(sc);
783 
784 	} else
785 		if_printf(ifp, "seems we can continue normally\n");
786 
787 	/* Start output */
788 	if (!ifq_is_empty(&ifp->if_snd))
789 		if_devstart(ifp);
790 }
791 
792 /*
793  * Despite the name of this function, it doesn't update statistics, it only
794  * helps in autonegotiation process.
795  */
796 static void
epic_stats_update(void * xsc)797 epic_stats_update(void *xsc)
798 {
799 	epic_softc_t *sc = xsc;
800 	struct ifnet *ifp = &sc->sc_if;
801 	struct mii_data * mii;
802 
803 	lwkt_serialize_enter(ifp->if_serializer);
804 
805 	mii = device_get_softc(sc->miibus);
806 	mii_tick(mii);
807 
808 	callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
809 
810 	lwkt_serialize_exit(ifp->if_serializer);
811 }
812 
813 /*
814  * Set media options.
815  */
816 static int
epic_ifmedia_upd(struct ifnet * ifp)817 epic_ifmedia_upd(struct ifnet *ifp)
818 {
819 	epic_softc_t *sc;
820 	struct mii_data *mii;
821 	struct ifmedia *ifm;
822 	struct mii_softc *miisc;
823 	int cfg, media;
824 
825 	sc = ifp->if_softc;
826 	mii = device_get_softc(sc->miibus);
827 	ifm = &mii->mii_media;
828 	media = ifm->ifm_cur->ifm_media;
829 
830 	/* Do not do anything if interface is not up */
831 	if ((ifp->if_flags & IFF_UP) == 0)
832 		return (0);
833 
834 	/*
835 	 * Lookup current selected PHY
836 	 */
837 	if (IFM_INST(media) == sc->serinst) {
838 		sc->phyid = EPIC_SERIAL;
839 		sc->physc = NULL;
840 	} else {
841 		/* If we're not selecting serial interface, select MII mode */
842 		sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
843 		CSR_WRITE_4(sc, MIICFG, sc->miicfg);
844 
845 		/* Default to unknown PHY */
846 		sc->phyid = EPIC_UNKN_PHY;
847 
848 		/* Lookup selected PHY */
849 		for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
850 		     miisc = LIST_NEXT(miisc, mii_list)) {
851 			if (IFM_INST(media) == miisc->mii_inst) {
852 				sc->physc = miisc;
853 				break;
854 			}
855 		}
856 
857 		/* Identify selected PHY */
858 		if (sc->physc) {
859 			int id1, id2, model, oui;
860 
861 			id1 = PHY_READ(sc->physc, MII_PHYIDR1);
862 			id2 = PHY_READ(sc->physc, MII_PHYIDR2);
863 
864 			oui = MII_OUI(id1, id2);
865 			model = MII_MODEL(id2);
866 			switch (oui) {
867 			case MII_OUI_QUALSEMI:
868 				if (model == MII_MODEL_QUALSEMI_QS6612)
869 					sc->phyid = EPIC_QS6612_PHY;
870 				break;
871 			case MII_OUI_xxALTIMA:
872 				if (model == MII_MODEL_xxALTIMA_AC101)
873 					sc->phyid = EPIC_AC101_PHY;
874 				break;
875 			case MII_OUI_xxLEVEL1:
876 				if (model == MII_MODEL_xxLEVEL1_LXT970)
877 					sc->phyid = EPIC_LXT970_PHY;
878 				break;
879 			}
880 		}
881 	}
882 
883 	/*
884 	 * Do PHY specific card setup
885 	 */
886 
887 	/* Call this, to isolate all not selected PHYs and
888 	 * set up selected
889 	 */
890 	mii_mediachg(mii);
891 
892 	/* Do our own setup */
893 	switch (sc->phyid) {
894 	case EPIC_QS6612_PHY:
895 		break;
896 	case EPIC_AC101_PHY:
897 		/* We have to powerup fiber tranceivers */
898 		if (IFM_SUBTYPE(media) == IFM_100_FX)
899 			sc->miicfg |= MIICFG_694_ENABLE;
900 		else
901 			sc->miicfg &= ~MIICFG_694_ENABLE;
902 		CSR_WRITE_4(sc, MIICFG, sc->miicfg);
903 
904 		break;
905 	case EPIC_LXT970_PHY:
906 		/* We have to powerup fiber tranceivers */
907 		cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
908 		if (IFM_SUBTYPE(media) == IFM_100_FX)
909 			cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
910 		else
911 			cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
912 		PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
913 
914 		break;
915 	case EPIC_SERIAL:
916 		/* Select serial PHY, (10base2/BNC usually) */
917 		sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
918 		CSR_WRITE_4(sc, MIICFG, sc->miicfg);
919 
920 		/* There is no driver to fill this */
921 		mii->mii_media_active = media;
922 		mii->mii_media_status = 0;
923 
924 		/* We need to call this manualy as i wasn't called
925 		 * in mii_mediachg()
926 		 */
927 		epic_miibus_statchg(sc->dev);
928 
929 		break;
930 	default:
931 		if_printf(ifp, "ERROR! Unknown PHY selected\n");
932 		return (EINVAL);
933 	}
934 
935 	return(0);
936 }
937 
938 /*
939  * Report current media status.
940  */
941 static void
epic_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)942 epic_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
943 {
944 	epic_softc_t *sc;
945 	struct mii_data *mii;
946 
947 	sc = ifp->if_softc;
948 	mii = device_get_softc(sc->miibus);
949 
950 	/* Nothing should be selected if interface is down */
951 	if ((ifp->if_flags & IFF_UP) == 0) {
952 		ifmr->ifm_active = IFM_NONE;
953 		ifmr->ifm_status = 0;
954 
955 		return;
956 	}
957 
958 	/* Call underlying pollstat, if not serial PHY */
959 	if (sc->phyid != EPIC_SERIAL)
960 		mii_pollstat(mii);
961 
962 	/* Simply copy media info */
963 	ifmr->ifm_active = mii->mii_media_active;
964 	ifmr->ifm_status = mii->mii_media_status;
965 
966 	return;
967 }
968 
969 /*
970  * Callback routine, called on media change.
971  */
972 static void
epic_miibus_statchg(device_t dev)973 epic_miibus_statchg(device_t dev)
974 {
975 	epic_softc_t *sc;
976 	struct mii_data *mii;
977 	int media;
978 
979 	sc = device_get_softc(dev);
980 	mii = device_get_softc(sc->miibus);
981 	media = mii->mii_media_active;
982 
983 	sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
984 
985 	/* If we are in full-duplex mode or loopback operation,
986 	 * we need to decouple receiver and transmitter.
987 	 */
988 	if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
989  		sc->txcon |= TXCON_FULL_DUPLEX;
990 
991 	/* On some cards we need manualy set fullduplex led */
992 	if (sc->cardid == SMC9432FTX ||
993 	    sc->cardid == SMC9432FTX_SC) {
994 		if (IFM_OPTIONS(media) & IFM_FDX)
995 			sc->miicfg |= MIICFG_694_ENABLE;
996 		else
997 			sc->miicfg &= ~MIICFG_694_ENABLE;
998 
999 		CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1000 	}
1001 
1002 	/* Update baudrate */
1003 	if (IFM_SUBTYPE(media) == IFM_100_TX ||
1004 	    IFM_SUBTYPE(media) == IFM_100_FX)
1005 		sc->sc_if.if_baudrate = 100000000;
1006 	else
1007 		sc->sc_if.if_baudrate = 10000000;
1008 
1009 	epic_stop_activity(sc);
1010 	epic_set_tx_mode(sc);
1011 	epic_start_activity(sc);
1012 
1013 	return;
1014 }
1015 
1016 static void
epic_miibus_mediainit(device_t dev)1017 epic_miibus_mediainit(device_t dev)
1018 {
1019 	epic_softc_t *sc;
1020 	struct mii_data *mii;
1021 	struct ifmedia *ifm;
1022 	int media;
1023 
1024 	sc = device_get_softc(dev);
1025 	mii = device_get_softc(sc->miibus);
1026 	ifm = &mii->mii_media;
1027 
1028 	/* Add Serial Media Interface if present, this applies to
1029 	 * SMC9432BTX serie
1030 	 */
1031 	if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1032 		/* Store its instance */
1033 		sc->serinst = mii->mii_instance++;
1034 
1035 		/* Add as 10base2/BNC media */
1036 		media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1037 		ifmedia_add(ifm, media, 0, NULL);
1038 
1039 		/* Report to user */
1040 		if_printf(&sc->sc_if, "serial PHY detected (10Base2/BNC)\n");
1041 	}
1042 
1043 	return;
1044 }
1045 
1046 /*
1047  * Reset chip, allocate rings, and update media.
1048  */
1049 static int
epic_init(epic_softc_t * sc)1050 epic_init(epic_softc_t *sc)
1051 {
1052 	struct ifnet *ifp = &sc->sc_if;
1053 	int	i;
1054 
1055 	/* If interface is already running, then we need not do anything */
1056 	if (ifp->if_flags & IFF_RUNNING) {
1057 		return 0;
1058 	}
1059 
1060 	/* Soft reset the chip (we have to power up card before) */
1061 	CSR_WRITE_4(sc, GENCTL, 0);
1062 	CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1063 
1064 	/*
1065 	 * Reset takes 15 pci ticks which depends on PCI bus speed.
1066 	 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1067 	 */
1068 	DELAY(500);
1069 
1070 	/* Wake up */
1071 	CSR_WRITE_4(sc, GENCTL, 0);
1072 
1073 	/* Workaround for Application Note 7-15 */
1074 	for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1075 
1076 	/* Initialize rings */
1077 	if (epic_init_rings(sc)) {
1078 		if_printf(ifp, "failed to init rings\n");
1079 		return -1;
1080 	}
1081 
1082 	/* Give rings to EPIC */
1083 	CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc));
1084 	CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc));
1085 
1086 	/* Put node address to EPIC */
1087 	CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]);
1088 	CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]);
1089 	CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]);
1090 
1091 	/* Set tx mode, includeing transmit threshold */
1092 	epic_set_tx_mode(sc);
1093 
1094 	/* Compute and set RXCON. */
1095 	epic_set_rx_mode(sc);
1096 
1097 	/* Set multicast table */
1098 	epic_set_mc_table(sc);
1099 
1100 	/* Enable interrupts by setting the interrupt mask. */
1101 	CSR_WRITE_4(sc, INTMASK,
1102 		INTSTAT_RCC  | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1103 		/* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1104 		INTSTAT_FATAL);
1105 
1106 	/* Acknowledge all pending interrupts */
1107 	CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1108 
1109 	/* Enable interrupts,  set for PCI read multiple and etc */
1110 	CSR_WRITE_4(sc, GENCTL,
1111 		GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1112 		GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1113 
1114 	/* Mark interface running ... */
1115 	if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING;
1116 	else ifp->if_flags &= ~IFF_RUNNING;
1117 
1118 	/* ... and free */
1119 	ifq_clr_oactive(&ifp->if_snd);
1120 
1121 	/* Start Rx process */
1122 	epic_start_activity(sc);
1123 
1124 	/* Set appropriate media */
1125 	epic_ifmedia_upd(ifp);
1126 
1127 	callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
1128 
1129 	return 0;
1130 }
1131 
1132 /*
1133  * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1134  * access RXCON.
1135  */
1136 static void
epic_set_rx_mode(epic_softc_t * sc)1137 epic_set_rx_mode(epic_softc_t *sc)
1138 {
1139 	u_int32_t 		flags = sc->sc_if.if_flags;
1140 	u_int32_t 		rxcon = RXCON_DEFAULT;
1141 
1142 #if defined(EPIC_EARLY_RX)
1143 	rxcon |= RXCON_EARLY_RX;
1144 #endif
1145 
1146 	rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1147 
1148 	CSR_WRITE_4(sc, RXCON, rxcon);
1149 
1150 	return;
1151 }
1152 
1153 /*
1154  * Synopsis: Set transmit control register. Chip must be in idle state to
1155  * access TXCON.
1156  */
1157 static void
epic_set_tx_mode(epic_softc_t * sc)1158 epic_set_tx_mode(epic_softc_t *sc)
1159 {
1160 	if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1161 		CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1162 
1163 	CSR_WRITE_4(sc, TXCON, sc->txcon);
1164 }
1165 
1166 /*
1167  * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1168  * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch
1169  * individual frames, multicast filter must be manually programmed)
1170  *
1171  * Note: EPIC must be in idle state.
1172  */
1173 static void
epic_set_mc_table(epic_softc_t * sc)1174 epic_set_mc_table(epic_softc_t *sc)
1175 {
1176 	struct ifnet *ifp = &sc->sc_if;
1177 	struct ifmultiaddr *ifma;
1178 	u_int16_t filter[4];
1179 	u_int8_t h;
1180 
1181 	if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1182 		CSR_WRITE_4(sc, MC0, 0xFFFF);
1183 		CSR_WRITE_4(sc, MC1, 0xFFFF);
1184 		CSR_WRITE_4(sc, MC2, 0xFFFF);
1185 		CSR_WRITE_4(sc, MC3, 0xFFFF);
1186 
1187 		return;
1188 	}
1189 
1190 	filter[0] = 0;
1191 	filter[1] = 0;
1192 	filter[2] = 0;
1193 	filter[3] = 0;
1194 
1195 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1196 		if (ifma->ifma_addr->sa_family != AF_LINK)
1197 			continue;
1198 		h = (ether_crc32_be(
1199 			LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1200 			ETHER_ADDR_LEN) >> 26) & 0x3f;
1201 		filter[h >> 4] |= 1 << (h & 0xF);
1202 	}
1203 
1204 	CSR_WRITE_4(sc, MC0, filter[0]);
1205 	CSR_WRITE_4(sc, MC1, filter[1]);
1206 	CSR_WRITE_4(sc, MC2, filter[2]);
1207 	CSR_WRITE_4(sc, MC3, filter[3]);
1208 
1209 	return;
1210 }
1211 
1212 /*
1213  * Synopsis: Start receive process and transmit one, if they need.
1214  */
1215 static void
epic_start_activity(epic_softc_t * sc)1216 epic_start_activity(epic_softc_t *sc)
1217 {
1218 	/* Start rx process */
1219 	CSR_WRITE_4(sc, COMMAND,
1220 		COMMAND_RXQUEUED | COMMAND_START_RX |
1221 		(sc->pending_txs?COMMAND_TXQUEUED:0));
1222 }
1223 
1224 /*
1225  * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1226  * packet needs to be queued to stop Tx DMA.
1227  */
1228 static void
epic_stop_activity(epic_softc_t * sc)1229 epic_stop_activity(epic_softc_t *sc)
1230 {
1231 	int status, i;
1232 
1233 	/* Stop Tx and Rx DMA */
1234 	CSR_WRITE_4(sc, COMMAND,
1235 	    COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1236 
1237 	/* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */
1238 	for (i=0; i<0x1000; i++) {
1239 		status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1240 		if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1241 			break;
1242 		DELAY(1);
1243 	}
1244 
1245 	/* Catch all finished packets */
1246 	epic_rx_done(sc);
1247 	epic_tx_done(sc);
1248 
1249 	status = CSR_READ_4(sc, INTSTAT);
1250 
1251 	if ((status & INTSTAT_RXIDLE) == 0)
1252 		if_printf(&sc->sc_if, "ERROR! Can't stop Rx DMA\n");
1253 
1254 	if ((status & INTSTAT_TXIDLE) == 0)
1255 		if_printf(&sc->sc_if, "ERROR! Can't stop Tx DMA\n");
1256 
1257 	/*
1258 	 * May need to queue one more packet if TQE, this is rare
1259 	 * but existing case.
1260 	 */
1261 	if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1262 		epic_queue_last_packet(sc);
1263 
1264 }
1265 
1266 /*
1267  * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1268  * a packet from current descriptor will be copied to internal RAM. We
1269  * compose a dummy packet here and queue it for transmission.
1270  *
1271  * XXX the packet will then be actually sent over network...
1272  */
1273 static int
epic_queue_last_packet(epic_softc_t * sc)1274 epic_queue_last_packet(epic_softc_t *sc)
1275 {
1276 	struct epic_tx_desc *desc;
1277 	struct epic_frag_list *flist;
1278 	struct epic_tx_buffer *buf;
1279 	struct mbuf *m0;
1280 	int i;
1281 
1282 	if_printf(&sc->sc_if, "queue last packet\n");
1283 
1284 	desc = sc->tx_desc + sc->cur_tx;
1285 	flist = sc->tx_flist + sc->cur_tx;
1286 	buf = sc->tx_buffer + sc->cur_tx;
1287 
1288 	if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1289 		return (EBUSY);
1290 
1291 	MGETHDR(m0, M_NOWAIT, MT_DATA);
1292 	if (NULL == m0)
1293 		return (ENOBUFS);
1294 
1295 	/* Prepare mbuf */
1296 	m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN);
1297 	flist->frag[0].fraglen = m0->m_len;
1298 	m0->m_pkthdr.len = m0->m_len;
1299 	m0->m_pkthdr.rcvif = &sc->sc_if;
1300 	bzero(mtod(m0,caddr_t), m0->m_len);
1301 
1302 	/* Fill fragments list */
1303 	flist->frag[0].fraglen = m0->m_len;
1304 	flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t));
1305 	flist->numfrags = 1;
1306 
1307 	/* Fill in descriptor */
1308 	buf->mbuf = m0;
1309 	sc->pending_txs++;
1310 	sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1311 	desc->control = 0x01;
1312 	desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
1313 	desc->status = 0x8000;
1314 
1315 	/* Launch transmition */
1316 	CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1317 
1318 	/* Wait Tx DMA to stop (for how long??? XXX) */
1319 	for (i=0; i<1000; i++) {
1320 		if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1321 			break;
1322 		DELAY(1);
1323 	}
1324 
1325 	if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1326 		if_printf(&sc->sc_if, "ERROR! can't stop Tx DMA (2)\n");
1327 	else
1328 		epic_tx_done(sc);
1329 
1330 	return 0;
1331 }
1332 
1333 /*
1334  *  Synopsis: Shut down board and deallocates rings.
1335  */
1336 static void
epic_stop(epic_softc_t * sc)1337 epic_stop(epic_softc_t *sc)
1338 {
1339 	sc->sc_if.if_timer = 0;
1340 
1341 	callout_stop(&sc->tx_stat_timer);
1342 
1343 	/* Disable interrupts */
1344 	CSR_WRITE_4(sc, INTMASK, 0);
1345 	CSR_WRITE_4(sc, GENCTL, 0);
1346 
1347 	/* Try to stop Rx and TX processes */
1348 	epic_stop_activity(sc);
1349 
1350 	/* Reset chip */
1351 	CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1352 	DELAY(1000);
1353 
1354 	/* Make chip go to bed */
1355 	CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1356 
1357 	/* Free memory allocated for rings */
1358 	epic_free_rings(sc);
1359 
1360 	/* Mark as stoped */
1361 	sc->sc_if.if_flags &= ~IFF_RUNNING;
1362 }
1363 
1364 /*
1365  * Synopsis: This function should free all memory allocated for rings.
1366  */
1367 static void
epic_free_rings(epic_softc_t * sc)1368 epic_free_rings(epic_softc_t *sc)
1369 {
1370 	int i;
1371 
1372 	for (i=0; i<RX_RING_SIZE; i++) {
1373 		struct epic_rx_buffer *buf = sc->rx_buffer + i;
1374 		struct epic_rx_desc *desc = sc->rx_desc + i;
1375 
1376 		desc->status = 0;
1377 		desc->buflength = 0;
1378 		desc->bufaddr = 0;
1379 
1380 		if (buf->mbuf) m_freem(buf->mbuf);
1381 		buf->mbuf = NULL;
1382 	}
1383 
1384 	for (i=0; i<TX_RING_SIZE; i++) {
1385 		struct epic_tx_buffer *buf = sc->tx_buffer + i;
1386 		struct epic_tx_desc *desc = sc->tx_desc + i;
1387 
1388 		desc->status = 0;
1389 		desc->buflength = 0;
1390 		desc->bufaddr = 0;
1391 
1392 		if (buf->mbuf) m_freem(buf->mbuf);
1393 		buf->mbuf = NULL;
1394 	}
1395 }
1396 
1397 /*
1398  * Synopsis:  Allocates mbufs for Rx ring and point Rx descs to them.
1399  * Point Tx descs to fragment lists. Check that all descs and fraglists
1400  * are bounded and aligned properly.
1401  */
1402 static int
epic_init_rings(epic_softc_t * sc)1403 epic_init_rings(epic_softc_t *sc)
1404 {
1405 	int i;
1406 
1407 	sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1408 
1409 	for (i = 0; i < RX_RING_SIZE; i++) {
1410 		struct epic_rx_buffer *buf = sc->rx_buffer + i;
1411 		struct epic_rx_desc *desc = sc->rx_desc + i;
1412 
1413 		desc->status = 0;		/* Owned by driver */
1414 		desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK));
1415 
1416 		if ((desc->next & 3) ||
1417 		    ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1418 			epic_free_rings(sc);
1419 			return EFAULT;
1420 		}
1421 
1422 		buf->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1423 		if (NULL == buf->mbuf) {
1424 			epic_free_rings(sc);
1425 			return ENOBUFS;
1426 		}
1427 		desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
1428 
1429 		desc->buflength = MCLBYTES;	/* Max RX buffer length */
1430 		desc->status = 0x8000;		/* Set owner bit to NIC */
1431 	}
1432 
1433 	for (i = 0; i < TX_RING_SIZE; i++) {
1434 		struct epic_tx_buffer *buf = sc->tx_buffer + i;
1435 		struct epic_tx_desc *desc = sc->tx_desc + i;
1436 
1437 		desc->status = 0;
1438 		desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK));
1439 
1440 		if ((desc->next & 3) ||
1441 		    ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1442 			epic_free_rings(sc);
1443 			return EFAULT;
1444 		}
1445 
1446 		buf->mbuf = NULL;
1447 		desc->bufaddr = vtophys(sc->tx_flist + i);
1448 
1449 		if ((desc->bufaddr & 3) ||
1450 		    ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1451 			epic_free_rings(sc);
1452 			return EFAULT;
1453 		}
1454 	}
1455 
1456 	return 0;
1457 }
1458 
1459 /*
1460  * EEPROM operation functions
1461  */
1462 static void
epic_write_eepromreg(epic_softc_t * sc,u_int8_t val)1463 epic_write_eepromreg(epic_softc_t *sc, u_int8_t val)
1464 {
1465 	u_int16_t i;
1466 
1467 	CSR_WRITE_1(sc, EECTL, val);
1468 
1469 	for (i=0; i<0xFF; i++)
1470 		if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break;
1471 
1472 	return;
1473 }
1474 
1475 static u_int8_t
epic_read_eepromreg(epic_softc_t * sc)1476 epic_read_eepromreg(epic_softc_t *sc)
1477 {
1478 	return CSR_READ_1(sc, EECTL);
1479 }
1480 
1481 static u_int8_t
epic_eeprom_clock(epic_softc_t * sc,u_int8_t val)1482 epic_eeprom_clock(epic_softc_t *sc, u_int8_t val)
1483 {
1484 	epic_write_eepromreg(sc, val);
1485 	epic_write_eepromreg(sc, (val | 0x4));
1486 	epic_write_eepromreg(sc, val);
1487 
1488 	return epic_read_eepromreg(sc);
1489 }
1490 
1491 static void
epic_output_eepromw(epic_softc_t * sc,u_int16_t val)1492 epic_output_eepromw(epic_softc_t *sc, u_int16_t val)
1493 {
1494 	int i;
1495 
1496 	for (i = 0xF; i >= 0; i--) {
1497 		if (val & (1 << i))
1498 			epic_eeprom_clock(sc, 0x0B);
1499 		else
1500 			epic_eeprom_clock(sc, 0x03);
1501 	}
1502 }
1503 
1504 static u_int16_t
epic_input_eepromw(epic_softc_t * sc)1505 epic_input_eepromw(epic_softc_t *sc)
1506 {
1507 	u_int16_t retval = 0;
1508 	int i;
1509 
1510 	for (i = 0xF; i >= 0; i--) {
1511 		if (epic_eeprom_clock(sc, 0x3) & 0x10)
1512 			retval |= (1 << i);
1513 	}
1514 
1515 	return retval;
1516 }
1517 
1518 static int
epic_read_eeprom(epic_softc_t * sc,u_int16_t loc)1519 epic_read_eeprom(epic_softc_t *sc, u_int16_t loc)
1520 {
1521 	u_int16_t dataval;
1522 	u_int16_t read_cmd;
1523 
1524 	epic_write_eepromreg(sc, 3);
1525 
1526 	if (epic_read_eepromreg(sc) & 0x40)
1527 		read_cmd = (loc & 0x3F) | 0x180;
1528 	else
1529 		read_cmd = (loc & 0xFF) | 0x600;
1530 
1531 	epic_output_eepromw(sc, read_cmd);
1532 
1533 	dataval = epic_input_eepromw(sc);
1534 
1535 	epic_write_eepromreg(sc, 1);
1536 
1537 	return dataval;
1538 }
1539 
1540 /*
1541  * Here goes MII read/write routines
1542  */
1543 static int
epic_read_phy_reg(epic_softc_t * sc,int phy,int reg)1544 epic_read_phy_reg(epic_softc_t *sc, int phy, int reg)
1545 {
1546 	int i;
1547 
1548 	CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1549 
1550 	for (i = 0; i < 0x100; i++) {
1551 		if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break;
1552 		DELAY(1);
1553 	}
1554 
1555 	return (CSR_READ_4(sc, MIIDATA));
1556 }
1557 
1558 static void
epic_write_phy_reg(epic_softc_t * sc,int phy,int reg,int val)1559 epic_write_phy_reg(epic_softc_t *sc, int phy, int reg, int val)
1560 {
1561 	int i;
1562 
1563 	CSR_WRITE_4(sc, MIIDATA, val);
1564 	CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1565 
1566 	for(i=0;i<0x100;i++) {
1567 		if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break;
1568 		DELAY(1);
1569 	}
1570 
1571 	return;
1572 }
1573 
1574 static int
epic_miibus_readreg(device_t dev,int phy,int reg)1575 epic_miibus_readreg(device_t dev, int phy, int reg)
1576 {
1577 	epic_softc_t *sc;
1578 
1579 	sc = device_get_softc(dev);
1580 
1581 	return (PHY_READ_2(sc, phy, reg));
1582 }
1583 
1584 static int
epic_miibus_writereg(device_t dev,int phy,int reg,int data)1585 epic_miibus_writereg(device_t dev, int phy, int reg, int data)
1586 {
1587 	epic_softc_t *sc;
1588 
1589 	sc = device_get_softc(dev);
1590 
1591 	PHY_WRITE_2(sc, phy, reg, data);
1592 
1593 	return (0);
1594 }
1595