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Searched defs:expected_max_minus1 (Results 1 – 18 of 18) sorted by relevance

/dports/lang/gcc6-aux/gcc-6-20180516/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c275 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
277 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
280 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
281 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
283 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
286 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
287 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
291 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
297 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
303 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c275 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
277 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
280 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
281 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
283 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
286 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
287 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
291 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
297 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
303 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c275 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
277 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
280 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
281 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
283 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
286 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
287 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
291 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
297 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
303 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c275 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
277 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
280 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
281 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
283 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
286 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
287 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
291 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
297 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
303 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c275 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
277 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
280 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
281 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
283 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
286 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
287 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
291 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
297 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
303 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c275 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
277 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
280 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
281 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
283 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
286 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
287 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
291 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
297 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
303 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c275 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
277 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
280 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
281 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
283 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
286 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
287 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
291 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
297 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
303 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c275 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
277 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
280 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
281 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
283 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
286 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
287 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
291 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
297 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
303 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c164 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
166 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
169 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
170 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
172 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
175 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
176 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
180 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
186 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
192 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c275 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
277 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
280 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
281 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
283 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
286 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
287 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
291 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
297 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
303 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c275 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
277 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
280 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
281 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
283 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
286 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
287 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
291 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
297 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
303 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c275 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
277 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
280 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
281 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
283 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
286 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
287 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
291 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
297 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
303 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/lang/gnat_util/gcc-6-20180516/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c275 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
277 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
280 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
281 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
283 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
286 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
287 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
291 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
297 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
303 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c164 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
166 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
169 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
170 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
172 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
175 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
176 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
180 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
186 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
192 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c275 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
277 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
280 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
281 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
283 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
286 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
287 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
291 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
297 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
303 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c164 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
166 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
169 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
170 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
172 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
175 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
176 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
180 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
186 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
192 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c275 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
277 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
280 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
281 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
283 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
286 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
287 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
291 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
297 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
303 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvqshl.c164 VECT_VAR_DECL(expected_max_minus1,int,8,8) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
166 VECT_VAR_DECL(expected_max_minus1,int,16,4) [] = { 0x3fff, 0x3fff, variable
169 VECT_VAR_DECL(expected_max_minus1,int,64,1) [] = { 0x3fffffffffffffff }; variable
170 VECT_VAR_DECL(expected_max_minus1,uint,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, variable
172 VECT_VAR_DECL(expected_max_minus1,uint,16,4) [] = { 0x7fff, 0x7fff, variable
175 VECT_VAR_DECL(expected_max_minus1,uint,64,1) [] = { 0x7fffffffffffffff }; variable
176 VECT_VAR_DECL(expected_max_minus1,int,8,16) [] = { 0x3f, 0x3f, 0x3f, 0x3f, variable
180 VECT_VAR_DECL(expected_max_minus1,int,16,8) [] = { 0x3fff, 0x3fff, variable
186 VECT_VAR_DECL(expected_max_minus1,int,64,2) [] = { 0x3fffffffffffffff, variable
192 VECT_VAR_DECL(expected_max_minus1,uint,16,8) [] = { 0x7fff, 0x7fff, variable
[all …]