| /dports/lang/gcc6-aux/gcc-6-20180516/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| /dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| /dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| /dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| /dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| /dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| /dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| H A D | vqrshrun_n.c | 27 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
29 VECT_VAR_DECL(expected_min_shmax,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable
30 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x0, 0x0 }; variable
|
| H A D | vqrshrun_high_n.c | 38 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x80, 0x80, 0x80, 0x80, variable
42 VECT_VAR_DECL(expected_min_shmax,uint,16,8) [] = { 0x8000, 0x8000, 0x8000, 0x8000, variable
44 VECT_VAR_DECL(expected_min_shmax,uint,32,4) [] = { 0x80000000, 0x80000000, variable
|
| /dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| /dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| /dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| /dports/lang/gnat_util/gcc-6-20180516/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| /dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| H A D | vqrshrun_high_n.c | 38 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x80, 0x80, 0x80, 0x80, variable
42 VECT_VAR_DECL(expected_min_shmax,uint,16,8) [] = { 0x8000, 0x8000, 0x8000, 0x8000, variable
44 VECT_VAR_DECL(expected_min_shmax,uint,32,4) [] = { 0x80000000, 0x80000000, variable
|
| H A D | vqrshrun_n.c | 27 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
29 VECT_VAR_DECL(expected_min_shmax,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable
30 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x0, 0x0 }; variable
|
| /dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
|
| /dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
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| H A D | vqrshrun_n.c | 27 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
29 VECT_VAR_DECL(expected_min_shmax,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable
30 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x0, 0x0 }; variable
|
| H A D | vqrshrun_high_n.c | 38 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x80, 0x80, 0x80, 0x80, variable
42 VECT_VAR_DECL(expected_min_shmax,uint,16,8) [] = { 0x8000, 0x8000, 0x8000, 0x8000, variable
44 VECT_VAR_DECL(expected_min_shmax,uint,32,4) [] = { 0x80000000, 0x80000000, variable
|
| /dports/lang/gcc10-devel/gcc-10-20211008/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
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| /dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrsra_n.c | 195 VECT_VAR_DECL(expected_min_shmax,int,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
198 VECT_VAR_DECL(expected_min_shmax,int,32,2) [] = { 0x0, 0x0 }; variable
199 VECT_VAR_DECL(expected_min_shmax,int,64,1) [] = { 0x0 }; variable
200 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x1, 0x1, 0x1, 0x1, variable
203 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x1, 0x1 }; variable
204 VECT_VAR_DECL(expected_min_shmax,uint,64,1) [] = { 0x1 }; variable
205 VECT_VAR_DECL(expected_min_shmax,int,8,16) [] = { 0x0, 0x0, 0x0, 0x0, variable
209 VECT_VAR_DECL(expected_min_shmax,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
212 VECT_VAR_DECL(expected_min_shmax,int,64,2) [] = { 0x0, 0x0 }; variable
213 VECT_VAR_DECL(expected_min_shmax,uint,8,16) [] = { 0x1, 0x1, 0x1, 0x1, variable
[all …]
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| H A D | vqrshrun_n.c | 27 VECT_VAR_DECL(expected_min_shmax,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0, variable
29 VECT_VAR_DECL(expected_min_shmax,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable
30 VECT_VAR_DECL(expected_min_shmax,uint,32,2) [] = { 0x0, 0x0 }; variable
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