| /dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vclez_1.c | 25 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|
| H A D | vcgez_1.c | 26 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|
| H A D | vcgtz_1.c | 26 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable
|
| H A D | vceqz_1.c | 23 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|
| H A D | vcltz_1.c | 25 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable
|
| /dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vclez_1.c | 25 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|
| H A D | vceqz_1.c | 23 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|
| H A D | vcltz_1.c | 25 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable
|
| H A D | vcgez_1.c | 26 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|
| H A D | vcgtz_1.c | 26 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable
|
| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vcgez_1.c | 26 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|
| H A D | vclez_1.c | 25 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|
| H A D | vcltz_1.c | 25 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable
|
| H A D | vceqz_1.c | 23 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|
| H A D | vcgtz_1.c | 26 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable
|
| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vceqz_1.c | 23 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|
| H A D | vclez_1.c | 25 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|
| H A D | vcgez_1.c | 26 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|
| H A D | vcgtz_1.c | 26 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable
|
| H A D | vcltz_1.c | 25 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable
|
| /dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vcgez_1.c | 26 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|
| H A D | vcltz_1.c | 25 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable
|
| H A D | vceqz_1.c | 23 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|
| H A D | vcgtz_1.c | 26 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 }; variable
|
| H A D | vclez_1.c | 25 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff, variable
|