1 //===- FastISel.cpp - Implementation of the FastISel class ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the implementation of the FastISel class.
10 //
11 // "Fast" instruction selection is designed to emit very poor code quickly.
12 // Also, it is not designed to be able to do much lowering, so most illegal
13 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
14 // also not intended to be able to do much optimization, except in a few cases
15 // where doing optimizations reduces overall compile time. For example, folding
16 // constants into immediate fields is often done, because it's cheap and it
17 // reduces the number of instructions later phases have to examine.
18 //
19 // "Fast" instruction selection is able to fail gracefully and transfer
20 // control to the SelectionDAG selector for operations that it doesn't
21 // support. In many cases, this allows us to avoid duplicating a lot of
22 // the complicated lowering logic that SelectionDAG currently has.
23 //
24 // The intended use for "fast" instruction selection is "-O0" mode
25 // compilation, where the quality of the generated code is irrelevant when
26 // weighed against the speed at which the code can be generated. Also,
27 // at -O0, the LLVM optimizers are not running, and this makes the
28 // compile time of codegen a much higher portion of the overall compile
29 // time. Despite its limitations, "fast" instruction selection is able to
30 // handle enough code on its own to provide noticeable overall speedups
31 // in -O0 compiles.
32 //
33 // Basic operations are supported in a target-independent way, by reading
34 // the same instruction descriptions that the SelectionDAG selector reads,
35 // and identifying simple arithmetic operations that can be directly selected
36 // from simple operators. More complicated operations currently require
37 // target-specific code.
38 //
39 //===----------------------------------------------------------------------===//
40
41 #include "llvm/CodeGen/FastISel.h"
42 #include "llvm/ADT/APFloat.h"
43 #include "llvm/ADT/APSInt.h"
44 #include "llvm/ADT/DenseMap.h"
45 #include "llvm/ADT/Optional.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/SmallVector.h"
49 #include "llvm/ADT/Statistic.h"
50 #include "llvm/Analysis/BranchProbabilityInfo.h"
51 #include "llvm/Analysis/TargetLibraryInfo.h"
52 #include "llvm/CodeGen/Analysis.h"
53 #include "llvm/CodeGen/FunctionLoweringInfo.h"
54 #include "llvm/CodeGen/ISDOpcodes.h"
55 #include "llvm/CodeGen/MachineBasicBlock.h"
56 #include "llvm/CodeGen/MachineFrameInfo.h"
57 #include "llvm/CodeGen/MachineInstr.h"
58 #include "llvm/CodeGen/MachineInstrBuilder.h"
59 #include "llvm/CodeGen/MachineMemOperand.h"
60 #include "llvm/CodeGen/MachineModuleInfo.h"
61 #include "llvm/CodeGen/MachineOperand.h"
62 #include "llvm/CodeGen/MachineRegisterInfo.h"
63 #include "llvm/CodeGen/StackMaps.h"
64 #include "llvm/CodeGen/TargetInstrInfo.h"
65 #include "llvm/CodeGen/TargetLowering.h"
66 #include "llvm/CodeGen/TargetSubtargetInfo.h"
67 #include "llvm/CodeGen/ValueTypes.h"
68 #include "llvm/IR/Argument.h"
69 #include "llvm/IR/Attributes.h"
70 #include "llvm/IR/BasicBlock.h"
71 #include "llvm/IR/CallingConv.h"
72 #include "llvm/IR/Constant.h"
73 #include "llvm/IR/Constants.h"
74 #include "llvm/IR/DataLayout.h"
75 #include "llvm/IR/DebugInfo.h"
76 #include "llvm/IR/DebugLoc.h"
77 #include "llvm/IR/DerivedTypes.h"
78 #include "llvm/IR/Function.h"
79 #include "llvm/IR/GetElementPtrTypeIterator.h"
80 #include "llvm/IR/GlobalValue.h"
81 #include "llvm/IR/InlineAsm.h"
82 #include "llvm/IR/InstrTypes.h"
83 #include "llvm/IR/Instruction.h"
84 #include "llvm/IR/Instructions.h"
85 #include "llvm/IR/IntrinsicInst.h"
86 #include "llvm/IR/LLVMContext.h"
87 #include "llvm/IR/Mangler.h"
88 #include "llvm/IR/Metadata.h"
89 #include "llvm/IR/Operator.h"
90 #include "llvm/IR/PatternMatch.h"
91 #include "llvm/IR/Type.h"
92 #include "llvm/IR/User.h"
93 #include "llvm/IR/Value.h"
94 #include "llvm/MC/MCContext.h"
95 #include "llvm/MC/MCInstrDesc.h"
96 #include "llvm/MC/MCRegisterInfo.h"
97 #include "llvm/Support/Casting.h"
98 #include "llvm/Support/Debug.h"
99 #include "llvm/Support/ErrorHandling.h"
100 #include "llvm/Support/MachineValueType.h"
101 #include "llvm/Support/MathExtras.h"
102 #include "llvm/Support/raw_ostream.h"
103 #include "llvm/Target/TargetMachine.h"
104 #include "llvm/Target/TargetOptions.h"
105 #include <algorithm>
106 #include <cassert>
107 #include <cstdint>
108 #include <iterator>
109 #include <utility>
110
111 using namespace llvm;
112 using namespace PatternMatch;
113
114 #define DEBUG_TYPE "isel"
115
116 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
117 "target-independent selector");
118 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "
119 "target-specific selector");
120 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");
121
122 /// Set the current block to which generated machine instructions will be
123 /// appended.
startNewBlock()124 void FastISel::startNewBlock() {
125 assert(LocalValueMap.empty() &&
126 "local values should be cleared after finishing a BB");
127
128 // Instructions are appended to FuncInfo.MBB. If the basic block already
129 // contains labels or copies, use the last instruction as the last local
130 // value.
131 EmitStartPt = nullptr;
132 if (!FuncInfo.MBB->empty())
133 EmitStartPt = &FuncInfo.MBB->back();
134 LastLocalValue = EmitStartPt;
135 }
136
finishBasicBlock()137 void FastISel::finishBasicBlock() { flushLocalValueMap(); }
138
lowerArguments()139 bool FastISel::lowerArguments() {
140 if (!FuncInfo.CanLowerReturn)
141 // Fallback to SDISel argument lowering code to deal with sret pointer
142 // parameter.
143 return false;
144
145 if (!fastLowerArguments())
146 return false;
147
148 // Enter arguments into ValueMap for uses in non-entry BBs.
149 for (Function::const_arg_iterator I = FuncInfo.Fn->arg_begin(),
150 E = FuncInfo.Fn->arg_end();
151 I != E; ++I) {
152 DenseMap<const Value *, Register>::iterator VI = LocalValueMap.find(&*I);
153 assert(VI != LocalValueMap.end() && "Missed an argument?");
154 FuncInfo.ValueMap[&*I] = VI->second;
155 }
156 return true;
157 }
158
159 /// Return the defined register if this instruction defines exactly one
160 /// virtual register and uses no other virtual registers. Otherwise return 0.
findLocalRegDef(MachineInstr & MI)161 static Register findLocalRegDef(MachineInstr &MI) {
162 Register RegDef;
163 for (const MachineOperand &MO : MI.operands()) {
164 if (!MO.isReg())
165 continue;
166 if (MO.isDef()) {
167 if (RegDef)
168 return Register();
169 RegDef = MO.getReg();
170 } else if (MO.getReg().isVirtual()) {
171 // This is another use of a vreg. Don't delete it.
172 return Register();
173 }
174 }
175 return RegDef;
176 }
177
isRegUsedByPhiNodes(Register DefReg,FunctionLoweringInfo & FuncInfo)178 static bool isRegUsedByPhiNodes(Register DefReg,
179 FunctionLoweringInfo &FuncInfo) {
180 for (auto &P : FuncInfo.PHINodesToUpdate)
181 if (P.second == DefReg)
182 return true;
183 return false;
184 }
185
flushLocalValueMap()186 void FastISel::flushLocalValueMap() {
187 // If FastISel bails out, it could leave local value instructions behind
188 // that aren't used for anything. Detect and erase those.
189 if (LastLocalValue != EmitStartPt) {
190 // Save the first instruction after local values, for later.
191 MachineBasicBlock::iterator FirstNonValue(LastLocalValue);
192 ++FirstNonValue;
193
194 MachineBasicBlock::reverse_iterator RE =
195 EmitStartPt ? MachineBasicBlock::reverse_iterator(EmitStartPt)
196 : FuncInfo.MBB->rend();
197 MachineBasicBlock::reverse_iterator RI(LastLocalValue);
198 for (; RI != RE;) {
199 MachineInstr &LocalMI = *RI;
200 // Increment before erasing what it points to.
201 ++RI;
202 Register DefReg = findLocalRegDef(LocalMI);
203 if (!DefReg)
204 continue;
205 if (FuncInfo.RegsWithFixups.count(DefReg))
206 continue;
207 bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo);
208 if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) {
209 if (EmitStartPt == &LocalMI)
210 EmitStartPt = EmitStartPt->getPrevNode();
211 LLVM_DEBUG(dbgs() << "removing dead local value materialization"
212 << LocalMI);
213 LocalMI.eraseFromParent();
214 }
215 }
216
217 if (FirstNonValue != FuncInfo.MBB->end()) {
218 // See if there are any local value instructions left. If so, we want to
219 // make sure the first one has a debug location; if it doesn't, use the
220 // first non-value instruction's debug location.
221
222 // If EmitStartPt is non-null, this block had copies at the top before
223 // FastISel started doing anything; it points to the last one, so the
224 // first local value instruction is the one after EmitStartPt.
225 // If EmitStartPt is null, the first local value instruction is at the
226 // top of the block.
227 MachineBasicBlock::iterator FirstLocalValue =
228 EmitStartPt ? ++MachineBasicBlock::iterator(EmitStartPt)
229 : FuncInfo.MBB->begin();
230 if (FirstLocalValue != FirstNonValue && !FirstLocalValue->getDebugLoc())
231 FirstLocalValue->setDebugLoc(FirstNonValue->getDebugLoc());
232 }
233 }
234
235 LocalValueMap.clear();
236 LastLocalValue = EmitStartPt;
237 recomputeInsertPt();
238 SavedInsertPt = FuncInfo.InsertPt;
239 }
240
getRegForValue(const Value * V)241 Register FastISel::getRegForValue(const Value *V) {
242 EVT RealVT = TLI.getValueType(DL, V->getType(), /*AllowUnknown=*/true);
243 // Don't handle non-simple values in FastISel.
244 if (!RealVT.isSimple())
245 return Register();
246
247 // Ignore illegal types. We must do this before looking up the value
248 // in ValueMap because Arguments are given virtual registers regardless
249 // of whether FastISel can handle them.
250 MVT VT = RealVT.getSimpleVT();
251 if (!TLI.isTypeLegal(VT)) {
252 // Handle integer promotions, though, because they're common and easy.
253 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
254 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
255 else
256 return Register();
257 }
258
259 // Look up the value to see if we already have a register for it.
260 Register Reg = lookUpRegForValue(V);
261 if (Reg)
262 return Reg;
263
264 // In bottom-up mode, just create the virtual register which will be used
265 // to hold the value. It will be materialized later.
266 if (isa<Instruction>(V) &&
267 (!isa<AllocaInst>(V) ||
268 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
269 return FuncInfo.InitializeRegForValue(V);
270
271 SavePoint SaveInsertPt = enterLocalValueArea();
272
273 // Materialize the value in a register. Emit any instructions in the
274 // local value area.
275 Reg = materializeRegForValue(V, VT);
276
277 leaveLocalValueArea(SaveInsertPt);
278
279 return Reg;
280 }
281
materializeConstant(const Value * V,MVT VT)282 Register FastISel::materializeConstant(const Value *V, MVT VT) {
283 Register Reg;
284 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
285 if (CI->getValue().getActiveBits() <= 64)
286 Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
287 } else if (isa<AllocaInst>(V))
288 Reg = fastMaterializeAlloca(cast<AllocaInst>(V));
289 else if (isa<ConstantPointerNull>(V))
290 // Translate this as an integer zero so that it can be
291 // local-CSE'd with actual integer zeros.
292 Reg =
293 getRegForValue(Constant::getNullValue(DL.getIntPtrType(V->getType())));
294 else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
295 if (CF->isNullValue())
296 Reg = fastMaterializeFloatZero(CF);
297 else
298 // Try to emit the constant directly.
299 Reg = fastEmit_f(VT, VT, ISD::ConstantFP, CF);
300
301 if (!Reg) {
302 // Try to emit the constant by using an integer constant with a cast.
303 const APFloat &Flt = CF->getValueAPF();
304 EVT IntVT = TLI.getPointerTy(DL);
305 uint32_t IntBitWidth = IntVT.getSizeInBits();
306 APSInt SIntVal(IntBitWidth, /*isUnsigned=*/false);
307 bool isExact;
308 (void)Flt.convertToInteger(SIntVal, APFloat::rmTowardZero, &isExact);
309 if (isExact) {
310 Register IntegerReg =
311 getRegForValue(ConstantInt::get(V->getContext(), SIntVal));
312 if (IntegerReg)
313 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
314 IntegerReg);
315 }
316 }
317 } else if (const auto *Op = dyn_cast<Operator>(V)) {
318 if (!selectOperator(Op, Op->getOpcode()))
319 if (!isa<Instruction>(Op) ||
320 !fastSelectInstruction(cast<Instruction>(Op)))
321 return 0;
322 Reg = lookUpRegForValue(Op);
323 } else if (isa<UndefValue>(V)) {
324 Reg = createResultReg(TLI.getRegClassFor(VT));
325 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
326 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
327 }
328 return Reg;
329 }
330
331 /// Helper for getRegForValue. This function is called when the value isn't
332 /// already available in a register and must be materialized with new
333 /// instructions.
materializeRegForValue(const Value * V,MVT VT)334 Register FastISel::materializeRegForValue(const Value *V, MVT VT) {
335 Register Reg;
336 // Give the target-specific code a try first.
337 if (isa<Constant>(V))
338 Reg = fastMaterializeConstant(cast<Constant>(V));
339
340 // If target-specific code couldn't or didn't want to handle the value, then
341 // give target-independent code a try.
342 if (!Reg)
343 Reg = materializeConstant(V, VT);
344
345 // Don't cache constant materializations in the general ValueMap.
346 // To do so would require tracking what uses they dominate.
347 if (Reg) {
348 LocalValueMap[V] = Reg;
349 LastLocalValue = MRI.getVRegDef(Reg);
350 }
351 return Reg;
352 }
353
lookUpRegForValue(const Value * V)354 Register FastISel::lookUpRegForValue(const Value *V) {
355 // Look up the value to see if we already have a register for it. We
356 // cache values defined by Instructions across blocks, and other values
357 // only locally. This is because Instructions already have the SSA
358 // def-dominates-use requirement enforced.
359 DenseMap<const Value *, Register>::iterator I = FuncInfo.ValueMap.find(V);
360 if (I != FuncInfo.ValueMap.end())
361 return I->second;
362 return LocalValueMap[V];
363 }
364
updateValueMap(const Value * I,Register Reg,unsigned NumRegs)365 void FastISel::updateValueMap(const Value *I, Register Reg, unsigned NumRegs) {
366 if (!isa<Instruction>(I)) {
367 LocalValueMap[I] = Reg;
368 return;
369 }
370
371 Register &AssignedReg = FuncInfo.ValueMap[I];
372 if (!AssignedReg)
373 // Use the new register.
374 AssignedReg = Reg;
375 else if (Reg != AssignedReg) {
376 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
377 for (unsigned i = 0; i < NumRegs; i++) {
378 FuncInfo.RegFixups[AssignedReg + i] = Reg + i;
379 FuncInfo.RegsWithFixups.insert(Reg + i);
380 }
381
382 AssignedReg = Reg;
383 }
384 }
385
getRegForGEPIndex(const Value * Idx)386 Register FastISel::getRegForGEPIndex(const Value *Idx) {
387 Register IdxN = getRegForValue(Idx);
388 if (!IdxN)
389 // Unhandled operand. Halt "fast" selection and bail.
390 return Register();
391
392 // If the index is smaller or larger than intptr_t, truncate or extend it.
393 MVT PtrVT = TLI.getPointerTy(DL);
394 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
395 if (IdxVT.bitsLT(PtrVT)) {
396 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
397 } else if (IdxVT.bitsGT(PtrVT)) {
398 IdxN =
399 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
400 }
401 return IdxN;
402 }
403
recomputeInsertPt()404 void FastISel::recomputeInsertPt() {
405 if (getLastLocalValue()) {
406 FuncInfo.InsertPt = getLastLocalValue();
407 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
408 ++FuncInfo.InsertPt;
409 } else
410 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
411
412 // Now skip past any EH_LABELs, which must remain at the beginning.
413 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
414 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
415 ++FuncInfo.InsertPt;
416 }
417
removeDeadCode(MachineBasicBlock::iterator I,MachineBasicBlock::iterator E)418 void FastISel::removeDeadCode(MachineBasicBlock::iterator I,
419 MachineBasicBlock::iterator E) {
420 assert(I.isValid() && E.isValid() && std::distance(I, E) > 0 &&
421 "Invalid iterator!");
422 while (I != E) {
423 if (SavedInsertPt == I)
424 SavedInsertPt = E;
425 if (EmitStartPt == I)
426 EmitStartPt = E.isValid() ? &*E : nullptr;
427 if (LastLocalValue == I)
428 LastLocalValue = E.isValid() ? &*E : nullptr;
429
430 MachineInstr *Dead = &*I;
431 ++I;
432 Dead->eraseFromParent();
433 ++NumFastIselDead;
434 }
435 recomputeInsertPt();
436 }
437
enterLocalValueArea()438 FastISel::SavePoint FastISel::enterLocalValueArea() {
439 SavePoint OldInsertPt = FuncInfo.InsertPt;
440 recomputeInsertPt();
441 return OldInsertPt;
442 }
443
leaveLocalValueArea(SavePoint OldInsertPt)444 void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) {
445 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
446 LastLocalValue = &*std::prev(FuncInfo.InsertPt);
447
448 // Restore the previous insert position.
449 FuncInfo.InsertPt = OldInsertPt;
450 }
451
selectBinaryOp(const User * I,unsigned ISDOpcode)452 bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) {
453 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
454 if (VT == MVT::Other || !VT.isSimple())
455 // Unhandled type. Halt "fast" selection and bail.
456 return false;
457
458 // We only handle legal types. For example, on x86-32 the instruction
459 // selector contains all of the 64-bit instructions from x86-64,
460 // under the assumption that i64 won't be used if the target doesn't
461 // support it.
462 if (!TLI.isTypeLegal(VT)) {
463 // MVT::i1 is special. Allow AND, OR, or XOR because they
464 // don't require additional zeroing, which makes them easy.
465 if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
466 ISDOpcode == ISD::XOR))
467 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
468 else
469 return false;
470 }
471
472 // Check if the first operand is a constant, and handle it as "ri". At -O0,
473 // we don't have anything that canonicalizes operand order.
474 if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
475 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
476 Register Op1 = getRegForValue(I->getOperand(1));
477 if (!Op1)
478 return false;
479
480 Register ResultReg =
481 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, CI->getZExtValue(),
482 VT.getSimpleVT());
483 if (!ResultReg)
484 return false;
485
486 // We successfully emitted code for the given LLVM Instruction.
487 updateValueMap(I, ResultReg);
488 return true;
489 }
490
491 Register Op0 = getRegForValue(I->getOperand(0));
492 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
493 return false;
494
495 // Check if the second operand is a constant and handle it appropriately.
496 if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
497 uint64_t Imm = CI->getSExtValue();
498
499 // Transform "sdiv exact X, 8" -> "sra X, 3".
500 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
501 cast<BinaryOperator>(I)->isExact() && isPowerOf2_64(Imm)) {
502 Imm = Log2_64(Imm);
503 ISDOpcode = ISD::SRA;
504 }
505
506 // Transform "urem x, pow2" -> "and x, pow2-1".
507 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
508 isPowerOf2_64(Imm)) {
509 --Imm;
510 ISDOpcode = ISD::AND;
511 }
512
513 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm,
514 VT.getSimpleVT());
515 if (!ResultReg)
516 return false;
517
518 // We successfully emitted code for the given LLVM Instruction.
519 updateValueMap(I, ResultReg);
520 return true;
521 }
522
523 Register Op1 = getRegForValue(I->getOperand(1));
524 if (!Op1) // Unhandled operand. Halt "fast" selection and bail.
525 return false;
526
527 // Now we have both operands in registers. Emit the instruction.
528 Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
529 ISDOpcode, Op0, Op1);
530 if (!ResultReg)
531 // Target-specific code wasn't able to find a machine opcode for
532 // the given ISD opcode and type. Halt "fast" selection and bail.
533 return false;
534
535 // We successfully emitted code for the given LLVM Instruction.
536 updateValueMap(I, ResultReg);
537 return true;
538 }
539
selectGetElementPtr(const User * I)540 bool FastISel::selectGetElementPtr(const User *I) {
541 Register N = getRegForValue(I->getOperand(0));
542 if (!N) // Unhandled operand. Halt "fast" selection and bail.
543 return false;
544
545 // FIXME: The code below does not handle vector GEPs. Halt "fast" selection
546 // and bail.
547 if (isa<VectorType>(I->getType()))
548 return false;
549
550 // Keep a running tab of the total offset to coalesce multiple N = N + Offset
551 // into a single N = N + TotalOffset.
552 uint64_t TotalOffs = 0;
553 // FIXME: What's a good SWAG number for MaxOffs?
554 uint64_t MaxOffs = 2048;
555 MVT VT = TLI.getPointerTy(DL);
556 for (gep_type_iterator GTI = gep_type_begin(I), E = gep_type_end(I);
557 GTI != E; ++GTI) {
558 const Value *Idx = GTI.getOperand();
559 if (StructType *StTy = GTI.getStructTypeOrNull()) {
560 uint64_t Field = cast<ConstantInt>(Idx)->getZExtValue();
561 if (Field) {
562 // N = N + Offset
563 TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
564 if (TotalOffs >= MaxOffs) {
565 N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
566 if (!N) // Unhandled operand. Halt "fast" selection and bail.
567 return false;
568 TotalOffs = 0;
569 }
570 }
571 } else {
572 Type *Ty = GTI.getIndexedType();
573
574 // If this is a constant subscript, handle it quickly.
575 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
576 if (CI->isZero())
577 continue;
578 // N = N + Offset
579 uint64_t IdxN = CI->getValue().sextOrTrunc(64).getSExtValue();
580 TotalOffs += DL.getTypeAllocSize(Ty) * IdxN;
581 if (TotalOffs >= MaxOffs) {
582 N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
583 if (!N) // Unhandled operand. Halt "fast" selection and bail.
584 return false;
585 TotalOffs = 0;
586 }
587 continue;
588 }
589 if (TotalOffs) {
590 N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
591 if (!N) // Unhandled operand. Halt "fast" selection and bail.
592 return false;
593 TotalOffs = 0;
594 }
595
596 // N = N + Idx * ElementSize;
597 uint64_t ElementSize = DL.getTypeAllocSize(Ty);
598 Register IdxN = getRegForGEPIndex(Idx);
599 if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
600 return false;
601
602 if (ElementSize != 1) {
603 IdxN = fastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
604 if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
605 return false;
606 }
607 N = fastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
608 if (!N) // Unhandled operand. Halt "fast" selection and bail.
609 return false;
610 }
611 }
612 if (TotalOffs) {
613 N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
614 if (!N) // Unhandled operand. Halt "fast" selection and bail.
615 return false;
616 }
617
618 // We successfully emitted code for the given LLVM Instruction.
619 updateValueMap(I, N);
620 return true;
621 }
622
addStackMapLiveVars(SmallVectorImpl<MachineOperand> & Ops,const CallInst * CI,unsigned StartIdx)623 bool FastISel::addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
624 const CallInst *CI, unsigned StartIdx) {
625 for (unsigned i = StartIdx, e = CI->getNumArgOperands(); i != e; ++i) {
626 Value *Val = CI->getArgOperand(i);
627 // Check for constants and encode them with a StackMaps::ConstantOp prefix.
628 if (const auto *C = dyn_cast<ConstantInt>(Val)) {
629 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
630 Ops.push_back(MachineOperand::CreateImm(C->getSExtValue()));
631 } else if (isa<ConstantPointerNull>(Val)) {
632 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
633 Ops.push_back(MachineOperand::CreateImm(0));
634 } else if (auto *AI = dyn_cast<AllocaInst>(Val)) {
635 // Values coming from a stack location also require a special encoding,
636 // but that is added later on by the target specific frame index
637 // elimination implementation.
638 auto SI = FuncInfo.StaticAllocaMap.find(AI);
639 if (SI != FuncInfo.StaticAllocaMap.end())
640 Ops.push_back(MachineOperand::CreateFI(SI->second));
641 else
642 return false;
643 } else {
644 Register Reg = getRegForValue(Val);
645 if (!Reg)
646 return false;
647 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
648 }
649 }
650 return true;
651 }
652
selectStackmap(const CallInst * I)653 bool FastISel::selectStackmap(const CallInst *I) {
654 // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
655 // [live variables...])
656 assert(I->getCalledFunction()->getReturnType()->isVoidTy() &&
657 "Stackmap cannot return a value.");
658
659 // The stackmap intrinsic only records the live variables (the arguments
660 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
661 // intrinsic, this won't be lowered to a function call. This means we don't
662 // have to worry about calling conventions and target-specific lowering code.
663 // Instead we perform the call lowering right here.
664 //
665 // CALLSEQ_START(0, 0...)
666 // STACKMAP(id, nbytes, ...)
667 // CALLSEQ_END(0, 0)
668 //
669 SmallVector<MachineOperand, 32> Ops;
670
671 // Add the <id> and <numBytes> constants.
672 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
673 "Expected a constant integer.");
674 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
675 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
676
677 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
678 "Expected a constant integer.");
679 const auto *NumBytes =
680 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
681 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
682
683 // Push live variables for the stack map (skipping the first two arguments
684 // <id> and <numBytes>).
685 if (!addStackMapLiveVars(Ops, I, 2))
686 return false;
687
688 // We are not adding any register mask info here, because the stackmap doesn't
689 // clobber anything.
690
691 // Add scratch registers as implicit def and early clobber.
692 CallingConv::ID CC = I->getCallingConv();
693 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
694 for (unsigned i = 0; ScratchRegs[i]; ++i)
695 Ops.push_back(MachineOperand::CreateReg(
696 ScratchRegs[i], /*isDef=*/true, /*isImp=*/true, /*isKill=*/false,
697 /*isDead=*/false, /*isUndef=*/false, /*isEarlyClobber=*/true));
698
699 // Issue CALLSEQ_START
700 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
701 auto Builder =
702 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown));
703 const MCInstrDesc &MCID = Builder.getInstr()->getDesc();
704 for (unsigned I = 0, E = MCID.getNumOperands(); I < E; ++I)
705 Builder.addImm(0);
706
707 // Issue STACKMAP.
708 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
709 TII.get(TargetOpcode::STACKMAP));
710 for (auto const &MO : Ops)
711 MIB.add(MO);
712
713 // Issue CALLSEQ_END
714 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
715 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
716 .addImm(0)
717 .addImm(0);
718
719 // Inform the Frame Information that we have a stackmap in this function.
720 FuncInfo.MF->getFrameInfo().setHasStackMap();
721
722 return true;
723 }
724
725 /// Lower an argument list according to the target calling convention.
726 ///
727 /// This is a helper for lowering intrinsics that follow a target calling
728 /// convention or require stack pointer adjustment. Only a subset of the
729 /// intrinsic's operands need to participate in the calling convention.
lowerCallOperands(const CallInst * CI,unsigned ArgIdx,unsigned NumArgs,const Value * Callee,bool ForceRetVoidTy,CallLoweringInfo & CLI)730 bool FastISel::lowerCallOperands(const CallInst *CI, unsigned ArgIdx,
731 unsigned NumArgs, const Value *Callee,
732 bool ForceRetVoidTy, CallLoweringInfo &CLI) {
733 ArgListTy Args;
734 Args.reserve(NumArgs);
735
736 // Populate the argument list.
737 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs; ArgI != ArgE; ++ArgI) {
738 Value *V = CI->getOperand(ArgI);
739
740 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
741
742 ArgListEntry Entry;
743 Entry.Val = V;
744 Entry.Ty = V->getType();
745 Entry.setAttributes(CI, ArgI);
746 Args.push_back(Entry);
747 }
748
749 Type *RetTy = ForceRetVoidTy ? Type::getVoidTy(CI->getType()->getContext())
750 : CI->getType();
751 CLI.setCallee(CI->getCallingConv(), RetTy, Callee, std::move(Args), NumArgs);
752
753 return lowerCallTo(CLI);
754 }
755
setCallee(const DataLayout & DL,MCContext & Ctx,CallingConv::ID CC,Type * ResultTy,StringRef Target,ArgListTy && ArgsList,unsigned FixedArgs)756 FastISel::CallLoweringInfo &FastISel::CallLoweringInfo::setCallee(
757 const DataLayout &DL, MCContext &Ctx, CallingConv::ID CC, Type *ResultTy,
758 StringRef Target, ArgListTy &&ArgsList, unsigned FixedArgs) {
759 SmallString<32> MangledName;
760 Mangler::getNameWithPrefix(MangledName, Target, DL);
761 MCSymbol *Sym = Ctx.getOrCreateSymbol(MangledName);
762 return setCallee(CC, ResultTy, Sym, std::move(ArgsList), FixedArgs);
763 }
764
selectPatchpoint(const CallInst * I)765 bool FastISel::selectPatchpoint(const CallInst *I) {
766 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
767 // i32 <numBytes>,
768 // i8* <target>,
769 // i32 <numArgs>,
770 // [Args...],
771 // [live variables...])
772 CallingConv::ID CC = I->getCallingConv();
773 bool IsAnyRegCC = CC == CallingConv::AnyReg;
774 bool HasDef = !I->getType()->isVoidTy();
775 Value *Callee = I->getOperand(PatchPointOpers::TargetPos)->stripPointerCasts();
776
777 // Get the real number of arguments participating in the call <numArgs>
778 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos)) &&
779 "Expected a constant integer.");
780 const auto *NumArgsVal =
781 cast<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos));
782 unsigned NumArgs = NumArgsVal->getZExtValue();
783
784 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
785 // This includes all meta-operands up to but not including CC.
786 unsigned NumMetaOpers = PatchPointOpers::CCPos;
787 assert(I->getNumArgOperands() >= NumMetaOpers + NumArgs &&
788 "Not enough arguments provided to the patchpoint intrinsic");
789
790 // For AnyRegCC the arguments are lowered later on manually.
791 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
792 CallLoweringInfo CLI;
793 CLI.setIsPatchPoint();
794 if (!lowerCallOperands(I, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC, CLI))
795 return false;
796
797 assert(CLI.Call && "No call instruction specified.");
798
799 SmallVector<MachineOperand, 32> Ops;
800
801 // Add an explicit result reg if we use the anyreg calling convention.
802 if (IsAnyRegCC && HasDef) {
803 assert(CLI.NumResultRegs == 0 && "Unexpected result register.");
804 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
805 CLI.NumResultRegs = 1;
806 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true));
807 }
808
809 // Add the <id> and <numBytes> constants.
810 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
811 "Expected a constant integer.");
812 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
813 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
814
815 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
816 "Expected a constant integer.");
817 const auto *NumBytes =
818 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
819 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
820
821 // Add the call target.
822 if (const auto *C = dyn_cast<IntToPtrInst>(Callee)) {
823 uint64_t CalleeConstAddr =
824 cast<ConstantInt>(C->getOperand(0))->getZExtValue();
825 Ops.push_back(MachineOperand::CreateImm(CalleeConstAddr));
826 } else if (const auto *C = dyn_cast<ConstantExpr>(Callee)) {
827 if (C->getOpcode() == Instruction::IntToPtr) {
828 uint64_t CalleeConstAddr =
829 cast<ConstantInt>(C->getOperand(0))->getZExtValue();
830 Ops.push_back(MachineOperand::CreateImm(CalleeConstAddr));
831 } else
832 llvm_unreachable("Unsupported ConstantExpr.");
833 } else if (const auto *GV = dyn_cast<GlobalValue>(Callee)) {
834 Ops.push_back(MachineOperand::CreateGA(GV, 0));
835 } else if (isa<ConstantPointerNull>(Callee))
836 Ops.push_back(MachineOperand::CreateImm(0));
837 else
838 llvm_unreachable("Unsupported callee address.");
839
840 // Adjust <numArgs> to account for any arguments that have been passed on
841 // the stack instead.
842 unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size();
843 Ops.push_back(MachineOperand::CreateImm(NumCallRegArgs));
844
845 // Add the calling convention
846 Ops.push_back(MachineOperand::CreateImm((unsigned)CC));
847
848 // Add the arguments we omitted previously. The register allocator should
849 // place these in any free register.
850 if (IsAnyRegCC) {
851 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) {
852 Register Reg = getRegForValue(I->getArgOperand(i));
853 if (!Reg)
854 return false;
855 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
856 }
857 }
858
859 // Push the arguments from the call instruction.
860 for (auto Reg : CLI.OutRegs)
861 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
862
863 // Push live variables for the stack map.
864 if (!addStackMapLiveVars(Ops, I, NumMetaOpers + NumArgs))
865 return false;
866
867 // Push the register mask info.
868 Ops.push_back(MachineOperand::CreateRegMask(
869 TRI.getCallPreservedMask(*FuncInfo.MF, CC)));
870
871 // Add scratch registers as implicit def and early clobber.
872 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
873 for (unsigned i = 0; ScratchRegs[i]; ++i)
874 Ops.push_back(MachineOperand::CreateReg(
875 ScratchRegs[i], /*isDef=*/true, /*isImp=*/true, /*isKill=*/false,
876 /*isDead=*/false, /*isUndef=*/false, /*isEarlyClobber=*/true));
877
878 // Add implicit defs (return values).
879 for (auto Reg : CLI.InRegs)
880 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true,
881 /*isImp=*/true));
882
883 // Insert the patchpoint instruction before the call generated by the target.
884 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, CLI.Call, DbgLoc,
885 TII.get(TargetOpcode::PATCHPOINT));
886
887 for (auto &MO : Ops)
888 MIB.add(MO);
889
890 MIB->setPhysRegsDeadExcept(CLI.InRegs, TRI);
891
892 // Delete the original call instruction.
893 CLI.Call->eraseFromParent();
894
895 // Inform the Frame Information that we have a patchpoint in this function.
896 FuncInfo.MF->getFrameInfo().setHasPatchPoint();
897
898 if (CLI.NumResultRegs)
899 updateValueMap(I, CLI.ResultReg, CLI.NumResultRegs);
900 return true;
901 }
902
selectXRayCustomEvent(const CallInst * I)903 bool FastISel::selectXRayCustomEvent(const CallInst *I) {
904 const auto &Triple = TM.getTargetTriple();
905 if (Triple.getArch() != Triple::x86_64 || !Triple.isOSLinux())
906 return true; // don't do anything to this instruction.
907 SmallVector<MachineOperand, 8> Ops;
908 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)),
909 /*isDef=*/false));
910 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)),
911 /*isDef=*/false));
912 MachineInstrBuilder MIB =
913 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
914 TII.get(TargetOpcode::PATCHABLE_EVENT_CALL));
915 for (auto &MO : Ops)
916 MIB.add(MO);
917
918 // Insert the Patchable Event Call instruction, that gets lowered properly.
919 return true;
920 }
921
selectXRayTypedEvent(const CallInst * I)922 bool FastISel::selectXRayTypedEvent(const CallInst *I) {
923 const auto &Triple = TM.getTargetTriple();
924 if (Triple.getArch() != Triple::x86_64 || !Triple.isOSLinux())
925 return true; // don't do anything to this instruction.
926 SmallVector<MachineOperand, 8> Ops;
927 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)),
928 /*isDef=*/false));
929 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)),
930 /*isDef=*/false));
931 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(2)),
932 /*isDef=*/false));
933 MachineInstrBuilder MIB =
934 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
935 TII.get(TargetOpcode::PATCHABLE_TYPED_EVENT_CALL));
936 for (auto &MO : Ops)
937 MIB.add(MO);
938
939 // Insert the Patchable Typed Event Call instruction, that gets lowered properly.
940 return true;
941 }
942
943 /// Returns an AttributeList representing the attributes applied to the return
944 /// value of the given call.
getReturnAttrs(FastISel::CallLoweringInfo & CLI)945 static AttributeList getReturnAttrs(FastISel::CallLoweringInfo &CLI) {
946 SmallVector<Attribute::AttrKind, 2> Attrs;
947 if (CLI.RetSExt)
948 Attrs.push_back(Attribute::SExt);
949 if (CLI.RetZExt)
950 Attrs.push_back(Attribute::ZExt);
951 if (CLI.IsInReg)
952 Attrs.push_back(Attribute::InReg);
953
954 return AttributeList::get(CLI.RetTy->getContext(), AttributeList::ReturnIndex,
955 Attrs);
956 }
957
lowerCallTo(const CallInst * CI,const char * SymName,unsigned NumArgs)958 bool FastISel::lowerCallTo(const CallInst *CI, const char *SymName,
959 unsigned NumArgs) {
960 MCContext &Ctx = MF->getContext();
961 SmallString<32> MangledName;
962 Mangler::getNameWithPrefix(MangledName, SymName, DL);
963 MCSymbol *Sym = Ctx.getOrCreateSymbol(MangledName);
964 return lowerCallTo(CI, Sym, NumArgs);
965 }
966
lowerCallTo(const CallInst * CI,MCSymbol * Symbol,unsigned NumArgs)967 bool FastISel::lowerCallTo(const CallInst *CI, MCSymbol *Symbol,
968 unsigned NumArgs) {
969 FunctionType *FTy = CI->getFunctionType();
970 Type *RetTy = CI->getType();
971
972 ArgListTy Args;
973 Args.reserve(NumArgs);
974
975 // Populate the argument list.
976 // Attributes for args start at offset 1, after the return attribute.
977 for (unsigned ArgI = 0; ArgI != NumArgs; ++ArgI) {
978 Value *V = CI->getOperand(ArgI);
979
980 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
981
982 ArgListEntry Entry;
983 Entry.Val = V;
984 Entry.Ty = V->getType();
985 Entry.setAttributes(CI, ArgI);
986 Args.push_back(Entry);
987 }
988 TLI.markLibCallAttributes(MF, CI->getCallingConv(), Args);
989
990 CallLoweringInfo CLI;
991 CLI.setCallee(RetTy, FTy, Symbol, std::move(Args), *CI, NumArgs);
992
993 return lowerCallTo(CLI);
994 }
995
lowerCallTo(CallLoweringInfo & CLI)996 bool FastISel::lowerCallTo(CallLoweringInfo &CLI) {
997 // Handle the incoming return values from the call.
998 CLI.clearIns();
999 SmallVector<EVT, 4> RetTys;
1000 ComputeValueVTs(TLI, DL, CLI.RetTy, RetTys);
1001
1002 SmallVector<ISD::OutputArg, 4> Outs;
1003 GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, TLI, DL);
1004
1005 bool CanLowerReturn = TLI.CanLowerReturn(
1006 CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
1007
1008 // FIXME: sret demotion isn't supported yet - bail out.
1009 if (!CanLowerReturn)
1010 return false;
1011
1012 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
1013 EVT VT = RetTys[I];
1014 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT);
1015 unsigned NumRegs = TLI.getNumRegisters(CLI.RetTy->getContext(), VT);
1016 for (unsigned i = 0; i != NumRegs; ++i) {
1017 ISD::InputArg MyFlags;
1018 MyFlags.VT = RegisterVT;
1019 MyFlags.ArgVT = VT;
1020 MyFlags.Used = CLI.IsReturnValueUsed;
1021 if (CLI.RetSExt)
1022 MyFlags.Flags.setSExt();
1023 if (CLI.RetZExt)
1024 MyFlags.Flags.setZExt();
1025 if (CLI.IsInReg)
1026 MyFlags.Flags.setInReg();
1027 CLI.Ins.push_back(MyFlags);
1028 }
1029 }
1030
1031 // Handle all of the outgoing arguments.
1032 CLI.clearOuts();
1033 for (auto &Arg : CLI.getArgs()) {
1034 Type *FinalType = Arg.Ty;
1035 if (Arg.IsByVal)
1036 FinalType = Arg.IndirectType;
1037 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
1038 FinalType, CLI.CallConv, CLI.IsVarArg);
1039
1040 ISD::ArgFlagsTy Flags;
1041 if (Arg.IsZExt)
1042 Flags.setZExt();
1043 if (Arg.IsSExt)
1044 Flags.setSExt();
1045 if (Arg.IsInReg)
1046 Flags.setInReg();
1047 if (Arg.IsSRet)
1048 Flags.setSRet();
1049 if (Arg.IsSwiftSelf)
1050 Flags.setSwiftSelf();
1051 if (Arg.IsSwiftAsync)
1052 Flags.setSwiftAsync();
1053 if (Arg.IsSwiftError)
1054 Flags.setSwiftError();
1055 if (Arg.IsCFGuardTarget)
1056 Flags.setCFGuardTarget();
1057 if (Arg.IsByVal)
1058 Flags.setByVal();
1059 if (Arg.IsInAlloca) {
1060 Flags.setInAlloca();
1061 // Set the byval flag for CCAssignFn callbacks that don't know about
1062 // inalloca. This way we can know how many bytes we should've allocated
1063 // and how many bytes a callee cleanup function will pop. If we port
1064 // inalloca to more targets, we'll have to add custom inalloca handling in
1065 // the various CC lowering callbacks.
1066 Flags.setByVal();
1067 }
1068 if (Arg.IsPreallocated) {
1069 Flags.setPreallocated();
1070 // Set the byval flag for CCAssignFn callbacks that don't know about
1071 // preallocated. This way we can know how many bytes we should've
1072 // allocated and how many bytes a callee cleanup function will pop. If we
1073 // port preallocated to more targets, we'll have to add custom
1074 // preallocated handling in the various CC lowering callbacks.
1075 Flags.setByVal();
1076 }
1077 MaybeAlign MemAlign = Arg.Alignment;
1078 if (Arg.IsByVal || Arg.IsInAlloca || Arg.IsPreallocated) {
1079 Type *ElementTy = Arg.IndirectType;
1080 assert(ElementTy && "Indirect type not set in ArgListEntry");
1081
1082 unsigned FrameSize = DL.getTypeAllocSize(ElementTy);
1083
1084 // For ByVal, alignment should come from FE. BE will guess if this info
1085 // is not there, but there are cases it cannot get right.
1086 if (!MemAlign)
1087 MemAlign = Align(TLI.getByValTypeAlignment(ElementTy, DL));
1088 Flags.setByValSize(FrameSize);
1089 } else if (!MemAlign) {
1090 MemAlign = DL.getABITypeAlign(Arg.Ty);
1091 }
1092 Flags.setMemAlign(*MemAlign);
1093 if (Arg.IsNest)
1094 Flags.setNest();
1095 if (NeedsRegBlock)
1096 Flags.setInConsecutiveRegs();
1097 Flags.setOrigAlign(DL.getABITypeAlign(Arg.Ty));
1098 CLI.OutVals.push_back(Arg.Val);
1099 CLI.OutFlags.push_back(Flags);
1100 }
1101
1102 if (!fastLowerCall(CLI))
1103 return false;
1104
1105 // Set all unused physreg defs as dead.
1106 assert(CLI.Call && "No call instruction specified.");
1107 CLI.Call->setPhysRegsDeadExcept(CLI.InRegs, TRI);
1108
1109 if (CLI.NumResultRegs && CLI.CB)
1110 updateValueMap(CLI.CB, CLI.ResultReg, CLI.NumResultRegs);
1111
1112 // Set labels for heapallocsite call.
1113 if (CLI.CB)
1114 if (MDNode *MD = CLI.CB->getMetadata("heapallocsite"))
1115 CLI.Call->setHeapAllocMarker(*MF, MD);
1116
1117 return true;
1118 }
1119
lowerCall(const CallInst * CI)1120 bool FastISel::lowerCall(const CallInst *CI) {
1121 FunctionType *FuncTy = CI->getFunctionType();
1122 Type *RetTy = CI->getType();
1123
1124 ArgListTy Args;
1125 ArgListEntry Entry;
1126 Args.reserve(CI->arg_size());
1127
1128 for (auto i = CI->arg_begin(), e = CI->arg_end(); i != e; ++i) {
1129 Value *V = *i;
1130
1131 // Skip empty types
1132 if (V->getType()->isEmptyTy())
1133 continue;
1134
1135 Entry.Val = V;
1136 Entry.Ty = V->getType();
1137
1138 // Skip the first return-type Attribute to get to params.
1139 Entry.setAttributes(CI, i - CI->arg_begin());
1140 Args.push_back(Entry);
1141 }
1142
1143 // Check if target-independent constraints permit a tail call here.
1144 // Target-dependent constraints are checked within fastLowerCall.
1145 bool IsTailCall = CI->isTailCall();
1146 if (IsTailCall && !isInTailCallPosition(*CI, TM))
1147 IsTailCall = false;
1148 if (IsTailCall && MF->getFunction()
1149 .getFnAttribute("disable-tail-calls")
1150 .getValueAsBool())
1151 IsTailCall = false;
1152
1153 CallLoweringInfo CLI;
1154 CLI.setCallee(RetTy, FuncTy, CI->getCalledOperand(), std::move(Args), *CI)
1155 .setTailCall(IsTailCall);
1156
1157 return lowerCallTo(CLI);
1158 }
1159
selectCall(const User * I)1160 bool FastISel::selectCall(const User *I) {
1161 const CallInst *Call = cast<CallInst>(I);
1162
1163 // Handle simple inline asms.
1164 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledOperand())) {
1165 // Don't attempt to handle constraints.
1166 if (!IA->getConstraintString().empty())
1167 return false;
1168
1169 unsigned ExtraInfo = 0;
1170 if (IA->hasSideEffects())
1171 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
1172 if (IA->isAlignStack())
1173 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
1174 if (Call->isConvergent())
1175 ExtraInfo |= InlineAsm::Extra_IsConvergent;
1176 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
1177
1178 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1179 TII.get(TargetOpcode::INLINEASM));
1180 MIB.addExternalSymbol(IA->getAsmString().c_str());
1181 MIB.addImm(ExtraInfo);
1182
1183 const MDNode *SrcLoc = Call->getMetadata("srcloc");
1184 if (SrcLoc)
1185 MIB.addMetadata(SrcLoc);
1186
1187 return true;
1188 }
1189
1190 // Handle intrinsic function calls.
1191 if (const auto *II = dyn_cast<IntrinsicInst>(Call))
1192 return selectIntrinsicCall(II);
1193
1194 return lowerCall(Call);
1195 }
1196
selectIntrinsicCall(const IntrinsicInst * II)1197 bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) {
1198 switch (II->getIntrinsicID()) {
1199 default:
1200 break;
1201 // At -O0 we don't care about the lifetime intrinsics.
1202 case Intrinsic::lifetime_start:
1203 case Intrinsic::lifetime_end:
1204 // The donothing intrinsic does, well, nothing.
1205 case Intrinsic::donothing:
1206 // Neither does the sideeffect intrinsic.
1207 case Intrinsic::sideeffect:
1208 // Neither does the assume intrinsic; it's also OK not to codegen its operand.
1209 case Intrinsic::assume:
1210 // Neither does the llvm.experimental.noalias.scope.decl intrinsic
1211 case Intrinsic::experimental_noalias_scope_decl:
1212 return true;
1213 case Intrinsic::dbg_declare: {
1214 const DbgDeclareInst *DI = cast<DbgDeclareInst>(II);
1215 assert(DI->getVariable() && "Missing variable");
1216 if (!FuncInfo.MF->getMMI().hasDebugInfo()) {
1217 LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI
1218 << " (!hasDebugInfo)\n");
1219 return true;
1220 }
1221
1222 const Value *Address = DI->getAddress();
1223 if (!Address || isa<UndefValue>(Address)) {
1224 LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI
1225 << " (bad/undef address)\n");
1226 return true;
1227 }
1228
1229 // Byval arguments with frame indices were already handled after argument
1230 // lowering and before isel.
1231 const auto *Arg =
1232 dyn_cast<Argument>(Address->stripInBoundsConstantOffsets());
1233 if (Arg && FuncInfo.getArgumentFrameIndex(Arg) != INT_MAX)
1234 return true;
1235
1236 Optional<MachineOperand> Op;
1237 if (Register Reg = lookUpRegForValue(Address))
1238 Op = MachineOperand::CreateReg(Reg, false);
1239
1240 // If we have a VLA that has a "use" in a metadata node that's then used
1241 // here but it has no other uses, then we have a problem. E.g.,
1242 //
1243 // int foo (const int *x) {
1244 // char a[*x];
1245 // return 0;
1246 // }
1247 //
1248 // If we assign 'a' a vreg and fast isel later on has to use the selection
1249 // DAG isel, it will want to copy the value to the vreg. However, there are
1250 // no uses, which goes counter to what selection DAG isel expects.
1251 if (!Op && !Address->use_empty() && isa<Instruction>(Address) &&
1252 (!isa<AllocaInst>(Address) ||
1253 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))
1254 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
1255 false);
1256
1257 if (Op) {
1258 assert(DI->getVariable()->isValidLocationForIntrinsic(DbgLoc) &&
1259 "Expected inlined-at fields to agree");
1260 // A dbg.declare describes the address of a source variable, so lower it
1261 // into an indirect DBG_VALUE.
1262 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1263 TII.get(TargetOpcode::DBG_VALUE), /*IsIndirect*/ true,
1264 *Op, DI->getVariable(), DI->getExpression());
1265 } else {
1266 // We can't yet handle anything else here because it would require
1267 // generating code, thus altering codegen because of debug info.
1268 LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI
1269 << " (no materialized reg for address)\n");
1270 }
1271 return true;
1272 }
1273 case Intrinsic::dbg_value: {
1274 // This form of DBG_VALUE is target-independent.
1275 const DbgValueInst *DI = cast<DbgValueInst>(II);
1276 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1277 const Value *V = DI->getValue();
1278 assert(DI->getVariable()->isValidLocationForIntrinsic(DbgLoc) &&
1279 "Expected inlined-at fields to agree");
1280 if (!V || isa<UndefValue>(V) || DI->hasArgList()) {
1281 // DI is either undef or cannot produce a valid DBG_VALUE, so produce an
1282 // undef DBG_VALUE to terminate any prior location.
1283 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, false, 0U,
1284 DI->getVariable(), DI->getExpression());
1285 } else if (const auto *CI = dyn_cast<ConstantInt>(V)) {
1286 if (CI->getBitWidth() > 64)
1287 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1288 .addCImm(CI)
1289 .addImm(0U)
1290 .addMetadata(DI->getVariable())
1291 .addMetadata(DI->getExpression());
1292 else
1293 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1294 .addImm(CI->getZExtValue())
1295 .addImm(0U)
1296 .addMetadata(DI->getVariable())
1297 .addMetadata(DI->getExpression());
1298 } else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
1299 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1300 .addFPImm(CF)
1301 .addImm(0U)
1302 .addMetadata(DI->getVariable())
1303 .addMetadata(DI->getExpression());
1304 } else if (Register Reg = lookUpRegForValue(V)) {
1305 // FIXME: This does not handle register-indirect values at offset 0.
1306 bool IsIndirect = false;
1307 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, IsIndirect, Reg,
1308 DI->getVariable(), DI->getExpression());
1309 } else {
1310 // We don't know how to handle other cases, so we drop.
1311 LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1312 }
1313 return true;
1314 }
1315 case Intrinsic::dbg_label: {
1316 const DbgLabelInst *DI = cast<DbgLabelInst>(II);
1317 assert(DI->getLabel() && "Missing label");
1318 if (!FuncInfo.MF->getMMI().hasDebugInfo()) {
1319 LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1320 return true;
1321 }
1322
1323 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1324 TII.get(TargetOpcode::DBG_LABEL)).addMetadata(DI->getLabel());
1325 return true;
1326 }
1327 case Intrinsic::objectsize:
1328 llvm_unreachable("llvm.objectsize.* should have been lowered already");
1329
1330 case Intrinsic::is_constant:
1331 llvm_unreachable("llvm.is.constant.* should have been lowered already");
1332
1333 case Intrinsic::launder_invariant_group:
1334 case Intrinsic::strip_invariant_group:
1335 case Intrinsic::expect: {
1336 Register ResultReg = getRegForValue(II->getArgOperand(0));
1337 if (!ResultReg)
1338 return false;
1339 updateValueMap(II, ResultReg);
1340 return true;
1341 }
1342 case Intrinsic::experimental_stackmap:
1343 return selectStackmap(II);
1344 case Intrinsic::experimental_patchpoint_void:
1345 case Intrinsic::experimental_patchpoint_i64:
1346 return selectPatchpoint(II);
1347
1348 case Intrinsic::xray_customevent:
1349 return selectXRayCustomEvent(II);
1350 case Intrinsic::xray_typedevent:
1351 return selectXRayTypedEvent(II);
1352 }
1353
1354 return fastLowerIntrinsicCall(II);
1355 }
1356
selectCast(const User * I,unsigned Opcode)1357 bool FastISel::selectCast(const User *I, unsigned Opcode) {
1358 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1359 EVT DstVT = TLI.getValueType(DL, I->getType());
1360
1361 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
1362 !DstVT.isSimple())
1363 // Unhandled type. Halt "fast" selection and bail.
1364 return false;
1365
1366 // Check if the destination type is legal.
1367 if (!TLI.isTypeLegal(DstVT))
1368 return false;
1369
1370 // Check if the source operand is legal.
1371 if (!TLI.isTypeLegal(SrcVT))
1372 return false;
1373
1374 Register InputReg = getRegForValue(I->getOperand(0));
1375 if (!InputReg)
1376 // Unhandled operand. Halt "fast" selection and bail.
1377 return false;
1378
1379 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1380 Opcode, InputReg);
1381 if (!ResultReg)
1382 return false;
1383
1384 updateValueMap(I, ResultReg);
1385 return true;
1386 }
1387
selectBitCast(const User * I)1388 bool FastISel::selectBitCast(const User *I) {
1389 // If the bitcast doesn't change the type, just use the operand value.
1390 if (I->getType() == I->getOperand(0)->getType()) {
1391 Register Reg = getRegForValue(I->getOperand(0));
1392 if (!Reg)
1393 return false;
1394 updateValueMap(I, Reg);
1395 return true;
1396 }
1397
1398 // Bitcasts of other values become reg-reg copies or BITCAST operators.
1399 EVT SrcEVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1400 EVT DstEVT = TLI.getValueType(DL, I->getType());
1401 if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
1402 !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
1403 // Unhandled type. Halt "fast" selection and bail.
1404 return false;
1405
1406 MVT SrcVT = SrcEVT.getSimpleVT();
1407 MVT DstVT = DstEVT.getSimpleVT();
1408 Register Op0 = getRegForValue(I->getOperand(0));
1409 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
1410 return false;
1411
1412 // First, try to perform the bitcast by inserting a reg-reg copy.
1413 Register ResultReg;
1414 if (SrcVT == DstVT) {
1415 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
1416 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
1417 // Don't attempt a cross-class copy. It will likely fail.
1418 if (SrcClass == DstClass) {
1419 ResultReg = createResultReg(DstClass);
1420 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1421 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
1422 }
1423 }
1424
1425 // If the reg-reg copy failed, select a BITCAST opcode.
1426 if (!ResultReg)
1427 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0);
1428
1429 if (!ResultReg)
1430 return false;
1431
1432 updateValueMap(I, ResultReg);
1433 return true;
1434 }
1435
selectFreeze(const User * I)1436 bool FastISel::selectFreeze(const User *I) {
1437 Register Reg = getRegForValue(I->getOperand(0));
1438 if (!Reg)
1439 // Unhandled operand.
1440 return false;
1441
1442 EVT ETy = TLI.getValueType(DL, I->getOperand(0)->getType());
1443 if (ETy == MVT::Other || !TLI.isTypeLegal(ETy))
1444 // Unhandled type, bail out.
1445 return false;
1446
1447 MVT Ty = ETy.getSimpleVT();
1448 const TargetRegisterClass *TyRegClass = TLI.getRegClassFor(Ty);
1449 Register ResultReg = createResultReg(TyRegClass);
1450 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1451 TII.get(TargetOpcode::COPY), ResultReg).addReg(Reg);
1452
1453 updateValueMap(I, ResultReg);
1454 return true;
1455 }
1456
1457 // Remove local value instructions starting from the instruction after
1458 // SavedLastLocalValue to the current function insert point.
removeDeadLocalValueCode(MachineInstr * SavedLastLocalValue)1459 void FastISel::removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue)
1460 {
1461 MachineInstr *CurLastLocalValue = getLastLocalValue();
1462 if (CurLastLocalValue != SavedLastLocalValue) {
1463 // Find the first local value instruction to be deleted.
1464 // This is the instruction after SavedLastLocalValue if it is non-NULL.
1465 // Otherwise it's the first instruction in the block.
1466 MachineBasicBlock::iterator FirstDeadInst(SavedLastLocalValue);
1467 if (SavedLastLocalValue)
1468 ++FirstDeadInst;
1469 else
1470 FirstDeadInst = FuncInfo.MBB->getFirstNonPHI();
1471 setLastLocalValue(SavedLastLocalValue);
1472 removeDeadCode(FirstDeadInst, FuncInfo.InsertPt);
1473 }
1474 }
1475
selectInstruction(const Instruction * I)1476 bool FastISel::selectInstruction(const Instruction *I) {
1477 // Flush the local value map before starting each instruction.
1478 // This improves locality and debugging, and can reduce spills.
1479 // Reuse of values across IR instructions is relatively uncommon.
1480 flushLocalValueMap();
1481
1482 MachineInstr *SavedLastLocalValue = getLastLocalValue();
1483 // Just before the terminator instruction, insert instructions to
1484 // feed PHI nodes in successor blocks.
1485 if (I->isTerminator()) {
1486 if (!handlePHINodesInSuccessorBlocks(I->getParent())) {
1487 // PHI node handling may have generated local value instructions,
1488 // even though it failed to handle all PHI nodes.
1489 // We remove these instructions because SelectionDAGISel will generate
1490 // them again.
1491 removeDeadLocalValueCode(SavedLastLocalValue);
1492 return false;
1493 }
1494 }
1495
1496 // FastISel does not handle any operand bundles except OB_funclet.
1497 if (auto *Call = dyn_cast<CallBase>(I))
1498 for (unsigned i = 0, e = Call->getNumOperandBundles(); i != e; ++i)
1499 if (Call->getOperandBundleAt(i).getTagID() != LLVMContext::OB_funclet)
1500 return false;
1501
1502 DbgLoc = I->getDebugLoc();
1503
1504 SavedInsertPt = FuncInfo.InsertPt;
1505
1506 if (const auto *Call = dyn_cast<CallInst>(I)) {
1507 const Function *F = Call->getCalledFunction();
1508 LibFunc Func;
1509
1510 // As a special case, don't handle calls to builtin library functions that
1511 // may be translated directly to target instructions.
1512 if (F && !F->hasLocalLinkage() && F->hasName() &&
1513 LibInfo->getLibFunc(F->getName(), Func) &&
1514 LibInfo->hasOptimizedCodeGen(Func))
1515 return false;
1516
1517 // Don't handle Intrinsic::trap if a trap function is specified.
1518 if (F && F->getIntrinsicID() == Intrinsic::trap &&
1519 Call->hasFnAttr("trap-func-name"))
1520 return false;
1521 }
1522
1523 // First, try doing target-independent selection.
1524 if (!SkipTargetIndependentISel) {
1525 if (selectOperator(I, I->getOpcode())) {
1526 ++NumFastIselSuccessIndependent;
1527 DbgLoc = DebugLoc();
1528 return true;
1529 }
1530 // Remove dead code.
1531 recomputeInsertPt();
1532 if (SavedInsertPt != FuncInfo.InsertPt)
1533 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1534 SavedInsertPt = FuncInfo.InsertPt;
1535 }
1536 // Next, try calling the target to attempt to handle the instruction.
1537 if (fastSelectInstruction(I)) {
1538 ++NumFastIselSuccessTarget;
1539 DbgLoc = DebugLoc();
1540 return true;
1541 }
1542 // Remove dead code.
1543 recomputeInsertPt();
1544 if (SavedInsertPt != FuncInfo.InsertPt)
1545 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1546
1547 DbgLoc = DebugLoc();
1548 // Undo phi node updates, because they will be added again by SelectionDAG.
1549 if (I->isTerminator()) {
1550 // PHI node handling may have generated local value instructions.
1551 // We remove them because SelectionDAGISel will generate them again.
1552 removeDeadLocalValueCode(SavedLastLocalValue);
1553 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
1554 }
1555 return false;
1556 }
1557
1558 /// Emit an unconditional branch to the given block, unless it is the immediate
1559 /// (fall-through) successor, and update the CFG.
fastEmitBranch(MachineBasicBlock * MSucc,const DebugLoc & DbgLoc)1560 void FastISel::fastEmitBranch(MachineBasicBlock *MSucc,
1561 const DebugLoc &DbgLoc) {
1562 if (FuncInfo.MBB->getBasicBlock()->sizeWithoutDebug() > 1 &&
1563 FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
1564 // For more accurate line information if this is the only non-debug
1565 // instruction in the block then emit it, otherwise we have the
1566 // unconditional fall-through case, which needs no instructions.
1567 } else {
1568 // The unconditional branch case.
1569 TII.insertBranch(*FuncInfo.MBB, MSucc, nullptr,
1570 SmallVector<MachineOperand, 0>(), DbgLoc);
1571 }
1572 if (FuncInfo.BPI) {
1573 auto BranchProbability = FuncInfo.BPI->getEdgeProbability(
1574 FuncInfo.MBB->getBasicBlock(), MSucc->getBasicBlock());
1575 FuncInfo.MBB->addSuccessor(MSucc, BranchProbability);
1576 } else
1577 FuncInfo.MBB->addSuccessorWithoutProb(MSucc);
1578 }
1579
finishCondBranch(const BasicBlock * BranchBB,MachineBasicBlock * TrueMBB,MachineBasicBlock * FalseMBB)1580 void FastISel::finishCondBranch(const BasicBlock *BranchBB,
1581 MachineBasicBlock *TrueMBB,
1582 MachineBasicBlock *FalseMBB) {
1583 // Add TrueMBB as successor unless it is equal to the FalseMBB: This can
1584 // happen in degenerate IR and MachineIR forbids to have a block twice in the
1585 // successor/predecessor lists.
1586 if (TrueMBB != FalseMBB) {
1587 if (FuncInfo.BPI) {
1588 auto BranchProbability =
1589 FuncInfo.BPI->getEdgeProbability(BranchBB, TrueMBB->getBasicBlock());
1590 FuncInfo.MBB->addSuccessor(TrueMBB, BranchProbability);
1591 } else
1592 FuncInfo.MBB->addSuccessorWithoutProb(TrueMBB);
1593 }
1594
1595 fastEmitBranch(FalseMBB, DbgLoc);
1596 }
1597
1598 /// Emit an FNeg operation.
selectFNeg(const User * I,const Value * In)1599 bool FastISel::selectFNeg(const User *I, const Value *In) {
1600 Register OpReg = getRegForValue(In);
1601 if (!OpReg)
1602 return false;
1603
1604 // If the target has ISD::FNEG, use it.
1605 EVT VT = TLI.getValueType(DL, I->getType());
1606 Register ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
1607 OpReg);
1608 if (ResultReg) {
1609 updateValueMap(I, ResultReg);
1610 return true;
1611 }
1612
1613 // Bitcast the value to integer, twiddle the sign bit with xor,
1614 // and then bitcast it back to floating-point.
1615 if (VT.getSizeInBits() > 64)
1616 return false;
1617 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
1618 if (!TLI.isTypeLegal(IntVT))
1619 return false;
1620
1621 Register IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
1622 ISD::BITCAST, OpReg);
1623 if (!IntReg)
1624 return false;
1625
1626 Register IntResultReg = fastEmit_ri_(
1627 IntVT.getSimpleVT(), ISD::XOR, IntReg,
1628 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT());
1629 if (!IntResultReg)
1630 return false;
1631
1632 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST,
1633 IntResultReg);
1634 if (!ResultReg)
1635 return false;
1636
1637 updateValueMap(I, ResultReg);
1638 return true;
1639 }
1640
selectExtractValue(const User * U)1641 bool FastISel::selectExtractValue(const User *U) {
1642 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
1643 if (!EVI)
1644 return false;
1645
1646 // Make sure we only try to handle extracts with a legal result. But also
1647 // allow i1 because it's easy.
1648 EVT RealVT = TLI.getValueType(DL, EVI->getType(), /*AllowUnknown=*/true);
1649 if (!RealVT.isSimple())
1650 return false;
1651 MVT VT = RealVT.getSimpleVT();
1652 if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
1653 return false;
1654
1655 const Value *Op0 = EVI->getOperand(0);
1656 Type *AggTy = Op0->getType();
1657
1658 // Get the base result register.
1659 unsigned ResultReg;
1660 DenseMap<const Value *, Register>::iterator I = FuncInfo.ValueMap.find(Op0);
1661 if (I != FuncInfo.ValueMap.end())
1662 ResultReg = I->second;
1663 else if (isa<Instruction>(Op0))
1664 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1665 else
1666 return false; // fast-isel can't handle aggregate constants at the moment
1667
1668 // Get the actual result register, which is an offset from the base register.
1669 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
1670
1671 SmallVector<EVT, 4> AggValueVTs;
1672 ComputeValueVTs(TLI, DL, AggTy, AggValueVTs);
1673
1674 for (unsigned i = 0; i < VTIndex; i++)
1675 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
1676
1677 updateValueMap(EVI, ResultReg);
1678 return true;
1679 }
1680
selectOperator(const User * I,unsigned Opcode)1681 bool FastISel::selectOperator(const User *I, unsigned Opcode) {
1682 switch (Opcode) {
1683 case Instruction::Add:
1684 return selectBinaryOp(I, ISD::ADD);
1685 case Instruction::FAdd:
1686 return selectBinaryOp(I, ISD::FADD);
1687 case Instruction::Sub:
1688 return selectBinaryOp(I, ISD::SUB);
1689 case Instruction::FSub:
1690 return selectBinaryOp(I, ISD::FSUB);
1691 case Instruction::Mul:
1692 return selectBinaryOp(I, ISD::MUL);
1693 case Instruction::FMul:
1694 return selectBinaryOp(I, ISD::FMUL);
1695 case Instruction::SDiv:
1696 return selectBinaryOp(I, ISD::SDIV);
1697 case Instruction::UDiv:
1698 return selectBinaryOp(I, ISD::UDIV);
1699 case Instruction::FDiv:
1700 return selectBinaryOp(I, ISD::FDIV);
1701 case Instruction::SRem:
1702 return selectBinaryOp(I, ISD::SREM);
1703 case Instruction::URem:
1704 return selectBinaryOp(I, ISD::UREM);
1705 case Instruction::FRem:
1706 return selectBinaryOp(I, ISD::FREM);
1707 case Instruction::Shl:
1708 return selectBinaryOp(I, ISD::SHL);
1709 case Instruction::LShr:
1710 return selectBinaryOp(I, ISD::SRL);
1711 case Instruction::AShr:
1712 return selectBinaryOp(I, ISD::SRA);
1713 case Instruction::And:
1714 return selectBinaryOp(I, ISD::AND);
1715 case Instruction::Or:
1716 return selectBinaryOp(I, ISD::OR);
1717 case Instruction::Xor:
1718 return selectBinaryOp(I, ISD::XOR);
1719
1720 case Instruction::FNeg:
1721 return selectFNeg(I, I->getOperand(0));
1722
1723 case Instruction::GetElementPtr:
1724 return selectGetElementPtr(I);
1725
1726 case Instruction::Br: {
1727 const BranchInst *BI = cast<BranchInst>(I);
1728
1729 if (BI->isUnconditional()) {
1730 const BasicBlock *LLVMSucc = BI->getSuccessor(0);
1731 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
1732 fastEmitBranch(MSucc, BI->getDebugLoc());
1733 return true;
1734 }
1735
1736 // Conditional branches are not handed yet.
1737 // Halt "fast" selection and bail.
1738 return false;
1739 }
1740
1741 case Instruction::Unreachable:
1742 if (TM.Options.TrapUnreachable)
1743 return fastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;
1744 else
1745 return true;
1746
1747 case Instruction::Alloca:
1748 // FunctionLowering has the static-sized case covered.
1749 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
1750 return true;
1751
1752 // Dynamic-sized alloca is not handled yet.
1753 return false;
1754
1755 case Instruction::Call:
1756 // On AIX, call lowering uses the DAG-ISEL path currently so that the
1757 // callee of the direct function call instruction will be mapped to the
1758 // symbol for the function's entry point, which is distinct from the
1759 // function descriptor symbol. The latter is the symbol whose XCOFF symbol
1760 // name is the C-linkage name of the source level function.
1761 if (TM.getTargetTriple().isOSAIX())
1762 return false;
1763 return selectCall(I);
1764
1765 case Instruction::BitCast:
1766 return selectBitCast(I);
1767
1768 case Instruction::FPToSI:
1769 return selectCast(I, ISD::FP_TO_SINT);
1770 case Instruction::ZExt:
1771 return selectCast(I, ISD::ZERO_EXTEND);
1772 case Instruction::SExt:
1773 return selectCast(I, ISD::SIGN_EXTEND);
1774 case Instruction::Trunc:
1775 return selectCast(I, ISD::TRUNCATE);
1776 case Instruction::SIToFP:
1777 return selectCast(I, ISD::SINT_TO_FP);
1778
1779 case Instruction::IntToPtr: // Deliberate fall-through.
1780 case Instruction::PtrToInt: {
1781 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1782 EVT DstVT = TLI.getValueType(DL, I->getType());
1783 if (DstVT.bitsGT(SrcVT))
1784 return selectCast(I, ISD::ZERO_EXTEND);
1785 if (DstVT.bitsLT(SrcVT))
1786 return selectCast(I, ISD::TRUNCATE);
1787 Register Reg = getRegForValue(I->getOperand(0));
1788 if (!Reg)
1789 return false;
1790 updateValueMap(I, Reg);
1791 return true;
1792 }
1793
1794 case Instruction::ExtractValue:
1795 return selectExtractValue(I);
1796
1797 case Instruction::Freeze:
1798 return selectFreeze(I);
1799
1800 case Instruction::PHI:
1801 llvm_unreachable("FastISel shouldn't visit PHI nodes!");
1802
1803 default:
1804 // Unhandled instruction. Halt "fast" selection and bail.
1805 return false;
1806 }
1807 }
1808
FastISel(FunctionLoweringInfo & FuncInfo,const TargetLibraryInfo * LibInfo,bool SkipTargetIndependentISel)1809 FastISel::FastISel(FunctionLoweringInfo &FuncInfo,
1810 const TargetLibraryInfo *LibInfo,
1811 bool SkipTargetIndependentISel)
1812 : FuncInfo(FuncInfo), MF(FuncInfo.MF), MRI(FuncInfo.MF->getRegInfo()),
1813 MFI(FuncInfo.MF->getFrameInfo()), MCP(*FuncInfo.MF->getConstantPool()),
1814 TM(FuncInfo.MF->getTarget()), DL(MF->getDataLayout()),
1815 TII(*MF->getSubtarget().getInstrInfo()),
1816 TLI(*MF->getSubtarget().getTargetLowering()),
1817 TRI(*MF->getSubtarget().getRegisterInfo()), LibInfo(LibInfo),
1818 SkipTargetIndependentISel(SkipTargetIndependentISel),
1819 LastLocalValue(nullptr), EmitStartPt(nullptr) {}
1820
1821 FastISel::~FastISel() = default;
1822
fastLowerArguments()1823 bool FastISel::fastLowerArguments() { return false; }
1824
fastLowerCall(CallLoweringInfo &)1825 bool FastISel::fastLowerCall(CallLoweringInfo & /*CLI*/) { return false; }
1826
fastLowerIntrinsicCall(const IntrinsicInst *)1827 bool FastISel::fastLowerIntrinsicCall(const IntrinsicInst * /*II*/) {
1828 return false;
1829 }
1830
fastEmit_(MVT,MVT,unsigned)1831 unsigned FastISel::fastEmit_(MVT, MVT, unsigned) { return 0; }
1832
fastEmit_r(MVT,MVT,unsigned,unsigned)1833 unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, unsigned /*Op0*/) {
1834 return 0;
1835 }
1836
fastEmit_rr(MVT,MVT,unsigned,unsigned,unsigned)1837 unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, unsigned /*Op0*/,
1838 unsigned /*Op1*/) {
1839 return 0;
1840 }
1841
fastEmit_i(MVT,MVT,unsigned,uint64_t)1842 unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1843 return 0;
1844 }
1845
fastEmit_f(MVT,MVT,unsigned,const ConstantFP *)1846 unsigned FastISel::fastEmit_f(MVT, MVT, unsigned,
1847 const ConstantFP * /*FPImm*/) {
1848 return 0;
1849 }
1850
fastEmit_ri(MVT,MVT,unsigned,unsigned,uint64_t)1851 unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
1852 uint64_t /*Imm*/) {
1853 return 0;
1854 }
1855
1856 /// This method is a wrapper of fastEmit_ri. It first tries to emit an
1857 /// instruction with an immediate operand using fastEmit_ri.
1858 /// If that fails, it materializes the immediate into a register and try
1859 /// fastEmit_rr instead.
fastEmit_ri_(MVT VT,unsigned Opcode,unsigned Op0,uint64_t Imm,MVT ImmType)1860 Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
1861 uint64_t Imm, MVT ImmType) {
1862 // If this is a multiply by a power of two, emit this as a shift left.
1863 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1864 Opcode = ISD::SHL;
1865 Imm = Log2_64(Imm);
1866 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1867 // div x, 8 -> srl x, 3
1868 Opcode = ISD::SRL;
1869 Imm = Log2_64(Imm);
1870 }
1871
1872 // Horrible hack (to be removed), check to make sure shift amounts are
1873 // in-range.
1874 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1875 Imm >= VT.getSizeInBits())
1876 return 0;
1877
1878 // First check if immediate type is legal. If not, we can't use the ri form.
1879 Register ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Imm);
1880 if (ResultReg)
1881 return ResultReg;
1882 Register MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1883 if (!MaterialReg) {
1884 // This is a bit ugly/slow, but failing here means falling out of
1885 // fast-isel, which would be very slow.
1886 IntegerType *ITy =
1887 IntegerType::get(FuncInfo.Fn->getContext(), VT.getSizeInBits());
1888 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1889 if (!MaterialReg)
1890 return 0;
1891 }
1892 return fastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
1893 }
1894
createResultReg(const TargetRegisterClass * RC)1895 Register FastISel::createResultReg(const TargetRegisterClass *RC) {
1896 return MRI.createVirtualRegister(RC);
1897 }
1898
constrainOperandRegClass(const MCInstrDesc & II,Register Op,unsigned OpNum)1899 Register FastISel::constrainOperandRegClass(const MCInstrDesc &II, Register Op,
1900 unsigned OpNum) {
1901 if (Op.isVirtual()) {
1902 const TargetRegisterClass *RegClass =
1903 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
1904 if (!MRI.constrainRegClass(Op, RegClass)) {
1905 // If it's not legal to COPY between the register classes, something
1906 // has gone very wrong before we got here.
1907 Register NewOp = createResultReg(RegClass);
1908 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1909 TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
1910 return NewOp;
1911 }
1912 }
1913 return Op;
1914 }
1915
fastEmitInst_(unsigned MachineInstOpcode,const TargetRegisterClass * RC)1916 Register FastISel::fastEmitInst_(unsigned MachineInstOpcode,
1917 const TargetRegisterClass *RC) {
1918 Register ResultReg = createResultReg(RC);
1919 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1920
1921 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
1922 return ResultReg;
1923 }
1924
fastEmitInst_r(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0)1925 Register FastISel::fastEmitInst_r(unsigned MachineInstOpcode,
1926 const TargetRegisterClass *RC, unsigned Op0) {
1927 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1928
1929 Register ResultReg = createResultReg(RC);
1930 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1931
1932 if (II.getNumDefs() >= 1)
1933 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1934 .addReg(Op0);
1935 else {
1936 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1937 .addReg(Op0);
1938 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1939 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1940 }
1941
1942 return ResultReg;
1943 }
1944
fastEmitInst_rr(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,unsigned Op1)1945 Register FastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1946 const TargetRegisterClass *RC, unsigned Op0,
1947 unsigned Op1) {
1948 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1949
1950 Register ResultReg = createResultReg(RC);
1951 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1952 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1953
1954 if (II.getNumDefs() >= 1)
1955 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1956 .addReg(Op0)
1957 .addReg(Op1);
1958 else {
1959 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1960 .addReg(Op0)
1961 .addReg(Op1);
1962 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1963 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1964 }
1965 return ResultReg;
1966 }
1967
fastEmitInst_rrr(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,unsigned Op1,unsigned Op2)1968 Register FastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
1969 const TargetRegisterClass *RC, unsigned Op0,
1970 unsigned Op1, unsigned Op2) {
1971 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1972
1973 Register ResultReg = createResultReg(RC);
1974 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1975 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1976 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
1977
1978 if (II.getNumDefs() >= 1)
1979 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1980 .addReg(Op0)
1981 .addReg(Op1)
1982 .addReg(Op2);
1983 else {
1984 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1985 .addReg(Op0)
1986 .addReg(Op1)
1987 .addReg(Op2);
1988 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1989 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1990 }
1991 return ResultReg;
1992 }
1993
fastEmitInst_ri(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,uint64_t Imm)1994 Register FastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
1995 const TargetRegisterClass *RC, unsigned Op0,
1996 uint64_t Imm) {
1997 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1998
1999 Register ResultReg = createResultReg(RC);
2000 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2001
2002 if (II.getNumDefs() >= 1)
2003 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2004 .addReg(Op0)
2005 .addImm(Imm);
2006 else {
2007 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
2008 .addReg(Op0)
2009 .addImm(Imm);
2010 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2011 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2012 }
2013 return ResultReg;
2014 }
2015
fastEmitInst_rii(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,uint64_t Imm1,uint64_t Imm2)2016 Register FastISel::fastEmitInst_rii(unsigned MachineInstOpcode,
2017 const TargetRegisterClass *RC, unsigned Op0,
2018 uint64_t Imm1, uint64_t Imm2) {
2019 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2020
2021 Register ResultReg = createResultReg(RC);
2022 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2023
2024 if (II.getNumDefs() >= 1)
2025 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2026 .addReg(Op0)
2027 .addImm(Imm1)
2028 .addImm(Imm2);
2029 else {
2030 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
2031 .addReg(Op0)
2032 .addImm(Imm1)
2033 .addImm(Imm2);
2034 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2035 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2036 }
2037 return ResultReg;
2038 }
2039
fastEmitInst_f(unsigned MachineInstOpcode,const TargetRegisterClass * RC,const ConstantFP * FPImm)2040 Register FastISel::fastEmitInst_f(unsigned MachineInstOpcode,
2041 const TargetRegisterClass *RC,
2042 const ConstantFP *FPImm) {
2043 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2044
2045 Register ResultReg = createResultReg(RC);
2046
2047 if (II.getNumDefs() >= 1)
2048 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2049 .addFPImm(FPImm);
2050 else {
2051 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
2052 .addFPImm(FPImm);
2053 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2054 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2055 }
2056 return ResultReg;
2057 }
2058
fastEmitInst_rri(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,unsigned Op1,uint64_t Imm)2059 Register FastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
2060 const TargetRegisterClass *RC, unsigned Op0,
2061 unsigned Op1, uint64_t Imm) {
2062 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2063
2064 Register ResultReg = createResultReg(RC);
2065 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2066 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2067
2068 if (II.getNumDefs() >= 1)
2069 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2070 .addReg(Op0)
2071 .addReg(Op1)
2072 .addImm(Imm);
2073 else {
2074 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
2075 .addReg(Op0)
2076 .addReg(Op1)
2077 .addImm(Imm);
2078 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2079 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2080 }
2081 return ResultReg;
2082 }
2083
fastEmitInst_i(unsigned MachineInstOpcode,const TargetRegisterClass * RC,uint64_t Imm)2084 Register FastISel::fastEmitInst_i(unsigned MachineInstOpcode,
2085 const TargetRegisterClass *RC, uint64_t Imm) {
2086 Register ResultReg = createResultReg(RC);
2087 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2088
2089 if (II.getNumDefs() >= 1)
2090 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2091 .addImm(Imm);
2092 else {
2093 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm);
2094 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2095 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2096 }
2097 return ResultReg;
2098 }
2099
fastEmitInst_extractsubreg(MVT RetVT,unsigned Op0,uint32_t Idx)2100 Register FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,
2101 uint32_t Idx) {
2102 Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
2103 assert(Register::isVirtualRegister(Op0) &&
2104 "Cannot yet extract from physregs");
2105 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
2106 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
2107 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
2108 ResultReg).addReg(Op0, 0, Idx);
2109 return ResultReg;
2110 }
2111
2112 /// Emit MachineInstrs to compute the value of Op with all but the least
2113 /// significant bit set to zero.
fastEmitZExtFromI1(MVT VT,unsigned Op0)2114 Register FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0) {
2115 return fastEmit_ri(VT, VT, ISD::AND, Op0, 1);
2116 }
2117
2118 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
2119 /// Emit code to ensure constants are copied into registers when needed.
2120 /// Remember the virtual registers that need to be added to the Machine PHI
2121 /// nodes as input. We cannot just directly add them, because expansion
2122 /// might result in multiple MBB's for one BB. As such, the start of the
2123 /// BB might correspond to a different MBB than the end.
handlePHINodesInSuccessorBlocks(const BasicBlock * LLVMBB)2124 bool FastISel::handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
2125 const Instruction *TI = LLVMBB->getTerminator();
2126
2127 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
2128 FuncInfo.OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
2129
2130 // Check successor nodes' PHI nodes that expect a constant to be available
2131 // from this block.
2132 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
2133 const BasicBlock *SuccBB = TI->getSuccessor(succ);
2134 if (!isa<PHINode>(SuccBB->begin()))
2135 continue;
2136 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
2137
2138 // If this terminator has multiple identical successors (common for
2139 // switches), only handle each succ once.
2140 if (!SuccsHandled.insert(SuccMBB).second)
2141 continue;
2142
2143 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
2144
2145 // At this point we know that there is a 1-1 correspondence between LLVM PHI
2146 // nodes and Machine PHI nodes, but the incoming operands have not been
2147 // emitted yet.
2148 for (const PHINode &PN : SuccBB->phis()) {
2149 // Ignore dead phi's.
2150 if (PN.use_empty())
2151 continue;
2152
2153 // Only handle legal types. Two interesting things to note here. First,
2154 // by bailing out early, we may leave behind some dead instructions,
2155 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
2156 // own moves. Second, this check is necessary because FastISel doesn't
2157 // use CreateRegs to create registers, so it always creates
2158 // exactly one register for each non-void instruction.
2159 EVT VT = TLI.getValueType(DL, PN.getType(), /*AllowUnknown=*/true);
2160 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
2161 // Handle integer promotions, though, because they're common and easy.
2162 if (!(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) {
2163 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
2164 return false;
2165 }
2166 }
2167
2168 const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB);
2169
2170 // Set the DebugLoc for the copy. Use the location of the operand if
2171 // there is one; otherwise no location, flushLocalValueMap will fix it.
2172 DbgLoc = DebugLoc();
2173 if (const auto *Inst = dyn_cast<Instruction>(PHIOp))
2174 DbgLoc = Inst->getDebugLoc();
2175
2176 Register Reg = getRegForValue(PHIOp);
2177 if (!Reg) {
2178 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
2179 return false;
2180 }
2181 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(&*MBBI++, Reg));
2182 DbgLoc = DebugLoc();
2183 }
2184 }
2185
2186 return true;
2187 }
2188
tryToFoldLoad(const LoadInst * LI,const Instruction * FoldInst)2189 bool FastISel::tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst) {
2190 assert(LI->hasOneUse() &&
2191 "tryToFoldLoad expected a LoadInst with a single use");
2192 // We know that the load has a single use, but don't know what it is. If it
2193 // isn't one of the folded instructions, then we can't succeed here. Handle
2194 // this by scanning the single-use users of the load until we get to FoldInst.
2195 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
2196
2197 const Instruction *TheUser = LI->user_back();
2198 while (TheUser != FoldInst && // Scan up until we find FoldInst.
2199 // Stay in the right block.
2200 TheUser->getParent() == FoldInst->getParent() &&
2201 --MaxUsers) { // Don't scan too far.
2202 // If there are multiple or no uses of this instruction, then bail out.
2203 if (!TheUser->hasOneUse())
2204 return false;
2205
2206 TheUser = TheUser->user_back();
2207 }
2208
2209 // If we didn't find the fold instruction, then we failed to collapse the
2210 // sequence.
2211 if (TheUser != FoldInst)
2212 return false;
2213
2214 // Don't try to fold volatile loads. Target has to deal with alignment
2215 // constraints.
2216 if (LI->isVolatile())
2217 return false;
2218
2219 // Figure out which vreg this is going into. If there is no assigned vreg yet
2220 // then there actually was no reference to it. Perhaps the load is referenced
2221 // by a dead instruction.
2222 Register LoadReg = getRegForValue(LI);
2223 if (!LoadReg)
2224 return false;
2225
2226 // We can't fold if this vreg has no uses or more than one use. Multiple uses
2227 // may mean that the instruction got lowered to multiple MIs, or the use of
2228 // the loaded value ended up being multiple operands of the result.
2229 if (!MRI.hasOneUse(LoadReg))
2230 return false;
2231
2232 MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg);
2233 MachineInstr *User = RI->getParent();
2234
2235 // Set the insertion point properly. Folding the load can cause generation of
2236 // other random instructions (like sign extends) for addressing modes; make
2237 // sure they get inserted in a logical place before the new instruction.
2238 FuncInfo.InsertPt = User;
2239 FuncInfo.MBB = User->getParent();
2240
2241 // Ask the target to try folding the load.
2242 return tryToFoldLoadIntoMI(User, RI.getOperandNo(), LI);
2243 }
2244
canFoldAddIntoGEP(const User * GEP,const Value * Add)2245 bool FastISel::canFoldAddIntoGEP(const User *GEP, const Value *Add) {
2246 // Must be an add.
2247 if (!isa<AddOperator>(Add))
2248 return false;
2249 // Type size needs to match.
2250 if (DL.getTypeSizeInBits(GEP->getType()) !=
2251 DL.getTypeSizeInBits(Add->getType()))
2252 return false;
2253 // Must be in the same basic block.
2254 if (isa<Instruction>(Add) &&
2255 FuncInfo.MBBMap[cast<Instruction>(Add)->getParent()] != FuncInfo.MBB)
2256 return false;
2257 // Must have a constant operand.
2258 return isa<ConstantInt>(cast<AddOperator>(Add)->getOperand(1));
2259 }
2260
2261 MachineMemOperand *
createMachineMemOperandFor(const Instruction * I) const2262 FastISel::createMachineMemOperandFor(const Instruction *I) const {
2263 const Value *Ptr;
2264 Type *ValTy;
2265 MaybeAlign Alignment;
2266 MachineMemOperand::Flags Flags;
2267 bool IsVolatile;
2268
2269 if (const auto *LI = dyn_cast<LoadInst>(I)) {
2270 Alignment = LI->getAlign();
2271 IsVolatile = LI->isVolatile();
2272 Flags = MachineMemOperand::MOLoad;
2273 Ptr = LI->getPointerOperand();
2274 ValTy = LI->getType();
2275 } else if (const auto *SI = dyn_cast<StoreInst>(I)) {
2276 Alignment = SI->getAlign();
2277 IsVolatile = SI->isVolatile();
2278 Flags = MachineMemOperand::MOStore;
2279 Ptr = SI->getPointerOperand();
2280 ValTy = SI->getValueOperand()->getType();
2281 } else
2282 return nullptr;
2283
2284 bool IsNonTemporal = I->hasMetadata(LLVMContext::MD_nontemporal);
2285 bool IsInvariant = I->hasMetadata(LLVMContext::MD_invariant_load);
2286 bool IsDereferenceable = I->hasMetadata(LLVMContext::MD_dereferenceable);
2287 const MDNode *Ranges = I->getMetadata(LLVMContext::MD_range);
2288
2289 AAMDNodes AAInfo;
2290 I->getAAMetadata(AAInfo);
2291
2292 if (!Alignment) // Ensure that codegen never sees alignment 0.
2293 Alignment = DL.getABITypeAlign(ValTy);
2294
2295 unsigned Size = DL.getTypeStoreSize(ValTy);
2296
2297 if (IsVolatile)
2298 Flags |= MachineMemOperand::MOVolatile;
2299 if (IsNonTemporal)
2300 Flags |= MachineMemOperand::MONonTemporal;
2301 if (IsDereferenceable)
2302 Flags |= MachineMemOperand::MODereferenceable;
2303 if (IsInvariant)
2304 Flags |= MachineMemOperand::MOInvariant;
2305
2306 return FuncInfo.MF->getMachineMemOperand(MachinePointerInfo(Ptr), Flags, Size,
2307 *Alignment, AAInfo, Ranges);
2308 }
2309
optimizeCmpPredicate(const CmpInst * CI) const2310 CmpInst::Predicate FastISel::optimizeCmpPredicate(const CmpInst *CI) const {
2311 // If both operands are the same, then try to optimize or fold the cmp.
2312 CmpInst::Predicate Predicate = CI->getPredicate();
2313 if (CI->getOperand(0) != CI->getOperand(1))
2314 return Predicate;
2315
2316 switch (Predicate) {
2317 default: llvm_unreachable("Invalid predicate!");
2318 case CmpInst::FCMP_FALSE: Predicate = CmpInst::FCMP_FALSE; break;
2319 case CmpInst::FCMP_OEQ: Predicate = CmpInst::FCMP_ORD; break;
2320 case CmpInst::FCMP_OGT: Predicate = CmpInst::FCMP_FALSE; break;
2321 case CmpInst::FCMP_OGE: Predicate = CmpInst::FCMP_ORD; break;
2322 case CmpInst::FCMP_OLT: Predicate = CmpInst::FCMP_FALSE; break;
2323 case CmpInst::FCMP_OLE: Predicate = CmpInst::FCMP_ORD; break;
2324 case CmpInst::FCMP_ONE: Predicate = CmpInst::FCMP_FALSE; break;
2325 case CmpInst::FCMP_ORD: Predicate = CmpInst::FCMP_ORD; break;
2326 case CmpInst::FCMP_UNO: Predicate = CmpInst::FCMP_UNO; break;
2327 case CmpInst::FCMP_UEQ: Predicate = CmpInst::FCMP_TRUE; break;
2328 case CmpInst::FCMP_UGT: Predicate = CmpInst::FCMP_UNO; break;
2329 case CmpInst::FCMP_UGE: Predicate = CmpInst::FCMP_TRUE; break;
2330 case CmpInst::FCMP_ULT: Predicate = CmpInst::FCMP_UNO; break;
2331 case CmpInst::FCMP_ULE: Predicate = CmpInst::FCMP_TRUE; break;
2332 case CmpInst::FCMP_UNE: Predicate = CmpInst::FCMP_UNO; break;
2333 case CmpInst::FCMP_TRUE: Predicate = CmpInst::FCMP_TRUE; break;
2334
2335 case CmpInst::ICMP_EQ: Predicate = CmpInst::FCMP_TRUE; break;
2336 case CmpInst::ICMP_NE: Predicate = CmpInst::FCMP_FALSE; break;
2337 case CmpInst::ICMP_UGT: Predicate = CmpInst::FCMP_FALSE; break;
2338 case CmpInst::ICMP_UGE: Predicate = CmpInst::FCMP_TRUE; break;
2339 case CmpInst::ICMP_ULT: Predicate = CmpInst::FCMP_FALSE; break;
2340 case CmpInst::ICMP_ULE: Predicate = CmpInst::FCMP_TRUE; break;
2341 case CmpInst::ICMP_SGT: Predicate = CmpInst::FCMP_FALSE; break;
2342 case CmpInst::ICMP_SGE: Predicate = CmpInst::FCMP_TRUE; break;
2343 case CmpInst::ICMP_SLT: Predicate = CmpInst::FCMP_FALSE; break;
2344 case CmpInst::ICMP_SLE: Predicate = CmpInst::FCMP_TRUE; break;
2345 }
2346
2347 return Predicate;
2348 }
2349