1 /* $NetBSD: fdt_clock.c,v 1.10 2019/11/09 23:28:26 jmcneill Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: fdt_clock.c,v 1.10 2019/11/09 23:28:26 jmcneill Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/kmem.h>
35 #include <sys/queue.h>
36
37 #include <libfdt.h>
38 #include <dev/fdt/fdtvar.h>
39
40 #include <dev/clk/clk_backend.h>
41
42 struct fdtbus_clock_controller {
43 device_t cc_dev;
44 int cc_phandle;
45 const struct fdtbus_clock_controller_func *cc_funcs;
46
47 LIST_ENTRY(fdtbus_clock_controller) cc_next;
48 };
49
50 static LIST_HEAD(, fdtbus_clock_controller) fdtbus_clock_controllers =
51 LIST_HEAD_INITIALIZER(fdtbus_clock_controller);
52
53 int
fdtbus_register_clock_controller(device_t dev,int phandle,const struct fdtbus_clock_controller_func * funcs)54 fdtbus_register_clock_controller(device_t dev, int phandle,
55 const struct fdtbus_clock_controller_func *funcs)
56 {
57 struct fdtbus_clock_controller *cc;
58
59 cc = kmem_alloc(sizeof(*cc), KM_SLEEP);
60 cc->cc_dev = dev;
61 cc->cc_phandle = phandle;
62 cc->cc_funcs = funcs;
63
64 LIST_INSERT_HEAD(&fdtbus_clock_controllers, cc, cc_next);
65
66 fdtbus_clock_assign(phandle);
67
68 return 0;
69 }
70
71 static struct fdtbus_clock_controller *
fdtbus_get_clock_controller(int phandle)72 fdtbus_get_clock_controller(int phandle)
73 {
74 struct fdtbus_clock_controller *cc;
75
76 LIST_FOREACH(cc, &fdtbus_clock_controllers, cc_next) {
77 if (cc->cc_phandle == phandle)
78 return cc;
79 }
80
81 return NULL;
82 }
83
84 static struct clk *
fdtbus_clock_get_index_prop(int phandle,u_int index,const char * prop)85 fdtbus_clock_get_index_prop(int phandle, u_int index, const char *prop)
86 {
87 struct fdtbus_clock_controller *cc;
88 struct clk *clk = NULL;
89 const u_int *p;
90 u_int n, clock_cells;
91 int len, resid;
92
93 p = fdtbus_get_prop(phandle, prop, &len);
94 if (p == NULL)
95 return NULL;
96
97 for (n = 0, resid = len; resid > 0; n++) {
98 const int cc_phandle =
99 fdtbus_get_phandle_from_native(be32toh(p[0]));
100 if (of_getprop_uint32(cc_phandle, "#clock-cells", &clock_cells))
101 break;
102 if (n == index) {
103 cc = fdtbus_get_clock_controller(cc_phandle);
104 if (cc == NULL)
105 break;
106 clk = cc->cc_funcs->decode(cc->cc_dev, cc_phandle,
107 clock_cells > 0 ? &p[1] : NULL, clock_cells * 4);
108 break;
109 }
110 resid -= (clock_cells + 1) * 4;
111 p += clock_cells + 1;
112 }
113
114 return clk;
115 }
116
117 struct clk *
fdtbus_clock_get_index(int phandle,u_int index)118 fdtbus_clock_get_index(int phandle, u_int index)
119 {
120 return fdtbus_clock_get_index_prop(phandle, index, "clocks");
121 }
122
123 static struct clk *
fdtbus_clock_get_prop(int phandle,const char * clkname,const char * prop)124 fdtbus_clock_get_prop(int phandle, const char *clkname, const char *prop)
125 {
126 u_int index;
127 int err;
128
129 err = fdtbus_get_index(phandle, prop, clkname, &index);
130 if (err != 0)
131 return NULL;
132
133 return fdtbus_clock_get_index(phandle, index);
134 }
135
136 u_int
fdtbus_clock_count(int phandle,const char * prop)137 fdtbus_clock_count(int phandle, const char *prop)
138 {
139 u_int n, clock_cells;
140 int len, resid;
141
142 const u_int *p = fdtbus_get_prop(phandle, prop, &len);
143 if (p == NULL)
144 return 0;
145
146 for (n = 0, resid = len; resid > 0; n++) {
147 const int cc_phandle =
148 fdtbus_get_phandle_from_native(be32toh(p[0]));
149 if (of_getprop_uint32(cc_phandle, "#clock-cells", &clock_cells))
150 break;
151 resid -= (clock_cells + 1) * 4;
152 p += clock_cells + 1;
153 }
154
155 return n;
156 }
157
158 struct clk *
fdtbus_clock_get(int phandle,const char * clkname)159 fdtbus_clock_get(int phandle, const char *clkname)
160 {
161 return fdtbus_clock_get_prop(phandle, clkname, "clock-names");
162 }
163
164 int
fdtbus_clock_enable(int phandle,const char * clkname,bool required)165 fdtbus_clock_enable(int phandle, const char *clkname, bool required)
166 {
167 struct clk *clk;
168
169 clk = fdtbus_clock_get(phandle, clkname);
170 if (clk == NULL)
171 return required ? ENOENT : 0;
172
173 return clk_enable(clk);
174 }
175
176 int
fdtbus_clock_enable_index(int phandle,u_int index,bool required)177 fdtbus_clock_enable_index(int phandle, u_int index, bool required)
178 {
179 struct clk *clk;
180
181 clk = fdtbus_clock_get_index(phandle, index);
182 if (clk == NULL)
183 return required ? ENOENT : 0;
184
185 return clk_enable(clk);
186 }
187
188 /*
189 * Search the DT for a clock by "clock-output-names" property.
190 *
191 * This should only be used by clk backends. Not for use by ordinary
192 * clock consumers!
193 */
194 struct clk *
fdtbus_clock_byname(const char * clkname)195 fdtbus_clock_byname(const char *clkname)
196 {
197 struct fdtbus_clock_controller *cc;
198 u_int index, clock_cells;
199 int err;
200
201 LIST_FOREACH(cc, &fdtbus_clock_controllers, cc_next) {
202 err = fdtbus_get_index(cc->cc_phandle, "clock-output-names", clkname, &index);
203 if (err != 0)
204 continue;
205 if (of_getprop_uint32(cc->cc_phandle, "#clock-cells", &clock_cells))
206 continue;
207 const u_int index_raw = htobe32(index);
208 return cc->cc_funcs->decode(cc->cc_dev,
209 cc->cc_phandle,
210 clock_cells > 0 ? &index_raw : NULL,
211 clock_cells > 0 ? 4 : 0);
212 }
213
214 return NULL;
215 }
216
217 /*
218 * Apply assigned clock parents and rates.
219 *
220 * This is automatically called by fdtbus_register_clock_controller, so clock
221 * drivers likely don't need to call this directly.
222 */
223 void
fdtbus_clock_assign(int phandle)224 fdtbus_clock_assign(int phandle)
225 {
226 u_int index, rates_len;
227 struct clk *clk, *clk_parent;
228 int error;
229
230 const u_int *rates = fdtbus_get_prop(phandle, "assigned-clock-rates", &rates_len);
231 if (rates == NULL)
232 rates_len = 0;
233
234 const u_int nclocks = fdtbus_clock_count(phandle, "assigned-clocks");
235 const u_int nparents = fdtbus_clock_count(phandle, "assigned-clock-parents");
236 const u_int nrates = rates_len / sizeof(*rates);
237
238 for (index = 0; index < nclocks; index++) {
239 clk = fdtbus_clock_get_index_prop(phandle, index, "assigned-clocks");
240 if (clk == NULL) {
241 aprint_debug("clk: assigned clock (%u) not found, skipping...\n", index);
242 continue;
243 }
244
245 if (index < nparents) {
246 clk_parent = fdtbus_clock_get_index_prop(phandle, index, "assigned-clock-parents");
247 if (clk_parent != NULL) {
248 error = clk_set_parent(clk, clk_parent);
249 if (error != 0) {
250 aprint_error("clk: failed to set %s parent to %s, error %d\n",
251 clk->name, clk_parent->name, error);
252 }
253 } else {
254 aprint_debug("clk: failed to set %s parent (not found)\n", clk->name);
255 }
256 }
257
258 if (index < nrates) {
259 const u_int rate = be32toh(rates[index]);
260 if (rate != 0) {
261 error = clk_set_rate(clk, rate);
262 if (error != 0)
263 aprint_error("clk: failed to set %s rate to %u Hz, error %d\n",
264 clk->name, rate, error);
265 }
266 }
267 }
268 }
269