1 /*
2 * SPDX-License-Identifier: MIT
3 *
4 * Copyright 2012 Red Hat Inc
5 */
6
7 #include <linux/dma-buf.h>
8 #include <linux/highmem.h>
9 #include <linux/dma-resv.h>
10 #include <linux/module.h>
11
12 #include <asm/smp.h>
13
14 #include "gem/i915_gem_dmabuf.h"
15 #include "i915_drv.h"
16 #include "i915_gem_object.h"
17 #include "i915_scatterlist.h"
18
19 MODULE_IMPORT_NS(DMA_BUF);
20
I915_SELFTEST_DECLARE(static bool force_different_devices;)21 I915_SELFTEST_DECLARE(static bool force_different_devices;)
22
23 static struct drm_i915_gem_object *dma_buf_to_obj(struct dma_buf *buf)
24 {
25 return to_intel_bo(buf->priv);
26 }
27
28 #ifdef notyet
29
i915_gem_map_dma_buf(struct dma_buf_attachment * attach,enum dma_data_direction dir)30 static struct sg_table *i915_gem_map_dma_buf(struct dma_buf_attachment *attach,
31 enum dma_data_direction dir)
32 {
33 struct drm_i915_gem_object *obj = dma_buf_to_obj(attach->dmabuf);
34 struct sg_table *sgt;
35 struct scatterlist *src, *dst;
36 int ret, i;
37
38 /*
39 * Make a copy of the object's sgt, so that we can make an independent
40 * mapping
41 */
42 sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
43 if (!sgt) {
44 ret = -ENOMEM;
45 goto err;
46 }
47
48 ret = sg_alloc_table(sgt, obj->mm.pages->orig_nents, GFP_KERNEL);
49 if (ret)
50 goto err_free;
51
52 dst = sgt->sgl;
53 for_each_sg(obj->mm.pages->sgl, src, obj->mm.pages->orig_nents, i) {
54 sg_set_page(dst, sg_page(src), src->length, 0);
55 dst = sg_next(dst);
56 }
57
58 ret = dma_map_sgtable(attach->dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC);
59 if (ret)
60 goto err_free_sg;
61
62 return sgt;
63
64 err_free_sg:
65 sg_free_table(sgt);
66 err_free:
67 kfree(sgt);
68 err:
69 return ERR_PTR(ret);
70 }
71
i915_gem_dmabuf_vmap(struct dma_buf * dma_buf,struct iosys_map * map)72 static int i915_gem_dmabuf_vmap(struct dma_buf *dma_buf,
73 struct iosys_map *map)
74 {
75 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
76 void *vaddr;
77
78 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
79 if (IS_ERR(vaddr))
80 return PTR_ERR(vaddr);
81
82 iosys_map_set_vaddr(map, vaddr);
83
84 return 0;
85 }
86
i915_gem_dmabuf_vunmap(struct dma_buf * dma_buf,struct iosys_map * map)87 static void i915_gem_dmabuf_vunmap(struct dma_buf *dma_buf,
88 struct iosys_map *map)
89 {
90 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
91
92 i915_gem_object_flush_map(obj);
93 i915_gem_object_unpin_map(obj);
94 }
95
i915_gem_dmabuf_mmap(struct dma_buf * dma_buf,struct vm_area_struct * vma)96 static int i915_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *vma)
97 {
98 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
99 struct drm_i915_private *i915 = to_i915(obj->base.dev);
100 int ret;
101
102 if (obj->base.size < vma->vm_end - vma->vm_start)
103 return -EINVAL;
104
105 if (HAS_LMEM(i915))
106 return drm_gem_prime_mmap(&obj->base, vma);
107
108 if (!obj->base.filp)
109 return -ENODEV;
110
111 ret = call_mmap(obj->base.filp, vma);
112 if (ret)
113 return ret;
114
115 vma_set_file(vma, obj->base.filp);
116
117 return 0;
118 }
119
i915_gem_begin_cpu_access(struct dma_buf * dma_buf,enum dma_data_direction direction)120 static int i915_gem_begin_cpu_access(struct dma_buf *dma_buf, enum dma_data_direction direction)
121 {
122 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
123 bool write = (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE);
124 struct i915_gem_ww_ctx ww;
125 int err;
126
127 i915_gem_ww_ctx_init(&ww, true);
128 retry:
129 err = i915_gem_object_lock(obj, &ww);
130 if (!err)
131 err = i915_gem_object_pin_pages(obj);
132 if (!err) {
133 err = i915_gem_object_set_to_cpu_domain(obj, write);
134 i915_gem_object_unpin_pages(obj);
135 }
136 if (err == -EDEADLK) {
137 err = i915_gem_ww_ctx_backoff(&ww);
138 if (!err)
139 goto retry;
140 }
141 i915_gem_ww_ctx_fini(&ww);
142 return err;
143 }
144
i915_gem_end_cpu_access(struct dma_buf * dma_buf,enum dma_data_direction direction)145 static int i915_gem_end_cpu_access(struct dma_buf *dma_buf, enum dma_data_direction direction)
146 {
147 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
148 struct i915_gem_ww_ctx ww;
149 int err;
150
151 i915_gem_ww_ctx_init(&ww, true);
152 retry:
153 err = i915_gem_object_lock(obj, &ww);
154 if (!err)
155 err = i915_gem_object_pin_pages(obj);
156 if (!err) {
157 err = i915_gem_object_set_to_gtt_domain(obj, false);
158 i915_gem_object_unpin_pages(obj);
159 }
160 if (err == -EDEADLK) {
161 err = i915_gem_ww_ctx_backoff(&ww);
162 if (!err)
163 goto retry;
164 }
165 i915_gem_ww_ctx_fini(&ww);
166 return err;
167 }
168
i915_gem_dmabuf_attach(struct dma_buf * dmabuf,struct dma_buf_attachment * attach)169 static int i915_gem_dmabuf_attach(struct dma_buf *dmabuf,
170 struct dma_buf_attachment *attach)
171 {
172 struct drm_i915_gem_object *obj = dma_buf_to_obj(dmabuf);
173 struct i915_gem_ww_ctx ww;
174 int err;
175
176 if (!i915_gem_object_can_migrate(obj, INTEL_REGION_SMEM))
177 return -EOPNOTSUPP;
178
179 for_i915_gem_ww(&ww, err, true) {
180 err = i915_gem_object_lock(obj, &ww);
181 if (err)
182 continue;
183
184 err = i915_gem_object_migrate(obj, &ww, INTEL_REGION_SMEM);
185 if (err)
186 continue;
187
188 err = i915_gem_object_wait_migration(obj, 0);
189 if (err)
190 continue;
191
192 err = i915_gem_object_pin_pages(obj);
193 }
194
195 return err;
196 }
197
i915_gem_dmabuf_detach(struct dma_buf * dmabuf,struct dma_buf_attachment * attach)198 static void i915_gem_dmabuf_detach(struct dma_buf *dmabuf,
199 struct dma_buf_attachment *attach)
200 {
201 struct drm_i915_gem_object *obj = dma_buf_to_obj(dmabuf);
202
203 i915_gem_object_unpin_pages(obj);
204 }
205
206 #endif /* notyet */
207
208 static const struct dma_buf_ops i915_dmabuf_ops = {
209 #ifdef notyet
210 .attach = i915_gem_dmabuf_attach,
211 .detach = i915_gem_dmabuf_detach,
212 .map_dma_buf = i915_gem_map_dma_buf,
213 .unmap_dma_buf = drm_gem_unmap_dma_buf,
214 #endif
215 .release = drm_gem_dmabuf_release,
216 #ifdef notyet
217 .mmap = i915_gem_dmabuf_mmap,
218 .vmap = i915_gem_dmabuf_vmap,
219 .vunmap = i915_gem_dmabuf_vunmap,
220 .begin_cpu_access = i915_gem_begin_cpu_access,
221 .end_cpu_access = i915_gem_end_cpu_access,
222 #endif
223 };
224
i915_gem_prime_export(struct drm_gem_object * gem_obj,int flags)225 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags)
226 {
227 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
228 DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
229
230 exp_info.ops = &i915_dmabuf_ops;
231 exp_info.size = gem_obj->size;
232 exp_info.flags = flags;
233 exp_info.priv = gem_obj;
234 exp_info.resv = obj->base.resv;
235
236 if (obj->ops->dmabuf_export) {
237 int ret = obj->ops->dmabuf_export(obj);
238 if (ret)
239 return ERR_PTR(ret);
240 }
241
242 return drm_gem_dmabuf_export(gem_obj->dev, &exp_info);
243 }
244
245 #ifdef notyet
246
i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object * obj)247 static int i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object *obj)
248 {
249 struct drm_i915_private *i915 = to_i915(obj->base.dev);
250 struct sg_table *sgt;
251
252 assert_object_held(obj);
253
254 sgt = dma_buf_map_attachment(obj->base.import_attach,
255 DMA_BIDIRECTIONAL);
256 if (IS_ERR(sgt))
257 return PTR_ERR(sgt);
258
259 /*
260 * DG1 is special here since it still snoops transactions even with
261 * CACHE_NONE. This is not the case with other HAS_SNOOP platforms. We
262 * might need to revisit this as we add new discrete platforms.
263 *
264 * XXX: Consider doing a vmap flush or something, where possible.
265 * Currently we just do a heavy handed wbinvd_on_all_cpus() here since
266 * the underlying sg_table might not even point to struct pages, so we
267 * can't just call drm_clflush_sg or similar, like we do elsewhere in
268 * the driver.
269 */
270 if (i915_gem_object_can_bypass_llc(obj) ||
271 (!HAS_LLC(i915) && !IS_DG1(i915)))
272 wbinvd_on_all_cpus();
273
274 __i915_gem_object_set_pages(obj, sgt);
275
276 return 0;
277 }
278
i915_gem_object_put_pages_dmabuf(struct drm_i915_gem_object * obj,struct sg_table * sgt)279 static void i915_gem_object_put_pages_dmabuf(struct drm_i915_gem_object *obj,
280 struct sg_table *sgt)
281 {
282 dma_buf_unmap_attachment(obj->base.import_attach, sgt,
283 DMA_BIDIRECTIONAL);
284 }
285
286 static const struct drm_i915_gem_object_ops i915_gem_object_dmabuf_ops = {
287 .name = "i915_gem_object_dmabuf",
288 .get_pages = i915_gem_object_get_pages_dmabuf,
289 .put_pages = i915_gem_object_put_pages_dmabuf,
290 };
291
292 #endif /* notyet */
293
i915_gem_prime_import(struct drm_device * dev,struct dma_buf * dma_buf)294 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
295 struct dma_buf *dma_buf)
296 {
297 static struct lock_class_key lock_class;
298 struct dma_buf_attachment *attach;
299 struct drm_i915_gem_object *obj;
300 int ret;
301
302 /* is this one of own objects? */
303 if (dma_buf->ops == &i915_dmabuf_ops) {
304 obj = dma_buf_to_obj(dma_buf);
305 /* is it from our device? */
306 if (obj->base.dev == dev &&
307 !I915_SELFTEST_ONLY(force_different_devices)) {
308 /*
309 * Importing dmabuf exported from out own gem increases
310 * refcount on gem itself instead of f_count of dmabuf.
311 */
312 return &i915_gem_object_get(obj)->base;
313 }
314 }
315
316 if (i915_gem_object_size_2big(dma_buf->size))
317 return ERR_PTR(-E2BIG);
318
319 /* need to attach */
320 attach = dma_buf_attach(dma_buf, dev->dev);
321 if (IS_ERR(attach))
322 return ERR_CAST(attach);
323
324 #ifdef notyet
325 get_dma_buf(dma_buf);
326
327 obj = i915_gem_object_alloc();
328 if (!obj) {
329 ret = -ENOMEM;
330 goto fail_detach;
331 }
332
333 drm_gem_private_object_init(dev, &obj->base, dma_buf->size);
334 i915_gem_object_init(obj, &i915_gem_object_dmabuf_ops, &lock_class,
335 I915_BO_ALLOC_USER);
336 obj->base.import_attach = attach;
337 obj->base.resv = dma_buf->resv;
338
339 /* We use GTT as shorthand for a coherent domain, one that is
340 * neither in the GPU cache nor in the CPU cache, where all
341 * writes are immediately visible in memory. (That's not strictly
342 * true, but it's close! There are internal buffers such as the
343 * write-combined buffer or a delay through the chipset for GTT
344 * writes that do require us to treat GTT as a separate cache domain.)
345 */
346 obj->read_domains = I915_GEM_DOMAIN_GTT;
347 obj->write_domain = 0;
348
349 return &obj->base;
350
351 fail_detach:
352 dma_buf_detach(dma_buf, attach);
353 dma_buf_put(dma_buf);
354
355 return ERR_PTR(ret);
356 #else
357 ret = 0;
358 panic(__func__);
359 #endif
360 }
361
362 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
363 #include "selftests/mock_dmabuf.c"
364 #include "selftests/i915_gem_dmabuf.c"
365 #endif
366