1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2004
2 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "regs.h"
29 #include "hard-reg-set.h"
30 #include "real.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
34 #include "output.h"
35 #include "insn-attr.h"
36 #include "flags.h"
37 #include "recog.h"
38 #include "reload.h"
39 #include "expr.h"
40 #include "obstack.h"
41 #include "except.h"
42 #include "function.h"
43 #include "optabs.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "tm_p.h"
47 #include "ggc.h"
48 #include <ctype.h>
49 #include "target.h"
50 #include "target-def.h"
51
52 #ifndef FRV_INLINE
53 #define FRV_INLINE inline
54 #endif
55
56 /* Temporary register allocation support structure. */
57 typedef struct frv_tmp_reg_struct
58 {
59 HARD_REG_SET regs; /* possible registers to allocate */
60 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
61 }
62 frv_tmp_reg_t;
63
64 /* Register state information for VLIW re-packing phase. These values must fit
65 within an unsigned char. */
66 #define REGSTATE_DEAD 0x00 /* register is currently dead */
67 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
68 #define REGSTATE_LIVE 0x08 /* register is live */
69 #define REGSTATE_MODIFIED 0x10 /* reg modified in current VLIW insn */
70 #define REGSTATE_IF_TRUE 0x20 /* reg modified in cond exec true */
71 #define REGSTATE_IF_FALSE 0x40 /* reg modified in cond exec false */
72 #define REGSTATE_UNUSED 0x80 /* bit for hire */
73 #define REGSTATE_MASK 0xff /* mask for the bits to set */
74
75 /* conditional expression used */
76 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
77
78 /* The following is not sure in the reg_state bytes, so can have a larger value
79 than 0xff. */
80 #define REGSTATE_CONDJUMP 0x100 /* conditional jump done in VLIW insn */
81
82 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
83 memory move. */
84 enum frv_stack_op
85 {
86 FRV_LOAD,
87 FRV_STORE
88 };
89
90 /* Information required by frv_frame_access. */
91 typedef struct
92 {
93 /* This field is FRV_LOAD if registers are to be loaded from the stack and
94 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
95 the move is being done by the prologue code while FRV_LOAD implies it
96 is being done by the epilogue. */
97 enum frv_stack_op op;
98
99 /* The base register to use when accessing the stack. This may be the
100 frame pointer, stack pointer, or a temporary. The choice of register
101 depends on which part of the frame is being accessed and how big the
102 frame is. */
103 rtx base;
104
105 /* The offset of BASE from the bottom of the current frame, in bytes. */
106 int base_offset;
107 } frv_frame_accessor_t;
108
109 /* Define the information needed to generate branch and scc insns. This is
110 stored from the compare operation. */
111 rtx frv_compare_op0;
112 rtx frv_compare_op1;
113
114 /* Conditional execution support gathered together in one structure. */
115 typedef struct
116 {
117 /* Linked list of insns to add if the conditional execution conversion was
118 successful. Each link points to an EXPR_LIST which points to the pattern
119 of the insn to add, and the insn to be inserted before. */
120 rtx added_insns_list;
121
122 /* Identify which registers are safe to allocate for if conversions to
123 conditional execution. We keep the last allocated register in the
124 register classes between COND_EXEC statements. This will mean we allocate
125 different registers for each different COND_EXEC group if we can. This
126 might allow the scheduler to intermix two different COND_EXEC sections. */
127 frv_tmp_reg_t tmp_reg;
128
129 /* For nested IFs, identify which CC registers are used outside of setting
130 via a compare isnsn, and using via a check insn. This will allow us to
131 know if we can rewrite the register to use a different register that will
132 be paired with the CR register controlling the nested IF-THEN blocks. */
133 HARD_REG_SET nested_cc_ok_rewrite;
134
135 /* Temporary registers allocated to hold constants during conditional
136 execution. */
137 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
138
139 /* Current number of temp registers available. */
140 int cur_scratch_regs;
141
142 /* Number of nested conditional execution blocks. */
143 int num_nested_cond_exec;
144
145 /* Map of insns that set up constants in scratch registers. */
146 bitmap scratch_insns_bitmap;
147
148 /* Conditional execution test register (CC0..CC7). */
149 rtx cr_reg;
150
151 /* Conditional execution compare register that is paired with cr_reg, so that
152 nested compares can be done. The csubcc and caddcc instructions don't
153 have enough bits to specify both a CC register to be set and a CR register
154 to do the test on, so the same bit number is used for both. Needless to
155 say, this is rather inconvenient for GCC. */
156 rtx nested_cc_reg;
157
158 /* Extra CR registers used for &&, ||. */
159 rtx extra_int_cr;
160 rtx extra_fp_cr;
161
162 /* Previous CR used in nested if, to make sure we are dealing with the same
163 nested if as the previous statement. */
164 rtx last_nested_if_cr;
165 }
166 frv_ifcvt_t;
167
168 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
169
170 /* Map register number to smallest register class. */
171 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
172
173 /* Map class letter into register class. */
174 enum reg_class reg_class_from_letter[256];
175
176 /* Cached value of frv_stack_info. */
177 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
178
179 /* -mbranch-cost= support */
180 const char *frv_branch_cost_string;
181 int frv_branch_cost_int = DEFAULT_BRANCH_COST;
182
183 /* -mcpu= support */
184 const char *frv_cpu_string; /* -mcpu= option */
185 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
186
187 /* -mcond-exec-insns= support */
188 const char *frv_condexec_insns_str; /* -mcond-exec-insns= option */
189 int frv_condexec_insns = DEFAULT_CONDEXEC_INSNS; /* value of -mcond-exec-insns*/
190
191 /* -mcond-exec-temps= support */
192 const char *frv_condexec_temps_str; /* -mcond-exec-temps= option */
193 int frv_condexec_temps = DEFAULT_CONDEXEC_TEMPS; /* value of -mcond-exec-temps*/
194
195 /* -msched-lookahead=n */
196 const char *frv_sched_lookahead_str; /* -msched-lookahead=n */
197 int frv_sched_lookahead = 4; /* -msched-lookahead=n */
198
199 /* Forward references */
200 static int frv_default_flags_for_cpu (void);
201 static int frv_string_begins_with (tree, const char *);
202 static FRV_INLINE int const_small_data_p (rtx);
203 static FRV_INLINE int plus_small_data_p (rtx, rtx);
204 static void frv_print_operand_memory_reference_reg
205 (FILE *, rtx);
206 static void frv_print_operand_memory_reference (FILE *, rtx, int);
207 static int frv_print_operand_jump_hint (rtx);
208 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
209 static rtx single_set_pattern (rtx);
210 static int frv_function_contains_far_jump (void);
211 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
212 enum reg_class,
213 enum machine_mode,
214 int, int);
215 static rtx frv_frame_offset_rtx (int);
216 static rtx frv_frame_mem (enum machine_mode, rtx, int);
217 static rtx frv_dwarf_store (rtx, int);
218 static void frv_frame_insn (rtx, rtx);
219 static void frv_frame_access (frv_frame_accessor_t*,
220 rtx, int);
221 static void frv_frame_access_multi (frv_frame_accessor_t*,
222 frv_stack_t *, int);
223 static void frv_frame_access_standard_regs (enum frv_stack_op,
224 frv_stack_t *);
225 static struct machine_function *frv_init_machine_status (void);
226 static int frv_legitimate_memory_operand (rtx, enum machine_mode, int);
227 static rtx frv_int_to_acc (enum insn_code, int, rtx);
228 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
229 static rtx frv_read_argument (tree *);
230 static int frv_check_constant_argument (enum insn_code, int, rtx);
231 static rtx frv_legitimize_target (enum insn_code, rtx);
232 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
233 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
234 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
235 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
236 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
237 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
238 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
239 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
240 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
241 static rtx frv_expand_mclracc_builtin (tree);
242 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
243 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
244 static rtx frv_expand_noargs_builtin (enum insn_code);
245 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
246 static int frv_clear_registers_used (rtx *, void *);
247 static void frv_ifcvt_add_insn (rtx, rtx, int);
248 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
249 static rtx frv_ifcvt_load_value (rtx, rtx);
250 static void frv_registers_update (rtx, unsigned char [],
251 int [], int *, int);
252 static int frv_registers_used_p (rtx, unsigned char [], int);
253 static int frv_registers_set_p (rtx, unsigned char [], int);
254 static int frv_issue_rate (void);
255 static int frv_use_dfa_pipeline_interface (void);
256 static void frv_pack_insns (void);
257 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
258 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
259 static bool frv_assemble_integer (rtx, unsigned, int);
260 static void frv_init_builtins (void);
261 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
262 static void frv_init_libfuncs (void);
263 static bool frv_in_small_data_p (tree);
264 static void frv_asm_output_mi_thunk
265 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
266 static bool frv_rtx_costs (rtx, int, int, int*);
267 static void frv_asm_out_constructor (rtx, int);
268 static void frv_asm_out_destructor (rtx, int);
269
270 /* Initialize the GCC target structure. */
271 #undef TARGET_ASM_FUNCTION_PROLOGUE
272 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
273 #undef TARGET_ASM_FUNCTION_EPILOGUE
274 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
275 #undef TARGET_ASM_INTEGER
276 #define TARGET_ASM_INTEGER frv_assemble_integer
277 #undef TARGET_INIT_BUILTINS
278 #define TARGET_INIT_BUILTINS frv_init_builtins
279 #undef TARGET_EXPAND_BUILTIN
280 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
281 #undef TARGET_INIT_LIBFUNCS
282 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
283 #undef TARGET_IN_SMALL_DATA_P
284 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
285 #undef TARGET_RTX_COSTS
286 #define TARGET_RTX_COSTS frv_rtx_costs
287 #undef TARGET_ASM_CONSTRUCTOR
288 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
289 #undef TARGET_ASM_DESTRUCTOR
290 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
291
292 #undef TARGET_ASM_OUTPUT_MI_THUNK
293 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
294 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
295 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
296
297 #undef TARGET_SCHED_ISSUE_RATE
298 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
299 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
300 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE frv_use_dfa_pipeline_interface
301
302 struct gcc_target targetm = TARGET_INITIALIZER;
303
304 /* Given a CONST, return true if the symbol_ref points to small data. */
305
306 static FRV_INLINE int
const_small_data_p(rtx x)307 const_small_data_p (rtx x)
308 {
309 rtx x0, x1;
310
311 if (GET_CODE (XEXP (x, 0)) != PLUS)
312 return FALSE;
313
314 x0 = XEXP (XEXP (x, 0), 0);
315 if (GET_CODE (x0) != SYMBOL_REF || !SYMBOL_REF_SMALL_P (x0))
316 return FALSE;
317
318 x1 = XEXP (XEXP (x, 0), 1);
319 if (GET_CODE (x1) != CONST_INT
320 || !IN_RANGE_P (INTVAL (x1), -2048, 2047))
321 return FALSE;
322
323 return TRUE;
324 }
325
326 /* Given a PLUS, return true if this is a small data reference. */
327
328 static FRV_INLINE int
plus_small_data_p(rtx op0,rtx op1)329 plus_small_data_p (rtx op0, rtx op1)
330 {
331 if (GET_MODE (op0) == SImode
332 && GET_CODE (op0) == REG
333 && REGNO (op0) == SDA_BASE_REG)
334 {
335 if (GET_CODE (op1) == SYMBOL_REF)
336 return SYMBOL_REF_SMALL_P (op1);
337
338 if (GET_CODE (op1) == CONST)
339 return const_small_data_p (op1);
340 }
341
342 return FALSE;
343 }
344
345
346 static int
frv_default_flags_for_cpu(void)347 frv_default_flags_for_cpu (void)
348 {
349 switch (frv_cpu_type)
350 {
351 case FRV_CPU_GENERIC:
352 return MASK_DEFAULT_FRV;
353
354 case FRV_CPU_FR500:
355 case FRV_CPU_TOMCAT:
356 return MASK_DEFAULT_FR500;
357
358 case FRV_CPU_FR400:
359 return MASK_DEFAULT_FR400;
360
361 case FRV_CPU_FR300:
362 case FRV_CPU_SIMPLE:
363 return MASK_DEFAULT_SIMPLE;
364 }
365 abort ();
366 }
367
368 /* Sometimes certain combinations of command options do not make
369 sense on a particular target machine. You can define a macro
370 `OVERRIDE_OPTIONS' to take account of this. This macro, if
371 defined, is executed once just after all the command options have
372 been parsed.
373
374 Don't use this macro to turn on various extra optimizations for
375 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
376
377 void
frv_override_options(void)378 frv_override_options (void)
379 {
380 int regno, i;
381
382 /* Set the cpu type. */
383 if (frv_cpu_string)
384 {
385 if (strcmp (frv_cpu_string, "simple") == 0)
386 frv_cpu_type = FRV_CPU_SIMPLE;
387
388 else if (strcmp (frv_cpu_string, "tomcat") == 0)
389 frv_cpu_type = FRV_CPU_TOMCAT;
390
391 else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0)
392 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
393
394 else
395 {
396 const char *p = frv_cpu_string + sizeof ("fr") - 1;
397 if (strcmp (p, "500") == 0)
398 frv_cpu_type = FRV_CPU_FR500;
399
400 else if (strcmp (p, "400") == 0)
401 frv_cpu_type = FRV_CPU_FR400;
402
403 else if (strcmp (p, "300") == 0)
404 frv_cpu_type = FRV_CPU_FR300;
405
406 else if (strcmp (p, "v") == 0)
407 frv_cpu_type = FRV_CPU_GENERIC;
408
409 else
410 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
411 }
412 }
413
414 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
415
416 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
417 linker about linking pic and non-pic code. */
418 if (TARGET_LIBPIC)
419 {
420 if (!flag_pic) /* -fPIC */
421 flag_pic = 2;
422
423 if (! g_switch_set) /* -G0 */
424 {
425 g_switch_set = 1;
426 g_switch_value = 0;
427 }
428 }
429
430 /* Both -fpic and -gdwarf want to use .previous and the assembler only keeps
431 one level. */
432 if (write_symbols == DWARF_DEBUG && flag_pic)
433 error ("-fpic and -gdwarf are incompatible (-fpic and -g/-gdwarf-2 are fine)");
434
435 /* Change the branch cost value. */
436 if (frv_branch_cost_string)
437 frv_branch_cost_int = atoi (frv_branch_cost_string);
438
439 /* Change the # of insns to be converted to conditional execution. */
440 if (frv_condexec_insns_str)
441 frv_condexec_insns = atoi (frv_condexec_insns_str);
442
443 /* Change # of temporary registers used to hold integer constants. */
444 if (frv_condexec_temps_str)
445 frv_condexec_temps = atoi (frv_condexec_temps_str);
446
447 /* Change scheduling look ahead. */
448 if (frv_sched_lookahead_str)
449 frv_sched_lookahead = atoi (frv_sched_lookahead_str);
450
451 /* A C expression whose value is a register class containing hard
452 register REGNO. In general there is more than one such class;
453 choose a class which is "minimal", meaning that no smaller class
454 also contains the register. */
455
456 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
457 {
458 enum reg_class class;
459
460 if (GPR_P (regno))
461 {
462 int gpr_reg = regno - GPR_FIRST;
463 if ((gpr_reg & 3) == 0)
464 class = QUAD_REGS;
465
466 else if ((gpr_reg & 1) == 0)
467 class = EVEN_REGS;
468
469 else
470 class = GPR_REGS;
471 }
472
473 else if (FPR_P (regno))
474 {
475 int fpr_reg = regno - GPR_FIRST;
476 if ((fpr_reg & 3) == 0)
477 class = QUAD_FPR_REGS;
478
479 else if ((fpr_reg & 1) == 0)
480 class = FEVEN_REGS;
481
482 else
483 class = FPR_REGS;
484 }
485
486 else if (regno == LR_REGNO)
487 class = LR_REG;
488
489 else if (regno == LCR_REGNO)
490 class = LCR_REG;
491
492 else if (ICC_P (regno))
493 class = ICC_REGS;
494
495 else if (FCC_P (regno))
496 class = FCC_REGS;
497
498 else if (ICR_P (regno))
499 class = ICR_REGS;
500
501 else if (FCR_P (regno))
502 class = FCR_REGS;
503
504 else if (ACC_P (regno))
505 {
506 int r = regno - ACC_FIRST;
507 if ((r & 3) == 0)
508 class = QUAD_ACC_REGS;
509 else if ((r & 1) == 0)
510 class = EVEN_ACC_REGS;
511 else
512 class = ACC_REGS;
513 }
514
515 else if (ACCG_P (regno))
516 class = ACCG_REGS;
517
518 else
519 class = NO_REGS;
520
521 regno_reg_class[regno] = class;
522 }
523
524 /* Check for small data option */
525 if (!g_switch_set)
526 g_switch_value = SDATA_DEFAULT_SIZE;
527
528 /* A C expression which defines the machine-dependent operand
529 constraint letters for register classes. If CHAR is such a
530 letter, the value should be the register class corresponding to
531 it. Otherwise, the value should be `NO_REGS'. The register
532 letter `r', corresponding to class `GENERAL_REGS', will not be
533 passed to this macro; you do not need to handle it.
534
535 The following letters are unavailable, due to being used as
536 constraints:
537 '0'..'9'
538 '<', '>'
539 'E', 'F', 'G', 'H'
540 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
541 'Q', 'R', 'S', 'T', 'U'
542 'V', 'X'
543 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
544
545 for (i = 0; i < 256; i++)
546 reg_class_from_letter[i] = NO_REGS;
547
548 reg_class_from_letter['a'] = ACC_REGS;
549 reg_class_from_letter['b'] = EVEN_ACC_REGS;
550 reg_class_from_letter['c'] = CC_REGS;
551 reg_class_from_letter['d'] = GPR_REGS;
552 reg_class_from_letter['e'] = EVEN_REGS;
553 reg_class_from_letter['f'] = FPR_REGS;
554 reg_class_from_letter['h'] = FEVEN_REGS;
555 reg_class_from_letter['l'] = LR_REG;
556 reg_class_from_letter['q'] = QUAD_REGS;
557 reg_class_from_letter['t'] = ICC_REGS;
558 reg_class_from_letter['u'] = FCC_REGS;
559 reg_class_from_letter['v'] = ICR_REGS;
560 reg_class_from_letter['w'] = FCR_REGS;
561 reg_class_from_letter['x'] = QUAD_FPR_REGS;
562 reg_class_from_letter['y'] = LCR_REG;
563 reg_class_from_letter['z'] = SPR_REGS;
564 reg_class_from_letter['A'] = QUAD_ACC_REGS;
565 reg_class_from_letter['B'] = ACCG_REGS;
566 reg_class_from_letter['C'] = CR_REGS;
567
568 /* There is no single unaligned SI op for PIC code. Sometimes we
569 need to use ".4byte" and sometimes we need to use ".picptr".
570 See frv_assemble_integer for details. */
571 if (flag_pic)
572 targetm.asm_out.unaligned_op.si = 0;
573
574 init_machine_status = frv_init_machine_status;
575 }
576
577
578 /* Some machines may desire to change what optimizations are performed for
579 various optimization levels. This macro, if defined, is executed once just
580 after the optimization level is determined and before the remainder of the
581 command options have been parsed. Values set in this macro are used as the
582 default values for the other command line options.
583
584 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
585 `-O' is specified, and 0 if neither is specified.
586
587 SIZE is nonzero if `-Os' is specified, 0 otherwise.
588
589 You should not use this macro to change options that are not
590 machine-specific. These should uniformly selected by the same optimization
591 level on all supported machines. Use this macro to enable machbine-specific
592 optimizations.
593
594 *Do not examine `write_symbols' in this macro!* The debugging options are
595 *not supposed to alter the generated code. */
596
597 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
598 scheduling pass at the current time. */
599 void
frv_optimization_options(int level,int size ATTRIBUTE_UNUSED)600 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
601 {
602 if (level >= 2)
603 {
604 #ifdef DISABLE_SCHED2
605 flag_schedule_insns_after_reload = 0;
606 #endif
607 #ifdef ENABLE_RCSP
608 flag_rcsp = 1;
609 #endif
610 }
611 }
612
613
614 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
615
616 static int
frv_string_begins_with(tree name,const char * prefix)617 frv_string_begins_with (tree name, const char *prefix)
618 {
619 int prefix_len = strlen (prefix);
620
621 /* Remember: NAME's length includes the null terminator. */
622 return (TREE_STRING_LENGTH (name) > prefix_len
623 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
624 }
625
626 /* Zero or more C statements that may conditionally modify two variables
627 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
628 been initialized from the two preceding macros.
629
630 This is necessary in case the fixed or call-clobbered registers depend on
631 target flags.
632
633 You need not define this macro if it has no work to do.
634
635 If the usage of an entire class of registers depends on the target flags,
636 you may indicate this to GCC by using this macro to modify `fixed_regs' and
637 `call_used_regs' to 1 for each of the registers in the classes which should
638 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
639 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
640
641 (However, if this class is not included in `GENERAL_REGS' and all of the
642 insn patterns whose constraints permit this class are controlled by target
643 switches, then GCC will automatically avoid using these registers when the
644 target switches are opposed to them.) */
645
646 void
frv_conditional_register_usage(void)647 frv_conditional_register_usage (void)
648 {
649 int i;
650
651 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
652 fixed_regs[i] = call_used_regs[i] = 1;
653
654 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
655 fixed_regs[i] = call_used_regs[i] = 1;
656
657 for (i = ACC_FIRST + NUM_ACCS; i <= ACC_LAST; i++)
658 fixed_regs[i] = call_used_regs[i] = 1;
659
660 for (i = ACCG_FIRST + NUM_ACCS; i <= ACCG_LAST; i++)
661 fixed_regs[i] = call_used_regs[i] = 1;
662
663 /* Reserve the registers used for conditional execution. At present, we need
664 1 ICC and 1 ICR register. */
665 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
666 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
667
668 if (TARGET_FIXED_CC)
669 {
670 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
671 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
672 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
673 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
674 }
675
676 #if 0
677 /* If -fpic, SDA_BASE_REG is the PIC register. */
678 if (g_switch_value == 0 && !flag_pic)
679 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
680
681 if (!flag_pic)
682 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
683 #endif
684 }
685
686
687 /*
688 * Compute the stack frame layout
689 *
690 * Register setup:
691 * +---------------+-----------------------+-----------------------+
692 * |Register |type |caller-save/callee-save|
693 * +---------------+-----------------------+-----------------------+
694 * |GR0 |Zero register | - |
695 * |GR1 |Stack pointer(SP) | - |
696 * |GR2 |Frame pointer(FP) | - |
697 * |GR3 |Hidden parameter | caller save |
698 * |GR4-GR7 | - | caller save |
699 * |GR8-GR13 |Argument register | caller save |
700 * |GR14-GR15 | - | caller save |
701 * |GR16-GR31 | - | callee save |
702 * |GR32-GR47 | - | caller save |
703 * |GR48-GR63 | - | callee save |
704 * |FR0-FR15 | - | caller save |
705 * |FR16-FR31 | - | callee save |
706 * |FR32-FR47 | - | caller save |
707 * |FR48-FR63 | - | callee save |
708 * +---------------+-----------------------+-----------------------+
709 *
710 * Stack frame setup:
711 * Low
712 * SP-> |-----------------------------------|
713 * | Argument area |
714 * |-----------------------------------|
715 * | Register save area |
716 * |-----------------------------------|
717 * | Local variable save area |
718 * FP-> |-----------------------------------|
719 * | Old FP |
720 * |-----------------------------------|
721 * | Hidden parameter save area |
722 * |-----------------------------------|
723 * | Return address(LR) storage area |
724 * |-----------------------------------|
725 * | Padding for alignment |
726 * |-----------------------------------|
727 * | Register argument area |
728 * OLD SP-> |-----------------------------------|
729 * | Parameter area |
730 * |-----------------------------------|
731 * High
732 *
733 * Argument area/Parameter area:
734 *
735 * When a function is called, this area is used for argument transfer. When
736 * the argument is set up by the caller function, this area is referred to as
737 * the argument area. When the argument is referenced by the callee function,
738 * this area is referred to as the parameter area. The area is allocated when
739 * all arguments cannot be placed on the argument register at the time of
740 * argument transfer.
741 *
742 * Register save area:
743 *
744 * This is a register save area that must be guaranteed for the caller
745 * function. This area is not secured when the register save operation is not
746 * needed.
747 *
748 * Local variable save area:
749 *
750 * This is the area for local variables and temporary variables.
751 *
752 * Old FP:
753 *
754 * This area stores the FP value of the caller function.
755 *
756 * Hidden parameter save area:
757 *
758 * This area stores the start address of the return value storage
759 * area for a struct/union return function.
760 * When a struct/union is used as the return value, the caller
761 * function stores the return value storage area start address in
762 * register GR3 and passes it to the caller function.
763 * The callee function interprets the address stored in the GR3
764 * as the return value storage area start address.
765 * When register GR3 needs to be saved into memory, the callee
766 * function saves it in the hidden parameter save area. This
767 * area is not secured when the save operation is not needed.
768 *
769 * Return address(LR) storage area:
770 *
771 * This area saves the LR. The LR stores the address of a return to the caller
772 * function for the purpose of function calling.
773 *
774 * Argument register area:
775 *
776 * This area saves the argument register. This area is not secured when the
777 * save operation is not needed.
778 *
779 * Argument:
780 *
781 * Arguments, the count of which equals the count of argument registers (6
782 * words), are positioned in registers GR8 to GR13 and delivered to the callee
783 * function. When a struct/union return function is called, the return value
784 * area address is stored in register GR3. Arguments not placed in the
785 * argument registers will be stored in the stack argument area for transfer
786 * purposes. When an 8-byte type argument is to be delivered using registers,
787 * it is divided into two and placed in two registers for transfer. When
788 * argument registers must be saved to memory, the callee function secures an
789 * argument register save area in the stack. In this case, a continuous
790 * argument register save area must be established in the parameter area. The
791 * argument register save area must be allocated as needed to cover the size of
792 * the argument register to be saved. If the function has a variable count of
793 * arguments, it saves all argument registers in the argument register save
794 * area.
795 *
796 * Argument Extension Format:
797 *
798 * When an argument is to be stored in the stack, its type is converted to an
799 * extended type in accordance with the individual argument type. The argument
800 * is freed by the caller function after the return from the callee function is
801 * made.
802 *
803 * +-----------------------+---------------+------------------------+
804 * | Argument Type |Extended Type |Stack Storage Size(byte)|
805 * +-----------------------+---------------+------------------------+
806 * |char |int | 4 |
807 * |signed char |int | 4 |
808 * |unsigned char |int | 4 |
809 * |[signed] short int |int | 4 |
810 * |unsigned short int |int | 4 |
811 * |[signed] int |No extension | 4 |
812 * |unsigned int |No extension | 4 |
813 * |[signed] long int |No extension | 4 |
814 * |unsigned long int |No extension | 4 |
815 * |[signed] long long int |No extension | 8 |
816 * |unsigned long long int |No extension | 8 |
817 * |float |double | 8 |
818 * |double |No extension | 8 |
819 * |long double |No extension | 8 |
820 * |pointer |No extension | 4 |
821 * |struct/union |- | 4 (*1) |
822 * +-----------------------+---------------+------------------------+
823 *
824 * When a struct/union is to be delivered as an argument, the caller copies it
825 * to the local variable area and delivers the address of that area.
826 *
827 * Return Value:
828 *
829 * +-------------------------------+----------------------+
830 * |Return Value Type |Return Value Interface|
831 * +-------------------------------+----------------------+
832 * |void |None |
833 * |[signed|unsigned] char |GR8 |
834 * |[signed|unsigned] short int |GR8 |
835 * |[signed|unsigned] int |GR8 |
836 * |[signed|unsigned] long int |GR8 |
837 * |pointer |GR8 |
838 * |[signed|unsigned] long long int|GR8 & GR9 |
839 * |float |GR8 |
840 * |double |GR8 & GR9 |
841 * |long double |GR8 & GR9 |
842 * |struct/union |(*1) |
843 * +-------------------------------+----------------------+
844 *
845 * When a struct/union is used as the return value, the caller function stores
846 * the start address of the return value storage area into GR3 and then passes
847 * it to the callee function. The callee function interprets GR3 as the start
848 * address of the return value storage area. When this address needs to be
849 * saved in memory, the callee function secures the hidden parameter save area
850 * and saves the address in that area.
851 */
852
853 frv_stack_t *
frv_stack_info(void)854 frv_stack_info (void)
855 {
856 static frv_stack_t info, zero_info;
857 frv_stack_t *info_ptr = &info;
858 tree fndecl = current_function_decl;
859 int varargs_p = 0;
860 tree cur_arg;
861 tree next_arg;
862 int range;
863 int alignment;
864 int offset;
865
866 /* If we've already calculated the values and reload is complete,
867 just return now. */
868 if (frv_stack_cache)
869 return frv_stack_cache;
870
871 /* Zero all fields. */
872 info = zero_info;
873
874 /* Set up the register range information. */
875 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
876 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
877 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
878 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
879
880 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
881 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
882 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
883 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
884
885 info_ptr->regs[STACK_REGS_LR].name = "lr";
886 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
887 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
888 info_ptr->regs[STACK_REGS_LR].special_p = 1;
889
890 info_ptr->regs[STACK_REGS_CC].name = "cc";
891 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
892 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
893 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
894
895 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
896 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
897 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
898
899 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
900 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
901 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
902 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
903 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
904
905 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
906 info_ptr->regs[STACK_REGS_STRUCT].first = STRUCT_VALUE_REGNUM;
907 info_ptr->regs[STACK_REGS_STRUCT].last = STRUCT_VALUE_REGNUM;
908 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
909
910 info_ptr->regs[STACK_REGS_FP].name = "fp";
911 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
912 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
913 info_ptr->regs[STACK_REGS_FP].special_p = 1;
914
915 /* Determine if this is a stdarg function. If so, allocate space to store
916 the 6 arguments. */
917 if (cfun->stdarg)
918 varargs_p = 1;
919
920 else
921 {
922 /* Find the last argument, and see if it is __builtin_va_alist. */
923 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
924 {
925 next_arg = TREE_CHAIN (cur_arg);
926 if (next_arg == (tree)0)
927 {
928 if (DECL_NAME (cur_arg)
929 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
930 varargs_p = 1;
931
932 break;
933 }
934 }
935 }
936
937 /* Iterate over all of the register ranges. */
938 for (range = 0; range < STACK_REGS_MAX; range++)
939 {
940 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
941 int first = reg_ptr->first;
942 int last = reg_ptr->last;
943 int size_1word = 0;
944 int size_2words = 0;
945 int regno;
946
947 /* Calculate which registers need to be saved & save area size. */
948 switch (range)
949 {
950 default:
951 for (regno = first; regno <= last; regno++)
952 {
953 if ((regs_ever_live[regno] && !call_used_regs[regno])
954 || (current_function_calls_eh_return
955 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
956 || (flag_pic && cfun->uses_pic_offset_table && regno == PIC_REGNO))
957 {
958 info_ptr->save_p[regno] = REG_SAVE_1WORD;
959 size_1word += UNITS_PER_WORD;
960 }
961 }
962 break;
963
964 /* Calculate whether we need to create a frame after everything else
965 has been processed. */
966 case STACK_REGS_FP:
967 break;
968
969 case STACK_REGS_LR:
970 if (regs_ever_live[LR_REGNO]
971 || profile_flag
972 || frame_pointer_needed
973 || (flag_pic && cfun->uses_pic_offset_table))
974 {
975 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
976 size_1word += UNITS_PER_WORD;
977 }
978 break;
979
980 case STACK_REGS_STDARG:
981 if (varargs_p)
982 {
983 /* If this is a stdarg function with a non varardic
984 argument split between registers and the stack,
985 adjust the saved registers downward. */
986 last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
987 / UNITS_PER_WORD);
988
989 for (regno = first; regno <= last; regno++)
990 {
991 info_ptr->save_p[regno] = REG_SAVE_1WORD;
992 size_1word += UNITS_PER_WORD;
993 }
994
995 info_ptr->stdarg_size = size_1word;
996 }
997 break;
998
999 case STACK_REGS_STRUCT:
1000 if (cfun->returns_struct)
1001 {
1002 info_ptr->save_p[STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1003 size_1word += UNITS_PER_WORD;
1004 }
1005 break;
1006 }
1007
1008
1009 if (size_1word)
1010 {
1011 /* If this is a field, it only takes one word. */
1012 if (reg_ptr->field_p)
1013 size_1word = UNITS_PER_WORD;
1014
1015 /* Determine which register pairs can be saved together. */
1016 else if (reg_ptr->dword_p && TARGET_DWORD)
1017 {
1018 for (regno = first; regno < last; regno += 2)
1019 {
1020 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1021 {
1022 size_2words += 2 * UNITS_PER_WORD;
1023 size_1word -= 2 * UNITS_PER_WORD;
1024 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1025 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1026 }
1027 }
1028 }
1029
1030 reg_ptr->size_1word = size_1word;
1031 reg_ptr->size_2words = size_2words;
1032
1033 if (! reg_ptr->special_p)
1034 {
1035 info_ptr->regs_size_1word += size_1word;
1036 info_ptr->regs_size_2words += size_2words;
1037 }
1038 }
1039 }
1040
1041 /* Set up the sizes of each each field in the frame body, making the sizes
1042 of each be divisible by the size of a dword if dword operations might
1043 be used, or the size of a word otherwise. */
1044 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1045
1046 info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment);
1047 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1048 + info_ptr->regs_size_1word,
1049 alignment);
1050 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1051
1052 info_ptr->pretend_size = cfun->pretend_args_size;
1053
1054 /* Work out the size of the frame, excluding the header. Both the frame
1055 body and register parameter area will be dword-aligned. */
1056 info_ptr->total_size
1057 = (ADDR_ALIGN (info_ptr->parameter_size
1058 + info_ptr->regs_size
1059 + info_ptr->vars_size,
1060 2 * UNITS_PER_WORD)
1061 + ADDR_ALIGN (info_ptr->pretend_size
1062 + info_ptr->stdarg_size,
1063 2 * UNITS_PER_WORD));
1064
1065 /* See if we need to create a frame at all, if so add header area. */
1066 if (info_ptr->total_size > 0
1067 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1068 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1069 {
1070 offset = info_ptr->parameter_size;
1071 info_ptr->header_size = 4 * UNITS_PER_WORD;
1072 info_ptr->total_size += 4 * UNITS_PER_WORD;
1073
1074 /* Calculate the offsets to save normal register pairs. */
1075 for (range = 0; range < STACK_REGS_MAX; range++)
1076 {
1077 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1078 if (! reg_ptr->special_p)
1079 {
1080 int first = reg_ptr->first;
1081 int last = reg_ptr->last;
1082 int regno;
1083
1084 for (regno = first; regno <= last; regno++)
1085 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1086 && regno != FRAME_POINTER_REGNUM
1087 && (regno < FIRST_ARG_REGNUM
1088 || regno > LAST_ARG_REGNUM))
1089 {
1090 info_ptr->reg_offset[regno] = offset;
1091 offset += 2 * UNITS_PER_WORD;
1092 }
1093 }
1094 }
1095
1096 /* Calculate the offsets to save normal single registers. */
1097 for (range = 0; range < STACK_REGS_MAX; range++)
1098 {
1099 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1100 if (! reg_ptr->special_p)
1101 {
1102 int first = reg_ptr->first;
1103 int last = reg_ptr->last;
1104 int regno;
1105
1106 for (regno = first; regno <= last; regno++)
1107 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1108 && regno != FRAME_POINTER_REGNUM
1109 && (regno < FIRST_ARG_REGNUM
1110 || regno > LAST_ARG_REGNUM))
1111 {
1112 info_ptr->reg_offset[regno] = offset;
1113 offset += UNITS_PER_WORD;
1114 }
1115 }
1116 }
1117
1118 /* Calculate the offset to save the local variables at. */
1119 offset = ADDR_ALIGN (offset, alignment);
1120 if (info_ptr->vars_size)
1121 {
1122 info_ptr->vars_offset = offset;
1123 offset += info_ptr->vars_size;
1124 }
1125
1126 /* Align header to a dword-boundary. */
1127 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1128
1129 /* Calculate the offsets in the fixed frame. */
1130 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1131 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1132 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1133
1134 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1135 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1136 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1137
1138 if (cfun->returns_struct)
1139 {
1140 info_ptr->save_p[STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1141 info_ptr->reg_offset[STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1142 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1143 }
1144
1145 /* Calculate the offsets to store the arguments passed in registers
1146 for stdarg functions. The register pairs are first and the single
1147 register if any is last. The register save area starts on a
1148 dword-boundary. */
1149 if (info_ptr->stdarg_size)
1150 {
1151 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1152 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1153 int regno;
1154
1155 /* Skip the header. */
1156 offset += 4 * UNITS_PER_WORD;
1157 for (regno = first; regno <= last; regno++)
1158 {
1159 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1160 {
1161 info_ptr->reg_offset[regno] = offset;
1162 offset += 2 * UNITS_PER_WORD;
1163 }
1164 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1165 {
1166 info_ptr->reg_offset[regno] = offset;
1167 offset += UNITS_PER_WORD;
1168 }
1169 }
1170 }
1171 }
1172
1173 if (reload_completed)
1174 frv_stack_cache = info_ptr;
1175
1176 return info_ptr;
1177 }
1178
1179
1180 /* Print the information about the frv stack offsets, etc. when debugging. */
1181
1182 void
frv_debug_stack(frv_stack_t * info)1183 frv_debug_stack (frv_stack_t *info)
1184 {
1185 int range;
1186
1187 if (!info)
1188 info = frv_stack_info ();
1189
1190 fprintf (stderr, "\nStack information for function %s:\n",
1191 ((current_function_decl && DECL_NAME (current_function_decl))
1192 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1193 : "<unknown>"));
1194
1195 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1196 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1197 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1198 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1199 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1200
1201 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1202 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1203 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1204 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1205
1206 for (range = 0; range < STACK_REGS_MAX; range++)
1207 {
1208 frv_stack_regs_t *regs = &(info->regs[range]);
1209 if ((regs->size_1word + regs->size_2words) > 0)
1210 {
1211 int first = regs->first;
1212 int last = regs->last;
1213 int regno;
1214
1215 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1216 regs->name, regs->size_1word + regs->size_2words,
1217 regs->size_1word, regs->size_2words);
1218
1219 for (regno = first; regno <= last; regno++)
1220 {
1221 if (info->save_p[regno] == REG_SAVE_1WORD)
1222 fprintf (stderr, " %s (%d)", reg_names[regno],
1223 info->reg_offset[regno]);
1224
1225 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1226 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1227 reg_names[regno+1], info->reg_offset[regno]);
1228 }
1229
1230 fputc ('\n', stderr);
1231 }
1232 }
1233
1234 fflush (stderr);
1235 }
1236
1237
1238
1239
1240 /* The following variable value is TRUE if the next output insn should
1241 finish cpu cycle. In order words the insn will have packing bit
1242 (which means absence of asm code suffix `.p' on assembler. */
1243
1244 static int frv_insn_packing_flag;
1245
1246 /* True if the current function contains a far jump. */
1247
1248 static int
frv_function_contains_far_jump(void)1249 frv_function_contains_far_jump (void)
1250 {
1251 rtx insn = get_insns ();
1252 while (insn != NULL
1253 && !(GET_CODE (insn) == JUMP_INSN
1254 /* Ignore tablejump patterns. */
1255 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1256 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1257 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1258 insn = NEXT_INSN (insn);
1259 return (insn != NULL);
1260 }
1261
1262 /* For the FRV, this function makes sure that a function with far jumps
1263 will return correctly. It also does the VLIW packing. */
1264
1265 static void
frv_function_prologue(FILE * file,HOST_WIDE_INT size ATTRIBUTE_UNUSED)1266 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1267 {
1268 /* If no frame was created, check whether the function uses a call
1269 instruction to implement a far jump. If so, save the link in gr3 and
1270 replace all returns to LR with returns to GR3. GR3 is used because it
1271 is call-clobbered, because is not available to the register allocator,
1272 and because all functions that take a hidden argument pointer will have
1273 a stack frame. */
1274 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1275 {
1276 rtx insn;
1277
1278 /* Just to check that the above comment is true. */
1279 if (regs_ever_live[GPR_FIRST + 3])
1280 abort ();
1281
1282 /* Generate the instruction that saves the link register. */
1283 fprintf (file, "\tmovsg lr,gr3\n");
1284
1285 /* Replace the LR with GR3 in *return_internal patterns. The insn
1286 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1287 simply emit a different assembly directive because bralr and jmpl
1288 execute in different units. */
1289 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1290 if (GET_CODE (insn) == JUMP_INSN)
1291 {
1292 rtx pattern = PATTERN (insn);
1293 if (GET_CODE (pattern) == PARALLEL
1294 && XVECLEN (pattern, 0) >= 2
1295 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1296 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1297 {
1298 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1299 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1300 REGNO (address) = GPR_FIRST + 3;
1301 }
1302 }
1303 }
1304
1305 frv_pack_insns ();
1306 frv_insn_packing_flag = TRUE;
1307 }
1308
1309
1310 /* Return the next available temporary register in a given class. */
1311
1312 static rtx
frv_alloc_temp_reg(frv_tmp_reg_t * info,enum reg_class class,enum machine_mode mode,int mark_as_used,int no_abort)1313 frv_alloc_temp_reg (
1314 frv_tmp_reg_t *info, /* which registers are available */
1315 enum reg_class class, /* register class desired */
1316 enum machine_mode mode, /* mode to allocate register with */
1317 int mark_as_used, /* register not available after allocation */
1318 int no_abort) /* return NULL instead of aborting */
1319 {
1320 int regno = info->next_reg[ (int)class ];
1321 int orig_regno = regno;
1322 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ];
1323 int i, nr;
1324
1325 for (;;)
1326 {
1327 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1328 && TEST_HARD_REG_BIT (info->regs, regno))
1329 break;
1330
1331 if (++regno >= FIRST_PSEUDO_REGISTER)
1332 regno = 0;
1333 if (regno == orig_regno)
1334 {
1335 if (no_abort)
1336 return NULL_RTX;
1337 else
1338 abort ();
1339 }
1340 }
1341
1342 nr = HARD_REGNO_NREGS (regno, mode);
1343 info->next_reg[ (int)class ] = regno + nr;
1344
1345 if (mark_as_used)
1346 for (i = 0; i < nr; i++)
1347 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1348
1349 return gen_rtx_REG (mode, regno);
1350 }
1351
1352
1353 /* Return an rtx with the value OFFSET, which will either be a register or a
1354 signed 12-bit integer. It can be used as the second operand in an "add"
1355 instruction, or as the index in a load or store.
1356
1357 The function returns a constant rtx if OFFSET is small enough, otherwise
1358 it loads the constant into register OFFSET_REGNO and returns that. */
1359 static rtx
frv_frame_offset_rtx(int offset)1360 frv_frame_offset_rtx (int offset)
1361 {
1362 rtx offset_rtx = GEN_INT (offset);
1363 if (IN_RANGE_P (offset, -2048, 2047))
1364 return offset_rtx;
1365 else
1366 {
1367 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1368 if (IN_RANGE_P (offset, -32768, 32767))
1369 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1370 else
1371 {
1372 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1373 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1374 }
1375 return reg_rtx;
1376 }
1377 }
1378
1379 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1380 prologue and epilogue uses such expressions to access the stack. */
1381 static rtx
frv_frame_mem(enum machine_mode mode,rtx base,int offset)1382 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1383 {
1384 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1385 base,
1386 frv_frame_offset_rtx (offset)));
1387 }
1388
1389 /* Generate a frame-related expression:
1390
1391 (set REG (mem (plus (sp) (const_int OFFSET)))).
1392
1393 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1394 instructions. Marking the expressions as frame-related is superfluous if
1395 the note contains just a single set. But if the note contains a PARALLEL
1396 or SEQUENCE that has several sets, each set must be individually marked
1397 as frame-related. */
1398 static rtx
frv_dwarf_store(rtx reg,int offset)1399 frv_dwarf_store (rtx reg, int offset)
1400 {
1401 rtx set = gen_rtx_SET (VOIDmode,
1402 gen_rtx_MEM (GET_MODE (reg),
1403 plus_constant (stack_pointer_rtx,
1404 offset)),
1405 reg);
1406 RTX_FRAME_RELATED_P (set) = 1;
1407 return set;
1408 }
1409
1410 /* Emit a frame-related instruction whose pattern is PATTERN. The
1411 instruction is the last in a sequence that cumulatively performs the
1412 operation described by DWARF_PATTERN. The instruction is marked as
1413 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1414 DWARF_PATTERN. */
1415 static void
frv_frame_insn(rtx pattern,rtx dwarf_pattern)1416 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1417 {
1418 rtx insn = emit_insn (pattern);
1419 RTX_FRAME_RELATED_P (insn) = 1;
1420 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1421 dwarf_pattern,
1422 REG_NOTES (insn));
1423 }
1424
1425 /* Emit instructions that transfer REG to or from the memory location (sp +
1426 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1427 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1428 function to store registers and only the epilogue uses it to load them.
1429
1430 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1431 The generated instruction will use BASE as its base register. BASE may
1432 simply be the stack pointer, but if several accesses are being made to a
1433 region far away from the stack pointer, it may be more efficient to set
1434 up a temporary instead.
1435
1436 Store instructions will be frame-related and will be annotated with the
1437 overall effect of the store. Load instructions will be followed by a
1438 (use) to prevent later optimizations from zapping them.
1439
1440 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1441 as a temporary in such cases. */
1442 static void
frv_frame_access(frv_frame_accessor_t * accessor,rtx reg,int stack_offset)1443 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1444 {
1445 enum machine_mode mode = GET_MODE (reg);
1446 rtx mem = frv_frame_mem (mode,
1447 accessor->base,
1448 stack_offset - accessor->base_offset);
1449
1450 if (accessor->op == FRV_LOAD)
1451 {
1452 if (SPR_P (REGNO (reg)))
1453 {
1454 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1455 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1456 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1457 }
1458 else
1459 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1460 emit_insn (gen_rtx_USE (VOIDmode, reg));
1461 }
1462 else
1463 {
1464 if (SPR_P (REGNO (reg)))
1465 {
1466 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1467 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1468 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1469 frv_dwarf_store (reg, stack_offset));
1470 }
1471 else if (GET_MODE (reg) == DImode)
1472 {
1473 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1474 with a separate save for each register. */
1475 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1476 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1477 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1478 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1479 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1480 gen_rtx_PARALLEL (VOIDmode,
1481 gen_rtvec (2, set1, set2)));
1482 }
1483 else
1484 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1485 frv_dwarf_store (reg, stack_offset));
1486 }
1487 }
1488
1489 /* A function that uses frv_frame_access to transfer a group of registers to
1490 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1491 is the stack information generated by frv_stack_info, and REG_SET is the
1492 number of the register set to transfer. */
1493 static void
frv_frame_access_multi(frv_frame_accessor_t * accessor,frv_stack_t * info,int reg_set)1494 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1495 frv_stack_t *info,
1496 int reg_set)
1497 {
1498 frv_stack_regs_t *regs_info;
1499 int regno;
1500
1501 regs_info = &info->regs[reg_set];
1502 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1503 if (info->save_p[regno])
1504 frv_frame_access (accessor,
1505 info->save_p[regno] == REG_SAVE_2WORDS
1506 ? gen_rtx_REG (DImode, regno)
1507 : gen_rtx_REG (SImode, regno),
1508 info->reg_offset[regno]);
1509 }
1510
1511 /* Save or restore callee-saved registers that are kept outside the frame
1512 header. The function saves the registers if OP is FRV_STORE and restores
1513 them if OP is FRV_LOAD. INFO is the stack information generated by
1514 frv_stack_info. */
1515 static void
frv_frame_access_standard_regs(enum frv_stack_op op,frv_stack_t * info)1516 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1517 {
1518 frv_frame_accessor_t accessor;
1519
1520 accessor.op = op;
1521 accessor.base = stack_pointer_rtx;
1522 accessor.base_offset = 0;
1523 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1524 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1525 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1526 }
1527
1528
1529 /* Called after register allocation to add any instructions needed for the
1530 prologue. Using a prologue insn is favored compared to putting all of the
1531 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1532 to intermix instructions with the saves of the caller saved registers. In
1533 some cases, it might be necessary to emit a barrier instruction as the last
1534 insn to prevent such scheduling.
1535
1536 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1537 so that the debug info generation code can handle them properly. */
1538 void
frv_expand_prologue(void)1539 frv_expand_prologue (void)
1540 {
1541 frv_stack_t *info = frv_stack_info ();
1542 rtx sp = stack_pointer_rtx;
1543 rtx fp = frame_pointer_rtx;
1544 frv_frame_accessor_t accessor;
1545
1546 if (TARGET_DEBUG_STACK)
1547 frv_debug_stack (info);
1548
1549 if (info->total_size == 0)
1550 return;
1551
1552 /* We're interested in three areas of the frame here:
1553
1554 A: the register save area
1555 B: the old FP
1556 C: the header after B
1557
1558 If the frame pointer isn't used, we'll have to set up A, B and C
1559 using the stack pointer. If the frame pointer is used, we'll access
1560 them as follows:
1561
1562 A: set up using sp
1563 B: set up using sp or a temporary (see below)
1564 C: set up using fp
1565
1566 We set up B using the stack pointer if the frame is small enough.
1567 Otherwise, it's more efficient to copy the old stack pointer into a
1568 temporary and use that.
1569
1570 Note that it's important to make sure the prologue and epilogue use the
1571 same registers to access A and C, since doing otherwise will confuse
1572 the aliasing code. */
1573
1574 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1575 isn't used, the same method will serve for C. */
1576 accessor.op = FRV_STORE;
1577 if (frame_pointer_needed && info->total_size > 2048)
1578 {
1579 rtx insn;
1580
1581 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1582 accessor.base_offset = info->total_size;
1583 insn = emit_insn (gen_movsi (accessor.base, sp));
1584 }
1585 else
1586 {
1587 accessor.base = stack_pointer_rtx;
1588 accessor.base_offset = 0;
1589 }
1590
1591 /* Allocate the stack space. */
1592 {
1593 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1594 rtx dwarf_offset = GEN_INT (-info->total_size);
1595
1596 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1597 gen_rtx_SET (Pmode,
1598 sp,
1599 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1600 }
1601
1602 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1603 and point the new one to that location. */
1604 if (frame_pointer_needed)
1605 {
1606 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1607
1608 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1609 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1610 pointer. */
1611 rtx asm_src = plus_constant (accessor.base,
1612 fp_offset - accessor.base_offset);
1613 rtx dwarf_src = plus_constant (sp, fp_offset);
1614
1615 /* Store the old frame pointer at (sp + FP_OFFSET). */
1616 frv_frame_access (&accessor, fp, fp_offset);
1617
1618 /* Set up the new frame pointer. */
1619 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1620 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1621
1622 /* Access region C from the frame pointer. */
1623 accessor.base = fp;
1624 accessor.base_offset = fp_offset;
1625 }
1626
1627 /* Set up region C. */
1628 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1629 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1630 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1631
1632 /* Set up region A. */
1633 frv_frame_access_standard_regs (FRV_STORE, info);
1634
1635 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1636 scheduler from moving loads before the stores saving the registers. */
1637 if (info->stdarg_size > 0)
1638 emit_insn (gen_blockage ());
1639
1640 /* Set up pic register/small data register for this function. */
1641 if (flag_pic && cfun->uses_pic_offset_table)
1642 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1643 gen_rtx_REG (Pmode, LR_REGNO),
1644 gen_rtx_REG (SImode, OFFSET_REGNO)));
1645 }
1646
1647
1648 /* Under frv, all of the work is done via frv_expand_epilogue, but
1649 this function provides a convenient place to do cleanup. */
1650
1651 static void
frv_function_epilogue(FILE * file ATTRIBUTE_UNUSED,HOST_WIDE_INT size ATTRIBUTE_UNUSED)1652 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1653 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1654 {
1655 frv_stack_cache = (frv_stack_t *)0;
1656
1657 /* Zap last used registers for conditional execution. */
1658 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1659
1660 /* Release the bitmap of created insns. */
1661 BITMAP_XFREE (frv_ifcvt.scratch_insns_bitmap);
1662 }
1663
1664
1665 /* Called after register allocation to add any instructions needed for the
1666 epilogue. Using an epilogue insn is favored compared to putting all of the
1667 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1668 to intermix instructions with the saves of the caller saved registers. In
1669 some cases, it might be necessary to emit a barrier instruction as the last
1670 insn to prevent such scheduling.
1671
1672 If SIBCALL_P is true, the final branch back to the calling function is
1673 omitted, and is used for sibling call (aka tail call) sites. For sibcalls,
1674 we must not clobber any arguments used for parameter passing or any stack
1675 slots for arguments passed to the current function. */
1676
1677 void
frv_expand_epilogue(int sibcall_p)1678 frv_expand_epilogue (int sibcall_p)
1679 {
1680 frv_stack_t *info = frv_stack_info ();
1681 rtx fp = frame_pointer_rtx;
1682 rtx sp = stack_pointer_rtx;
1683 rtx return_addr;
1684 int fp_offset;
1685
1686 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1687
1688 /* Restore the stack pointer to its original value if alloca or the like
1689 is used. */
1690 if (! current_function_sp_is_unchanging)
1691 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1692
1693 /* Restore the callee-saved registers that were used in this function. */
1694 frv_frame_access_standard_regs (FRV_LOAD, info);
1695
1696 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1697 no return instruction should be emitted. */
1698 if (sibcall_p)
1699 return_addr = 0;
1700 else if (info->save_p[LR_REGNO])
1701 {
1702 int lr_offset;
1703 rtx mem;
1704
1705 /* Use the same method to access the link register's slot as we did in
1706 the prologue. In other words, use the frame pointer if available,
1707 otherwise use the stack pointer.
1708
1709 LR_OFFSET is the offset of the link register's slot from the start
1710 of the frame and MEM is a memory rtx for it. */
1711 lr_offset = info->reg_offset[LR_REGNO];
1712 if (frame_pointer_needed)
1713 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1714 else
1715 mem = frv_frame_mem (Pmode, sp, lr_offset);
1716
1717 /* Load the old link register into a GPR. */
1718 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1719 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1720 }
1721 else
1722 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1723
1724 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1725 the load is preserved. */
1726 if (frame_pointer_needed)
1727 {
1728 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1729 emit_insn (gen_rtx_USE (VOIDmode, fp));
1730 }
1731
1732 /* Deallocate the stack frame. */
1733 if (info->total_size != 0)
1734 {
1735 rtx offset = frv_frame_offset_rtx (info->total_size);
1736 emit_insn (gen_stack_adjust (sp, sp, offset));
1737 }
1738
1739 /* If this function uses eh_return, add the final stack adjustment now. */
1740 if (current_function_calls_eh_return)
1741 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1742
1743 if (return_addr)
1744 emit_jump_insn (gen_epilogue_return (return_addr));
1745 }
1746
1747
1748 /* A C compound statement that outputs the assembler code for a thunk function,
1749 used to implement C++ virtual function calls with multiple inheritance. The
1750 thunk acts as a wrapper around a virtual function, adjusting the implicit
1751 object parameter before handing control off to the real function.
1752
1753 First, emit code to add the integer DELTA to the location that contains the
1754 incoming first argument. Assume that this argument contains a pointer, and
1755 is the one used to pass the `this' pointer in C++. This is the incoming
1756 argument *before* the function prologue, e.g. `%o0' on a sparc. The
1757 addition must preserve the values of all other incoming arguments.
1758
1759 After the addition, emit code to jump to FUNCTION, which is a
1760 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch
1761 the return address. Hence returning from FUNCTION will return to whoever
1762 called the current `thunk'.
1763
1764 The effect must be as if FUNCTION had been called directly with the adjusted
1765 first argument. This macro is responsible for emitting all of the code for
1766 a thunk function; `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' are not
1767 invoked.
1768
1769 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been
1770 extracted from it.) It might possibly be useful on some targets, but
1771 probably not.
1772
1773 If you do not define this macro, the target-independent code in the C++
1774 frontend will generate a less efficient heavyweight thunk that calls
1775 FUNCTION instead of jumping to it. The generic approach does not support
1776 varargs. */
1777
1778 static void
frv_asm_output_mi_thunk(FILE * file,tree thunk_fndecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,tree function)1779 frv_asm_output_mi_thunk (FILE *file,
1780 tree thunk_fndecl ATTRIBUTE_UNUSED,
1781 HOST_WIDE_INT delta,
1782 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1783 tree function)
1784 {
1785 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1786 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1787 const char *name_jmp = reg_names[JUMP_REGNO];
1788 const char *parallel = ((PACKING_FLAG_USED_P ()) ? ".p" : "");
1789
1790 /* Do the add using an addi if possible. */
1791 if (IN_RANGE_P (delta, -2048, 2047))
1792 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1793 else
1794 {
1795 const char *const name_add = reg_names[TEMP_REGNO];
1796 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1797 parallel, delta, name_add);
1798 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1799 delta, name_add);
1800 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1801 }
1802
1803 if (!flag_pic)
1804 {
1805 fprintf (file, "\tsethi%s #hi(", parallel);
1806 assemble_name (file, name_func);
1807 fprintf (file, "),%s\n", name_jmp);
1808
1809 fprintf (file, "\tsetlo #lo(");
1810 assemble_name (file, name_func);
1811 fprintf (file, "),%s\n", name_jmp);
1812 }
1813 else
1814 {
1815 /* Use JUMP_REGNO as a temporary PIC register. */
1816 const char *name_lr = reg_names[LR_REGNO];
1817 const char *name_gppic = name_jmp;
1818 const char *name_tmp = reg_names[TEMP_REGNO];
1819
1820 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
1821 fprintf (file, "\tcall 1f\n");
1822 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
1823 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
1824 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
1825 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
1826 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
1827
1828 fprintf (file, "\tsethi%s #gprelhi(", parallel);
1829 assemble_name (file, name_func);
1830 fprintf (file, "),%s\n", name_tmp);
1831
1832 fprintf (file, "\tsetlo #gprello(");
1833 assemble_name (file, name_func);
1834 fprintf (file, "),%s\n", name_tmp);
1835
1836 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
1837 }
1838
1839 /* Jump to the function address. */
1840 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
1841 }
1842
1843
1844 /* A C expression which is nonzero if a function must have and use a frame
1845 pointer. This expression is evaluated in the reload pass. If its value is
1846 nonzero the function will have a frame pointer.
1847
1848 The expression can in principle examine the current function and decide
1849 according to the facts, but on most machines the constant 0 or the constant
1850 1 suffices. Use 0 when the machine allows code to be generated with no
1851 frame pointer, and doing so saves some time or space. Use 1 when there is
1852 no possible advantage to avoiding a frame pointer.
1853
1854 In certain cases, the compiler does not know how to produce valid code
1855 without a frame pointer. The compiler recognizes those cases and
1856 automatically gives the function a frame pointer regardless of what
1857 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
1858
1859 In a function that does not require a frame pointer, the frame pointer
1860 register can be allocated for ordinary usage, unless you mark it as a fixed
1861 register. See `FIXED_REGISTERS' for more information. */
1862
1863 /* On frv, create a frame whenever we need to create stack. */
1864
1865 int
frv_frame_pointer_required(void)1866 frv_frame_pointer_required (void)
1867 {
1868 if (! current_function_is_leaf)
1869 return TRUE;
1870
1871 if (get_frame_size () != 0)
1872 return TRUE;
1873
1874 if (cfun->stdarg)
1875 return TRUE;
1876
1877 if (!current_function_sp_is_unchanging)
1878 return TRUE;
1879
1880 if (flag_pic && cfun->uses_pic_offset_table)
1881 return TRUE;
1882
1883 if (profile_flag)
1884 return TRUE;
1885
1886 if (cfun->machine->frame_needed)
1887 return TRUE;
1888
1889 return FALSE;
1890 }
1891
1892
1893 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
1894 initial difference between the specified pair of registers. This macro must
1895 be defined if `ELIMINABLE_REGS' is defined. */
1896
1897 /* See frv_stack_info for more details on the frv stack frame. */
1898
1899 int
frv_initial_elimination_offset(int from,int to)1900 frv_initial_elimination_offset (int from, int to)
1901 {
1902 frv_stack_t *info = frv_stack_info ();
1903 int ret = 0;
1904
1905 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
1906 ret = info->total_size - info->pretend_size;
1907
1908 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
1909 ret = info->reg_offset[FRAME_POINTER_REGNUM];
1910
1911 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
1912 ret = (info->total_size
1913 - info->reg_offset[FRAME_POINTER_REGNUM]
1914 - info->pretend_size);
1915
1916 else
1917 abort ();
1918
1919 if (TARGET_DEBUG_STACK)
1920 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
1921 reg_names [from], reg_names[to], ret);
1922
1923 return ret;
1924 }
1925
1926
1927 /* This macro offers an alternative to using `__builtin_saveregs' and defining
1928 the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
1929 arguments into the stack so that all the arguments appear to have been
1930 passed consecutively on the stack. Once this is done, you can use the
1931 standard implementation of varargs that works for machines that pass all
1932 their arguments on the stack.
1933
1934 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
1935 the values that obtain after processing of the named arguments. The
1936 arguments MODE and TYPE describe the last named argument--its machine mode
1937 and its data type as a tree node.
1938
1939 The macro implementation should do two things: first, push onto the stack
1940 all the argument registers *not* used for the named arguments, and second,
1941 store the size of the data thus pushed into the `int'-valued variable whose
1942 name is supplied as the argument PRETEND_ARGS_SIZE. The value that you
1943 store here will serve as additional offset for setting up the stack frame.
1944
1945 Because you must generate code to push the anonymous arguments at compile
1946 time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
1947 useful on machines that have just a single category of argument register and
1948 use it uniformly for all data types.
1949
1950 If the argument SECOND_TIME is nonzero, it means that the arguments of the
1951 function are being analyzed for the second time. This happens for an inline
1952 function, which is not actually compiled until the end of the source file.
1953 The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
1954 this case. */
1955
1956 void
frv_setup_incoming_varargs(CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type ATTRIBUTE_UNUSED,int * pretend_size,int second_time)1957 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
1958 enum machine_mode mode,
1959 tree type ATTRIBUTE_UNUSED,
1960 int *pretend_size,
1961 int second_time)
1962 {
1963 if (TARGET_DEBUG_ARG)
1964 fprintf (stderr,
1965 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
1966 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
1967 }
1968
1969
1970 /* If defined, is a C expression that produces the machine-specific code for a
1971 call to `__builtin_saveregs'. This code will be moved to the very beginning
1972 of the function, before any parameter access are made. The return value of
1973 this function should be an RTX that contains the value to use as the return
1974 of `__builtin_saveregs'.
1975
1976 If this macro is not defined, the compiler will output an ordinary call to
1977 the library function `__builtin_saveregs'. */
1978
1979 rtx
frv_expand_builtin_saveregs(void)1980 frv_expand_builtin_saveregs (void)
1981 {
1982 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
1983
1984 if (TARGET_DEBUG_ARG)
1985 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
1986 offset);
1987
1988 return gen_rtx (PLUS, Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
1989 }
1990
1991
1992 /* Expand __builtin_va_start to do the va_start macro. */
1993
1994 void
frv_expand_builtin_va_start(tree valist,rtx nextarg)1995 frv_expand_builtin_va_start (tree valist, rtx nextarg)
1996 {
1997 tree t;
1998 int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
1999
2000 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2001 GEN_INT (UNITS_PER_WORD * num));
2002
2003 if (TARGET_DEBUG_ARG)
2004 {
2005 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2006 cfun->args_info, num);
2007
2008 debug_rtx (nextarg);
2009 }
2010
2011 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2012 make_tree (ptr_type_node, nextarg));
2013 TREE_SIDE_EFFECTS (t) = 1;
2014
2015 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2016 }
2017
2018
2019 /* Expand __builtin_va_arg to do the va_arg macro. */
2020
2021 rtx
frv_expand_builtin_va_arg(tree valist,tree type)2022 frv_expand_builtin_va_arg (tree valist, tree type)
2023 {
2024 rtx addr;
2025 rtx mem;
2026 rtx reg;
2027
2028 if (TARGET_DEBUG_ARG)
2029 {
2030 fprintf (stderr, "va_arg:\n");
2031 debug_tree (type);
2032 }
2033
2034 if (! AGGREGATE_TYPE_P (type))
2035 return std_expand_builtin_va_arg (valist, type);
2036
2037 addr = std_expand_builtin_va_arg (valist, ptr_type_node);
2038 mem = gen_rtx_MEM (Pmode, addr);
2039 reg = gen_reg_rtx (Pmode);
2040
2041 set_mem_alias_set (mem, get_varargs_alias_set ());
2042 emit_move_insn (reg, mem);
2043
2044 return reg;
2045 }
2046
2047
2048 /* Expand a block move operation, and return 1 if successful. Return 0
2049 if we should let the compiler generate normal code.
2050
2051 operands[0] is the destination
2052 operands[1] is the source
2053 operands[2] is the length
2054 operands[3] is the alignment */
2055
2056 /* Maximum number of loads to do before doing the stores */
2057 #ifndef MAX_MOVE_REG
2058 #define MAX_MOVE_REG 4
2059 #endif
2060
2061 /* Maximum number of total loads to do. */
2062 #ifndef TOTAL_MOVE_REG
2063 #define TOTAL_MOVE_REG 8
2064 #endif
2065
2066 int
frv_expand_block_move(rtx operands[])2067 frv_expand_block_move (rtx operands[])
2068 {
2069 rtx orig_dest = operands[0];
2070 rtx orig_src = operands[1];
2071 rtx bytes_rtx = operands[2];
2072 rtx align_rtx = operands[3];
2073 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2074 int align;
2075 int bytes;
2076 int offset;
2077 int num_reg;
2078 int i;
2079 rtx src_reg;
2080 rtx dest_reg;
2081 rtx src_addr;
2082 rtx dest_addr;
2083 rtx src_mem;
2084 rtx dest_mem;
2085 rtx tmp_reg;
2086 rtx stores[MAX_MOVE_REG];
2087 int move_bytes;
2088 enum machine_mode mode;
2089
2090 /* If this is not a fixed size move, just call memcpy. */
2091 if (! constp)
2092 return FALSE;
2093
2094 /* If this is not a fixed size alignment, abort. */
2095 if (GET_CODE (align_rtx) != CONST_INT)
2096 abort ();
2097
2098 align = INTVAL (align_rtx);
2099
2100 /* Anything to move? */
2101 bytes = INTVAL (bytes_rtx);
2102 if (bytes <= 0)
2103 return TRUE;
2104
2105 /* Don't support real large moves. */
2106 if (bytes > TOTAL_MOVE_REG*align)
2107 return FALSE;
2108
2109 /* Move the address into scratch registers. */
2110 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2111 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2112
2113 num_reg = offset = 0;
2114 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2115 {
2116 /* Calculate the correct offset for src/dest. */
2117 if (offset == 0)
2118 {
2119 src_addr = src_reg;
2120 dest_addr = dest_reg;
2121 }
2122 else
2123 {
2124 src_addr = plus_constant (src_reg, offset);
2125 dest_addr = plus_constant (dest_reg, offset);
2126 }
2127
2128 /* Generate the appropriate load and store, saving the stores
2129 for later. */
2130 if (bytes >= 4 && align >= 4)
2131 mode = SImode;
2132 else if (bytes >= 2 && align >= 2)
2133 mode = HImode;
2134 else
2135 mode = QImode;
2136
2137 move_bytes = GET_MODE_SIZE (mode);
2138 tmp_reg = gen_reg_rtx (mode);
2139 src_mem = change_address (orig_src, mode, src_addr);
2140 dest_mem = change_address (orig_dest, mode, dest_addr);
2141 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2142 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2143
2144 if (num_reg >= MAX_MOVE_REG)
2145 {
2146 for (i = 0; i < num_reg; i++)
2147 emit_insn (stores[i]);
2148 num_reg = 0;
2149 }
2150 }
2151
2152 for (i = 0; i < num_reg; i++)
2153 emit_insn (stores[i]);
2154
2155 return TRUE;
2156 }
2157
2158
2159 /* Expand a block clear operation, and return 1 if successful. Return 0
2160 if we should let the compiler generate normal code.
2161
2162 operands[0] is the destination
2163 operands[1] is the length
2164 operands[2] is the alignment */
2165
2166 int
frv_expand_block_clear(rtx operands[])2167 frv_expand_block_clear (rtx operands[])
2168 {
2169 rtx orig_dest = operands[0];
2170 rtx bytes_rtx = operands[1];
2171 rtx align_rtx = operands[2];
2172 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2173 int align;
2174 int bytes;
2175 int offset;
2176 int num_reg;
2177 rtx dest_reg;
2178 rtx dest_addr;
2179 rtx dest_mem;
2180 int clear_bytes;
2181 enum machine_mode mode;
2182
2183 /* If this is not a fixed size move, just call memcpy. */
2184 if (! constp)
2185 return FALSE;
2186
2187 /* If this is not a fixed size alignment, abort. */
2188 if (GET_CODE (align_rtx) != CONST_INT)
2189 abort ();
2190
2191 align = INTVAL (align_rtx);
2192
2193 /* Anything to move? */
2194 bytes = INTVAL (bytes_rtx);
2195 if (bytes <= 0)
2196 return TRUE;
2197
2198 /* Don't support real large clears. */
2199 if (bytes > TOTAL_MOVE_REG*align)
2200 return FALSE;
2201
2202 /* Move the address into a scratch register. */
2203 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2204
2205 num_reg = offset = 0;
2206 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2207 {
2208 /* Calculate the correct offset for src/dest. */
2209 dest_addr = ((offset == 0)
2210 ? dest_reg
2211 : plus_constant (dest_reg, offset));
2212
2213 /* Generate the appropriate store of gr0. */
2214 if (bytes >= 4 && align >= 4)
2215 mode = SImode;
2216 else if (bytes >= 2 && align >= 2)
2217 mode = HImode;
2218 else
2219 mode = QImode;
2220
2221 clear_bytes = GET_MODE_SIZE (mode);
2222 dest_mem = change_address (orig_dest, mode, dest_addr);
2223 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2224 }
2225
2226 return TRUE;
2227 }
2228
2229
2230 /* The following variable is used to output modifiers of assembler
2231 code of the current output insn. */
2232
2233 static rtx *frv_insn_operands;
2234
2235 /* The following function is used to add assembler insn code suffix .p
2236 if it is necessary. */
2237
2238 const char *
frv_asm_output_opcode(FILE * f,const char * ptr)2239 frv_asm_output_opcode (FILE *f, const char *ptr)
2240 {
2241 int c;
2242
2243 if (! PACKING_FLAG_USED_P())
2244 return ptr;
2245
2246 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2247 {
2248 c = *ptr++;
2249 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2250 || (*ptr >= 'A' && *ptr <= 'Z')))
2251 {
2252 int letter = *ptr++;
2253
2254 c = atoi (ptr);
2255 frv_print_operand (f, frv_insn_operands [c], letter);
2256 while ((c = *ptr) >= '0' && c <= '9')
2257 ptr++;
2258 }
2259 else
2260 fputc (c, f);
2261 }
2262
2263 if (!frv_insn_packing_flag)
2264 fprintf (f, ".p");
2265
2266 return ptr;
2267 }
2268
2269 /* The following function sets up the packing bit for the current
2270 output insn. Remember that the function is not called for asm
2271 insns. */
2272
2273 void
frv_final_prescan_insn(rtx insn,rtx * opvec,int noperands ATTRIBUTE_UNUSED)2274 frv_final_prescan_insn (rtx insn, rtx *opvec, int noperands ATTRIBUTE_UNUSED)
2275 {
2276 if (! PACKING_FLAG_USED_P())
2277 return;
2278
2279 if (!INSN_P (insn))
2280 return;
2281
2282 frv_insn_operands = opvec;
2283
2284 /* Look for the next printable instruction. frv_pack_insns () has set
2285 things up so that any printable instruction will have TImode if it
2286 starts a new packet and VOIDmode if it should be packed with the
2287 previous instruction.
2288
2289 Printable instructions will be asm_operands or match one of the .md
2290 patterns. Since asm instructions cannot be packed -- and will
2291 therefore have TImode -- this loop terminates on any recognizable
2292 instruction, and on any unrecognizable instruction with TImode. */
2293 for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn))
2294 {
2295 if (NOTE_P (insn))
2296 continue;
2297 else if (!INSN_P (insn))
2298 break;
2299 else if (GET_MODE (insn) == TImode || INSN_CODE (insn) != -1)
2300 break;
2301 }
2302
2303 /* Set frv_insn_packing_flag to FALSE if the next instruction should
2304 be packed with this one. Set it to TRUE otherwise. If the next
2305 instruction is an asm instruction, this statement will set the
2306 flag to TRUE, and that value will still hold when the asm operands
2307 themselves are printed. */
2308 frv_insn_packing_flag = ! (insn && INSN_P (insn)
2309 && GET_MODE (insn) != TImode);
2310 }
2311
2312
2313
2314 /* A C expression whose value is RTL representing the address in a stack frame
2315 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2316 an RTL expression for the address of the stack frame itself.
2317
2318 If you don't define this macro, the default is to return the value of
2319 FRAMEADDR--that is, the stack frame address is also the address of the stack
2320 word that points to the previous frame. */
2321
2322 /* The default is correct, but we need to make sure the frame gets created. */
2323 rtx
frv_dynamic_chain_address(rtx frame)2324 frv_dynamic_chain_address (rtx frame)
2325 {
2326 cfun->machine->frame_needed = 1;
2327 return frame;
2328 }
2329
2330
2331 /* A C expression whose value is RTL representing the value of the return
2332 address for the frame COUNT steps up from the current frame, after the
2333 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2334 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2335 defined.
2336
2337 The value of the expression must always be the correct address when COUNT is
2338 zero, but may be `NULL_RTX' if there is not way to determine the return
2339 address of other frames. */
2340
2341 rtx
frv_return_addr_rtx(int count ATTRIBUTE_UNUSED,rtx frame)2342 frv_return_addr_rtx (int count ATTRIBUTE_UNUSED, rtx frame)
2343 {
2344 cfun->machine->frame_needed = 1;
2345 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2346 }
2347
2348 /* Given a memory reference MEMREF, interpret the referenced memory as
2349 an array of MODE values, and return a reference to the element
2350 specified by INDEX. Assume that any pre-modification implicit in
2351 MEMREF has already happened.
2352
2353 MEMREF must be a legitimate operand for modes larger than SImode.
2354 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2355 this function cannot handle. */
2356 rtx
frv_index_memory(rtx memref,enum machine_mode mode,int index)2357 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2358 {
2359 rtx base = XEXP (memref, 0);
2360 if (GET_CODE (base) == PRE_MODIFY)
2361 base = XEXP (base, 0);
2362 return change_address (memref, mode,
2363 plus_constant (base, index * GET_MODE_SIZE (mode)));
2364 }
2365
2366
2367 /* Print a memory address as an operand to reference that memory location. */
2368 void
frv_print_operand_address(FILE * stream,rtx x)2369 frv_print_operand_address (FILE * stream, rtx x)
2370 {
2371 if (GET_CODE (x) == MEM)
2372 x = XEXP (x, 0);
2373
2374 switch (GET_CODE (x))
2375 {
2376 case REG:
2377 fputs (reg_names [ REGNO (x)], stream);
2378 return;
2379
2380 case CONST_INT:
2381 fprintf (stream, "%ld", (long) INTVAL (x));
2382 return;
2383
2384 case SYMBOL_REF:
2385 assemble_name (stream, XSTR (x, 0));
2386 return;
2387
2388 case LABEL_REF:
2389 case CONST:
2390 output_addr_const (stream, x);
2391 return;
2392
2393 default:
2394 break;
2395 }
2396
2397 fatal_insn ("Bad insn to frv_print_operand_address:", x);
2398 }
2399
2400
2401 static void
frv_print_operand_memory_reference_reg(FILE * stream,rtx x)2402 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2403 {
2404 int regno = true_regnum (x);
2405 if (GPR_P (regno))
2406 fputs (reg_names[regno], stream);
2407 else
2408 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x);
2409 }
2410
2411 /* Print a memory reference suitable for the ld/st instructions. */
2412
2413 static void
frv_print_operand_memory_reference(FILE * stream,rtx x,int addr_offset)2414 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2415 {
2416 rtx x0 = NULL_RTX;
2417 rtx x1 = NULL_RTX;
2418
2419 switch (GET_CODE (x))
2420 {
2421 case SUBREG:
2422 case REG:
2423 x0 = x;
2424 break;
2425
2426 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2427 x0 = XEXP (x, 0);
2428 x1 = XEXP (XEXP (x, 1), 1);
2429 break;
2430
2431 case CONST_INT:
2432 x1 = x;
2433 break;
2434
2435 case PLUS:
2436 x0 = XEXP (x, 0);
2437 x1 = XEXP (x, 1);
2438 if (GET_CODE (x0) == CONST_INT)
2439 {
2440 x0 = XEXP (x, 1);
2441 x1 = XEXP (x, 0);
2442 }
2443 break;
2444
2445 default:
2446 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2447 break;
2448
2449 }
2450
2451 if (addr_offset)
2452 {
2453 if (!x1)
2454 x1 = const0_rtx;
2455 else if (GET_CODE (x1) != CONST_INT)
2456 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2457 }
2458
2459 fputs ("@(", stream);
2460 if (!x0)
2461 fputs (reg_names[GPR_R0], stream);
2462 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2463 frv_print_operand_memory_reference_reg (stream, x0);
2464 else
2465 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2466
2467 fputs (",", stream);
2468 if (!x1)
2469 fputs (reg_names [GPR_R0], stream);
2470
2471 else
2472 {
2473 switch (GET_CODE (x1))
2474 {
2475 case SUBREG:
2476 case REG:
2477 frv_print_operand_memory_reference_reg (stream, x1);
2478 break;
2479
2480 case CONST_INT:
2481 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2482 break;
2483
2484 case SYMBOL_REF:
2485 if (x0 && GET_CODE (x0) == REG && REGNO (x0) == SDA_BASE_REG
2486 && SYMBOL_REF_SMALL_P (x1))
2487 {
2488 fputs ("#gprel12(", stream);
2489 assemble_name (stream, XSTR (x1, 0));
2490 fputs (")", stream);
2491 }
2492 else
2493 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2494 break;
2495
2496 case CONST:
2497 if (x0 && GET_CODE (x0) == REG && REGNO (x0) == SDA_BASE_REG
2498 && const_small_data_p (x1))
2499 {
2500 fputs ("#gprel12(", stream);
2501 assemble_name (stream, XSTR (XEXP (XEXP (x1, 0), 0), 0));
2502 fprintf (stream, "+"HOST_WIDE_INT_PRINT_DEC")",
2503 INTVAL (XEXP (XEXP (x1, 0), 1)));
2504 }
2505 else
2506 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2507 break;
2508
2509 default:
2510 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2511 }
2512 }
2513
2514 fputs (")", stream);
2515 }
2516
2517
2518 /* Return 2 for likely branches and 0 for non-likely branches */
2519
2520 #define FRV_JUMP_LIKELY 2
2521 #define FRV_JUMP_NOT_LIKELY 0
2522
2523 static int
frv_print_operand_jump_hint(rtx insn)2524 frv_print_operand_jump_hint (rtx insn)
2525 {
2526 rtx note;
2527 rtx labelref;
2528 int ret;
2529 HOST_WIDE_INT prob = -1;
2530 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2531
2532 if (GET_CODE (insn) != JUMP_INSN)
2533 abort ();
2534
2535 /* Assume any non-conditional jump is likely. */
2536 if (! any_condjump_p (insn))
2537 ret = FRV_JUMP_LIKELY;
2538
2539 else
2540 {
2541 labelref = condjump_label (insn);
2542 if (labelref)
2543 {
2544 rtx label = XEXP (labelref, 0);
2545 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2546 ? BACKWARD
2547 : FORWARD);
2548 }
2549
2550 note = find_reg_note (insn, REG_BR_PROB, 0);
2551 if (!note)
2552 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2553
2554 else
2555 {
2556 prob = INTVAL (XEXP (note, 0));
2557 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2558 ? FRV_JUMP_LIKELY
2559 : FRV_JUMP_NOT_LIKELY);
2560 }
2561 }
2562
2563 #if 0
2564 if (TARGET_DEBUG)
2565 {
2566 char *direction;
2567
2568 switch (jump_type)
2569 {
2570 default:
2571 case UNKNOWN: direction = "unknown jump direction"; break;
2572 case BACKWARD: direction = "jump backward"; break;
2573 case FORWARD: direction = "jump forward"; break;
2574 }
2575
2576 fprintf (stderr,
2577 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2578 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2579 (long)INSN_UID (insn), direction, (long)prob,
2580 (long)REG_BR_PROB_BASE, ret);
2581 }
2582 #endif
2583
2584 return ret;
2585 }
2586
2587
2588 /* Print an operand to an assembler instruction.
2589
2590 `%' followed by a letter and a digit says to output an operand in an
2591 alternate fashion. Four letters have standard, built-in meanings described
2592 below. The machine description macro `PRINT_OPERAND' can define additional
2593 letters with nonstandard meanings.
2594
2595 `%cDIGIT' can be used to substitute an operand that is a constant value
2596 without the syntax that normally indicates an immediate operand.
2597
2598 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2599 before printing.
2600
2601 `%aDIGIT' can be used to substitute an operand as if it were a memory
2602 reference, with the actual operand treated as the address. This may be
2603 useful when outputting a "load address" instruction, because often the
2604 assembler syntax for such an instruction requires you to write the operand
2605 as if it were a memory reference.
2606
2607 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2608
2609 `%=' outputs a number which is unique to each instruction in the entire
2610 compilation. This is useful for making local labels to be referred to more
2611 than once in a single template that generates multiple assembler
2612 instructions.
2613
2614 `%' followed by a punctuation character specifies a substitution that does
2615 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2616 assembler code. Other nonstandard cases can be defined in the
2617 `PRINT_OPERAND' macro. You must also define which punctuation characters
2618 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2619
2620 void
frv_print_operand(FILE * file,rtx x,int code)2621 frv_print_operand (FILE * file, rtx x, int code)
2622 {
2623 HOST_WIDE_INT value;
2624 int offset;
2625
2626 if (code != 0 && !isalpha (code))
2627 value = 0;
2628
2629 else if (GET_CODE (x) == CONST_INT)
2630 value = INTVAL (x);
2631
2632 else if (GET_CODE (x) == CONST_DOUBLE)
2633 {
2634 if (GET_MODE (x) == SFmode)
2635 {
2636 REAL_VALUE_TYPE rv;
2637 long l;
2638
2639 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2640 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2641 value = l;
2642 }
2643
2644 else if (GET_MODE (x) == VOIDmode)
2645 value = CONST_DOUBLE_LOW (x);
2646
2647 else
2648 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x);
2649 }
2650
2651 else
2652 value = 0;
2653
2654 switch (code)
2655 {
2656
2657 case '.':
2658 /* Output r0. */
2659 fputs (reg_names[GPR_R0], file);
2660 break;
2661
2662 case '#':
2663 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2664 break;
2665
2666 case '@':
2667 /* Output small data area base register (gr16). */
2668 fputs (reg_names[SDA_BASE_REG], file);
2669 break;
2670
2671 case '~':
2672 /* Output pic register (gr17). */
2673 fputs (reg_names[PIC_REGNO], file);
2674 break;
2675
2676 case '*':
2677 /* Output the temporary integer CCR register. */
2678 fputs (reg_names[ICR_TEMP], file);
2679 break;
2680
2681 case '&':
2682 /* Output the temporary integer CC register. */
2683 fputs (reg_names[ICC_TEMP], file);
2684 break;
2685
2686 /* case 'a': print an address. */
2687
2688 case 'C':
2689 /* Print appropriate test for integer branch false operation. */
2690 switch (GET_CODE (x))
2691 {
2692 default:
2693 fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x);
2694
2695 case EQ: fputs ("ne", file); break;
2696 case NE: fputs ("eq", file); break;
2697 case LT: fputs ("ge", file); break;
2698 case LE: fputs ("gt", file); break;
2699 case GT: fputs ("le", file); break;
2700 case GE: fputs ("lt", file); break;
2701 case LTU: fputs ("nc", file); break;
2702 case LEU: fputs ("hi", file); break;
2703 case GTU: fputs ("ls", file); break;
2704 case GEU: fputs ("c", file); break;
2705 }
2706 break;
2707
2708 /* case 'c': print a constant without the constant prefix. If
2709 CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */
2710
2711 case 'c':
2712 /* Print appropriate test for integer branch true operation. */
2713 switch (GET_CODE (x))
2714 {
2715 default:
2716 fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x);
2717
2718 case EQ: fputs ("eq", file); break;
2719 case NE: fputs ("ne", file); break;
2720 case LT: fputs ("lt", file); break;
2721 case LE: fputs ("le", file); break;
2722 case GT: fputs ("gt", file); break;
2723 case GE: fputs ("ge", file); break;
2724 case LTU: fputs ("c", file); break;
2725 case LEU: fputs ("ls", file); break;
2726 case GTU: fputs ("hi", file); break;
2727 case GEU: fputs ("nc", file); break;
2728 }
2729 break;
2730
2731 case 'e':
2732 /* Print 1 for a NE and 0 for an EQ to give the final argument
2733 for a conditional instruction. */
2734 if (GET_CODE (x) == NE)
2735 fputs ("1", file);
2736
2737 else if (GET_CODE (x) == EQ)
2738 fputs ("0", file);
2739
2740 else
2741 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x);
2742 break;
2743
2744 case 'F':
2745 /* Print appropriate test for floating point branch false operation. */
2746 switch (GET_CODE (x))
2747 {
2748 default:
2749 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x);
2750
2751 case EQ: fputs ("ne", file); break;
2752 case NE: fputs ("eq", file); break;
2753 case LT: fputs ("uge", file); break;
2754 case LE: fputs ("ug", file); break;
2755 case GT: fputs ("ule", file); break;
2756 case GE: fputs ("ul", file); break;
2757 }
2758 break;
2759
2760 case 'f':
2761 /* Print appropriate test for floating point branch true operation. */
2762 switch (GET_CODE (x))
2763 {
2764 default:
2765 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x);
2766
2767 case EQ: fputs ("eq", file); break;
2768 case NE: fputs ("ne", file); break;
2769 case LT: fputs ("lt", file); break;
2770 case LE: fputs ("le", file); break;
2771 case GT: fputs ("gt", file); break;
2772 case GE: fputs ("ge", file); break;
2773 }
2774 break;
2775
2776 case 'I':
2777 /* Print 'i' if the operand is a constant, or is a memory reference that
2778 adds a constant. */
2779 if (GET_CODE (x) == MEM)
2780 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2781 ? XEXP (XEXP (x, 0), 1)
2782 : XEXP (x, 0));
2783
2784 switch (GET_CODE (x))
2785 {
2786 default:
2787 break;
2788
2789 case CONST_INT:
2790 case SYMBOL_REF:
2791 case CONST:
2792 fputs ("i", file);
2793 break;
2794 }
2795 break;
2796
2797 case 'i':
2798 /* For jump instructions, print 'i' if the operand is a constant or
2799 is an expression that adds a constant. */
2800 if (GET_CODE (x) == CONST_INT)
2801 fputs ("i", file);
2802
2803 else
2804 {
2805 if (GET_CODE (x) == CONST_INT
2806 || (GET_CODE (x) == PLUS
2807 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2808 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2809 fputs ("i", file);
2810 }
2811 break;
2812
2813 case 'L':
2814 /* Print the lower register of a double word register pair */
2815 if (GET_CODE (x) == REG)
2816 fputs (reg_names[ REGNO (x)+1 ], file);
2817 else
2818 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x);
2819 break;
2820
2821 /* case 'l': print a LABEL_REF. */
2822
2823 case 'M':
2824 case 'N':
2825 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2826 for the second word of double memory operations. */
2827 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2828 switch (GET_CODE (x))
2829 {
2830 default:
2831 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x);
2832
2833 case MEM:
2834 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2835 break;
2836
2837 case REG:
2838 case SUBREG:
2839 case CONST_INT:
2840 case PLUS:
2841 case SYMBOL_REF:
2842 frv_print_operand_memory_reference (file, x, offset);
2843 break;
2844 }
2845 break;
2846
2847 case 'O':
2848 /* Print the opcode of a command. */
2849 switch (GET_CODE (x))
2850 {
2851 default:
2852 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x);
2853
2854 case PLUS: fputs ("add", file); break;
2855 case MINUS: fputs ("sub", file); break;
2856 case AND: fputs ("and", file); break;
2857 case IOR: fputs ("or", file); break;
2858 case XOR: fputs ("xor", file); break;
2859 case ASHIFT: fputs ("sll", file); break;
2860 case ASHIFTRT: fputs ("sra", file); break;
2861 case LSHIFTRT: fputs ("srl", file); break;
2862 }
2863 break;
2864
2865 /* case 'n': negate and print a constant int. */
2866
2867 case 'P':
2868 /* Print PIC label using operand as the number. */
2869 if (GET_CODE (x) != CONST_INT)
2870 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x);
2871
2872 fprintf (file, ".LCF%ld", (long)INTVAL (x));
2873 break;
2874
2875 case 'U':
2876 /* Print 'u' if the operand is a update load/store. */
2877 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
2878 fputs ("u", file);
2879 break;
2880
2881 case 'z':
2882 /* If value is 0, print gr0, otherwise it must be a register. */
2883 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2884 fputs (reg_names[GPR_R0], file);
2885
2886 else if (GET_CODE (x) == REG)
2887 fputs (reg_names [REGNO (x)], file);
2888
2889 else
2890 fatal_insn ("Bad insn in frv_print_operand, z case", x);
2891 break;
2892
2893 case 'x':
2894 /* Print constant in hex. */
2895 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2896 {
2897 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
2898 break;
2899 }
2900
2901 /* Fall through. */
2902
2903 case '\0':
2904 if (GET_CODE (x) == REG)
2905 fputs (reg_names [REGNO (x)], file);
2906
2907 else if (GET_CODE (x) == CONST_INT
2908 || GET_CODE (x) == CONST_DOUBLE)
2909 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
2910
2911 else if (GET_CODE (x) == MEM)
2912 frv_print_operand_address (file, XEXP (x, 0));
2913
2914 else if (CONSTANT_ADDRESS_P (x))
2915 frv_print_operand_address (file, x);
2916
2917 else
2918 fatal_insn ("Bad insn in frv_print_operand, 0 case", x);
2919
2920 break;
2921
2922 default:
2923 fatal_insn ("frv_print_operand: unknown code", x);
2924 break;
2925 }
2926
2927 return;
2928 }
2929
2930
2931 /* A C statement (sans semicolon) for initializing the variable CUM for the
2932 state at the beginning of the argument list. The variable has type
2933 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
2934 of the function which will receive the args, or 0 if the args are to a
2935 compiler support library function. The value of INDIRECT is nonzero when
2936 processing an indirect call, for example a call through a function pointer.
2937 The value of INDIRECT is zero for a call to an explicitly named function, a
2938 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
2939 arguments for the function being compiled.
2940
2941 When processing a call to a compiler support library function, LIBNAME
2942 identifies which one. It is a `symbol_ref' rtx which contains the name of
2943 the function, as a string. LIBNAME is 0 when an ordinary C function call is
2944 being processed. Thus, each time this macro is called, either LIBNAME or
2945 FNTYPE is nonzero, but never both of them at once. */
2946
2947 void
frv_init_cumulative_args(CUMULATIVE_ARGS * cum,tree fntype,rtx libname,tree fndecl,int incoming)2948 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
2949 tree fntype,
2950 rtx libname,
2951 tree fndecl,
2952 int incoming)
2953 {
2954 *cum = FIRST_ARG_REGNUM;
2955
2956 if (TARGET_DEBUG_ARG)
2957 {
2958 fprintf (stderr, "\ninit_cumulative_args:");
2959 if (!fndecl && fntype)
2960 fputs (" indirect", stderr);
2961
2962 if (incoming)
2963 fputs (" incoming", stderr);
2964
2965 if (fntype)
2966 {
2967 tree ret_type = TREE_TYPE (fntype);
2968 fprintf (stderr, " return=%s,",
2969 tree_code_name[ (int)TREE_CODE (ret_type) ]);
2970 }
2971
2972 if (libname && GET_CODE (libname) == SYMBOL_REF)
2973 fprintf (stderr, " libname=%s", XSTR (libname, 0));
2974
2975 if (cfun->returns_struct)
2976 fprintf (stderr, " return-struct");
2977
2978 putc ('\n', stderr);
2979 }
2980 }
2981
2982
2983 /* If defined, a C expression that gives the alignment boundary, in bits, of an
2984 argument with the specified mode and type. If it is not defined,
2985 `PARM_BOUNDARY' is used for all arguments. */
2986
2987 int
frv_function_arg_boundary(enum machine_mode mode ATTRIBUTE_UNUSED,tree type ATTRIBUTE_UNUSED)2988 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
2989 tree type ATTRIBUTE_UNUSED)
2990 {
2991 return BITS_PER_WORD;
2992 }
2993
2994
2995 /* A C expression that controls whether a function argument is passed in a
2996 register, and which register.
2997
2998 The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way
2999 defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous
3000 arguments so far passed in registers; MODE, the machine mode of the argument;
3001 TYPE, the data type of the argument as a tree node or 0 if that is not known
3002 (which happens for C support library functions); and NAMED, which is 1 for an
3003 ordinary argument and 0 for nameless arguments that correspond to `...' in the
3004 called function's prototype.
3005
3006 The value of the expression should either be a `reg' RTX for the hard
3007 register in which to pass the argument, or zero to pass the argument on the
3008 stack.
3009
3010 For machines like the VAX and 68000, where normally all arguments are
3011 pushed, zero suffices as a definition.
3012
3013 The usual way to make the ANSI library `stdarg.h' work on a machine where
3014 some arguments are usually passed in registers, is to cause nameless
3015 arguments to be passed on the stack instead. This is done by making
3016 `FUNCTION_ARG' return 0 whenever NAMED is 0.
3017
3018 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
3019 this macro to determine if this argument is of a type that must be passed in
3020 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
3021 returns nonzero for such an argument, the compiler will abort. If
3022 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
3023 stack and then loaded into a register. */
3024
3025 rtx
frv_function_arg(CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type ATTRIBUTE_UNUSED,int named,int incoming ATTRIBUTE_UNUSED)3026 frv_function_arg (CUMULATIVE_ARGS *cum,
3027 enum machine_mode mode,
3028 tree type ATTRIBUTE_UNUSED,
3029 int named,
3030 int incoming ATTRIBUTE_UNUSED)
3031 {
3032 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3033 int arg_num = *cum;
3034 rtx ret;
3035 const char *debstr;
3036
3037 /* Return a marker for use in the call instruction. */
3038 if (xmode == VOIDmode)
3039 {
3040 ret = const0_rtx;
3041 debstr = "<0>";
3042 }
3043
3044 else if (arg_num <= LAST_ARG_REGNUM)
3045 {
3046 ret = gen_rtx (REG, xmode, arg_num);
3047 debstr = reg_names[arg_num];
3048 }
3049
3050 else
3051 {
3052 ret = NULL_RTX;
3053 debstr = "memory";
3054 }
3055
3056 if (TARGET_DEBUG_ARG)
3057 fprintf (stderr,
3058 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3059 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3060
3061 return ret;
3062 }
3063
3064
3065 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3066 advance past an argument in the argument list. The values MODE, TYPE and
3067 NAMED describe that argument. Once this is done, the variable CUM is
3068 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3069
3070 This macro need not do anything if the argument in question was passed on
3071 the stack. The compiler knows how to track the amount of stack space used
3072 for arguments without any special help. */
3073
3074 void
frv_function_arg_advance(CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type ATTRIBUTE_UNUSED,int named)3075 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3076 enum machine_mode mode,
3077 tree type ATTRIBUTE_UNUSED,
3078 int named)
3079 {
3080 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3081 int bytes = GET_MODE_SIZE (xmode);
3082 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3083 int arg_num = *cum;
3084
3085 *cum = arg_num + words;
3086
3087 if (TARGET_DEBUG_ARG)
3088 fprintf (stderr,
3089 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3090 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3091 }
3092
3093
3094 /* A C expression for the number of words, at the beginning of an argument,
3095 must be put in registers. The value must be zero for arguments that are
3096 passed entirely in registers or that are entirely pushed on the stack.
3097
3098 On some machines, certain arguments must be passed partially in registers
3099 and partially in memory. On these machines, typically the first N words of
3100 arguments are passed in registers, and the rest on the stack. If a
3101 multi-word argument (a `double' or a structure) crosses that boundary, its
3102 first few words must be passed in registers and the rest must be pushed.
3103 This macro tells the compiler when this occurs, and how many of the words
3104 should go in registers.
3105
3106 `FUNCTION_ARG' for these arguments should return the first register to be
3107 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3108 the called function. */
3109
3110 int
frv_function_arg_partial_nregs(CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type ATTRIBUTE_UNUSED,int named ATTRIBUTE_UNUSED)3111 frv_function_arg_partial_nregs (CUMULATIVE_ARGS *cum,
3112 enum machine_mode mode,
3113 tree type ATTRIBUTE_UNUSED,
3114 int named ATTRIBUTE_UNUSED)
3115 {
3116 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3117 int bytes = GET_MODE_SIZE (xmode);
3118 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3119 int arg_num = *cum;
3120 int ret;
3121
3122 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3123 ? LAST_ARG_REGNUM - arg_num + 1
3124 : 0);
3125
3126 if (TARGET_DEBUG_ARG && ret)
3127 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
3128
3129 return ret;
3130
3131 }
3132
3133
3134
3135 /* A C expression that indicates when an argument must be passed by reference.
3136 If nonzero for an argument, a copy of that argument is made in memory and a
3137 pointer to the argument is passed instead of the argument itself. The
3138 pointer is passed in whatever way is appropriate for passing a pointer to
3139 that type.
3140
3141 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
3142 definition of this macro might be
3143 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
3144 MUST_PASS_IN_STACK (MODE, TYPE) */
3145
3146 int
frv_function_arg_pass_by_reference(CUMULATIVE_ARGS * cum ATTRIBUTE_UNUSED,enum machine_mode mode,tree type,int named ATTRIBUTE_UNUSED)3147 frv_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3148 enum machine_mode mode,
3149 tree type,
3150 int named ATTRIBUTE_UNUSED)
3151 {
3152 return MUST_PASS_IN_STACK (mode, type);
3153 }
3154
3155 /* If defined, a C expression that indicates when it is the called function's
3156 responsibility to make a copy of arguments passed by invisible reference.
3157 Normally, the caller makes a copy and passes the address of the copy to the
3158 routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is
3159 nonzero, the caller does not make a copy. Instead, it passes a pointer to
3160 the "live" value. The called function must not modify this value. If it
3161 can be determined that the value won't be modified, it need not make a copy;
3162 otherwise a copy must be made. */
3163
3164 int
frv_function_arg_callee_copies(CUMULATIVE_ARGS * cum ATTRIBUTE_UNUSED,enum machine_mode mode ATTRIBUTE_UNUSED,tree type ATTRIBUTE_UNUSED,int named ATTRIBUTE_UNUSED)3165 frv_function_arg_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3166 enum machine_mode mode ATTRIBUTE_UNUSED,
3167 tree type ATTRIBUTE_UNUSED,
3168 int named ATTRIBUTE_UNUSED)
3169 {
3170 return 0;
3171 }
3172
3173 /* If defined, a C expression that indicates when it is more desirable to keep
3174 an argument passed by invisible reference as a reference, rather than
3175 copying it to a pseudo register. */
3176
3177 int
frv_function_arg_keep_as_reference(CUMULATIVE_ARGS * cum ATTRIBUTE_UNUSED,enum machine_mode mode ATTRIBUTE_UNUSED,tree type ATTRIBUTE_UNUSED,int named ATTRIBUTE_UNUSED)3178 frv_function_arg_keep_as_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3179 enum machine_mode mode ATTRIBUTE_UNUSED,
3180 tree type ATTRIBUTE_UNUSED,
3181 int named ATTRIBUTE_UNUSED)
3182 {
3183 return 0;
3184 }
3185
3186
3187 /* Return true if a register is ok to use as a base or index register. */
3188
3189 static FRV_INLINE int
frv_regno_ok_for_base_p(int regno,int strict_p)3190 frv_regno_ok_for_base_p (int regno, int strict_p)
3191 {
3192 if (GPR_P (regno))
3193 return TRUE;
3194
3195 if (strict_p)
3196 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3197
3198 if (regno == ARG_POINTER_REGNUM)
3199 return TRUE;
3200
3201 return (regno >= FIRST_PSEUDO_REGISTER);
3202 }
3203
3204
3205 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3206 RTX) is a legitimate memory address on the target machine for a memory
3207 operand of mode MODE.
3208
3209 It usually pays to define several simpler macros to serve as subroutines for
3210 this one. Otherwise it may be too complicated to understand.
3211
3212 This macro must exist in two variants: a strict variant and a non-strict
3213 one. The strict variant is used in the reload pass. It must be defined so
3214 that any pseudo-register that has not been allocated a hard register is
3215 considered a memory reference. In contexts where some kind of register is
3216 required, a pseudo-register with no hard register must be rejected.
3217
3218 The non-strict variant is used in other passes. It must be defined to
3219 accept all pseudo-registers in every context where some kind of register is
3220 required.
3221
3222 Compiler source files that want to use the strict variant of this macro
3223 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3224 conditional to define the strict variant in that case and the non-strict
3225 variant otherwise.
3226
3227 Subroutines to check for acceptable registers for various purposes (one for
3228 base registers, one for index registers, and so on) are typically among the
3229 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3230 subroutine macros need have two variants; the higher levels of macros may be
3231 the same whether strict or not.
3232
3233 Normally, constant addresses which are the sum of a `symbol_ref' and an
3234 integer are stored inside a `const' RTX to mark them as constant.
3235 Therefore, there is no need to recognize such sums specifically as
3236 legitimate addresses. Normally you would simply recognize any `const' as
3237 legitimate.
3238
3239 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3240 are not marked with `const'. It assumes that a naked `plus' indicates
3241 indexing. If so, then you *must* reject such naked constant sums as
3242 illegitimate addresses, so that none of them will be given to
3243 `PRINT_OPERAND_ADDRESS'.
3244
3245 On some machines, whether a symbolic address is legitimate depends on the
3246 section that the address refers to. On these machines, define the macro
3247 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3248 then check for it here. When you see a `const', you will have to look
3249 inside it to find the `symbol_ref' in order to determine the section.
3250
3251 The best way to modify the name string is by adding text to the beginning,
3252 with suitable punctuation to prevent any ambiguity. Allocate the new name
3253 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3254 remove and decode the added text and output the name accordingly, and define
3255 `(* targetm.strip_name_encoding)' to access the original name string.
3256
3257 You can check the information stored here into the `symbol_ref' in the
3258 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3259 `PRINT_OPERAND_ADDRESS'. */
3260
3261 int
frv_legitimate_address_p(enum machine_mode mode,rtx x,int strict_p,int condexec_p)3262 frv_legitimate_address_p (enum machine_mode mode,
3263 rtx x,
3264 int strict_p,
3265 int condexec_p)
3266 {
3267 rtx x0, x1;
3268 int ret = 0;
3269 HOST_WIDE_INT value;
3270 unsigned regno0;
3271
3272 switch (GET_CODE (x))
3273 {
3274 default:
3275 break;
3276
3277 case SUBREG:
3278 x = SUBREG_REG (x);
3279 if (GET_CODE (x) != REG)
3280 break;
3281
3282 /* Fall through. */
3283
3284 case REG:
3285 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3286 break;
3287
3288 case PRE_MODIFY:
3289 x0 = XEXP (x, 0);
3290 x1 = XEXP (x, 1);
3291 if (GET_CODE (x0) != REG
3292 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3293 || GET_CODE (x1) != PLUS
3294 || ! rtx_equal_p (x0, XEXP (x1, 0))
3295 || GET_CODE (XEXP (x1, 1)) != REG
3296 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3297 break;
3298
3299 ret = 1;
3300 break;
3301
3302 case CONST_INT:
3303 /* 12 bit immediate */
3304 if (condexec_p)
3305 ret = FALSE;
3306 else
3307 {
3308 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3309
3310 /* If we can't use load/store double operations, make sure we can
3311 address the second word. */
3312 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3313 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3314 -2048, 2047);
3315 }
3316 break;
3317
3318 case PLUS:
3319 x0 = XEXP (x, 0);
3320 x1 = XEXP (x, 1);
3321
3322 if (GET_CODE (x0) == SUBREG)
3323 x0 = SUBREG_REG (x0);
3324
3325 if (GET_CODE (x0) != REG)
3326 break;
3327
3328 regno0 = REGNO (x0);
3329 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3330 break;
3331
3332 switch (GET_CODE (x1))
3333 {
3334 default:
3335 break;
3336
3337 case SUBREG:
3338 x1 = SUBREG_REG (x1);
3339 if (GET_CODE (x1) != REG)
3340 break;
3341
3342 /* Fall through. */
3343
3344 case REG:
3345 /* Do not allow reg+reg addressing for modes > 1 word if we
3346 can't depend on having move double instructions. */
3347 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3348 ret = FALSE;
3349 else
3350 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3351 break;
3352
3353 case CONST_INT:
3354 /* 12 bit immediate */
3355 if (condexec_p)
3356 ret = FALSE;
3357 else
3358 {
3359 value = INTVAL (x1);
3360 ret = IN_RANGE_P (value, -2048, 2047);
3361
3362 /* If we can't use load/store double operations, make sure we can
3363 address the second word. */
3364 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3365 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3366 }
3367 break;
3368
3369 case SYMBOL_REF:
3370 if (!condexec_p
3371 && regno0 == SDA_BASE_REG
3372 && SYMBOL_REF_SMALL_P (x1))
3373 ret = TRUE;
3374 break;
3375
3376 case CONST:
3377 if (!condexec_p && regno0 == SDA_BASE_REG && const_small_data_p (x1))
3378 ret = TRUE;
3379 break;
3380
3381 }
3382 break;
3383 }
3384
3385 if (TARGET_DEBUG_ADDR)
3386 {
3387 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3388 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3389 (condexec_p) ? ", inside conditional code" : "");
3390 debug_rtx (x);
3391 }
3392
3393 return ret;
3394 }
3395
3396
3397 /* A C compound statement that attempts to replace X with a valid memory
3398 address for an operand of mode MODE. WIN will be a C statement label
3399 elsewhere in the code; the macro definition may use
3400
3401 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3402
3403 to avoid further processing if the address has become legitimate.
3404
3405 X will always be the result of a call to `break_out_memory_refs', and OLDX
3406 will be the operand that was given to that function to produce X.
3407
3408 The code generated by this macro should not alter the substructure of X. If
3409 it transforms X into a more legitimate form, it should assign X (which will
3410 always be a C variable) a new value.
3411
3412 It is not necessary for this macro to come up with a legitimate address.
3413 The compiler has standard ways of doing so in all cases. In fact, it is
3414 safe for this macro to do nothing. But often a machine-dependent strategy
3415 can generate better code. */
3416
3417 rtx
frv_legitimize_address(rtx x,rtx oldx ATTRIBUTE_UNUSED,enum machine_mode mode ATTRIBUTE_UNUSED)3418 frv_legitimize_address (rtx x,
3419 rtx oldx ATTRIBUTE_UNUSED,
3420 enum machine_mode mode ATTRIBUTE_UNUSED)
3421 {
3422 rtx ret = NULL_RTX;
3423
3424 /* Don't try to legitimize addresses if we are not optimizing, since the
3425 address we generate is not a general operand, and will horribly mess
3426 things up when force_reg is called to try and put it in a register because
3427 we aren't optimizing. */
3428 if (optimize
3429 && ((GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_SMALL_P (x))
3430 || (GET_CODE (x) == CONST && const_small_data_p (x))))
3431 {
3432 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, SDA_BASE_REG), x);
3433 if (flag_pic)
3434 cfun->uses_pic_offset_table = TRUE;
3435 }
3436
3437 if (TARGET_DEBUG_ADDR && ret != NULL_RTX)
3438 {
3439 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, mode = %s, modified address\n",
3440 GET_MODE_NAME (mode));
3441 debug_rtx (ret);
3442 }
3443
3444 return ret;
3445 }
3446
3447 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3448 the operand is used by a predicated instruction. */
3449
3450 static int
frv_legitimate_memory_operand(rtx op,enum machine_mode mode,int condexec_p)3451 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3452 {
3453 return ((GET_MODE (op) == mode || mode == VOIDmode)
3454 && GET_CODE (op) == MEM
3455 && frv_legitimate_address_p (mode, XEXP (op, 0),
3456 reload_completed, condexec_p));
3457 }
3458
3459
3460 /* Return 1 is OP is a memory operand, or will be turned into one by
3461 reload. */
3462
3463 int
frv_load_operand(rtx op,enum machine_mode mode)3464 frv_load_operand (rtx op, enum machine_mode mode)
3465 {
3466 if (GET_MODE (op) != mode && mode != VOIDmode)
3467 return FALSE;
3468
3469 if (reload_in_progress)
3470 {
3471 rtx tmp = op;
3472 if (GET_CODE (tmp) == SUBREG)
3473 tmp = SUBREG_REG (tmp);
3474 if (GET_CODE (tmp) == REG
3475 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
3476 op = reg_equiv_memory_loc[REGNO (tmp)];
3477 }
3478
3479 return op && memory_operand (op, mode);
3480 }
3481
3482
3483 /* Return 1 if operand is a GPR register or a FPR register. */
3484
3485 int
gpr_or_fpr_operand(rtx op,enum machine_mode mode)3486 gpr_or_fpr_operand (rtx op, enum machine_mode mode)
3487 {
3488 int regno;
3489
3490 if (GET_MODE (op) != mode && mode != VOIDmode)
3491 return FALSE;
3492
3493 if (GET_CODE (op) == SUBREG)
3494 {
3495 if (GET_CODE (SUBREG_REG (op)) != REG)
3496 return register_operand (op, mode);
3497
3498 op = SUBREG_REG (op);
3499 }
3500
3501 if (GET_CODE (op) != REG)
3502 return FALSE;
3503
3504 regno = REGNO (op);
3505 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3506 return TRUE;
3507
3508 return FALSE;
3509 }
3510
3511 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3512
3513 int
gpr_or_int12_operand(rtx op,enum machine_mode mode)3514 gpr_or_int12_operand (rtx op, enum machine_mode mode)
3515 {
3516 if (GET_CODE (op) == CONST_INT)
3517 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3518
3519 if (GET_MODE (op) != mode && mode != VOIDmode)
3520 return FALSE;
3521
3522 if (GET_CODE (op) == SUBREG)
3523 {
3524 if (GET_CODE (SUBREG_REG (op)) != REG)
3525 return register_operand (op, mode);
3526
3527 op = SUBREG_REG (op);
3528 }
3529
3530 if (GET_CODE (op) != REG)
3531 return FALSE;
3532
3533 return GPR_OR_PSEUDO_P (REGNO (op));
3534 }
3535
3536 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3537 signed immediate. */
3538
3539 int
gpr_fpr_or_int12_operand(rtx op,enum machine_mode mode)3540 gpr_fpr_or_int12_operand (rtx op, enum machine_mode mode)
3541 {
3542 int regno;
3543
3544 if (GET_CODE (op) == CONST_INT)
3545 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3546
3547 if (GET_MODE (op) != mode && mode != VOIDmode)
3548 return FALSE;
3549
3550 if (GET_CODE (op) == SUBREG)
3551 {
3552 if (GET_CODE (SUBREG_REG (op)) != REG)
3553 return register_operand (op, mode);
3554
3555 op = SUBREG_REG (op);
3556 }
3557
3558 if (GET_CODE (op) != REG)
3559 return FALSE;
3560
3561 regno = REGNO (op);
3562 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3563 return TRUE;
3564
3565 return FALSE;
3566 }
3567
3568 /* Return 1 if operand is a register or 6 bit signed immediate. */
3569
3570 int
fpr_or_int6_operand(rtx op,enum machine_mode mode)3571 fpr_or_int6_operand (rtx op, enum machine_mode mode)
3572 {
3573 if (GET_CODE (op) == CONST_INT)
3574 return IN_RANGE_P (INTVAL (op), -32, 31);
3575
3576 if (GET_MODE (op) != mode && mode != VOIDmode)
3577 return FALSE;
3578
3579 if (GET_CODE (op) == SUBREG)
3580 {
3581 if (GET_CODE (SUBREG_REG (op)) != REG)
3582 return register_operand (op, mode);
3583
3584 op = SUBREG_REG (op);
3585 }
3586
3587 if (GET_CODE (op) != REG)
3588 return FALSE;
3589
3590 return FPR_OR_PSEUDO_P (REGNO (op));
3591 }
3592
3593 /* Return 1 if operand is a register or 10 bit signed immediate. */
3594
3595 int
gpr_or_int10_operand(rtx op,enum machine_mode mode)3596 gpr_or_int10_operand (rtx op, enum machine_mode mode)
3597 {
3598 if (GET_CODE (op) == CONST_INT)
3599 return IN_RANGE_P (INTVAL (op), -512, 511);
3600
3601 if (GET_MODE (op) != mode && mode != VOIDmode)
3602 return FALSE;
3603
3604 if (GET_CODE (op) == SUBREG)
3605 {
3606 if (GET_CODE (SUBREG_REG (op)) != REG)
3607 return register_operand (op, mode);
3608
3609 op = SUBREG_REG (op);
3610 }
3611
3612 if (GET_CODE (op) != REG)
3613 return FALSE;
3614
3615 return GPR_OR_PSEUDO_P (REGNO (op));
3616 }
3617
3618 /* Return 1 if operand is a register or an integer immediate. */
3619
3620 int
gpr_or_int_operand(rtx op,enum machine_mode mode)3621 gpr_or_int_operand (rtx op, enum machine_mode mode)
3622 {
3623 if (GET_CODE (op) == CONST_INT)
3624 return TRUE;
3625
3626 if (GET_MODE (op) != mode && mode != VOIDmode)
3627 return FALSE;
3628
3629 if (GET_CODE (op) == SUBREG)
3630 {
3631 if (GET_CODE (SUBREG_REG (op)) != REG)
3632 return register_operand (op, mode);
3633
3634 op = SUBREG_REG (op);
3635 }
3636
3637 if (GET_CODE (op) != REG)
3638 return FALSE;
3639
3640 return GPR_OR_PSEUDO_P (REGNO (op));
3641 }
3642
3643 /* Return 1 if operand is a 12 bit signed immediate. */
3644
3645 int
int12_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)3646 int12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3647 {
3648 if (GET_CODE (op) != CONST_INT)
3649 return FALSE;
3650
3651 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3652 }
3653
3654 /* Return 1 if operand is a 6 bit signed immediate. */
3655
3656 int
int6_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)3657 int6_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3658 {
3659 if (GET_CODE (op) != CONST_INT)
3660 return FALSE;
3661
3662 return IN_RANGE_P (INTVAL (op), -32, 31);
3663 }
3664
3665 /* Return 1 if operand is a 5 bit signed immediate. */
3666
3667 int
int5_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)3668 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3669 {
3670 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
3671 }
3672
3673 /* Return 1 if operand is a 5 bit unsigned immediate. */
3674
3675 int
uint5_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)3676 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3677 {
3678 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
3679 }
3680
3681 /* Return 1 if operand is a 4 bit unsigned immediate. */
3682
3683 int
uint4_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)3684 uint4_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3685 {
3686 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
3687 }
3688
3689 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3690
3691 int
uint1_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)3692 uint1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3693 {
3694 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1);
3695 }
3696
3697 /* Return 1 if operand is an integer constant that takes 2 instructions
3698 to load up and can be split into sethi/setlo instructions.. */
3699
3700 int
int_2word_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)3701 int_2word_operand(rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3702 {
3703 HOST_WIDE_INT value;
3704 REAL_VALUE_TYPE rv;
3705 long l;
3706
3707 switch (GET_CODE (op))
3708 {
3709 default:
3710 break;
3711
3712 case LABEL_REF:
3713 return (flag_pic == 0);
3714
3715 case CONST:
3716 /* small data references are already 1 word */
3717 return (flag_pic == 0) && (! const_small_data_p (op));
3718
3719 case SYMBOL_REF:
3720 /* small data references are already 1 word */
3721 return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op));
3722
3723 case CONST_INT:
3724 return ! IN_RANGE_P (INTVAL (op), -32768, 32767);
3725
3726 case CONST_DOUBLE:
3727 if (GET_MODE (op) == SFmode)
3728 {
3729 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
3730 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
3731 value = l;
3732 return ! IN_RANGE_P (value, -32768, 32767);
3733 }
3734 else if (GET_MODE (op) == VOIDmode)
3735 {
3736 value = CONST_DOUBLE_LOW (op);
3737 return ! IN_RANGE_P (value, -32768, 32767);
3738 }
3739 break;
3740 }
3741
3742 return FALSE;
3743 }
3744
3745 /* Return 1 if operand is the pic address register. */
3746 int
pic_register_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)3747 pic_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3748 {
3749 if (! flag_pic)
3750 return FALSE;
3751
3752 if (GET_CODE (op) != REG)
3753 return FALSE;
3754
3755 if (REGNO (op) != PIC_REGNO)
3756 return FALSE;
3757
3758 return TRUE;
3759 }
3760
3761 /* Return 1 if operand is a symbolic reference when a PIC option is specified
3762 that takes 3 separate instructions to form. */
3763
3764 int
pic_symbolic_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)3765 pic_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3766 {
3767 if (! flag_pic)
3768 return FALSE;
3769
3770 switch (GET_CODE (op))
3771 {
3772 default:
3773 break;
3774
3775 case LABEL_REF:
3776 return TRUE;
3777
3778 case SYMBOL_REF:
3779 /* small data references are already 1 word */
3780 return ! SYMBOL_REF_SMALL_P (op);
3781
3782 case CONST:
3783 /* small data references are already 1 word */
3784 return ! const_small_data_p (op);
3785 }
3786
3787 return FALSE;
3788 }
3789
3790 /* Return 1 if operand is the small data register. */
3791 int
small_data_register_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)3792 small_data_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3793 {
3794 if (GET_CODE (op) != REG)
3795 return FALSE;
3796
3797 if (REGNO (op) != SDA_BASE_REG)
3798 return FALSE;
3799
3800 return TRUE;
3801 }
3802
3803 /* Return 1 if operand is a symbolic reference to a small data area static or
3804 global object. */
3805
3806 int
small_data_symbolic_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)3807 small_data_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3808 {
3809 switch (GET_CODE (op))
3810 {
3811 default:
3812 break;
3813
3814 case CONST:
3815 return const_small_data_p (op);
3816
3817 case SYMBOL_REF:
3818 return SYMBOL_REF_SMALL_P (op);
3819 }
3820
3821 return FALSE;
3822 }
3823
3824 /* Return 1 if operand is a 16 bit unsigned immediate. */
3825
3826 int
uint16_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)3827 uint16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3828 {
3829 if (GET_CODE (op) != CONST_INT)
3830 return FALSE;
3831
3832 return IN_RANGE_P (INTVAL (op), 0, 0xffff);
3833 }
3834
3835 /* Return 1 if operand is an integer constant with the bottom 16 bits
3836 clear. */
3837
3838 int
upper_int16_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)3839 upper_int16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3840 {
3841 if (GET_CODE (op) != CONST_INT)
3842 return FALSE;
3843
3844 return ((INTVAL (op) & 0xffff) == 0);
3845 }
3846
3847 /* Return true if operand is a GPR register. */
3848
3849 int
integer_register_operand(rtx op,enum machine_mode mode)3850 integer_register_operand (rtx op, enum machine_mode mode)
3851 {
3852 if (GET_MODE (op) != mode && mode != VOIDmode)
3853 return FALSE;
3854
3855 if (GET_CODE (op) == SUBREG)
3856 {
3857 if (GET_CODE (SUBREG_REG (op)) != REG)
3858 return register_operand (op, mode);
3859
3860 op = SUBREG_REG (op);
3861 }
3862
3863 if (GET_CODE (op) != REG)
3864 return FALSE;
3865
3866 return GPR_OR_PSEUDO_P (REGNO (op));
3867 }
3868
3869 /* Return true if operand is a GPR register. Do not allow SUBREG's
3870 here, in order to prevent a combine bug. */
3871
3872 int
gpr_no_subreg_operand(rtx op,enum machine_mode mode)3873 gpr_no_subreg_operand (rtx op, enum machine_mode mode)
3874 {
3875 if (GET_MODE (op) != mode && mode != VOIDmode)
3876 return FALSE;
3877
3878 if (GET_CODE (op) != REG)
3879 return FALSE;
3880
3881 return GPR_OR_PSEUDO_P (REGNO (op));
3882 }
3883
3884 /* Return true if operand is a FPR register. */
3885
3886 int
fpr_operand(rtx op,enum machine_mode mode)3887 fpr_operand (rtx op, enum machine_mode mode)
3888 {
3889 if (GET_MODE (op) != mode && mode != VOIDmode)
3890 return FALSE;
3891
3892 if (GET_CODE (op) == SUBREG)
3893 {
3894 if (GET_CODE (SUBREG_REG (op)) != REG)
3895 return register_operand (op, mode);
3896
3897 op = SUBREG_REG (op);
3898 }
3899
3900 if (GET_CODE (op) != REG)
3901 return FALSE;
3902
3903 return FPR_OR_PSEUDO_P (REGNO (op));
3904 }
3905
3906 /* Return true if operand is an even GPR or FPR register. */
3907
3908 int
even_reg_operand(rtx op,enum machine_mode mode)3909 even_reg_operand (rtx op, enum machine_mode mode)
3910 {
3911 int regno;
3912
3913 if (GET_MODE (op) != mode && mode != VOIDmode)
3914 return FALSE;
3915
3916 if (GET_CODE (op) == SUBREG)
3917 {
3918 if (GET_CODE (SUBREG_REG (op)) != REG)
3919 return register_operand (op, mode);
3920
3921 op = SUBREG_REG (op);
3922 }
3923
3924 if (GET_CODE (op) != REG)
3925 return FALSE;
3926
3927 regno = REGNO (op);
3928 if (regno >= FIRST_PSEUDO_REGISTER)
3929 return TRUE;
3930
3931 if (GPR_P (regno))
3932 return (((regno - GPR_FIRST) & 1) == 0);
3933
3934 if (FPR_P (regno))
3935 return (((regno - FPR_FIRST) & 1) == 0);
3936
3937 return FALSE;
3938 }
3939
3940 /* Return true if operand is an odd GPR register. */
3941
3942 int
odd_reg_operand(rtx op,enum machine_mode mode)3943 odd_reg_operand (rtx op, enum machine_mode mode)
3944 {
3945 int regno;
3946
3947 if (GET_MODE (op) != mode && mode != VOIDmode)
3948 return FALSE;
3949
3950 if (GET_CODE (op) == SUBREG)
3951 {
3952 if (GET_CODE (SUBREG_REG (op)) != REG)
3953 return register_operand (op, mode);
3954
3955 op = SUBREG_REG (op);
3956 }
3957
3958 if (GET_CODE (op) != REG)
3959 return FALSE;
3960
3961 regno = REGNO (op);
3962 /* Assume that reload will give us an even register. */
3963 if (regno >= FIRST_PSEUDO_REGISTER)
3964 return FALSE;
3965
3966 if (GPR_P (regno))
3967 return (((regno - GPR_FIRST) & 1) != 0);
3968
3969 if (FPR_P (regno))
3970 return (((regno - FPR_FIRST) & 1) != 0);
3971
3972 return FALSE;
3973 }
3974
3975 /* Return true if operand is an even GPR register. */
3976
3977 int
even_gpr_operand(rtx op,enum machine_mode mode)3978 even_gpr_operand (rtx op, enum machine_mode mode)
3979 {
3980 int regno;
3981
3982 if (GET_MODE (op) != mode && mode != VOIDmode)
3983 return FALSE;
3984
3985 if (GET_CODE (op) == SUBREG)
3986 {
3987 if (GET_CODE (SUBREG_REG (op)) != REG)
3988 return register_operand (op, mode);
3989
3990 op = SUBREG_REG (op);
3991 }
3992
3993 if (GET_CODE (op) != REG)
3994 return FALSE;
3995
3996 regno = REGNO (op);
3997 if (regno >= FIRST_PSEUDO_REGISTER)
3998 return TRUE;
3999
4000 if (! GPR_P (regno))
4001 return FALSE;
4002
4003 return (((regno - GPR_FIRST) & 1) == 0);
4004 }
4005
4006 /* Return true if operand is an odd GPR register. */
4007
4008 int
odd_gpr_operand(rtx op,enum machine_mode mode)4009 odd_gpr_operand (rtx op, enum machine_mode mode)
4010 {
4011 int regno;
4012
4013 if (GET_MODE (op) != mode && mode != VOIDmode)
4014 return FALSE;
4015
4016 if (GET_CODE (op) == SUBREG)
4017 {
4018 if (GET_CODE (SUBREG_REG (op)) != REG)
4019 return register_operand (op, mode);
4020
4021 op = SUBREG_REG (op);
4022 }
4023
4024 if (GET_CODE (op) != REG)
4025 return FALSE;
4026
4027 regno = REGNO (op);
4028 /* Assume that reload will give us an even register. */
4029 if (regno >= FIRST_PSEUDO_REGISTER)
4030 return FALSE;
4031
4032 if (! GPR_P (regno))
4033 return FALSE;
4034
4035 return (((regno - GPR_FIRST) & 1) != 0);
4036 }
4037
4038 /* Return true if operand is a quad aligned FPR register. */
4039
4040 int
quad_fpr_operand(rtx op,enum machine_mode mode)4041 quad_fpr_operand (rtx op, enum machine_mode mode)
4042 {
4043 int regno;
4044
4045 if (GET_MODE (op) != mode && mode != VOIDmode)
4046 return FALSE;
4047
4048 if (GET_CODE (op) == SUBREG)
4049 {
4050 if (GET_CODE (SUBREG_REG (op)) != REG)
4051 return register_operand (op, mode);
4052
4053 op = SUBREG_REG (op);
4054 }
4055
4056 if (GET_CODE (op) != REG)
4057 return FALSE;
4058
4059 regno = REGNO (op);
4060 if (regno >= FIRST_PSEUDO_REGISTER)
4061 return TRUE;
4062
4063 if (! FPR_P (regno))
4064 return FALSE;
4065
4066 return (((regno - FPR_FIRST) & 3) == 0);
4067 }
4068
4069 /* Return true if operand is an even FPR register. */
4070
4071 int
even_fpr_operand(rtx op,enum machine_mode mode)4072 even_fpr_operand (rtx op, enum machine_mode mode)
4073 {
4074 int regno;
4075
4076 if (GET_MODE (op) != mode && mode != VOIDmode)
4077 return FALSE;
4078
4079 if (GET_CODE (op) == SUBREG)
4080 {
4081 if (GET_CODE (SUBREG_REG (op)) != REG)
4082 return register_operand (op, mode);
4083
4084 op = SUBREG_REG (op);
4085 }
4086
4087 if (GET_CODE (op) != REG)
4088 return FALSE;
4089
4090 regno = REGNO (op);
4091 if (regno >= FIRST_PSEUDO_REGISTER)
4092 return TRUE;
4093
4094 if (! FPR_P (regno))
4095 return FALSE;
4096
4097 return (((regno - FPR_FIRST) & 1) == 0);
4098 }
4099
4100 /* Return true if operand is an odd FPR register. */
4101
4102 int
odd_fpr_operand(rtx op,enum machine_mode mode)4103 odd_fpr_operand (rtx op, enum machine_mode mode)
4104 {
4105 int regno;
4106
4107 if (GET_MODE (op) != mode && mode != VOIDmode)
4108 return FALSE;
4109
4110 if (GET_CODE (op) == SUBREG)
4111 {
4112 if (GET_CODE (SUBREG_REG (op)) != REG)
4113 return register_operand (op, mode);
4114
4115 op = SUBREG_REG (op);
4116 }
4117
4118 if (GET_CODE (op) != REG)
4119 return FALSE;
4120
4121 regno = REGNO (op);
4122 /* Assume that reload will give us an even register. */
4123 if (regno >= FIRST_PSEUDO_REGISTER)
4124 return FALSE;
4125
4126 if (! FPR_P (regno))
4127 return FALSE;
4128
4129 return (((regno - FPR_FIRST) & 1) != 0);
4130 }
4131
4132 /* Return true if operand is a 2 word memory address that can be loaded in one
4133 instruction to load or store. We assume the stack and frame pointers are
4134 suitably aligned, and variables in the small data area. FIXME -- at some we
4135 should recognize other globals and statics. We can't assume that any old
4136 pointer is aligned, given that arguments could be passed on an odd word on
4137 the stack and the address taken and passed through to another function. */
4138
4139 int
dbl_memory_one_insn_operand(rtx op,enum machine_mode mode)4140 dbl_memory_one_insn_operand (rtx op, enum machine_mode mode)
4141 {
4142 rtx addr;
4143 rtx addr_reg;
4144
4145 if (! TARGET_DWORD)
4146 return FALSE;
4147
4148 if (GET_CODE (op) != MEM)
4149 return FALSE;
4150
4151 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4152 return FALSE;
4153
4154 addr = XEXP (op, 0);
4155 if (GET_CODE (addr) == REG)
4156 addr_reg = addr;
4157
4158 else if (GET_CODE (addr) == PLUS)
4159 {
4160 rtx addr0 = XEXP (addr, 0);
4161 rtx addr1 = XEXP (addr, 1);
4162
4163 if (GET_CODE (addr0) != REG)
4164 return FALSE;
4165
4166 if (plus_small_data_p (addr0, addr1))
4167 return TRUE;
4168
4169 if (GET_CODE (addr1) != CONST_INT)
4170 return FALSE;
4171
4172 if ((INTVAL (addr1) & 7) != 0)
4173 return FALSE;
4174
4175 addr_reg = addr0;
4176 }
4177
4178 else
4179 return FALSE;
4180
4181 if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx)
4182 return TRUE;
4183
4184 return FALSE;
4185 }
4186
4187 /* Return true if operand is a 2 word memory address that needs to
4188 use two instructions to load or store. */
4189
4190 int
dbl_memory_two_insn_operand(rtx op,enum machine_mode mode)4191 dbl_memory_two_insn_operand (rtx op, enum machine_mode mode)
4192 {
4193 if (GET_CODE (op) != MEM)
4194 return FALSE;
4195
4196 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4197 return FALSE;
4198
4199 if (! TARGET_DWORD)
4200 return TRUE;
4201
4202 return ! dbl_memory_one_insn_operand (op, mode);
4203 }
4204
4205 /* Return true if operand is something that can be an output for a move
4206 operation. */
4207
4208 int
move_destination_operand(rtx op,enum machine_mode mode)4209 move_destination_operand (rtx op, enum machine_mode mode)
4210 {
4211 rtx subreg;
4212 enum rtx_code code;
4213
4214 switch (GET_CODE (op))
4215 {
4216 default:
4217 break;
4218
4219 case SUBREG:
4220 if (GET_MODE (op) != mode && mode != VOIDmode)
4221 return FALSE;
4222
4223 subreg = SUBREG_REG (op);
4224 code = GET_CODE (subreg);
4225 if (code == MEM)
4226 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4227 reload_completed, FALSE);
4228
4229 return (code == REG);
4230
4231 case REG:
4232 if (GET_MODE (op) != mode && mode != VOIDmode)
4233 return FALSE;
4234
4235 return TRUE;
4236
4237 case MEM:
4238 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4239 return TRUE;
4240
4241 return frv_legitimate_memory_operand (op, mode, FALSE);
4242 }
4243
4244 return FALSE;
4245 }
4246
4247 /* Return true if operand is something that can be an input for a move
4248 operation. */
4249
4250 int
move_source_operand(rtx op,enum machine_mode mode)4251 move_source_operand (rtx op, enum machine_mode mode)
4252 {
4253 rtx subreg;
4254 enum rtx_code code;
4255
4256 switch (GET_CODE (op))
4257 {
4258 default:
4259 break;
4260
4261 case CONST_INT:
4262 case CONST_DOUBLE:
4263 case SYMBOL_REF:
4264 case LABEL_REF:
4265 case CONST:
4266 return immediate_operand (op, mode);
4267
4268 case SUBREG:
4269 if (GET_MODE (op) != mode && mode != VOIDmode)
4270 return FALSE;
4271
4272 subreg = SUBREG_REG (op);
4273 code = GET_CODE (subreg);
4274 if (code == MEM)
4275 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4276 reload_completed, FALSE);
4277
4278 return (code == REG);
4279
4280 case REG:
4281 if (GET_MODE (op) != mode && mode != VOIDmode)
4282 return FALSE;
4283
4284 return TRUE;
4285
4286 case MEM:
4287 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4288 return TRUE;
4289
4290 return frv_legitimate_memory_operand (op, mode, FALSE);
4291 }
4292
4293 return FALSE;
4294 }
4295
4296 /* Return true if operand is something that can be an output for a conditional
4297 move operation. */
4298
4299 int
condexec_dest_operand(rtx op,enum machine_mode mode)4300 condexec_dest_operand (rtx op, enum machine_mode mode)
4301 {
4302 rtx subreg;
4303 enum rtx_code code;
4304
4305 switch (GET_CODE (op))
4306 {
4307 default:
4308 break;
4309
4310 case SUBREG:
4311 if (GET_MODE (op) != mode && mode != VOIDmode)
4312 return FALSE;
4313
4314 subreg = SUBREG_REG (op);
4315 code = GET_CODE (subreg);
4316 if (code == MEM)
4317 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4318 reload_completed, TRUE);
4319
4320 return (code == REG);
4321
4322 case REG:
4323 if (GET_MODE (op) != mode && mode != VOIDmode)
4324 return FALSE;
4325
4326 return TRUE;
4327
4328 case MEM:
4329 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4330 return TRUE;
4331
4332 return frv_legitimate_memory_operand (op, mode, TRUE);
4333 }
4334
4335 return FALSE;
4336 }
4337
4338 /* Return true if operand is something that can be an input for a conditional
4339 move operation. */
4340
4341 int
condexec_source_operand(rtx op,enum machine_mode mode)4342 condexec_source_operand (rtx op, enum machine_mode mode)
4343 {
4344 rtx subreg;
4345 enum rtx_code code;
4346
4347 switch (GET_CODE (op))
4348 {
4349 default:
4350 break;
4351
4352 case CONST_INT:
4353 case CONST_DOUBLE:
4354 return ZERO_P (op);
4355
4356 case SUBREG:
4357 if (GET_MODE (op) != mode && mode != VOIDmode)
4358 return FALSE;
4359
4360 subreg = SUBREG_REG (op);
4361 code = GET_CODE (subreg);
4362 if (code == MEM)
4363 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4364 reload_completed, TRUE);
4365
4366 return (code == REG);
4367
4368 case REG:
4369 if (GET_MODE (op) != mode && mode != VOIDmode)
4370 return FALSE;
4371
4372 return TRUE;
4373
4374 case MEM:
4375 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4376 return TRUE;
4377
4378 return frv_legitimate_memory_operand (op, mode, TRUE);
4379 }
4380
4381 return FALSE;
4382 }
4383
4384 /* Return true if operand is a register of any flavor or a 0 of the
4385 appropriate type. */
4386
4387 int
reg_or_0_operand(rtx op,enum machine_mode mode)4388 reg_or_0_operand (rtx op, enum machine_mode mode)
4389 {
4390 switch (GET_CODE (op))
4391 {
4392 default:
4393 break;
4394
4395 case REG:
4396 case SUBREG:
4397 if (GET_MODE (op) != mode && mode != VOIDmode)
4398 return FALSE;
4399
4400 return register_operand (op, mode);
4401
4402 case CONST_INT:
4403 case CONST_DOUBLE:
4404 return ZERO_P (op);
4405 }
4406
4407 return FALSE;
4408 }
4409
4410 /* Return true if operand is the link register. */
4411
4412 int
lr_operand(rtx op,enum machine_mode mode)4413 lr_operand (rtx op, enum machine_mode mode)
4414 {
4415 if (GET_CODE (op) != REG)
4416 return FALSE;
4417
4418 if (GET_MODE (op) != mode && mode != VOIDmode)
4419 return FALSE;
4420
4421 if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4422 return FALSE;
4423
4424 return TRUE;
4425 }
4426
4427 /* Return true if operand is a gpr register or a valid memory operation. */
4428
4429 int
gpr_or_memory_operand(rtx op,enum machine_mode mode)4430 gpr_or_memory_operand (rtx op, enum machine_mode mode)
4431 {
4432 return (integer_register_operand (op, mode)
4433 || frv_legitimate_memory_operand (op, mode, FALSE));
4434 }
4435
4436 /* Return true if operand is a fpr register or a valid memory operation. */
4437
4438 int
fpr_or_memory_operand(rtx op,enum machine_mode mode)4439 fpr_or_memory_operand (rtx op, enum machine_mode mode)
4440 {
4441 return (fpr_operand (op, mode)
4442 || frv_legitimate_memory_operand (op, mode, FALSE));
4443 }
4444
4445 /* Return true if operand is an icc register. */
4446
4447 int
icc_operand(rtx op,enum machine_mode mode)4448 icc_operand (rtx op, enum machine_mode mode)
4449 {
4450 int regno;
4451
4452 if (GET_MODE (op) != mode && mode != VOIDmode)
4453 return FALSE;
4454
4455 if (GET_CODE (op) != REG)
4456 return FALSE;
4457
4458 regno = REGNO (op);
4459 return ICC_OR_PSEUDO_P (regno);
4460 }
4461
4462 /* Return true if operand is an fcc register. */
4463
4464 int
fcc_operand(rtx op,enum machine_mode mode)4465 fcc_operand (rtx op, enum machine_mode mode)
4466 {
4467 int regno;
4468
4469 if (GET_MODE (op) != mode && mode != VOIDmode)
4470 return FALSE;
4471
4472 if (GET_CODE (op) != REG)
4473 return FALSE;
4474
4475 regno = REGNO (op);
4476 return FCC_OR_PSEUDO_P (regno);
4477 }
4478
4479 /* Return true if operand is either an fcc or icc register. */
4480
4481 int
cc_operand(rtx op,enum machine_mode mode)4482 cc_operand (rtx op, enum machine_mode mode)
4483 {
4484 int regno;
4485
4486 if (GET_MODE (op) != mode && mode != VOIDmode)
4487 return FALSE;
4488
4489 if (GET_CODE (op) != REG)
4490 return FALSE;
4491
4492 regno = REGNO (op);
4493 if (CC_OR_PSEUDO_P (regno))
4494 return TRUE;
4495
4496 return FALSE;
4497 }
4498
4499 /* Return true if operand is an integer CCR register. */
4500
4501 int
icr_operand(rtx op,enum machine_mode mode)4502 icr_operand (rtx op, enum machine_mode mode)
4503 {
4504 int regno;
4505
4506 if (GET_MODE (op) != mode && mode != VOIDmode)
4507 return FALSE;
4508
4509 if (GET_CODE (op) != REG)
4510 return FALSE;
4511
4512 regno = REGNO (op);
4513 return ICR_OR_PSEUDO_P (regno);
4514 }
4515
4516 /* Return true if operand is an fcc register. */
4517
4518 int
fcr_operand(rtx op,enum machine_mode mode)4519 fcr_operand (rtx op, enum machine_mode mode)
4520 {
4521 int regno;
4522
4523 if (GET_MODE (op) != mode && mode != VOIDmode)
4524 return FALSE;
4525
4526 if (GET_CODE (op) != REG)
4527 return FALSE;
4528
4529 regno = REGNO (op);
4530 return FCR_OR_PSEUDO_P (regno);
4531 }
4532
4533 /* Return true if operand is either an fcc or icc register. */
4534
4535 int
cr_operand(rtx op,enum machine_mode mode)4536 cr_operand (rtx op, enum machine_mode mode)
4537 {
4538 int regno;
4539
4540 if (GET_MODE (op) != mode && mode != VOIDmode)
4541 return FALSE;
4542
4543 if (GET_CODE (op) != REG)
4544 return FALSE;
4545
4546 regno = REGNO (op);
4547 if (CR_OR_PSEUDO_P (regno))
4548 return TRUE;
4549
4550 return FALSE;
4551 }
4552
4553 /* Return true if operand is a memory reference suitable for a call. */
4554
4555 int
call_operand(rtx op,enum machine_mode mode)4556 call_operand (rtx op, enum machine_mode mode)
4557 {
4558 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4559 return FALSE;
4560
4561 if (GET_CODE (op) == SYMBOL_REF)
4562 return TRUE;
4563
4564 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4565 never occur anyway), but prevents reload from not handling the case
4566 properly of a call through a pointer on a function that calls
4567 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4568 return gpr_or_int12_operand (op, mode);
4569 }
4570
4571 /* Return true if operator is a kind of relational operator. */
4572
4573 int
relational_operator(rtx op,enum machine_mode mode)4574 relational_operator (rtx op, enum machine_mode mode)
4575 {
4576 rtx op0;
4577 rtx op1;
4578 int regno;
4579
4580 if (mode != VOIDmode && mode != GET_MODE (op))
4581 return FALSE;
4582
4583 switch (GET_CODE (op))
4584 {
4585 default:
4586 return FALSE;
4587
4588 case EQ:
4589 case NE:
4590 case LE:
4591 case LT:
4592 case GE:
4593 case GT:
4594 case LEU:
4595 case LTU:
4596 case GEU:
4597 case GTU:
4598 break;
4599 }
4600
4601 op1 = XEXP (op, 1);
4602 if (op1 != const0_rtx)
4603 return FALSE;
4604
4605 op0 = XEXP (op, 0);
4606 if (GET_CODE (op0) != REG)
4607 return FALSE;
4608
4609 regno = REGNO (op0);
4610 switch (GET_MODE (op0))
4611 {
4612 default:
4613 break;
4614
4615 case CCmode:
4616 case CC_UNSmode:
4617 return ICC_OR_PSEUDO_P (regno);
4618
4619 case CC_FPmode:
4620 return FCC_OR_PSEUDO_P (regno);
4621
4622 case CC_CCRmode:
4623 return CR_OR_PSEUDO_P (regno);
4624 }
4625
4626 return FALSE;
4627 }
4628
4629 /* Return true if operator is a signed integer relational operator. */
4630
4631 int
signed_relational_operator(rtx op,enum machine_mode mode)4632 signed_relational_operator (rtx op, enum machine_mode mode)
4633 {
4634 rtx op0;
4635 rtx op1;
4636 int regno;
4637
4638 if (mode != VOIDmode && mode != GET_MODE (op))
4639 return FALSE;
4640
4641 switch (GET_CODE (op))
4642 {
4643 default:
4644 return FALSE;
4645
4646 case EQ:
4647 case NE:
4648 case LE:
4649 case LT:
4650 case GE:
4651 case GT:
4652 break;
4653 }
4654
4655 op1 = XEXP (op, 1);
4656 if (op1 != const0_rtx)
4657 return FALSE;
4658
4659 op0 = XEXP (op, 0);
4660 if (GET_CODE (op0) != REG)
4661 return FALSE;
4662
4663 regno = REGNO (op0);
4664 if (GET_MODE (op0) == CCmode && ICC_OR_PSEUDO_P (regno))
4665 return TRUE;
4666
4667 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4668 return TRUE;
4669
4670 return FALSE;
4671 }
4672
4673 /* Return true if operator is a signed integer relational operator. */
4674
4675 int
unsigned_relational_operator(rtx op,enum machine_mode mode)4676 unsigned_relational_operator (rtx op, enum machine_mode mode)
4677 {
4678 rtx op0;
4679 rtx op1;
4680 int regno;
4681
4682 if (mode != VOIDmode && mode != GET_MODE (op))
4683 return FALSE;
4684
4685 switch (GET_CODE (op))
4686 {
4687 default:
4688 return FALSE;
4689
4690 case LEU:
4691 case LTU:
4692 case GEU:
4693 case GTU:
4694 break;
4695 }
4696
4697 op1 = XEXP (op, 1);
4698 if (op1 != const0_rtx)
4699 return FALSE;
4700
4701 op0 = XEXP (op, 0);
4702 if (GET_CODE (op0) != REG)
4703 return FALSE;
4704
4705 regno = REGNO (op0);
4706 if (GET_MODE (op0) == CC_UNSmode && ICC_OR_PSEUDO_P (regno))
4707 return TRUE;
4708
4709 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4710 return TRUE;
4711
4712 return FALSE;
4713 }
4714
4715 /* Return true if operator is a floating point relational operator. */
4716
4717 int
float_relational_operator(rtx op,enum machine_mode mode)4718 float_relational_operator (rtx op, enum machine_mode mode)
4719 {
4720 rtx op0;
4721 rtx op1;
4722 int regno;
4723
4724 if (mode != VOIDmode && mode != GET_MODE (op))
4725 return FALSE;
4726
4727 switch (GET_CODE (op))
4728 {
4729 default:
4730 return FALSE;
4731
4732 case EQ: case NE:
4733 case LE: case LT:
4734 case GE: case GT:
4735 #if 0
4736 case UEQ: case UNE:
4737 case ULE: case ULT:
4738 case UGE: case UGT:
4739 case ORDERED:
4740 case UNORDERED:
4741 #endif
4742 break;
4743 }
4744
4745 op1 = XEXP (op, 1);
4746 if (op1 != const0_rtx)
4747 return FALSE;
4748
4749 op0 = XEXP (op, 0);
4750 if (GET_CODE (op0) != REG)
4751 return FALSE;
4752
4753 regno = REGNO (op0);
4754 if (GET_MODE (op0) == CC_FPmode && FCC_OR_PSEUDO_P (regno))
4755 return TRUE;
4756
4757 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4758 return TRUE;
4759
4760 return FALSE;
4761 }
4762
4763 /* Return true if operator is EQ/NE of a conditional execution register. */
4764
4765 int
ccr_eqne_operator(rtx op,enum machine_mode mode)4766 ccr_eqne_operator (rtx op, enum machine_mode mode)
4767 {
4768 enum machine_mode op_mode = GET_MODE (op);
4769 rtx op0;
4770 rtx op1;
4771 int regno;
4772
4773 if (mode != VOIDmode && op_mode != mode)
4774 return FALSE;
4775
4776 switch (GET_CODE (op))
4777 {
4778 default:
4779 return FALSE;
4780
4781 case EQ:
4782 case NE:
4783 break;
4784 }
4785
4786 op1 = XEXP (op, 1);
4787 if (op1 != const0_rtx)
4788 return FALSE;
4789
4790 op0 = XEXP (op, 0);
4791 if (GET_CODE (op0) != REG)
4792 return FALSE;
4793
4794 regno = REGNO (op0);
4795 if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4796 return TRUE;
4797
4798 return FALSE;
4799 }
4800
4801 /* Return true if operator is a minimum or maximum operator (both signed and
4802 unsigned). */
4803
4804 int
minmax_operator(rtx op,enum machine_mode mode)4805 minmax_operator (rtx op, enum machine_mode mode)
4806 {
4807 if (mode != VOIDmode && mode != GET_MODE (op))
4808 return FALSE;
4809
4810 switch (GET_CODE (op))
4811 {
4812 default:
4813 return FALSE;
4814
4815 case SMIN:
4816 case SMAX:
4817 case UMIN:
4818 case UMAX:
4819 break;
4820 }
4821
4822 if (! integer_register_operand (XEXP (op, 0), mode))
4823 return FALSE;
4824
4825 if (! gpr_or_int10_operand (XEXP (op, 1), mode))
4826 return FALSE;
4827
4828 return TRUE;
4829 }
4830
4831 /* Return true if operator is an integer binary operator that can executed
4832 conditionally and takes 1 cycle. */
4833
4834 int
condexec_si_binary_operator(rtx op,enum machine_mode mode)4835 condexec_si_binary_operator (rtx op, enum machine_mode mode)
4836 {
4837 enum machine_mode op_mode = GET_MODE (op);
4838
4839 if (mode != VOIDmode && op_mode != mode)
4840 return FALSE;
4841
4842 switch (GET_CODE (op))
4843 {
4844 default:
4845 return FALSE;
4846
4847 case PLUS:
4848 case MINUS:
4849 case AND:
4850 case IOR:
4851 case XOR:
4852 case ASHIFT:
4853 case ASHIFTRT:
4854 case LSHIFTRT:
4855 return TRUE;
4856 }
4857 }
4858
4859 /* Return true if operator is an integer binary operator that can be
4860 executed conditionally by a media instruction. */
4861
4862 int
condexec_si_media_operator(rtx op,enum machine_mode mode)4863 condexec_si_media_operator (rtx op, enum machine_mode mode)
4864 {
4865 enum machine_mode op_mode = GET_MODE (op);
4866
4867 if (mode != VOIDmode && op_mode != mode)
4868 return FALSE;
4869
4870 switch (GET_CODE (op))
4871 {
4872 default:
4873 return FALSE;
4874
4875 case AND:
4876 case IOR:
4877 case XOR:
4878 return TRUE;
4879 }
4880 }
4881
4882 /* Return true if operator is an integer division operator that can executed
4883 conditionally. */
4884
4885 int
condexec_si_divide_operator(rtx op,enum machine_mode mode)4886 condexec_si_divide_operator (rtx op, enum machine_mode mode)
4887 {
4888 enum machine_mode op_mode = GET_MODE (op);
4889
4890 if (mode != VOIDmode && op_mode != mode)
4891 return FALSE;
4892
4893 switch (GET_CODE (op))
4894 {
4895 default:
4896 return FALSE;
4897
4898 case DIV:
4899 case UDIV:
4900 return TRUE;
4901 }
4902 }
4903
4904 /* Return true if operator is an integer unary operator that can executed
4905 conditionally. */
4906
4907 int
condexec_si_unary_operator(rtx op,enum machine_mode mode)4908 condexec_si_unary_operator (rtx op, enum machine_mode mode)
4909 {
4910 enum machine_mode op_mode = GET_MODE (op);
4911
4912 if (mode != VOIDmode && op_mode != mode)
4913 return FALSE;
4914
4915 switch (GET_CODE (op))
4916 {
4917 default:
4918 return FALSE;
4919
4920 case NEG:
4921 case NOT:
4922 return TRUE;
4923 }
4924 }
4925
4926 /* Return true if operator is a conversion-type expression that can be
4927 evaluated conditionally by floating-point instructions. */
4928
4929 int
condexec_sf_conv_operator(rtx op,enum machine_mode mode)4930 condexec_sf_conv_operator (rtx op, enum machine_mode mode)
4931 {
4932 enum machine_mode op_mode = GET_MODE (op);
4933
4934 if (mode != VOIDmode && op_mode != mode)
4935 return FALSE;
4936
4937 switch (GET_CODE (op))
4938 {
4939 default:
4940 return FALSE;
4941
4942 case NEG:
4943 case ABS:
4944 return TRUE;
4945 }
4946 }
4947
4948 /* Return true if operator is an addition or subtraction expression.
4949 Such expressions can be evaluated conditionally by floating-point
4950 instructions. */
4951
4952 int
condexec_sf_add_operator(rtx op,enum machine_mode mode)4953 condexec_sf_add_operator (rtx op, enum machine_mode mode)
4954 {
4955 enum machine_mode op_mode = GET_MODE (op);
4956
4957 if (mode != VOIDmode && op_mode != mode)
4958 return FALSE;
4959
4960 switch (GET_CODE (op))
4961 {
4962 default:
4963 return FALSE;
4964
4965 case PLUS:
4966 case MINUS:
4967 return TRUE;
4968 }
4969 }
4970
4971 /* Return true if the memory operand is one that can be conditionally
4972 executed. */
4973
4974 int
condexec_memory_operand(rtx op,enum machine_mode mode)4975 condexec_memory_operand (rtx op, enum machine_mode mode)
4976 {
4977 enum machine_mode op_mode = GET_MODE (op);
4978 rtx addr;
4979
4980 if (mode != VOIDmode && op_mode != mode)
4981 return FALSE;
4982
4983 switch (op_mode)
4984 {
4985 default:
4986 return FALSE;
4987
4988 case QImode:
4989 case HImode:
4990 case SImode:
4991 case SFmode:
4992 break;
4993 }
4994
4995 if (GET_CODE (op) != MEM)
4996 return FALSE;
4997
4998 addr = XEXP (op, 0);
4999 if (GET_CODE (addr) == ADDRESSOF)
5000 return TRUE;
5001
5002 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE);
5003 }
5004
5005 /* Return true if operator is an integer binary operator that can be combined
5006 with a setcc operation. Do not allow the arithmetic operations that could
5007 potentially overflow since the FR-V sets the condition code based on the
5008 "true" value of the result, not the result after truncating to a 32-bit
5009 register. */
5010
5011 int
intop_compare_operator(rtx op,enum machine_mode mode)5012 intop_compare_operator (rtx op, enum machine_mode mode)
5013 {
5014 enum machine_mode op_mode = GET_MODE (op);
5015
5016 if (mode != VOIDmode && op_mode != mode)
5017 return FALSE;
5018
5019 switch (GET_CODE (op))
5020 {
5021 default:
5022 return FALSE;
5023
5024 case AND:
5025 case IOR:
5026 case XOR:
5027 case ASHIFTRT:
5028 case LSHIFTRT:
5029 break;
5030 }
5031
5032 if (! integer_register_operand (XEXP (op, 0), SImode))
5033 return FALSE;
5034
5035 if (! gpr_or_int10_operand (XEXP (op, 1), SImode))
5036 return FALSE;
5037
5038 return TRUE;
5039 }
5040
5041 /* Return true if operator is an integer binary operator that can be combined
5042 with a setcc operation inside of a conditional execution. */
5043
5044 int
condexec_intop_cmp_operator(rtx op,enum machine_mode mode)5045 condexec_intop_cmp_operator (rtx op, enum machine_mode mode)
5046 {
5047 enum machine_mode op_mode = GET_MODE (op);
5048
5049 if (mode != VOIDmode && op_mode != mode)
5050 return FALSE;
5051
5052 switch (GET_CODE (op))
5053 {
5054 default:
5055 return FALSE;
5056
5057 case AND:
5058 case IOR:
5059 case XOR:
5060 case ASHIFTRT:
5061 case LSHIFTRT:
5062 break;
5063 }
5064
5065 if (! integer_register_operand (XEXP (op, 0), SImode))
5066 return FALSE;
5067
5068 if (! integer_register_operand (XEXP (op, 1), SImode))
5069 return FALSE;
5070
5071 return TRUE;
5072 }
5073
5074 /* Return 1 if operand is a valid ACC register number. */
5075
5076 int
acc_operand(rtx op,enum machine_mode mode)5077 acc_operand (rtx op, enum machine_mode mode)
5078 {
5079 int regno;
5080
5081 if (GET_MODE (op) != mode && mode != VOIDmode)
5082 return FALSE;
5083
5084 if (GET_CODE (op) == SUBREG)
5085 {
5086 if (GET_CODE (SUBREG_REG (op)) != REG)
5087 return register_operand (op, mode);
5088
5089 op = SUBREG_REG (op);
5090 }
5091
5092 if (GET_CODE (op) != REG)
5093 return FALSE;
5094
5095 regno = REGNO (op);
5096 return ACC_OR_PSEUDO_P (regno);
5097 }
5098
5099 /* Return 1 if operand is a valid even ACC register number. */
5100
5101 int
even_acc_operand(rtx op,enum machine_mode mode)5102 even_acc_operand (rtx op, enum machine_mode mode)
5103 {
5104 int regno;
5105
5106 if (GET_MODE (op) != mode && mode != VOIDmode)
5107 return FALSE;
5108
5109 if (GET_CODE (op) == SUBREG)
5110 {
5111 if (GET_CODE (SUBREG_REG (op)) != REG)
5112 return register_operand (op, mode);
5113
5114 op = SUBREG_REG (op);
5115 }
5116
5117 if (GET_CODE (op) != REG)
5118 return FALSE;
5119
5120 regno = REGNO (op);
5121 return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 1) == 0);
5122 }
5123
5124 /* Return 1 if operand is zero or four. */
5125
5126 int
quad_acc_operand(rtx op,enum machine_mode mode)5127 quad_acc_operand (rtx op, enum machine_mode mode)
5128 {
5129 int regno;
5130
5131 if (GET_MODE (op) != mode && mode != VOIDmode)
5132 return FALSE;
5133
5134 if (GET_CODE (op) == SUBREG)
5135 {
5136 if (GET_CODE (SUBREG_REG (op)) != REG)
5137 return register_operand (op, mode);
5138
5139 op = SUBREG_REG (op);
5140 }
5141
5142 if (GET_CODE (op) != REG)
5143 return FALSE;
5144
5145 regno = REGNO (op);
5146 return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 3) == 0);
5147 }
5148
5149 /* Return 1 if operand is a valid ACCG register number. */
5150
5151 int
accg_operand(rtx op,enum machine_mode mode)5152 accg_operand (rtx op, enum machine_mode mode)
5153 {
5154 if (GET_MODE (op) != mode && mode != VOIDmode)
5155 return FALSE;
5156
5157 if (GET_CODE (op) == SUBREG)
5158 {
5159 if (GET_CODE (SUBREG_REG (op)) != REG)
5160 return register_operand (op, mode);
5161
5162 op = SUBREG_REG (op);
5163 }
5164
5165 if (GET_CODE (op) != REG)
5166 return FALSE;
5167
5168 return ACCG_OR_PSEUDO_P (REGNO (op));
5169 }
5170
5171
5172 /* Return true if the bare return instruction can be used outside of the
5173 epilog code. For frv, we only do it if there was no stack allocation. */
5174
5175 int
direct_return_p(void)5176 direct_return_p (void)
5177 {
5178 frv_stack_t *info;
5179
5180 if (!reload_completed)
5181 return FALSE;
5182
5183 info = frv_stack_info ();
5184 return (info->total_size == 0);
5185 }
5186
5187
5188 /* Emit code to handle a MOVSI, adding in the small data register or pic
5189 register if needed to load up addresses. Return TRUE if the appropriate
5190 instructions are emitted. */
5191
5192 int
frv_emit_movsi(rtx dest,rtx src)5193 frv_emit_movsi (rtx dest, rtx src)
5194 {
5195 int base_regno = -1;
5196
5197 if (!reload_in_progress
5198 && !reload_completed
5199 && !register_operand (dest, SImode)
5200 && (!reg_or_0_operand (src, SImode)
5201 /* Virtual registers will almost always be replaced by an
5202 add instruction, so expose this to CSE by copying to
5203 an intermediate register. */
5204 || (GET_CODE (src) == REG
5205 && IN_RANGE_P (REGNO (src),
5206 FIRST_VIRTUAL_REGISTER,
5207 LAST_VIRTUAL_REGISTER))))
5208 {
5209 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
5210 return TRUE;
5211 }
5212
5213 /* Explicitly add in the PIC or small data register if needed. */
5214 switch (GET_CODE (src))
5215 {
5216 default:
5217 break;
5218
5219 case LABEL_REF:
5220 if (flag_pic)
5221 base_regno = PIC_REGNO;
5222
5223 break;
5224
5225 case CONST:
5226 if (const_small_data_p (src))
5227 base_regno = SDA_BASE_REG;
5228
5229 else if (flag_pic)
5230 base_regno = PIC_REGNO;
5231
5232 break;
5233
5234 case SYMBOL_REF:
5235 if (SYMBOL_REF_SMALL_P (src))
5236 base_regno = SDA_BASE_REG;
5237
5238 else if (flag_pic)
5239 base_regno = PIC_REGNO;
5240
5241 break;
5242 }
5243
5244 if (base_regno >= 0)
5245 {
5246 emit_insn (gen_rtx_SET (VOIDmode, dest,
5247 gen_rtx_PLUS (Pmode,
5248 gen_rtx_REG (Pmode, base_regno),
5249 src)));
5250
5251 if (base_regno == PIC_REGNO)
5252 cfun->uses_pic_offset_table = TRUE;
5253
5254 return TRUE;
5255 }
5256
5257 return FALSE;
5258 }
5259
5260
5261 /* Return a string to output a single word move. */
5262
5263 const char *
output_move_single(rtx operands[],rtx insn)5264 output_move_single (rtx operands[], rtx insn)
5265 {
5266 rtx dest = operands[0];
5267 rtx src = operands[1];
5268
5269 if (GET_CODE (dest) == REG)
5270 {
5271 int dest_regno = REGNO (dest);
5272 enum machine_mode mode = GET_MODE (dest);
5273
5274 if (GPR_P (dest_regno))
5275 {
5276 if (GET_CODE (src) == REG)
5277 {
5278 /* gpr <- some sort of register */
5279 int src_regno = REGNO (src);
5280
5281 if (GPR_P (src_regno))
5282 return "mov %1, %0";
5283
5284 else if (FPR_P (src_regno))
5285 return "movfg %1, %0";
5286
5287 else if (SPR_P (src_regno))
5288 return "movsg %1, %0";
5289 }
5290
5291 else if (GET_CODE (src) == MEM)
5292 {
5293 /* gpr <- memory */
5294 switch (mode)
5295 {
5296 default:
5297 break;
5298
5299 case QImode:
5300 return "ldsb%I1%U1 %M1,%0";
5301
5302 case HImode:
5303 return "ldsh%I1%U1 %M1,%0";
5304
5305 case SImode:
5306 case SFmode:
5307 return "ld%I1%U1 %M1, %0";
5308 }
5309 }
5310
5311 else if (GET_CODE (src) == CONST_INT
5312 || GET_CODE (src) == CONST_DOUBLE)
5313 {
5314 /* gpr <- integer/floating constant */
5315 HOST_WIDE_INT value;
5316
5317 if (GET_CODE (src) == CONST_INT)
5318 value = INTVAL (src);
5319
5320 else if (mode == SFmode)
5321 {
5322 REAL_VALUE_TYPE rv;
5323 long l;
5324
5325 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
5326 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5327 value = l;
5328 }
5329
5330 else
5331 value = CONST_DOUBLE_LOW (src);
5332
5333 if (IN_RANGE_P (value, -32768, 32767))
5334 return "setlos %1, %0";
5335
5336 return "#";
5337 }
5338
5339 else if (GET_CODE (src) == SYMBOL_REF
5340 || GET_CODE (src) == LABEL_REF
5341 || GET_CODE (src) == CONST)
5342 {
5343 /* Silently fix up instances where the small data pointer is not
5344 used in the address. */
5345 if (small_data_symbolic_operand (src, GET_MODE (src)))
5346 return "addi %@, #gprel12(%1), %0";
5347
5348 return "#";
5349 }
5350 }
5351
5352 else if (FPR_P (dest_regno))
5353 {
5354 if (GET_CODE (src) == REG)
5355 {
5356 /* fpr <- some sort of register */
5357 int src_regno = REGNO (src);
5358
5359 if (GPR_P (src_regno))
5360 return "movgf %1, %0";
5361
5362 else if (FPR_P (src_regno))
5363 {
5364 if (TARGET_HARD_FLOAT)
5365 return "fmovs %1, %0";
5366 else
5367 return "mor %1, %1, %0";
5368 }
5369 }
5370
5371 else if (GET_CODE (src) == MEM)
5372 {
5373 /* fpr <- memory */
5374 switch (mode)
5375 {
5376 default:
5377 break;
5378
5379 case QImode:
5380 return "ldbf%I1%U1 %M1,%0";
5381
5382 case HImode:
5383 return "ldhf%I1%U1 %M1,%0";
5384
5385 case SImode:
5386 case SFmode:
5387 return "ldf%I1%U1 %M1, %0";
5388 }
5389 }
5390
5391 else if (ZERO_P (src))
5392 return "movgf %., %0";
5393 }
5394
5395 else if (SPR_P (dest_regno))
5396 {
5397 if (GET_CODE (src) == REG)
5398 {
5399 /* spr <- some sort of register */
5400 int src_regno = REGNO (src);
5401
5402 if (GPR_P (src_regno))
5403 return "movgs %1, %0";
5404 }
5405 }
5406 }
5407
5408 else if (GET_CODE (dest) == MEM)
5409 {
5410 if (GET_CODE (src) == REG)
5411 {
5412 int src_regno = REGNO (src);
5413 enum machine_mode mode = GET_MODE (dest);
5414
5415 if (GPR_P (src_regno))
5416 {
5417 switch (mode)
5418 {
5419 default:
5420 break;
5421
5422 case QImode:
5423 return "stb%I0%U0 %1, %M0";
5424
5425 case HImode:
5426 return "sth%I0%U0 %1, %M0";
5427
5428 case SImode:
5429 case SFmode:
5430 return "st%I0%U0 %1, %M0";
5431 }
5432 }
5433
5434 else if (FPR_P (src_regno))
5435 {
5436 switch (mode)
5437 {
5438 default:
5439 break;
5440
5441 case QImode:
5442 return "stbf%I0%U0 %1, %M0";
5443
5444 case HImode:
5445 return "sthf%I0%U0 %1, %M0";
5446
5447 case SImode:
5448 case SFmode:
5449 return "stf%I0%U0 %1, %M0";
5450 }
5451 }
5452 }
5453
5454 else if (ZERO_P (src))
5455 {
5456 switch (GET_MODE (dest))
5457 {
5458 default:
5459 break;
5460
5461 case QImode:
5462 return "stb%I0%U0 %., %M0";
5463
5464 case HImode:
5465 return "sth%I0%U0 %., %M0";
5466
5467 case SImode:
5468 case SFmode:
5469 return "st%I0%U0 %., %M0";
5470 }
5471 }
5472 }
5473
5474 fatal_insn ("Bad output_move_single operand", insn);
5475 return "";
5476 }
5477
5478
5479 /* Return a string to output a double word move. */
5480
5481 const char *
output_move_double(rtx operands[],rtx insn)5482 output_move_double (rtx operands[], rtx insn)
5483 {
5484 rtx dest = operands[0];
5485 rtx src = operands[1];
5486 enum machine_mode mode = GET_MODE (dest);
5487
5488 if (GET_CODE (dest) == REG)
5489 {
5490 int dest_regno = REGNO (dest);
5491
5492 if (GPR_P (dest_regno))
5493 {
5494 if (GET_CODE (src) == REG)
5495 {
5496 /* gpr <- some sort of register */
5497 int src_regno = REGNO (src);
5498
5499 if (GPR_P (src_regno))
5500 return "#";
5501
5502 else if (FPR_P (src_regno))
5503 {
5504 if (((dest_regno - GPR_FIRST) & 1) == 0
5505 && ((src_regno - FPR_FIRST) & 1) == 0)
5506 return "movfgd %1, %0";
5507
5508 return "#";
5509 }
5510 }
5511
5512 else if (GET_CODE (src) == MEM)
5513 {
5514 /* gpr <- memory */
5515 if (dbl_memory_one_insn_operand (src, mode))
5516 return "ldd%I1%U1 %M1, %0";
5517
5518 return "#";
5519 }
5520
5521 else if (GET_CODE (src) == CONST_INT
5522 || GET_CODE (src) == CONST_DOUBLE)
5523 return "#";
5524 }
5525
5526 else if (FPR_P (dest_regno))
5527 {
5528 if (GET_CODE (src) == REG)
5529 {
5530 /* fpr <- some sort of register */
5531 int src_regno = REGNO (src);
5532
5533 if (GPR_P (src_regno))
5534 {
5535 if (((dest_regno - FPR_FIRST) & 1) == 0
5536 && ((src_regno - GPR_FIRST) & 1) == 0)
5537 return "movgfd %1, %0";
5538
5539 return "#";
5540 }
5541
5542 else if (FPR_P (src_regno))
5543 {
5544 if (TARGET_DOUBLE
5545 && ((dest_regno - FPR_FIRST) & 1) == 0
5546 && ((src_regno - FPR_FIRST) & 1) == 0)
5547 return "fmovd %1, %0";
5548
5549 return "#";
5550 }
5551 }
5552
5553 else if (GET_CODE (src) == MEM)
5554 {
5555 /* fpr <- memory */
5556 if (dbl_memory_one_insn_operand (src, mode))
5557 return "lddf%I1%U1 %M1, %0";
5558
5559 return "#";
5560 }
5561
5562 else if (ZERO_P (src))
5563 return "#";
5564 }
5565 }
5566
5567 else if (GET_CODE (dest) == MEM)
5568 {
5569 if (GET_CODE (src) == REG)
5570 {
5571 int src_regno = REGNO (src);
5572
5573 if (GPR_P (src_regno))
5574 {
5575 if (((src_regno - GPR_FIRST) & 1) == 0
5576 && dbl_memory_one_insn_operand (dest, mode))
5577 return "std%I0%U0 %1, %M0";
5578
5579 return "#";
5580 }
5581
5582 if (FPR_P (src_regno))
5583 {
5584 if (((src_regno - FPR_FIRST) & 1) == 0
5585 && dbl_memory_one_insn_operand (dest, mode))
5586 return "stdf%I0%U0 %1, %M0";
5587
5588 return "#";
5589 }
5590 }
5591
5592 else if (ZERO_P (src))
5593 {
5594 if (dbl_memory_one_insn_operand (dest, mode))
5595 return "std%I0%U0 %., %M0";
5596
5597 return "#";
5598 }
5599 }
5600
5601 fatal_insn ("Bad output_move_double operand", insn);
5602 return "";
5603 }
5604
5605
5606 /* Return a string to output a single word conditional move.
5607 Operand0 -- EQ/NE of ccr register and 0
5608 Operand1 -- CCR register
5609 Operand2 -- destination
5610 Operand3 -- source */
5611
5612 const char *
output_condmove_single(rtx operands[],rtx insn)5613 output_condmove_single (rtx operands[], rtx insn)
5614 {
5615 rtx dest = operands[2];
5616 rtx src = operands[3];
5617
5618 if (GET_CODE (dest) == REG)
5619 {
5620 int dest_regno = REGNO (dest);
5621 enum machine_mode mode = GET_MODE (dest);
5622
5623 if (GPR_P (dest_regno))
5624 {
5625 if (GET_CODE (src) == REG)
5626 {
5627 /* gpr <- some sort of register */
5628 int src_regno = REGNO (src);
5629
5630 if (GPR_P (src_regno))
5631 return "cmov %z3, %2, %1, %e0";
5632
5633 else if (FPR_P (src_regno))
5634 return "cmovfg %3, %2, %1, %e0";
5635 }
5636
5637 else if (GET_CODE (src) == MEM)
5638 {
5639 /* gpr <- memory */
5640 switch (mode)
5641 {
5642 default:
5643 break;
5644
5645 case QImode:
5646 return "cldsb%I3%U3 %M3, %2, %1, %e0";
5647
5648 case HImode:
5649 return "cldsh%I3%U3 %M3, %2, %1, %e0";
5650
5651 case SImode:
5652 case SFmode:
5653 return "cld%I3%U3 %M3, %2, %1, %e0";
5654 }
5655 }
5656
5657 else if (ZERO_P (src))
5658 return "cmov %., %2, %1, %e0";
5659 }
5660
5661 else if (FPR_P (dest_regno))
5662 {
5663 if (GET_CODE (src) == REG)
5664 {
5665 /* fpr <- some sort of register */
5666 int src_regno = REGNO (src);
5667
5668 if (GPR_P (src_regno))
5669 return "cmovgf %3, %2, %1, %e0";
5670
5671 else if (FPR_P (src_regno))
5672 {
5673 if (TARGET_HARD_FLOAT)
5674 return "cfmovs %3,%2,%1,%e0";
5675 else
5676 return "cmor %3, %3, %2, %1, %e0";
5677 }
5678 }
5679
5680 else if (GET_CODE (src) == MEM)
5681 {
5682 /* fpr <- memory */
5683 if (mode == SImode || mode == SFmode)
5684 return "cldf%I3%U3 %M3, %2, %1, %e0";
5685 }
5686
5687 else if (ZERO_P (src))
5688 return "cmovgf %., %2, %1, %e0";
5689 }
5690 }
5691
5692 else if (GET_CODE (dest) == MEM)
5693 {
5694 if (GET_CODE (src) == REG)
5695 {
5696 int src_regno = REGNO (src);
5697 enum machine_mode mode = GET_MODE (dest);
5698
5699 if (GPR_P (src_regno))
5700 {
5701 switch (mode)
5702 {
5703 default:
5704 break;
5705
5706 case QImode:
5707 return "cstb%I2%U2 %3, %M2, %1, %e0";
5708
5709 case HImode:
5710 return "csth%I2%U2 %3, %M2, %1, %e0";
5711
5712 case SImode:
5713 case SFmode:
5714 return "cst%I2%U2 %3, %M2, %1, %e0";
5715 }
5716 }
5717
5718 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
5719 return "cstf%I2%U2 %3, %M2, %1, %e0";
5720 }
5721
5722 else if (ZERO_P (src))
5723 {
5724 enum machine_mode mode = GET_MODE (dest);
5725 switch (mode)
5726 {
5727 default:
5728 break;
5729
5730 case QImode:
5731 return "cstb%I2%U2 %., %M2, %1, %e0";
5732
5733 case HImode:
5734 return "csth%I2%U2 %., %M2, %1, %e0";
5735
5736 case SImode:
5737 case SFmode:
5738 return "cst%I2%U2 %., %M2, %1, %e0";
5739 }
5740 }
5741 }
5742
5743 fatal_insn ("Bad output_condmove_single operand", insn);
5744 return "";
5745 }
5746
5747
5748 /* Emit the appropriate code to do a comparison, returning the register the
5749 comparison was done it. */
5750
5751 static rtx
frv_emit_comparison(enum rtx_code test,rtx op0,rtx op1)5752 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
5753 {
5754 enum machine_mode cc_mode;
5755 rtx cc_reg;
5756
5757 /* Floating point doesn't have comparison against a constant. */
5758 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
5759 op1 = force_reg (GET_MODE (op0), op1);
5760
5761 /* Possibly disable using anything but a fixed register in order to work
5762 around cse moving comparisons past function calls. */
5763 cc_mode = SELECT_CC_MODE (test, op0, op1);
5764 cc_reg = ((TARGET_ALLOC_CC)
5765 ? gen_reg_rtx (cc_mode)
5766 : gen_rtx_REG (cc_mode,
5767 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
5768
5769 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
5770 gen_rtx_COMPARE (cc_mode, op0, op1)));
5771
5772 return cc_reg;
5773 }
5774
5775
5776 /* Emit code for a conditional branch. The comparison operands were previously
5777 stored in frv_compare_op0 and frv_compare_op1.
5778
5779 XXX: I originally wanted to add a clobber of a CCR register to use in
5780 conditional execution, but that confuses the rest of the compiler. */
5781
5782 int
frv_emit_cond_branch(enum rtx_code test,rtx label)5783 frv_emit_cond_branch (enum rtx_code test, rtx label)
5784 {
5785 rtx test_rtx;
5786 rtx label_ref;
5787 rtx if_else;
5788 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
5789 enum machine_mode cc_mode = GET_MODE (cc_reg);
5790
5791 /* Branches generate:
5792 (set (pc)
5793 (if_then_else (<test>, <cc_reg>, (const_int 0))
5794 (label_ref <branch_label>)
5795 (pc))) */
5796 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
5797 test_rtx = gen_rtx (test, cc_mode, cc_reg, const0_rtx);
5798 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
5799 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
5800 return TRUE;
5801 }
5802
5803
5804 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
5805 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
5806
5807 int
frv_emit_scc(enum rtx_code test,rtx target)5808 frv_emit_scc (enum rtx_code test, rtx target)
5809 {
5810 rtx set;
5811 rtx test_rtx;
5812 rtx clobber;
5813 rtx cr_reg;
5814 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
5815
5816 /* SCC instructions generate:
5817 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
5818 (clobber (<ccr_reg>))]) */
5819 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
5820 set = gen_rtx_SET (VOIDmode, target, test_rtx);
5821
5822 cr_reg = ((TARGET_ALLOC_CC)
5823 ? gen_reg_rtx (CC_CCRmode)
5824 : gen_rtx_REG (CC_CCRmode,
5825 ((GET_MODE (cc_reg) == CC_FPmode)
5826 ? FCR_FIRST
5827 : ICR_FIRST)));
5828
5829 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
5830 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
5831 return TRUE;
5832 }
5833
5834
5835 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
5836 the separate insns. */
5837
5838 rtx
frv_split_scc(rtx dest,rtx test,rtx cc_reg,rtx cr_reg,HOST_WIDE_INT value)5839 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
5840 {
5841 rtx ret;
5842
5843 start_sequence ();
5844
5845 /* Set the appropriate CCR bit. */
5846 emit_insn (gen_rtx_SET (VOIDmode,
5847 cr_reg,
5848 gen_rtx_fmt_ee (GET_CODE (test),
5849 GET_MODE (cr_reg),
5850 cc_reg,
5851 const0_rtx)));
5852
5853 /* Move the value into the destination. */
5854 emit_move_insn (dest, GEN_INT (value));
5855
5856 /* Move 0 into the destination if the test failed */
5857 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5858 gen_rtx_EQ (GET_MODE (cr_reg),
5859 cr_reg,
5860 const0_rtx),
5861 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
5862
5863 /* Finish up, return sequence. */
5864 ret = get_insns ();
5865 end_sequence ();
5866 return ret;
5867 }
5868
5869
5870 /* Emit the code for a conditional move, return TRUE if we could do the
5871 move. */
5872
5873 int
frv_emit_cond_move(rtx dest,rtx test_rtx,rtx src1,rtx src2)5874 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
5875 {
5876 rtx set;
5877 rtx clobber_cc;
5878 rtx test2;
5879 rtx cr_reg;
5880 rtx if_rtx;
5881 enum rtx_code test = GET_CODE (test_rtx);
5882 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
5883 enum machine_mode cc_mode = GET_MODE (cc_reg);
5884
5885 /* Conditional move instructions generate:
5886 (parallel [(set <target>
5887 (if_then_else (<test> <cc_reg> (const_int 0))
5888 <src1>
5889 <src2>))
5890 (clobber (<ccr_reg>))]) */
5891
5892 /* Handle various cases of conditional move involving two constants. */
5893 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
5894 {
5895 HOST_WIDE_INT value1 = INTVAL (src1);
5896 HOST_WIDE_INT value2 = INTVAL (src2);
5897
5898 /* Having 0 as one of the constants can be done by loading the other
5899 constant, and optionally moving in gr0. */
5900 if (value1 == 0 || value2 == 0)
5901 ;
5902
5903 /* If the first value is within an addi range and also the difference
5904 between the two fits in an addi's range, load up the difference, then
5905 conditionally move in 0, and then unconditionally add the first
5906 value. */
5907 else if (IN_RANGE_P (value1, -2048, 2047)
5908 && IN_RANGE_P (value2 - value1, -2048, 2047))
5909 ;
5910
5911 /* If neither condition holds, just force the constant into a
5912 register. */
5913 else
5914 {
5915 src1 = force_reg (GET_MODE (dest), src1);
5916 src2 = force_reg (GET_MODE (dest), src2);
5917 }
5918 }
5919
5920 /* If one value is a register, insure the other value is either 0 or a
5921 register. */
5922 else
5923 {
5924 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
5925 src1 = force_reg (GET_MODE (dest), src1);
5926
5927 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5928 src2 = force_reg (GET_MODE (dest), src2);
5929 }
5930
5931 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
5932 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
5933
5934 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
5935
5936 cr_reg = ((TARGET_ALLOC_CC)
5937 ? gen_reg_rtx (CC_CCRmode)
5938 : gen_rtx_REG (CC_CCRmode,
5939 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
5940
5941 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
5942 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
5943 return TRUE;
5944 }
5945
5946
5947 /* Split a conditional move into constituent parts, returning a SEQUENCE
5948 containing all of the insns. */
5949
5950 rtx
frv_split_cond_move(rtx operands[])5951 frv_split_cond_move (rtx operands[])
5952 {
5953 rtx dest = operands[0];
5954 rtx test = operands[1];
5955 rtx cc_reg = operands[2];
5956 rtx src1 = operands[3];
5957 rtx src2 = operands[4];
5958 rtx cr_reg = operands[5];
5959 rtx ret;
5960 enum machine_mode cr_mode = GET_MODE (cr_reg);
5961
5962 start_sequence ();
5963
5964 /* Set the appropriate CCR bit. */
5965 emit_insn (gen_rtx_SET (VOIDmode,
5966 cr_reg,
5967 gen_rtx_fmt_ee (GET_CODE (test),
5968 GET_MODE (cr_reg),
5969 cc_reg,
5970 const0_rtx)));
5971
5972 /* Handle various cases of conditional move involving two constants. */
5973 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
5974 {
5975 HOST_WIDE_INT value1 = INTVAL (src1);
5976 HOST_WIDE_INT value2 = INTVAL (src2);
5977
5978 /* Having 0 as one of the constants can be done by loading the other
5979 constant, and optionally moving in gr0. */
5980 if (value1 == 0)
5981 {
5982 emit_move_insn (dest, src2);
5983 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5984 gen_rtx_NE (cr_mode, cr_reg,
5985 const0_rtx),
5986 gen_rtx_SET (VOIDmode, dest, src1)));
5987 }
5988
5989 else if (value2 == 0)
5990 {
5991 emit_move_insn (dest, src1);
5992 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5993 gen_rtx_EQ (cr_mode, cr_reg,
5994 const0_rtx),
5995 gen_rtx_SET (VOIDmode, dest, src2)));
5996 }
5997
5998 /* If the first value is within an addi range and also the difference
5999 between the two fits in an addi's range, load up the difference, then
6000 conditionally move in 0, and then unconditionally add the first
6001 value. */
6002 else if (IN_RANGE_P (value1, -2048, 2047)
6003 && IN_RANGE_P (value2 - value1, -2048, 2047))
6004 {
6005 rtx dest_si = ((GET_MODE (dest) == SImode)
6006 ? dest
6007 : gen_rtx_SUBREG (SImode, dest, 0));
6008
6009 emit_move_insn (dest_si, GEN_INT (value2 - value1));
6010 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6011 gen_rtx_NE (cr_mode, cr_reg,
6012 const0_rtx),
6013 gen_rtx_SET (VOIDmode, dest_si,
6014 const0_rtx)));
6015 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
6016 }
6017
6018 else
6019 abort ();
6020 }
6021 else
6022 {
6023 /* Emit the conditional move for the test being true if needed. */
6024 if (! rtx_equal_p (dest, src1))
6025 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6026 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6027 gen_rtx_SET (VOIDmode, dest, src1)));
6028
6029 /* Emit the conditional move for the test being false if needed. */
6030 if (! rtx_equal_p (dest, src2))
6031 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6032 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6033 gen_rtx_SET (VOIDmode, dest, src2)));
6034 }
6035
6036 /* Finish up, return sequence. */
6037 ret = get_insns ();
6038 end_sequence ();
6039 return ret;
6040 }
6041
6042
6043 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6044 memory location that is not known to be dword-aligned. */
6045 void
frv_split_double_load(rtx dest,rtx source)6046 frv_split_double_load (rtx dest, rtx source)
6047 {
6048 int regno = REGNO (dest);
6049 rtx dest1 = gen_highpart (SImode, dest);
6050 rtx dest2 = gen_lowpart (SImode, dest);
6051 rtx address = XEXP (source, 0);
6052
6053 /* If the address is pre-modified, load the lower-numbered register
6054 first, then load the other register using an integer offset from
6055 the modified base register. This order should always be safe,
6056 since the pre-modification cannot affect the same registers as the
6057 load does.
6058
6059 The situation for other loads is more complicated. Loading one
6060 of the registers could affect the value of ADDRESS, so we must
6061 be careful which order we do them in. */
6062 if (GET_CODE (address) == PRE_MODIFY
6063 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
6064 {
6065 /* It is safe to load the lower-numbered register first. */
6066 emit_move_insn (dest1, change_address (source, SImode, NULL));
6067 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6068 }
6069 else
6070 {
6071 /* ADDRESS is not pre-modified and the address depends on the
6072 lower-numbered register. Load the higher-numbered register
6073 first. */
6074 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6075 emit_move_insn (dest1, change_address (source, SImode, NULL));
6076 }
6077 }
6078
6079 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6080 and SOURCE is either a double register or the constant zero. */
6081 void
frv_split_double_store(rtx dest,rtx source)6082 frv_split_double_store (rtx dest, rtx source)
6083 {
6084 rtx dest1 = change_address (dest, SImode, NULL);
6085 rtx dest2 = frv_index_memory (dest, SImode, 1);
6086 if (ZERO_P (source))
6087 {
6088 emit_move_insn (dest1, CONST0_RTX (SImode));
6089 emit_move_insn (dest2, CONST0_RTX (SImode));
6090 }
6091 else
6092 {
6093 emit_move_insn (dest1, gen_highpart (SImode, source));
6094 emit_move_insn (dest2, gen_lowpart (SImode, source));
6095 }
6096 }
6097
6098
6099 /* Split a min/max operation returning a SEQUENCE containing all of the
6100 insns. */
6101
6102 rtx
frv_split_minmax(rtx operands[])6103 frv_split_minmax (rtx operands[])
6104 {
6105 rtx dest = operands[0];
6106 rtx minmax = operands[1];
6107 rtx src1 = operands[2];
6108 rtx src2 = operands[3];
6109 rtx cc_reg = operands[4];
6110 rtx cr_reg = operands[5];
6111 rtx ret;
6112 enum rtx_code test_code;
6113 enum machine_mode cr_mode = GET_MODE (cr_reg);
6114
6115 start_sequence ();
6116
6117 /* Figure out which test to use. */
6118 switch (GET_CODE (minmax))
6119 {
6120 default:
6121 abort ();
6122
6123 case SMIN: test_code = LT; break;
6124 case SMAX: test_code = GT; break;
6125 case UMIN: test_code = LTU; break;
6126 case UMAX: test_code = GTU; break;
6127 }
6128
6129 /* Issue the compare instruction. */
6130 emit_insn (gen_rtx_SET (VOIDmode,
6131 cc_reg,
6132 gen_rtx_COMPARE (GET_MODE (cc_reg),
6133 src1, src2)));
6134
6135 /* Set the appropriate CCR bit. */
6136 emit_insn (gen_rtx_SET (VOIDmode,
6137 cr_reg,
6138 gen_rtx_fmt_ee (test_code,
6139 GET_MODE (cr_reg),
6140 cc_reg,
6141 const0_rtx)));
6142
6143 /* If are taking the min/max of a nonzero constant, load that first, and
6144 then do a conditional move of the other value. */
6145 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6146 {
6147 if (rtx_equal_p (dest, src1))
6148 abort ();
6149
6150 emit_move_insn (dest, src2);
6151 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6152 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6153 gen_rtx_SET (VOIDmode, dest, src1)));
6154 }
6155
6156 /* Otherwise, do each half of the move. */
6157 else
6158 {
6159 /* Emit the conditional move for the test being true if needed. */
6160 if (! rtx_equal_p (dest, src1))
6161 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6162 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6163 gen_rtx_SET (VOIDmode, dest, src1)));
6164
6165 /* Emit the conditional move for the test being false if needed. */
6166 if (! rtx_equal_p (dest, src2))
6167 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6168 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6169 gen_rtx_SET (VOIDmode, dest, src2)));
6170 }
6171
6172 /* Finish up, return sequence. */
6173 ret = get_insns ();
6174 end_sequence ();
6175 return ret;
6176 }
6177
6178
6179 /* Split an integer abs operation returning a SEQUENCE containing all of the
6180 insns. */
6181
6182 rtx
frv_split_abs(rtx operands[])6183 frv_split_abs (rtx operands[])
6184 {
6185 rtx dest = operands[0];
6186 rtx src = operands[1];
6187 rtx cc_reg = operands[2];
6188 rtx cr_reg = operands[3];
6189 rtx ret;
6190
6191 start_sequence ();
6192
6193 /* Issue the compare < 0 instruction. */
6194 emit_insn (gen_rtx_SET (VOIDmode,
6195 cc_reg,
6196 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
6197
6198 /* Set the appropriate CCR bit. */
6199 emit_insn (gen_rtx_SET (VOIDmode,
6200 cr_reg,
6201 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
6202
6203 /* Emit the conditional negate if the value is negative. */
6204 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6205 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
6206 gen_negsi2 (dest, src)));
6207
6208 /* Emit the conditional move for the test being false if needed. */
6209 if (! rtx_equal_p (dest, src))
6210 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6211 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
6212 gen_rtx_SET (VOIDmode, dest, src)));
6213
6214 /* Finish up, return sequence. */
6215 ret = get_insns ();
6216 end_sequence ();
6217 return ret;
6218 }
6219
6220
6221 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6222 register used in an insn. */
6223
6224 static int
frv_clear_registers_used(rtx * ptr,void * data)6225 frv_clear_registers_used (rtx *ptr, void *data)
6226 {
6227 if (GET_CODE (*ptr) == REG)
6228 {
6229 int regno = REGNO (*ptr);
6230 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
6231
6232 if (regno < FIRST_PSEUDO_REGISTER)
6233 {
6234 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
6235
6236 while (regno < reg_max)
6237 {
6238 CLEAR_HARD_REG_BIT (*p_regs, regno);
6239 regno++;
6240 }
6241 }
6242 }
6243
6244 return 0;
6245 }
6246
6247
6248 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6249
6250 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6251 initialize the static storage. */
6252 void
frv_ifcvt_init_extra_fields(ce_if_block_t * ce_info ATTRIBUTE_UNUSED)6253 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6254 {
6255 frv_ifcvt.added_insns_list = NULL_RTX;
6256 frv_ifcvt.cur_scratch_regs = 0;
6257 frv_ifcvt.num_nested_cond_exec = 0;
6258 frv_ifcvt.cr_reg = NULL_RTX;
6259 frv_ifcvt.nested_cc_reg = NULL_RTX;
6260 frv_ifcvt.extra_int_cr = NULL_RTX;
6261 frv_ifcvt.extra_fp_cr = NULL_RTX;
6262 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6263 }
6264
6265
6266 /* Internal function to add a potenial insn to the list of insns to be inserted
6267 if the conditional execution conversion is successful. */
6268
6269 static void
frv_ifcvt_add_insn(rtx pattern,rtx insn,int before_p)6270 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
6271 {
6272 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
6273
6274 link->jump = before_p; /* Mark to add this before or after insn. */
6275 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
6276 frv_ifcvt.added_insns_list);
6277
6278 if (TARGET_DEBUG_COND_EXEC)
6279 {
6280 fprintf (stderr,
6281 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6282 (before_p) ? "before" : "after",
6283 (int)INSN_UID (insn));
6284
6285 debug_rtx (pattern);
6286 }
6287 }
6288
6289
6290 /* A C expression to modify the code described by the conditional if
6291 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6292 FALSE_EXPR for converting if-then and if-then-else code to conditional
6293 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6294 tests cannot be converted. */
6295
6296 void
frv_ifcvt_modify_tests(ce_if_block_t * ce_info,rtx * p_true,rtx * p_false)6297 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
6298 {
6299 basic_block test_bb = ce_info->test_bb; /* test basic block */
6300 basic_block then_bb = ce_info->then_bb; /* THEN */
6301 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
6302 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
6303 rtx true_expr = *p_true;
6304 rtx cr;
6305 rtx cc;
6306 rtx nested_cc;
6307 enum machine_mode mode = GET_MODE (true_expr);
6308 int j;
6309 basic_block *bb;
6310 int num_bb;
6311 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
6312 rtx check_insn;
6313 rtx sub_cond_exec_reg;
6314 enum rtx_code code;
6315 enum rtx_code code_true;
6316 enum rtx_code code_false;
6317 enum reg_class cc_class;
6318 enum reg_class cr_class;
6319 int cc_first;
6320 int cc_last;
6321
6322 /* Make sure we are only dealing with hard registers. Also honor the
6323 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6324 applicable. */
6325 if (!reload_completed || TARGET_NO_COND_EXEC
6326 || (TARGET_NO_NESTED_CE && ce_info->pass > 1))
6327 goto fail;
6328
6329 /* Figure out which registers we can allocate for our own purposes. Only
6330 consider registers that are not preserved across function calls and are
6331 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6332 if we did not need to use them in reloading other registers. */
6333 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
6334 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
6335 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
6336 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
6337 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
6338
6339 /* If this is a nested IF, we need to discover whether the CC registers that
6340 are set/used inside of the block are used anywhere else. If not, we can
6341 change them to be the CC register that is paired with the CR register that
6342 controls the outermost IF block. */
6343 if (ce_info->pass > 1)
6344 {
6345 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
6346 for (j = CC_FIRST; j <= CC_LAST; j++)
6347 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6348 {
6349 if (REGNO_REG_SET_P (then_bb->global_live_at_start, j))
6350 continue;
6351
6352 if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j))
6353 continue;
6354
6355 if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j))
6356 continue;
6357
6358 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
6359 }
6360 }
6361
6362 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
6363 frv_ifcvt.scratch_regs[j] = NULL_RTX;
6364
6365 frv_ifcvt.added_insns_list = NULL_RTX;
6366 frv_ifcvt.cur_scratch_regs = 0;
6367
6368 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
6369 * sizeof (basic_block));
6370
6371 if (join_bb)
6372 {
6373 int regno;
6374
6375 /* Remove anything live at the beginning of the join block from being
6376 available for allocation. */
6377 EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno,
6378 {
6379 if (regno < FIRST_PSEUDO_REGISTER)
6380 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6381 });
6382 }
6383
6384 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6385 num_bb = 0;
6386 if (ce_info->num_multiple_test_blocks)
6387 {
6388 basic_block multiple_test_bb = ce_info->last_test_bb;
6389
6390 while (multiple_test_bb != test_bb)
6391 {
6392 bb[num_bb++] = multiple_test_bb;
6393 multiple_test_bb = multiple_test_bb->pred->src;
6394 }
6395 }
6396
6397 /* Add in the THEN and ELSE blocks to be scanned. */
6398 bb[num_bb++] = then_bb;
6399 if (else_bb)
6400 bb[num_bb++] = else_bb;
6401
6402 sub_cond_exec_reg = NULL_RTX;
6403 frv_ifcvt.num_nested_cond_exec = 0;
6404
6405 /* Scan all of the blocks for registers that must not be allocated. */
6406 for (j = 0; j < num_bb; j++)
6407 {
6408 rtx last_insn = BB_END (bb[j]);
6409 rtx insn = BB_HEAD (bb[j]);
6410 int regno;
6411
6412 if (rtl_dump_file)
6413 fprintf (rtl_dump_file, "Scanning %s block %d, start %d, end %d\n",
6414 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
6415 (int) bb[j]->index,
6416 (int) INSN_UID (BB_HEAD (bb[j])),
6417 (int) INSN_UID (BB_END (bb[j])));
6418
6419 /* Anything live at the beginning of the block is obviously unavailable
6420 for allocation. */
6421 EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno,
6422 {
6423 if (regno < FIRST_PSEUDO_REGISTER)
6424 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6425 });
6426
6427 /* Loop through the insns in the block. */
6428 for (;;)
6429 {
6430 /* Mark any new registers that are created as being unavailable for
6431 allocation. Also see if the CC register used in nested IFs can be
6432 reallocated. */
6433 if (INSN_P (insn))
6434 {
6435 rtx pattern;
6436 rtx set;
6437 int skip_nested_if = FALSE;
6438
6439 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6440 (void *)&tmp_reg->regs);
6441
6442 pattern = PATTERN (insn);
6443 if (GET_CODE (pattern) == COND_EXEC)
6444 {
6445 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
6446
6447 if (reg != sub_cond_exec_reg)
6448 {
6449 sub_cond_exec_reg = reg;
6450 frv_ifcvt.num_nested_cond_exec++;
6451 }
6452 }
6453
6454 set = single_set_pattern (pattern);
6455 if (set)
6456 {
6457 rtx dest = SET_DEST (set);
6458 rtx src = SET_SRC (set);
6459
6460 if (GET_CODE (dest) == REG)
6461 {
6462 int regno = REGNO (dest);
6463 enum rtx_code src_code = GET_CODE (src);
6464
6465 if (CC_P (regno) && src_code == COMPARE)
6466 skip_nested_if = TRUE;
6467
6468 else if (CR_P (regno)
6469 && (src_code == IF_THEN_ELSE
6470 || GET_RTX_CLASS (src_code) == '<'))
6471 skip_nested_if = TRUE;
6472 }
6473 }
6474
6475 if (! skip_nested_if)
6476 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6477 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
6478 }
6479
6480 if (insn == last_insn)
6481 break;
6482
6483 insn = NEXT_INSN (insn);
6484 }
6485 }
6486
6487 /* If this is a nested if, rewrite the CC registers that are available to
6488 include the ones that can be rewritten, to increase the chance of being
6489 able to allocate a paired CC/CR register combination. */
6490 if (ce_info->pass > 1)
6491 {
6492 for (j = CC_FIRST; j <= CC_LAST; j++)
6493 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
6494 SET_HARD_REG_BIT (tmp_reg->regs, j);
6495 else
6496 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
6497 }
6498
6499 if (rtl_dump_file)
6500 {
6501 int num_gprs = 0;
6502 fprintf (rtl_dump_file, "Available GPRs: ");
6503
6504 for (j = GPR_FIRST; j <= GPR_LAST; j++)
6505 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6506 {
6507 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6508 if (++num_gprs > GPR_TEMP_NUM+2)
6509 break;
6510 }
6511
6512 fprintf (rtl_dump_file, "%s\nAvailable CRs: ",
6513 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
6514
6515 for (j = CR_FIRST; j <= CR_LAST; j++)
6516 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6517 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6518
6519 fputs ("\n", rtl_dump_file);
6520
6521 if (ce_info->pass > 1)
6522 {
6523 fprintf (rtl_dump_file, "Modifiable CCs: ");
6524 for (j = CC_FIRST; j <= CC_LAST; j++)
6525 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6526 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6527
6528 fprintf (rtl_dump_file, "\n%d nested COND_EXEC statements\n",
6529 frv_ifcvt.num_nested_cond_exec);
6530 }
6531 }
6532
6533 /* Allocate the appropriate temporary condition code register. Try to
6534 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6535 that conditional cmp's can be done. */
6536 if (mode == CCmode || mode == CC_UNSmode)
6537 {
6538 cr_class = ICR_REGS;
6539 cc_class = ICC_REGS;
6540 cc_first = ICC_FIRST;
6541 cc_last = ICC_LAST;
6542 }
6543 else if (mode == CC_FPmode)
6544 {
6545 cr_class = FCR_REGS;
6546 cc_class = FCC_REGS;
6547 cc_first = FCC_FIRST;
6548 cc_last = FCC_LAST;
6549 }
6550 else
6551 {
6552 cc_first = cc_last = 0;
6553 cr_class = cc_class = NO_REGS;
6554 }
6555
6556 cc = XEXP (true_expr, 0);
6557 nested_cc = cr = NULL_RTX;
6558 if (cc_class != NO_REGS)
6559 {
6560 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6561 so we can execute a csubcc/caddcc/cfcmps instruction. */
6562 int cc_regno;
6563
6564 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
6565 {
6566 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
6567
6568 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
6569 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
6570 {
6571 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
6572 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
6573 TRUE);
6574
6575 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
6576 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
6577 TRUE, TRUE);
6578 break;
6579 }
6580 }
6581 }
6582
6583 if (! cr)
6584 {
6585 if (rtl_dump_file)
6586 fprintf (rtl_dump_file, "Could not allocate a CR temporary register\n");
6587
6588 goto fail;
6589 }
6590
6591 if (rtl_dump_file)
6592 fprintf (rtl_dump_file,
6593 "Will use %s for conditional execution, %s for nested comparisons\n",
6594 reg_names[ REGNO (cr)],
6595 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
6596
6597 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
6598 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
6599 bit being true. We don't do this for floating point, because of NaNs. */
6600 code = GET_CODE (true_expr);
6601 if (GET_MODE (cc) != CC_FPmode)
6602 {
6603 code = reverse_condition (code);
6604 code_true = EQ;
6605 code_false = NE;
6606 }
6607 else
6608 {
6609 code_true = NE;
6610 code_false = EQ;
6611 }
6612
6613 check_insn = gen_rtx_SET (VOIDmode, cr,
6614 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
6615
6616 /* Record the check insn to be inserted later. */
6617 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
6618
6619 /* Update the tests. */
6620 frv_ifcvt.cr_reg = cr;
6621 frv_ifcvt.nested_cc_reg = nested_cc;
6622 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
6623 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
6624 return;
6625
6626 /* Fail, don't do this conditional execution. */
6627 fail:
6628 *p_true = NULL_RTX;
6629 *p_false = NULL_RTX;
6630 if (rtl_dump_file)
6631 fprintf (rtl_dump_file, "Disabling this conditional execution.\n");
6632
6633 return;
6634 }
6635
6636
6637 /* A C expression to modify the code described by the conditional if
6638 information CE_INFO, for the basic block BB, possibly updating the tests in
6639 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
6640 if-then-else code to conditional instructions. Set either TRUE_EXPR or
6641 FALSE_EXPR to a null pointer if the tests cannot be converted. */
6642
6643 /* p_true and p_false are given expressions of the form:
6644
6645 (and (eq:CC_CCR (reg:CC_CCR)
6646 (const_int 0))
6647 (eq:CC (reg:CC)
6648 (const_int 0))) */
6649
6650 void
frv_ifcvt_modify_multiple_tests(ce_if_block_t * ce_info,basic_block bb,rtx * p_true,rtx * p_false)6651 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
6652 basic_block bb,
6653 rtx *p_true,
6654 rtx *p_false)
6655 {
6656 rtx old_true = XEXP (*p_true, 0);
6657 rtx old_false = XEXP (*p_false, 0);
6658 rtx true_expr = XEXP (*p_true, 1);
6659 rtx false_expr = XEXP (*p_false, 1);
6660 rtx test_expr;
6661 rtx old_test;
6662 rtx cr = XEXP (old_true, 0);
6663 rtx check_insn;
6664 rtx new_cr = NULL_RTX;
6665 rtx *p_new_cr = (rtx *)0;
6666 rtx if_else;
6667 rtx compare;
6668 rtx cc;
6669 enum reg_class cr_class;
6670 enum machine_mode mode = GET_MODE (true_expr);
6671 rtx (*logical_func)(rtx, rtx, rtx);
6672
6673 if (TARGET_DEBUG_COND_EXEC)
6674 {
6675 fprintf (stderr,
6676 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
6677 ce_info->and_and_p ? "&&" : "||");
6678
6679 debug_rtx (*p_true);
6680
6681 fputs ("\nfalse insn:\n", stderr);
6682 debug_rtx (*p_false);
6683 }
6684
6685 if (TARGET_NO_MULTI_CE)
6686 goto fail;
6687
6688 if (GET_CODE (cr) != REG)
6689 goto fail;
6690
6691 if (mode == CCmode || mode == CC_UNSmode)
6692 {
6693 cr_class = ICR_REGS;
6694 p_new_cr = &frv_ifcvt.extra_int_cr;
6695 }
6696 else if (mode == CC_FPmode)
6697 {
6698 cr_class = FCR_REGS;
6699 p_new_cr = &frv_ifcvt.extra_fp_cr;
6700 }
6701 else
6702 goto fail;
6703
6704 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
6705 more &&/|| tests. */
6706 new_cr = *p_new_cr;
6707 if (! new_cr)
6708 {
6709 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
6710 CC_CCRmode, TRUE, TRUE);
6711 if (! new_cr)
6712 goto fail;
6713 }
6714
6715 if (ce_info->and_and_p)
6716 {
6717 old_test = old_false;
6718 test_expr = true_expr;
6719 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
6720 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
6721 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
6722 }
6723 else
6724 {
6725 old_test = old_false;
6726 test_expr = false_expr;
6727 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
6728 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
6729 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
6730 }
6731
6732 /* First add the andcr/andncr/orcr/orncr, which will be added after the
6733 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
6734 stack. */
6735 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
6736
6737 /* Now add the conditional check insn. */
6738 cc = XEXP (test_expr, 0);
6739 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
6740 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
6741
6742 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
6743
6744 /* Add the new check insn to the list of check insns that need to be
6745 inserted. */
6746 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
6747
6748 if (TARGET_DEBUG_COND_EXEC)
6749 {
6750 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
6751 stderr);
6752
6753 debug_rtx (*p_true);
6754
6755 fputs ("\nfalse insn:\n", stderr);
6756 debug_rtx (*p_false);
6757 }
6758
6759 return;
6760
6761 fail:
6762 *p_true = *p_false = NULL_RTX;
6763
6764 /* If we allocated a CR register, release it. */
6765 if (new_cr)
6766 {
6767 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
6768 *p_new_cr = NULL_RTX;
6769 }
6770
6771 if (TARGET_DEBUG_COND_EXEC)
6772 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
6773
6774 return;
6775 }
6776
6777
6778 /* Return a register which will be loaded with a value if an IF block is
6779 converted to conditional execution. This is used to rewrite instructions
6780 that use constants to ones that just use registers. */
6781
6782 static rtx
frv_ifcvt_load_value(rtx value,rtx insn ATTRIBUTE_UNUSED)6783 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
6784 {
6785 int num_alloc = frv_ifcvt.cur_scratch_regs;
6786 int i;
6787 rtx reg;
6788
6789 /* We know gr0 == 0, so replace any errant uses. */
6790 if (value == const0_rtx)
6791 return gen_rtx_REG (SImode, GPR_FIRST);
6792
6793 /* First search all registers currently loaded to see if we have an
6794 applicable constant. */
6795 if (CONSTANT_P (value)
6796 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
6797 {
6798 for (i = 0; i < num_alloc; i++)
6799 {
6800 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
6801 return SET_DEST (frv_ifcvt.scratch_regs[i]);
6802 }
6803 }
6804
6805 /* Have we exhausted the number of registers available? */
6806 if (num_alloc >= GPR_TEMP_NUM)
6807 {
6808 if (rtl_dump_file)
6809 fprintf (rtl_dump_file, "Too many temporary registers allocated\n");
6810
6811 return NULL_RTX;
6812 }
6813
6814 /* Allocate the new register. */
6815 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
6816 if (! reg)
6817 {
6818 if (rtl_dump_file)
6819 fputs ("Could not find a scratch register\n", rtl_dump_file);
6820
6821 return NULL_RTX;
6822 }
6823
6824 frv_ifcvt.cur_scratch_regs++;
6825 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
6826
6827 if (rtl_dump_file)
6828 {
6829 if (GET_CODE (value) == CONST_INT)
6830 fprintf (rtl_dump_file, "Register %s will hold %ld\n",
6831 reg_names[ REGNO (reg)], (long)INTVAL (value));
6832
6833 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
6834 fprintf (rtl_dump_file, "Register %s will hold LR\n",
6835 reg_names[ REGNO (reg)]);
6836
6837 else
6838 fprintf (rtl_dump_file, "Register %s will hold a saved value\n",
6839 reg_names[ REGNO (reg)]);
6840 }
6841
6842 return reg;
6843 }
6844
6845
6846 /* Update a MEM used in conditional code that might contain an offset to put
6847 the offset into a scratch register, so that the conditional load/store
6848 operations can be used. This function returns the original pointer if the
6849 MEM is valid to use in conditional code, NULL if we can't load up the offset
6850 into a temporary register, or the new MEM if we were successful. */
6851
6852 static rtx
frv_ifcvt_rewrite_mem(rtx mem,enum machine_mode mode,rtx insn)6853 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
6854 {
6855 rtx addr = XEXP (mem, 0);
6856
6857 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE))
6858 {
6859 if (GET_CODE (addr) == PLUS)
6860 {
6861 rtx addr_op0 = XEXP (addr, 0);
6862 rtx addr_op1 = XEXP (addr, 1);
6863
6864 if (plus_small_data_p (addr_op0, addr_op1))
6865 addr = frv_ifcvt_load_value (addr, insn);
6866
6867 else if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
6868 {
6869 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
6870 if (!reg)
6871 return NULL_RTX;
6872
6873 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
6874 }
6875
6876 else
6877 return NULL_RTX;
6878 }
6879
6880 else if (CONSTANT_P (addr))
6881 addr = frv_ifcvt_load_value (addr, insn);
6882
6883 else
6884 return NULL_RTX;
6885
6886 if (addr == NULL_RTX)
6887 return NULL_RTX;
6888
6889 else if (XEXP (mem, 0) != addr)
6890 return change_address (mem, mode, addr);
6891 }
6892
6893 return mem;
6894 }
6895
6896
6897 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
6898 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
6899
6900 static rtx
single_set_pattern(rtx pattern)6901 single_set_pattern (rtx pattern)
6902 {
6903 rtx set;
6904 int i;
6905
6906 if (GET_CODE (pattern) == COND_EXEC)
6907 pattern = COND_EXEC_CODE (pattern);
6908
6909 if (GET_CODE (pattern) == SET)
6910 return pattern;
6911
6912 else if (GET_CODE (pattern) == PARALLEL)
6913 {
6914 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
6915 {
6916 rtx sub = XVECEXP (pattern, 0, i);
6917
6918 switch (GET_CODE (sub))
6919 {
6920 case USE:
6921 case CLOBBER:
6922 break;
6923
6924 case SET:
6925 if (set)
6926 return 0;
6927 else
6928 set = sub;
6929 break;
6930
6931 default:
6932 return 0;
6933 }
6934 }
6935 return set;
6936 }
6937
6938 return 0;
6939 }
6940
6941
6942 /* A C expression to modify the code described by the conditional if
6943 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
6944 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
6945 insn cannot be converted to be executed conditionally. */
6946
6947 rtx
frv_ifcvt_modify_insn(ce_if_block_t * ce_info,rtx pattern,rtx insn)6948 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
6949 rtx pattern,
6950 rtx insn)
6951 {
6952 rtx orig_ce_pattern = pattern;
6953 rtx set;
6954 rtx op0;
6955 rtx op1;
6956 rtx test;
6957
6958 if (GET_CODE (pattern) != COND_EXEC)
6959 abort ();
6960
6961 test = COND_EXEC_TEST (pattern);
6962 if (GET_CODE (test) == AND)
6963 {
6964 rtx cr = frv_ifcvt.cr_reg;
6965 rtx test_reg;
6966
6967 op0 = XEXP (test, 0);
6968 if (! rtx_equal_p (cr, XEXP (op0, 0)))
6969 goto fail;
6970
6971 op1 = XEXP (test, 1);
6972 test_reg = XEXP (op1, 0);
6973 if (GET_CODE (test_reg) != REG)
6974 goto fail;
6975
6976 /* Is this the first nested if block in this sequence? If so, generate
6977 an andcr or andncr. */
6978 if (! frv_ifcvt.last_nested_if_cr)
6979 {
6980 rtx and_op;
6981
6982 frv_ifcvt.last_nested_if_cr = test_reg;
6983 if (GET_CODE (op0) == NE)
6984 and_op = gen_andcr (test_reg, cr, test_reg);
6985 else
6986 and_op = gen_andncr (test_reg, cr, test_reg);
6987
6988 frv_ifcvt_add_insn (and_op, insn, TRUE);
6989 }
6990
6991 /* If this isn't the first statement in the nested if sequence, see if we
6992 are dealing with the same register. */
6993 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
6994 goto fail;
6995
6996 COND_EXEC_TEST (pattern) = test = op1;
6997 }
6998
6999 /* If this isn't a nested if, reset state variables. */
7000 else
7001 {
7002 frv_ifcvt.last_nested_if_cr = NULL_RTX;
7003 }
7004
7005 set = single_set_pattern (pattern);
7006 if (set)
7007 {
7008 rtx dest = SET_DEST (set);
7009 rtx src = SET_SRC (set);
7010 enum machine_mode mode = GET_MODE (dest);
7011
7012 /* Check for normal binary operators. */
7013 if (mode == SImode
7014 && (GET_RTX_CLASS (GET_CODE (src)) == '2'
7015 || GET_RTX_CLASS (GET_CODE (src)) == 'c'))
7016 {
7017 op0 = XEXP (src, 0);
7018 op1 = XEXP (src, 1);
7019
7020 /* Special case load of small data address which looks like:
7021 r16+symbol_ref */
7022 if (GET_CODE (src) == PLUS && plus_small_data_p (op0, op1))
7023 {
7024 src = frv_ifcvt_load_value (src, insn);
7025 if (src)
7026 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7027 else
7028 goto fail;
7029 }
7030
7031 else if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
7032 {
7033 op1 = frv_ifcvt_load_value (op1, insn);
7034 if (op1)
7035 COND_EXEC_CODE (pattern)
7036 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
7037 GET_MODE (src),
7038 op0, op1));
7039 else
7040 goto fail;
7041 }
7042 }
7043
7044 /* For multiply by a constant, we need to handle the sign extending
7045 correctly. Add a USE of the value after the multiply to prevent flow
7046 from cratering because only one register out of the two were used. */
7047 else if (mode == DImode && GET_CODE (src) == MULT)
7048 {
7049 op0 = XEXP (src, 0);
7050 op1 = XEXP (src, 1);
7051 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
7052 {
7053 op1 = frv_ifcvt_load_value (op1, insn);
7054 if (op1)
7055 {
7056 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
7057 COND_EXEC_CODE (pattern)
7058 = gen_rtx_SET (VOIDmode, dest,
7059 gen_rtx_MULT (DImode, op0, op1));
7060 }
7061 else
7062 goto fail;
7063 }
7064
7065 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE);
7066 }
7067
7068 /* If we are just loading a constant created for a nested conditional
7069 execution statement, just load the constant without any conditional
7070 execution, since we know that the constant will not interfere with any
7071 other registers. */
7072 else if (frv_ifcvt.scratch_insns_bitmap
7073 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
7074 INSN_UID (insn))
7075 /* We must not unconditionally set a reg set used as
7076 scratch in the THEN branch if the same reg is live
7077 in the ELSE branch. */
7078 && REG_P (SET_DEST (set))
7079 && (! ce_info->else_bb
7080 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
7081 || ! (REGNO_REG_SET_P
7082 (ce_info->else_bb->global_live_at_start,
7083 REGNO (SET_DEST (set))))))
7084 pattern = set;
7085
7086 else if (mode == QImode || mode == HImode || mode == SImode
7087 || mode == SFmode)
7088 {
7089 int changed_p = FALSE;
7090
7091 /* Check for just loading up a constant */
7092 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
7093 {
7094 src = frv_ifcvt_load_value (src, insn);
7095 if (!src)
7096 goto fail;
7097
7098 changed_p = TRUE;
7099 }
7100
7101 /* See if we need to fix up stores */
7102 if (GET_CODE (dest) == MEM)
7103 {
7104 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
7105
7106 if (!new_mem)
7107 goto fail;
7108
7109 else if (new_mem != dest)
7110 {
7111 changed_p = TRUE;
7112 dest = new_mem;
7113 }
7114 }
7115
7116 /* See if we need to fix up loads */
7117 if (GET_CODE (src) == MEM)
7118 {
7119 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
7120
7121 if (!new_mem)
7122 goto fail;
7123
7124 else if (new_mem != src)
7125 {
7126 changed_p = TRUE;
7127 src = new_mem;
7128 }
7129 }
7130
7131 /* If either src or destination changed, redo SET. */
7132 if (changed_p)
7133 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7134 }
7135
7136 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7137 rewriting the CC register to be the same as the paired CC/CR register
7138 for nested ifs. */
7139 else if (mode == CC_CCRmode && GET_RTX_CLASS (GET_CODE (src)) == '<')
7140 {
7141 int regno = REGNO (XEXP (src, 0));
7142 rtx if_else;
7143
7144 if (ce_info->pass > 1
7145 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
7146 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
7147 {
7148 src = gen_rtx_fmt_ee (GET_CODE (src),
7149 CC_CCRmode,
7150 frv_ifcvt.nested_cc_reg,
7151 XEXP (src, 1));
7152 }
7153
7154 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
7155 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
7156 }
7157
7158 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7159 else if (ce_info->pass > 1
7160 && GET_CODE (dest) == REG
7161 && CC_P (REGNO (dest))
7162 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
7163 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
7164 REGNO (dest))
7165 && GET_CODE (src) == COMPARE)
7166 {
7167 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
7168 COND_EXEC_CODE (pattern)
7169 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
7170 }
7171 }
7172
7173 if (TARGET_DEBUG_COND_EXEC)
7174 {
7175 rtx orig_pattern = PATTERN (insn);
7176
7177 PATTERN (insn) = pattern;
7178 fprintf (stderr,
7179 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7180 ce_info->pass);
7181
7182 debug_rtx (insn);
7183 PATTERN (insn) = orig_pattern;
7184 }
7185
7186 return pattern;
7187
7188 fail:
7189 if (TARGET_DEBUG_COND_EXEC)
7190 {
7191 rtx orig_pattern = PATTERN (insn);
7192
7193 PATTERN (insn) = orig_ce_pattern;
7194 fprintf (stderr,
7195 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7196 ce_info->pass);
7197
7198 debug_rtx (insn);
7199 PATTERN (insn) = orig_pattern;
7200 }
7201
7202 return NULL_RTX;
7203 }
7204
7205
7206 /* A C expression to perform any final machine dependent modifications in
7207 converting code to conditional execution in the code described by the
7208 conditional if information CE_INFO. */
7209
7210 void
frv_ifcvt_modify_final(ce_if_block_t * ce_info ATTRIBUTE_UNUSED)7211 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7212 {
7213 rtx existing_insn;
7214 rtx check_insn;
7215 rtx p = frv_ifcvt.added_insns_list;
7216 int i;
7217
7218 /* Loop inserting the check insns. The last check insn is the first test,
7219 and is the appropriate place to insert constants. */
7220 if (! p)
7221 abort ();
7222
7223 do
7224 {
7225 rtx check_and_insert_insns = XEXP (p, 0);
7226 rtx old_p = p;
7227
7228 check_insn = XEXP (check_and_insert_insns, 0);
7229 existing_insn = XEXP (check_and_insert_insns, 1);
7230 p = XEXP (p, 1);
7231
7232 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7233 the existing insn, otherwise it is to be inserted AFTER. */
7234 if (check_and_insert_insns->jump)
7235 {
7236 emit_insn_before (check_insn, existing_insn);
7237 check_and_insert_insns->jump = 0;
7238 }
7239 else
7240 emit_insn_after (check_insn, existing_insn);
7241
7242 free_EXPR_LIST_node (check_and_insert_insns);
7243 free_EXPR_LIST_node (old_p);
7244 }
7245 while (p != NULL_RTX);
7246
7247 /* Load up any constants needed into temp gprs */
7248 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7249 {
7250 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
7251 if (! frv_ifcvt.scratch_insns_bitmap)
7252 frv_ifcvt.scratch_insns_bitmap = BITMAP_XMALLOC ();
7253 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
7254 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7255 }
7256
7257 frv_ifcvt.added_insns_list = NULL_RTX;
7258 frv_ifcvt.cur_scratch_regs = 0;
7259 }
7260
7261
7262 /* A C expression to cancel any machine dependent modifications in converting
7263 code to conditional execution in the code described by the conditional if
7264 information CE_INFO. */
7265
7266 void
frv_ifcvt_modify_cancel(ce_if_block_t * ce_info ATTRIBUTE_UNUSED)7267 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7268 {
7269 int i;
7270 rtx p = frv_ifcvt.added_insns_list;
7271
7272 /* Loop freeing up the EXPR_LIST's allocated. */
7273 while (p != NULL_RTX)
7274 {
7275 rtx check_and_jump = XEXP (p, 0);
7276 rtx old_p = p;
7277
7278 p = XEXP (p, 1);
7279 free_EXPR_LIST_node (check_and_jump);
7280 free_EXPR_LIST_node (old_p);
7281 }
7282
7283 /* Release any temporary gprs allocated. */
7284 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7285 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7286
7287 frv_ifcvt.added_insns_list = NULL_RTX;
7288 frv_ifcvt.cur_scratch_regs = 0;
7289 return;
7290 }
7291
7292 /* A C expression for the size in bytes of the trampoline, as an integer.
7293 The template is:
7294
7295 setlo #0, <jmp_reg>
7296 setlo #0, <static_chain>
7297 sethi #0, <jmp_reg>
7298 sethi #0, <static_chain>
7299 jmpl @(gr0,<jmp_reg>) */
7300
7301 int
frv_trampoline_size(void)7302 frv_trampoline_size (void)
7303 {
7304 return 5 /* instructions */ * 4 /* instruction size */;
7305 }
7306
7307
7308 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7309 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7310 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7311 should be passed to the function when it is called.
7312
7313 The template is:
7314
7315 setlo #0, <jmp_reg>
7316 setlo #0, <static_chain>
7317 sethi #0, <jmp_reg>
7318 sethi #0, <static_chain>
7319 jmpl @(gr0,<jmp_reg>) */
7320
7321 void
frv_initialize_trampoline(rtx addr,rtx fnaddr,rtx static_chain)7322 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
7323 {
7324 rtx sc_reg = force_reg (Pmode, static_chain);
7325
7326 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
7327 FALSE, VOIDmode, 4,
7328 addr, Pmode,
7329 GEN_INT (frv_trampoline_size ()), SImode,
7330 fnaddr, Pmode,
7331 sc_reg, Pmode);
7332 }
7333
7334
7335 /* Many machines have some registers that cannot be copied directly to or from
7336 memory or even from other types of registers. An example is the `MQ'
7337 register, which on most machines, can only be copied to or from general
7338 registers, but not memory. Some machines allow copying all registers to and
7339 from memory, but require a scratch register for stores to some memory
7340 locations (e.g., those with symbolic address on the RT, and those with
7341 certain symbolic address on the SPARC when compiling PIC). In some cases,
7342 both an intermediate and a scratch register are required.
7343
7344 You should define these macros to indicate to the reload phase that it may
7345 need to allocate at least one register for a reload in addition to the
7346 register to contain the data. Specifically, if copying X to a register
7347 CLASS in MODE requires an intermediate register, you should define
7348 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7349 whose registers can be used as intermediate registers or scratch registers.
7350
7351 If copying a register CLASS in MODE to X requires an intermediate or scratch
7352 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7353 largest register class required. If the requirements for input and output
7354 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7355 instead of defining both macros identically.
7356
7357 The values returned by these macros are often `GENERAL_REGS'. Return
7358 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7359 to or from a register of CLASS in MODE without requiring a scratch register.
7360 Do not define this macro if it would always return `NO_REGS'.
7361
7362 If a scratch register is required (either with or without an intermediate
7363 register), you should define patterns for `reload_inM' or `reload_outM', as
7364 required.. These patterns, which will normally be implemented with a
7365 `define_expand', should be similar to the `movM' patterns, except that
7366 operand 2 is the scratch register.
7367
7368 Define constraints for the reload register and scratch register that contain
7369 a single register class. If the original reload register (whose class is
7370 CLASS) can meet the constraint given in the pattern, the value returned by
7371 these macros is used for the class of the scratch register. Otherwise, two
7372 additional reload registers are required. Their classes are obtained from
7373 the constraints in the insn pattern.
7374
7375 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7376 either be in a hard register or in memory. Use `true_regnum' to find out;
7377 it will return -1 if the pseudo is in memory and the hard register number if
7378 it is in a register.
7379
7380 These macros should not be used in the case where a particular class of
7381 registers can only be copied to memory and not to another class of
7382 registers. In that case, secondary reload registers are not needed and
7383 would not be helpful. Instead, a stack location must be used to perform the
7384 copy and the `movM' pattern should use memory as an intermediate storage.
7385 This case often occurs between floating-point and general registers. */
7386
7387 enum reg_class
frv_secondary_reload_class(enum reg_class class,enum machine_mode mode ATTRIBUTE_UNUSED,rtx x,int in_p ATTRIBUTE_UNUSED)7388 frv_secondary_reload_class (enum reg_class class,
7389 enum machine_mode mode ATTRIBUTE_UNUSED,
7390 rtx x,
7391 int in_p ATTRIBUTE_UNUSED)
7392 {
7393 enum reg_class ret;
7394
7395 switch (class)
7396 {
7397 default:
7398 ret = NO_REGS;
7399 break;
7400
7401 /* Accumulators/Accumulator guard registers need to go through floating
7402 point registers. */
7403 case QUAD_REGS:
7404 case EVEN_REGS:
7405 case GPR_REGS:
7406 ret = NO_REGS;
7407 if (x && GET_CODE (x) == REG)
7408 {
7409 int regno = REGNO (x);
7410
7411 if (ACC_P (regno) || ACCG_P (regno))
7412 ret = FPR_REGS;
7413 }
7414 break;
7415
7416 /* Nonzero constants should be loaded into an FPR through a GPR. */
7417 case QUAD_FPR_REGS:
7418 case FEVEN_REGS:
7419 case FPR_REGS:
7420 if (x && CONSTANT_P (x) && !ZERO_P (x))
7421 ret = GPR_REGS;
7422 else
7423 ret = NO_REGS;
7424 break;
7425
7426 /* All of these types need gpr registers. */
7427 case ICC_REGS:
7428 case FCC_REGS:
7429 case CC_REGS:
7430 case ICR_REGS:
7431 case FCR_REGS:
7432 case CR_REGS:
7433 case LCR_REG:
7434 case LR_REG:
7435 ret = GPR_REGS;
7436 break;
7437
7438 /* The accumulators need fpr registers */
7439 case ACC_REGS:
7440 case EVEN_ACC_REGS:
7441 case QUAD_ACC_REGS:
7442 case ACCG_REGS:
7443 ret = FPR_REGS;
7444 break;
7445 }
7446
7447 return ret;
7448 }
7449
7450
7451 /* A C expression whose value is nonzero if pseudos that have been assigned to
7452 registers of class CLASS would likely be spilled because registers of CLASS
7453 are needed for spill registers.
7454
7455 The default value of this macro returns 1 if CLASS has exactly one register
7456 and zero otherwise. On most machines, this default should be used. Only
7457 define this macro to some other expression if pseudo allocated by
7458 `local-alloc.c' end up in memory because their hard registers were needed
7459 for spill registers. If this macro returns nonzero for those classes, those
7460 pseudos will only be allocated by `global.c', which knows how to reallocate
7461 the pseudo to another register. If there would not be another register
7462 available for reallocation, you should not change the definition of this
7463 macro since the only effect of such a definition would be to slow down
7464 register allocation. */
7465
7466 int
frv_class_likely_spilled_p(enum reg_class class)7467 frv_class_likely_spilled_p (enum reg_class class)
7468 {
7469 switch (class)
7470 {
7471 default:
7472 break;
7473
7474 case ICC_REGS:
7475 case FCC_REGS:
7476 case CC_REGS:
7477 case ICR_REGS:
7478 case FCR_REGS:
7479 case CR_REGS:
7480 case LCR_REG:
7481 case LR_REG:
7482 case SPR_REGS:
7483 case QUAD_ACC_REGS:
7484 case EVEN_ACC_REGS:
7485 case ACC_REGS:
7486 case ACCG_REGS:
7487 return TRUE;
7488 }
7489
7490 return FALSE;
7491 }
7492
7493
7494 /* An expression for the alignment of a structure field FIELD if the
7495 alignment computed in the usual way is COMPUTED. GCC uses this
7496 value instead of the value in `BIGGEST_ALIGNMENT' or
7497 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7498
7499 /* The definition type of the bit field data is either char, short, long or
7500 long long. The maximum bit size is the number of bits of its own type.
7501
7502 The bit field data is assigned to a storage unit that has an adequate size
7503 for bit field data retention and is located at the smallest address.
7504
7505 Consecutive bit field data are packed at consecutive bits having the same
7506 storage unit, with regard to the type, beginning with the MSB and continuing
7507 toward the LSB.
7508
7509 If a field to be assigned lies over a bit field type boundary, its
7510 assignment is completed by aligning it with a boundary suitable for the
7511 type.
7512
7513 When a bit field having a bit length of 0 is declared, it is forcibly
7514 assigned to the next storage unit.
7515
7516 e.g)
7517 struct {
7518 int a:2;
7519 int b:6;
7520 char c:4;
7521 int d:10;
7522 int :0;
7523 int f:2;
7524 } x;
7525
7526 +0 +1 +2 +3
7527 &x 00000000 00000000 00000000 00000000
7528 MLM----L
7529 a b
7530 &x+4 00000000 00000000 00000000 00000000
7531 M--L
7532 c
7533 &x+8 00000000 00000000 00000000 00000000
7534 M----------L
7535 d
7536 &x+12 00000000 00000000 00000000 00000000
7537 ML
7538 f
7539 */
7540
7541 int
frv_adjust_field_align(tree field,int computed)7542 frv_adjust_field_align (tree field, int computed)
7543 {
7544 /* Make sure that the bitfield is not wider than the type. */
7545 if (DECL_BIT_FIELD (field)
7546 && !DECL_ARTIFICIAL (field))
7547 {
7548 tree parent = DECL_CONTEXT (field);
7549 tree prev = NULL_TREE;
7550 tree cur;
7551
7552 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
7553 {
7554 if (TREE_CODE (cur) != FIELD_DECL)
7555 continue;
7556
7557 prev = cur;
7558 }
7559
7560 if (!cur)
7561 abort ();
7562
7563 /* If this isn't a :0 field and if the previous element is a bitfield
7564 also, see if the type is different, if so, we will need to align the
7565 bit-field to the next boundary. */
7566 if (prev
7567 && ! DECL_PACKED (field)
7568 && ! integer_zerop (DECL_SIZE (field))
7569 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
7570 {
7571 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
7572 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
7573 computed = (prev_align > cur_align) ? prev_align : cur_align;
7574 }
7575 }
7576
7577 return computed;
7578 }
7579
7580
7581 /* A C expression that is nonzero if it is permissible to store a value of mode
7582 MODE in hard register number REGNO (or in several registers starting with
7583 that one). For a machine where all registers are equivalent, a suitable
7584 definition is
7585
7586 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7587
7588 It is not necessary for this macro to check for the numbers of fixed
7589 registers, because the allocation mechanism considers them to be always
7590 occupied.
7591
7592 On some machines, double-precision values must be kept in even/odd register
7593 pairs. The way to implement that is to define this macro to reject odd
7594 register numbers for such modes.
7595
7596 The minimum requirement for a mode to be OK in a register is that the
7597 `movMODE' instruction pattern support moves between the register and any
7598 other hard register for which the mode is OK; and that moving a value into
7599 the register and back out not alter it.
7600
7601 Since the same instruction used to move `SImode' will work for all narrower
7602 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7603 to distinguish between these modes, provided you define patterns `movhi',
7604 etc., to take advantage of this. This is useful because of the interaction
7605 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
7606 all integer modes to be tieable.
7607
7608 Many machines have special registers for floating point arithmetic. Often
7609 people assume that floating point machine modes are allowed only in floating
7610 point registers. This is not true. Any registers that can hold integers
7611 can safely *hold* a floating point machine mode, whether or not floating
7612 arithmetic can be done on it in those registers. Integer move instructions
7613 can be used to move the values.
7614
7615 On some machines, though, the converse is true: fixed-point machine modes
7616 may not go in floating registers. This is true if the floating registers
7617 normalize any value stored in them, because storing a non-floating value
7618 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
7619 fixed-point machine modes in floating registers. But if the floating
7620 registers do not automatically normalize, if you can store any bit pattern
7621 in one and retrieve it unchanged without a trap, then any machine mode may
7622 go in a floating register, so you can define this macro to say so.
7623
7624 The primary significance of special floating registers is rather that they
7625 are the registers acceptable in floating point arithmetic instructions.
7626 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
7627 writing the proper constraints for those instructions.
7628
7629 On some machines, the floating registers are especially slow to access, so
7630 that it is better to store a value in a stack frame than in such a register
7631 if floating point arithmetic is not being done. As long as the floating
7632 registers are not in class `GENERAL_REGS', they will not be used unless some
7633 pattern's constraint asks for one. */
7634
7635 int
frv_hard_regno_mode_ok(int regno,enum machine_mode mode)7636 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
7637 {
7638 int base;
7639 int mask;
7640
7641 switch (mode)
7642 {
7643 case CCmode:
7644 case CC_UNSmode:
7645 return ICC_P (regno) || GPR_P (regno);
7646
7647 case CC_CCRmode:
7648 return CR_P (regno) || GPR_P (regno);
7649
7650 case CC_FPmode:
7651 return FCC_P (regno) || GPR_P (regno);
7652
7653 default:
7654 break;
7655 }
7656
7657 /* Set BASE to the first register in REGNO's class. Set MASK to the
7658 bits that must be clear in (REGNO - BASE) for the register to be
7659 well-aligned. */
7660 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
7661 {
7662 if (ACCG_P (regno))
7663 {
7664 /* ACCGs store one byte. Two-byte quantities must start in
7665 even-numbered registers, four-byte ones in registers whose
7666 numbers are divisible by four, and so on. */
7667 base = ACCG_FIRST;
7668 mask = GET_MODE_SIZE (mode) - 1;
7669 }
7670 else
7671 {
7672 /* The other registers store one word. */
7673 if (GPR_P (regno) || regno == AP_FIRST)
7674 base = GPR_FIRST;
7675
7676 else if (FPR_P (regno))
7677 base = FPR_FIRST;
7678
7679 else if (ACC_P (regno))
7680 base = ACC_FIRST;
7681
7682 else if (SPR_P (regno))
7683 return mode == SImode;
7684
7685 /* Fill in the table. */
7686 else
7687 return 0;
7688
7689 /* Anything smaller than an SI is OK in any word-sized register. */
7690 if (GET_MODE_SIZE (mode) < 4)
7691 return 1;
7692
7693 mask = (GET_MODE_SIZE (mode) / 4) - 1;
7694 }
7695 return (((regno - base) & mask) == 0);
7696 }
7697
7698 return 0;
7699 }
7700
7701
7702 /* A C expression for the number of consecutive hard registers, starting at
7703 register number REGNO, required to hold a value of mode MODE.
7704
7705 On a machine where all registers are exactly one word, a suitable definition
7706 of this macro is
7707
7708 #define HARD_REGNO_NREGS(REGNO, MODE) \
7709 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
7710 / UNITS_PER_WORD)) */
7711
7712 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
7713 that we can build the appropriate instructions to properly reload the
7714 values. Also, make the byte-sized accumulator guards use one guard
7715 for each byte. */
7716
7717 int
frv_hard_regno_nregs(int regno,enum machine_mode mode)7718 frv_hard_regno_nregs (int regno, enum machine_mode mode)
7719 {
7720 if (ACCG_P (regno))
7721 return GET_MODE_SIZE (mode);
7722 else
7723 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7724 }
7725
7726
7727 /* A C expression for the maximum number of consecutive registers of
7728 class CLASS needed to hold a value of mode MODE.
7729
7730 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
7731 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
7732 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
7733
7734 This macro helps control the handling of multiple-word values in
7735 the reload pass.
7736
7737 This declaration is required. */
7738
7739 int
frv_class_max_nregs(enum reg_class class,enum machine_mode mode)7740 frv_class_max_nregs (enum reg_class class, enum machine_mode mode)
7741 {
7742 if (class == ACCG_REGS)
7743 /* An N-byte value requires N accumulator guards. */
7744 return GET_MODE_SIZE (mode);
7745 else
7746 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7747 }
7748
7749
7750 /* A C expression that is nonzero if X is a legitimate constant for an
7751 immediate operand on the target machine. You can assume that X satisfies
7752 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
7753 definition for this macro on machines where anything `CONSTANT_P' is valid. */
7754
7755 int
frv_legitimate_constant_p(rtx x)7756 frv_legitimate_constant_p (rtx x)
7757 {
7758 enum machine_mode mode = GET_MODE (x);
7759
7760 /* All of the integer constants are ok. */
7761 if (GET_CODE (x) != CONST_DOUBLE)
7762 return TRUE;
7763
7764 /* double integer constants are ok. */
7765 if (mode == VOIDmode || mode == DImode)
7766 return TRUE;
7767
7768 /* 0 is always ok. */
7769 if (x == CONST0_RTX (mode))
7770 return TRUE;
7771
7772 /* If floating point is just emulated, allow any constant, since it will be
7773 constructed in the GPRs. */
7774 if (!TARGET_HAS_FPRS)
7775 return TRUE;
7776
7777 if (mode == DFmode && !TARGET_DOUBLE)
7778 return TRUE;
7779
7780 /* Otherwise store the constant away and do a load. */
7781 return FALSE;
7782 }
7783
7784 /* A C expression for the cost of moving data from a register in class FROM to
7785 one in class TO. The classes are expressed using the enumeration values
7786 such as `GENERAL_REGS'. A value of 4 is the default; other values are
7787 interpreted relative to that.
7788
7789 It is not required that the cost always equal 2 when FROM is the same as TO;
7790 on some machines it is expensive to move between registers if they are not
7791 general registers.
7792
7793 If reload sees an insn consisting of a single `set' between two hard
7794 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
7795 value of 2, reload does not check to ensure that the constraints of the insn
7796 are met. Setting a cost of other than 2 will allow reload to verify that
7797 the constraints are met. You should do this if the `movM' pattern's
7798 constraints do not allow such copying. */
7799
7800 #define HIGH_COST 40
7801 #define MEDIUM_COST 3
7802 #define LOW_COST 1
7803
7804 int
frv_register_move_cost(enum reg_class from,enum reg_class to)7805 frv_register_move_cost (enum reg_class from, enum reg_class to)
7806 {
7807 switch (from)
7808 {
7809 default:
7810 break;
7811
7812 case QUAD_REGS:
7813 case EVEN_REGS:
7814 case GPR_REGS:
7815 switch (to)
7816 {
7817 default:
7818 break;
7819
7820 case QUAD_REGS:
7821 case EVEN_REGS:
7822 case GPR_REGS:
7823 return LOW_COST;
7824
7825 case FEVEN_REGS:
7826 case FPR_REGS:
7827 return LOW_COST;
7828
7829 case LCR_REG:
7830 case LR_REG:
7831 case SPR_REGS:
7832 return LOW_COST;
7833 }
7834
7835 case FEVEN_REGS:
7836 case FPR_REGS:
7837 switch (to)
7838 {
7839 default:
7840 break;
7841
7842 case QUAD_REGS:
7843 case EVEN_REGS:
7844 case GPR_REGS:
7845 case ACC_REGS:
7846 case EVEN_ACC_REGS:
7847 case QUAD_ACC_REGS:
7848 case ACCG_REGS:
7849 return MEDIUM_COST;
7850
7851 case FEVEN_REGS:
7852 case FPR_REGS:
7853 return LOW_COST;
7854 }
7855
7856 case LCR_REG:
7857 case LR_REG:
7858 case SPR_REGS:
7859 switch (to)
7860 {
7861 default:
7862 break;
7863
7864 case QUAD_REGS:
7865 case EVEN_REGS:
7866 case GPR_REGS:
7867 return MEDIUM_COST;
7868 }
7869
7870 case ACC_REGS:
7871 case EVEN_ACC_REGS:
7872 case QUAD_ACC_REGS:
7873 case ACCG_REGS:
7874 switch (to)
7875 {
7876 default:
7877 break;
7878
7879 case FEVEN_REGS:
7880 case FPR_REGS:
7881 return MEDIUM_COST;
7882
7883 }
7884 }
7885
7886 return HIGH_COST;
7887 }
7888
7889 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
7890 use ".picptr" to generate safe relocations for PIC code. We also
7891 need a fixup entry for aligned (non-debugging) code. */
7892
7893 static bool
frv_assemble_integer(rtx value,unsigned int size,int aligned_p)7894 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
7895 {
7896 if (flag_pic && size == UNITS_PER_WORD)
7897 {
7898 if (GET_CODE (value) == CONST
7899 || GET_CODE (value) == SYMBOL_REF
7900 || GET_CODE (value) == LABEL_REF)
7901 {
7902 if (aligned_p)
7903 {
7904 static int label_num = 0;
7905 char buf[256];
7906 const char *p;
7907
7908 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
7909 p = (* targetm.strip_name_encoding) (buf);
7910
7911 fprintf (asm_out_file, "%s:\n", p);
7912 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
7913 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
7914 fprintf (asm_out_file, "\t.previous\n");
7915 }
7916 assemble_integer_with_op ("\t.picptr\t", value);
7917 return true;
7918 }
7919 if (!aligned_p)
7920 {
7921 /* We've set the unaligned SI op to NULL, so we always have to
7922 handle the unaligned case here. */
7923 assemble_integer_with_op ("\t.4byte\t", value);
7924 return true;
7925 }
7926 }
7927 return default_assemble_integer (value, size, aligned_p);
7928 }
7929
7930 /* Function to set up the backend function structure. */
7931
7932 static struct machine_function *
frv_init_machine_status(void)7933 frv_init_machine_status (void)
7934 {
7935 return ggc_alloc_cleared (sizeof (struct machine_function));
7936 }
7937
7938 /* Implement TARGET_SCHED_ISSUE_RATE. */
7939
7940 static int
frv_issue_rate(void)7941 frv_issue_rate (void)
7942 {
7943 if (!TARGET_PACK)
7944 return 1;
7945
7946 switch (frv_cpu_type)
7947 {
7948 default:
7949 case FRV_CPU_FR300:
7950 case FRV_CPU_SIMPLE:
7951 return 1;
7952
7953 case FRV_CPU_FR400:
7954 return 2;
7955
7956 case FRV_CPU_GENERIC:
7957 case FRV_CPU_FR500:
7958 case FRV_CPU_TOMCAT:
7959 return 4;
7960 }
7961 }
7962
7963
7964 /* Implement TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. */
7965
7966 static int
frv_use_dfa_pipeline_interface(void)7967 frv_use_dfa_pipeline_interface (void)
7968 {
7969 return true;
7970 }
7971
7972 /* Update the register state information, to know about which registers are set
7973 or clobbered. */
7974
7975 static void
frv_registers_update(rtx x,unsigned char reg_state[],int modified[],int * p_num_mod,int flag)7976 frv_registers_update (rtx x,
7977 unsigned char reg_state[],
7978 int modified[],
7979 int *p_num_mod,
7980 int flag)
7981 {
7982 int regno, reg_max;
7983 rtx reg;
7984 rtx cond;
7985 const char *format;
7986 int length;
7987 int j;
7988
7989 switch (GET_CODE (x))
7990 {
7991 default:
7992 break;
7993
7994 /* Clobber just modifies a register, it doesn't make it live. */
7995 case CLOBBER:
7996 frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod,
7997 flag | REGSTATE_MODIFIED);
7998 return;
7999
8000 /* Pre modify updates the first argument, just references the second. */
8001 case PRE_MODIFY:
8002 case SET:
8003 frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod,
8004 flag | REGSTATE_MODIFIED | REGSTATE_LIVE);
8005 frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod, flag);
8006 return;
8007
8008 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8009 statement, but just to be sure, make sure it is the type of cond_exec
8010 we expect. */
8011 case COND_EXEC:
8012 cond = XEXP (x, 0);
8013 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8014 && GET_CODE (XEXP (cond, 0)) == REG
8015 && CR_P (REGNO (XEXP (cond, 0)))
8016 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8017 && INTVAL (XEXP (cond, 1)) == 0
8018 && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0)
8019 {
8020 frv_registers_update (cond, reg_state, modified, p_num_mod, flag);
8021 flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8022 | ((GET_CODE (cond) == NE)
8023 ? REGSTATE_IF_TRUE
8024 : REGSTATE_IF_FALSE));
8025
8026 frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod,
8027 flag);
8028 return;
8029 }
8030 else
8031 fatal_insn ("frv_registers_update", x);
8032
8033 /* MEM resets the modification bits. */
8034 case MEM:
8035 flag &= ~REGSTATE_MODIFIED;
8036 break;
8037
8038 /* See if we need to set the modified flag. */
8039 case SUBREG:
8040 reg = SUBREG_REG (x);
8041 if (GET_CODE (reg) == REG)
8042 {
8043 regno = subreg_regno (x);
8044 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8045 goto reg_common;
8046 }
8047 break;
8048
8049 case REG:
8050 regno = REGNO (x);
8051 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8052 /* Fall through. */
8053
8054 reg_common:
8055 if (flag & REGSTATE_MODIFIED)
8056 {
8057 flag &= REGSTATE_MASK;
8058 while (regno < reg_max)
8059 {
8060 int rs = reg_state[regno];
8061
8062 if (flag != rs)
8063 {
8064 if ((rs & REGSTATE_MODIFIED) == 0)
8065 {
8066 modified[ *p_num_mod ] = regno;
8067 (*p_num_mod)++;
8068 }
8069
8070 /* If the previous register state had the register as
8071 modified, possibly in some conditional execution context,
8072 and the current insn modifies in some other context, or
8073 outside of conditional execution, just mark the variable
8074 as modified. */
8075 else
8076 flag &= ~(REGSTATE_IF_EITHER | REGSTATE_CC_MASK);
8077
8078 reg_state[regno] = (rs | flag);
8079 }
8080 regno++;
8081 }
8082 }
8083 return;
8084 }
8085
8086
8087 length = GET_RTX_LENGTH (GET_CODE (x));
8088 format = GET_RTX_FORMAT (GET_CODE (x));
8089
8090 for (j = 0; j < length; ++j)
8091 {
8092 switch (format[j])
8093 {
8094 case 'e':
8095 frv_registers_update (XEXP (x, j), reg_state, modified, p_num_mod,
8096 flag);
8097 break;
8098
8099 case 'V':
8100 case 'E':
8101 if (XVEC (x, j) != 0)
8102 {
8103 int k;
8104 for (k = 0; k < XVECLEN (x, j); ++k)
8105 frv_registers_update (XVECEXP (x, j, k), reg_state, modified,
8106 p_num_mod, flag);
8107 }
8108 break;
8109
8110 default:
8111 /* Nothing to do. */
8112 break;
8113 }
8114 }
8115
8116 return;
8117 }
8118
8119
8120 /* Return if any registers in a hard register set were used an insn. */
8121
8122 static int
frv_registers_used_p(rtx x,unsigned char reg_state[],int flag)8123 frv_registers_used_p (rtx x, unsigned char reg_state[], int flag)
8124 {
8125 int regno, reg_max;
8126 rtx reg;
8127 rtx cond;
8128 rtx dest;
8129 const char *format;
8130 int result;
8131 int length;
8132 int j;
8133
8134 switch (GET_CODE (x))
8135 {
8136 default:
8137 break;
8138
8139 /* Skip clobber, that doesn't use the previous value. */
8140 case CLOBBER:
8141 return FALSE;
8142
8143 /* For SET, if a conditional jump has occurred in the same insn, only
8144 allow a set of a CR register if that register is not currently live.
8145 This is because on the FR-V, B0/B1 instructions are always last.
8146 Otherwise, don't look at the result, except within a MEM, but do look
8147 at the source. */
8148 case SET:
8149 dest = SET_DEST (x);
8150 if (flag & REGSTATE_CONDJUMP
8151 && GET_CODE (dest) == REG && CR_P (REGNO (dest))
8152 && (reg_state[ REGNO (dest) ] & REGSTATE_LIVE) != 0)
8153 return TRUE;
8154
8155 if (GET_CODE (dest) == MEM)
8156 {
8157 result = frv_registers_used_p (XEXP (dest, 0), reg_state, flag);
8158 if (result)
8159 return result;
8160 }
8161
8162 return frv_registers_used_p (SET_SRC (x), reg_state, flag);
8163
8164 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8165 statement, but just to be sure, make sure it is the type of cond_exec
8166 we expect. */
8167 case COND_EXEC:
8168 cond = XEXP (x, 0);
8169 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8170 && GET_CODE (XEXP (cond, 0)) == REG
8171 && CR_P (REGNO (XEXP (cond, 0)))
8172 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8173 && INTVAL (XEXP (cond, 1)) == 0
8174 && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0)
8175 {
8176 result = frv_registers_used_p (cond, reg_state, flag);
8177 if (result)
8178 return result;
8179
8180 flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8181 | ((GET_CODE (cond) == NE)
8182 ? REGSTATE_IF_TRUE
8183 : REGSTATE_IF_FALSE));
8184
8185 return frv_registers_used_p (XEXP (x, 1), reg_state, flag);
8186 }
8187 else
8188 fatal_insn ("frv_registers_used_p", x);
8189
8190 /* See if a register or subreg was modified in the same VLIW insn. */
8191 case SUBREG:
8192 reg = SUBREG_REG (x);
8193 if (GET_CODE (reg) == REG)
8194 {
8195 regno = subreg_regno (x);
8196 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8197 goto reg_common;
8198 }
8199 break;
8200
8201 case REG:
8202 regno = REGNO (x);
8203 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8204 /* Fall through. */
8205
8206 reg_common:
8207 while (regno < reg_max)
8208 {
8209 int rs = reg_state[regno];
8210
8211 if (rs & REGSTATE_MODIFIED)
8212 {
8213 int rs_if = rs & REGSTATE_IF_EITHER;
8214 int flag_if = flag & REGSTATE_IF_EITHER;
8215
8216 /* Simple modification, no conditional execution */
8217 if ((rs & REGSTATE_IF_EITHER) == 0)
8218 return TRUE;
8219
8220 /* See if the variable is only modified in a conditional
8221 execution expression opposite to the conditional execution
8222 expression that governs this expression (ie, true vs. false
8223 for the same CC register). If this isn't two halves of the
8224 same conditional expression, consider the register
8225 modified. */
8226 if (((rs_if == REGSTATE_IF_TRUE && flag_if == REGSTATE_IF_FALSE)
8227 || (rs_if == REGSTATE_IF_FALSE && flag_if == REGSTATE_IF_TRUE))
8228 && ((rs & REGSTATE_CC_MASK) == (flag & REGSTATE_CC_MASK)))
8229 ;
8230 else
8231 return TRUE;
8232 }
8233
8234 regno++;
8235 }
8236 return FALSE;
8237 }
8238
8239
8240 length = GET_RTX_LENGTH (GET_CODE (x));
8241 format = GET_RTX_FORMAT (GET_CODE (x));
8242
8243 for (j = 0; j < length; ++j)
8244 {
8245 switch (format[j])
8246 {
8247 case 'e':
8248 result = frv_registers_used_p (XEXP (x, j), reg_state, flag);
8249 if (result != 0)
8250 return result;
8251 break;
8252
8253 case 'V':
8254 case 'E':
8255 if (XVEC (x, j) != 0)
8256 {
8257 int k;
8258 for (k = 0; k < XVECLEN (x, j); ++k)
8259 {
8260 result = frv_registers_used_p (XVECEXP (x, j, k), reg_state,
8261 flag);
8262 if (result != 0)
8263 return result;
8264 }
8265 }
8266 break;
8267
8268 default:
8269 /* Nothing to do. */
8270 break;
8271 }
8272 }
8273
8274 return 0;
8275 }
8276
8277 /* Return if any registers in a hard register set were set in an insn. */
8278
8279 static int
frv_registers_set_p(rtx x,unsigned char reg_state[],int modify_p)8280 frv_registers_set_p (rtx x, unsigned char reg_state[], int modify_p)
8281 {
8282 int regno, reg_max;
8283 rtx reg;
8284 rtx cond;
8285 const char *format;
8286 int length;
8287 int j;
8288
8289 switch (GET_CODE (x))
8290 {
8291 default:
8292 break;
8293
8294 case CLOBBER:
8295 return frv_registers_set_p (XEXP (x, 0), reg_state, TRUE);
8296
8297 case PRE_MODIFY:
8298 case SET:
8299 return (frv_registers_set_p (XEXP (x, 0), reg_state, TRUE)
8300 || frv_registers_set_p (XEXP (x, 1), reg_state, FALSE));
8301
8302 case COND_EXEC:
8303 cond = XEXP (x, 0);
8304 /* Just to be sure, make sure it is the type of cond_exec we
8305 expect. */
8306 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8307 && GET_CODE (XEXP (cond, 0)) == REG
8308 && CR_P (REGNO (XEXP (cond, 0)))
8309 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8310 && INTVAL (XEXP (cond, 1)) == 0
8311 && !modify_p)
8312 return frv_registers_set_p (XEXP (x, 1), reg_state, modify_p);
8313 else
8314 fatal_insn ("frv_registers_set_p", x);
8315
8316 /* MEM resets the modification bits. */
8317 case MEM:
8318 modify_p = FALSE;
8319 break;
8320
8321 /* See if we need to set the modified modify_p. */
8322 case SUBREG:
8323 reg = SUBREG_REG (x);
8324 if (GET_CODE (reg) == REG)
8325 {
8326 regno = subreg_regno (x);
8327 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8328 goto reg_common;
8329 }
8330 break;
8331
8332 case REG:
8333 regno = REGNO (x);
8334 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8335 /* Fall through. */
8336
8337 reg_common:
8338 if (modify_p)
8339 while (regno < reg_max)
8340 {
8341 int rs = reg_state[regno];
8342
8343 if (rs & REGSTATE_MODIFIED)
8344 return TRUE;
8345 regno++;
8346 }
8347 return FALSE;
8348 }
8349
8350
8351 length = GET_RTX_LENGTH (GET_CODE (x));
8352 format = GET_RTX_FORMAT (GET_CODE (x));
8353
8354 for (j = 0; j < length; ++j)
8355 {
8356 switch (format[j])
8357 {
8358 case 'e':
8359 if (frv_registers_set_p (XEXP (x, j), reg_state, modify_p))
8360 return TRUE;
8361 break;
8362
8363 case 'V':
8364 case 'E':
8365 if (XVEC (x, j) != 0)
8366 {
8367 int k;
8368 for (k = 0; k < XVECLEN (x, j); ++k)
8369 if (frv_registers_set_p (XVECEXP (x, j, k), reg_state,
8370 modify_p))
8371 return TRUE;
8372 }
8373 break;
8374
8375 default:
8376 /* Nothing to do. */
8377 break;
8378 }
8379 }
8380
8381 return FALSE;
8382 }
8383
8384
8385 /* On the FR-V, this pass is used to rescan the insn chain, and pack
8386 conditional branches/calls/jumps, etc. with previous insns where it can. It
8387 does not reorder the instructions. We assume the scheduler left the flow
8388 information in a reasonable state. */
8389
8390 static void
frv_pack_insns(void)8391 frv_pack_insns (void)
8392 {
8393 state_t frv_state; /* frv state machine */
8394 int cur_start_vliw_p; /* current insn starts a VLIW insn */
8395 int next_start_vliw_p; /* next insn starts a VLIW insn */
8396 int cur_condjump_p; /* flag if current insn is a cond jump*/
8397 int next_condjump_p; /* flag if next insn is a cond jump */
8398 rtx insn;
8399 rtx link;
8400 int j;
8401 int num_mod = 0; /* # of modified registers */
8402 int modified[FIRST_PSEUDO_REGISTER]; /* registers modified in current VLIW */
8403 /* register state information */
8404 unsigned char reg_state[FIRST_PSEUDO_REGISTER];
8405
8406 /* If we weren't going to pack the insns, don't bother with this pass. */
8407 if (!optimize
8408 || !flag_schedule_insns_after_reload
8409 || TARGET_NO_VLIW_BRANCH
8410 || frv_issue_rate () == 1)
8411 return;
8412
8413 /* Set up the instruction and register states. */
8414 dfa_start ();
8415 frv_state = (state_t) xmalloc (state_size ());
8416 memset (reg_state, REGSTATE_DEAD, sizeof (reg_state));
8417
8418 /* Go through the insns, and repack the insns. */
8419 state_reset (frv_state);
8420 cur_start_vliw_p = FALSE;
8421 next_start_vliw_p = TRUE;
8422 cur_condjump_p = 0;
8423 next_condjump_p = 0;
8424
8425 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
8426 {
8427 enum rtx_code code = GET_CODE (insn);
8428 enum rtx_code pattern_code;
8429
8430 /* For basic block begin notes redo the live information, and skip other
8431 notes. */
8432 if (code == NOTE)
8433 {
8434 if (NOTE_LINE_NUMBER (insn) == (int)NOTE_INSN_BASIC_BLOCK)
8435 {
8436 regset live;
8437
8438 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
8439 reg_state[j] &= ~ REGSTATE_LIVE;
8440
8441 live = NOTE_BASIC_BLOCK (insn)->global_live_at_start;
8442 EXECUTE_IF_SET_IN_REG_SET(live, 0, j,
8443 {
8444 reg_state[j] |= REGSTATE_LIVE;
8445 });
8446 }
8447
8448 continue;
8449 }
8450
8451 /* Things like labels reset everything. */
8452 if (GET_RTX_CLASS (code) != 'i')
8453 {
8454 next_start_vliw_p = TRUE;
8455 continue;
8456 }
8457
8458 /* Clear the VLIW start flag on random USE and CLOBBER insns, which is
8459 set on the USE insn that precedes the return, and potentially on
8460 CLOBBERs for setting multiword variables. Also skip the ADDR_VEC
8461 holding the case table labels. */
8462 pattern_code = GET_CODE (PATTERN (insn));
8463 if (pattern_code == USE || pattern_code == CLOBBER
8464 || pattern_code == ADDR_VEC || pattern_code == ADDR_DIFF_VEC)
8465 {
8466 CLEAR_VLIW_START (insn);
8467 continue;
8468 }
8469
8470 cur_start_vliw_p = next_start_vliw_p;
8471 next_start_vliw_p = FALSE;
8472
8473 cur_condjump_p |= next_condjump_p;
8474 next_condjump_p = 0;
8475
8476 /* Unconditional branches and calls end the current VLIW insn. */
8477 if (code == CALL_INSN)
8478 {
8479 next_start_vliw_p = TRUE;
8480
8481 /* On a TOMCAT, calls must be alone in the VLIW insns. */
8482 if (frv_cpu_type == FRV_CPU_TOMCAT)
8483 cur_start_vliw_p = TRUE;
8484 }
8485 else if (code == JUMP_INSN)
8486 {
8487 if (any_condjump_p (insn))
8488 next_condjump_p = REGSTATE_CONDJUMP;
8489 else
8490 next_start_vliw_p = TRUE;
8491 }
8492
8493 /* Only allow setting a CCR register after a conditional branch. */
8494 else if (((cur_condjump_p & REGSTATE_CONDJUMP) != 0)
8495 && get_attr_type (insn) != TYPE_CCR)
8496 cur_start_vliw_p = TRUE;
8497
8498 /* Determine if we need to start a new VLIW instruction. */
8499 if (cur_start_vliw_p
8500 /* Do not check for register conflicts in a setlo instruction
8501 because any output or true dependencies will be with the
8502 partnering sethi instruction, with which it can be packed.
8503
8504 Although output dependencies are rare they are still
8505 possible. So check output dependencies in VLIW insn. */
8506 || (get_attr_type (insn) != TYPE_SETLO
8507 && (frv_registers_used_p (PATTERN (insn),
8508 reg_state,
8509 cur_condjump_p)
8510 || frv_registers_set_p (PATTERN (insn), reg_state, FALSE)))
8511 || state_transition (frv_state, insn) >= 0)
8512 {
8513 SET_VLIW_START (insn);
8514 state_reset (frv_state);
8515 state_transition (frv_state, insn);
8516 cur_condjump_p = 0;
8517
8518 /* Update the modified registers. */
8519 for (j = 0; j < num_mod; j++)
8520 reg_state[ modified[j] ] &= ~(REGSTATE_CC_MASK
8521 | REGSTATE_IF_EITHER
8522 | REGSTATE_MODIFIED);
8523
8524 num_mod = 0;
8525 }
8526 else
8527 CLEAR_VLIW_START (insn);
8528
8529 /* Record which registers are modified. */
8530 frv_registers_update (PATTERN (insn), reg_state, modified, &num_mod, 0);
8531
8532 /* Process the death notices. */
8533 for (link = REG_NOTES (insn);
8534 link != NULL_RTX;
8535 link = XEXP (link, 1))
8536 {
8537 rtx reg = XEXP (link, 0);
8538
8539 if (REG_NOTE_KIND (link) == REG_DEAD && GET_CODE (reg) == REG)
8540 {
8541 int regno = REGNO (reg);
8542 int n = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8543 for (; regno < n; regno++)
8544 reg_state[regno] &= ~REGSTATE_LIVE;
8545 }
8546 }
8547 }
8548
8549 free (frv_state);
8550 dfa_finish ();
8551 return;
8552 }
8553
8554
8555 #define def_builtin(name, type, code) \
8556 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8557
8558 struct builtin_description
8559 {
8560 enum insn_code icode;
8561 const char *name;
8562 enum frv_builtins code;
8563 enum rtx_code comparison;
8564 unsigned int flag;
8565 };
8566
8567 /* Media intrinsics that take a single, constant argument. */
8568
8569 static struct builtin_description bdesc_set[] =
8570 {
8571 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8572 };
8573
8574 /* Media intrinsics that take just one argument. */
8575
8576 static struct builtin_description bdesc_1arg[] =
8577 {
8578 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8579 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8580 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8581 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8582 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 }
8583 };
8584
8585 /* Media intrinsics that take two arguments. */
8586
8587 static struct builtin_description bdesc_2arg[] =
8588 {
8589 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8590 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8591 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8592 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8593 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8594 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8595 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8596 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8597 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8598 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8599 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8600 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8601 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8602 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8603 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8604 { CODE_FOR_mdpackh, "__MDPACKH", FRV_BUILTIN_MDPACKH, 0, 0 },
8605 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8606 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8607 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8608 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 }
8609 };
8610
8611 /* Media intrinsics that take two arguments, the first being an ACC number. */
8612
8613 static struct builtin_description bdesc_cut[] =
8614 {
8615 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8616 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8617 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8618 };
8619
8620 /* Two-argument media intrinsics with an immediate second argument. */
8621
8622 static struct builtin_description bdesc_2argimm[] =
8623 {
8624 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8625 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8626 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8627 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8628 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8629 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8630 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8631 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8632 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8633 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8634 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8635 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8636 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8637 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8638 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 }
8639 };
8640
8641 /* Media intrinsics that take two arguments and return void, the first argument
8642 being a pointer to 4 words in memory. */
8643
8644 static struct builtin_description bdesc_void2arg[] =
8645 {
8646 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8647 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8648 };
8649
8650 /* Media intrinsics that take three arguments, the first being a const_int that
8651 denotes an accumulator, and that return void. */
8652
8653 static struct builtin_description bdesc_void3arg[] =
8654 {
8655 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8656 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8657 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8658 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8659 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8660 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8661 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8662 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8663 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8664 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8665 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8666 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8667 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8668 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8669 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8670 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8671 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8672 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8673 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8674 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8675 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8676 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8677 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8678 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8679 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8680 };
8681
8682 /* Media intrinsics that take two accumulator numbers as argument and
8683 return void. */
8684
8685 static struct builtin_description bdesc_voidacc[] =
8686 {
8687 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8688 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8689 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8690 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8691 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8692 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8693 };
8694
8695 /* Initialize media builtins. */
8696
8697 static void
frv_init_builtins(void)8698 frv_init_builtins (void)
8699 {
8700 tree endlink = void_list_node;
8701 tree accumulator = integer_type_node;
8702 tree integer = integer_type_node;
8703 tree voidt = void_type_node;
8704 tree uhalf = short_unsigned_type_node;
8705 tree sword1 = long_integer_type_node;
8706 tree uword1 = long_unsigned_type_node;
8707 tree sword2 = long_long_integer_type_node;
8708 tree uword2 = long_long_unsigned_type_node;
8709 tree uword4 = build_pointer_type (uword1);
8710
8711 #define UNARY(RET, T1) \
8712 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8713
8714 #define BINARY(RET, T1, T2) \
8715 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8716 tree_cons (NULL_TREE, T2, endlink)))
8717
8718 #define TRINARY(RET, T1, T2, T3) \
8719 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8720 tree_cons (NULL_TREE, T2, \
8721 tree_cons (NULL_TREE, T3, endlink))))
8722
8723 tree void_ftype_void = build_function_type (voidt, endlink);
8724
8725 tree void_ftype_acc = UNARY (voidt, accumulator);
8726 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8727 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8728 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8729 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8730 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8731 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8732 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8733 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8734
8735 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8736 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8737 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8738 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8739 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8740 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8741 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8742 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8743 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8744 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8745 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8746
8747 tree sw1_ftype_int = UNARY (sword1, integer);
8748 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8749 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8750
8751 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8752 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8753 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8754 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8755 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8756
8757 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8758
8759 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8760 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8761 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8762 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8763 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8764 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8765 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8766 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8767 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8768 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8769 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8770 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8771 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8772 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8773 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8774 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8775 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8776 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8777 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8778 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8779 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8780 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8781 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8782 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8783 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8784 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8785 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8786 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8787 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8788 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8789 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8790 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8791 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8792 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8793 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8794 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8795 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8796 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8797 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8798 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8799 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8800 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8801 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8802 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8803 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8804 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8805 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8806 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8807 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8808 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2, FRV_BUILTIN_MDPACKH);
8809 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8810 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8811 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8812 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8813 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8814 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8815 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8816 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8817 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8818 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8819 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8820 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8821 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8822 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8823 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8824 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8825 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8826 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8827 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8828 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8829 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8830 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8831 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8832 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8833 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8834 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8835 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8836 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8837 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8838 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8839 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8840 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8841 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8842 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8843
8844 #undef UNARY
8845 #undef BINARY
8846 #undef TRINARY
8847 }
8848
8849 /* Set the names for various arithmetic operations according to the
8850 FRV ABI. */
8851 static void
frv_init_libfuncs(void)8852 frv_init_libfuncs (void)
8853 {
8854 set_optab_libfunc (smod_optab, SImode, "__modi");
8855 set_optab_libfunc (umod_optab, SImode, "__umodi");
8856
8857 set_optab_libfunc (add_optab, DImode, "__addll");
8858 set_optab_libfunc (sub_optab, DImode, "__subll");
8859 set_optab_libfunc (smul_optab, DImode, "__mulll");
8860 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8861 set_optab_libfunc (smod_optab, DImode, "__modll");
8862 set_optab_libfunc (umod_optab, DImode, "__umodll");
8863 set_optab_libfunc (and_optab, DImode, "__andll");
8864 set_optab_libfunc (ior_optab, DImode, "__orll");
8865 set_optab_libfunc (xor_optab, DImode, "__xorll");
8866 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8867
8868 set_optab_libfunc (add_optab, SFmode, "__addf");
8869 set_optab_libfunc (sub_optab, SFmode, "__subf");
8870 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8871 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8872
8873 set_optab_libfunc (add_optab, DFmode, "__addd");
8874 set_optab_libfunc (sub_optab, DFmode, "__subd");
8875 set_optab_libfunc (smul_optab, DFmode, "__muld");
8876 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8877
8878 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8879 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8880
8881 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8882 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8883 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8884 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8885
8886 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8887 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8888 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8889 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8890
8891 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8892 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8893 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8894 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8895 }
8896
8897 /* Convert an integer constant to an accumulator register. ICODE is the
8898 code of the target instruction, OPNUM is the number of the
8899 accumulator operand and OPVAL is the constant integer. Try both
8900 ACC and ACCG registers; only report an error if neither fit the
8901 instruction. */
8902
8903 static rtx
frv_int_to_acc(enum insn_code icode,int opnum,rtx opval)8904 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8905 {
8906 rtx reg;
8907
8908 if (GET_CODE (opval) != CONST_INT)
8909 {
8910 error ("accumulator is not a constant integer");
8911 return NULL_RTX;
8912 }
8913 if (! IN_RANGE_P (INTVAL (opval), 0, NUM_ACCS - 1))
8914 {
8915 error ("accumulator number is out of bounds");
8916 return NULL_RTX;
8917 }
8918
8919 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8920 ACC_FIRST + INTVAL (opval));
8921 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8922 REGNO (reg) = ACCG_FIRST + INTVAL (opval);
8923
8924 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8925 {
8926 error ("inappropriate accumulator for `%s'", insn_data[icode].name);
8927 return NULL_RTX;
8928 }
8929 return reg;
8930 }
8931
8932 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8933 should have. */
8934
8935 static enum machine_mode
frv_matching_accg_mode(enum machine_mode mode)8936 frv_matching_accg_mode (enum machine_mode mode)
8937 {
8938 switch (mode)
8939 {
8940 case V4SImode:
8941 return V4QImode;
8942
8943 case DImode:
8944 return HImode;
8945
8946 case SImode:
8947 return QImode;
8948
8949 default:
8950 abort ();
8951 }
8952 }
8953
8954 /* Return the accumulator guard that should be paired with accumulator
8955 register ACC. The mode of the returned register is in the same
8956 class as ACC, but is four times smaller. */
8957
8958 rtx
frv_matching_accg_for_acc(rtx acc)8959 frv_matching_accg_for_acc (rtx acc)
8960 {
8961 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8962 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8963 }
8964
8965 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
8966 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
8967 list. */
8968
8969 static rtx
frv_read_argument(tree * arglistptr)8970 frv_read_argument (tree *arglistptr)
8971 {
8972 tree next = TREE_VALUE (*arglistptr);
8973 *arglistptr = TREE_CHAIN (*arglistptr);
8974 return expand_expr (next, NULL_RTX, VOIDmode, 0);
8975 }
8976
8977 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8978 The instruction should require a constant operand of some sort. The
8979 function prints an error if OPVAL is not valid. */
8980
8981 static int
frv_check_constant_argument(enum insn_code icode,int opnum,rtx opval)8982 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8983 {
8984 if (GET_CODE (opval) != CONST_INT)
8985 {
8986 error ("`%s' expects a constant argument", insn_data[icode].name);
8987 return FALSE;
8988 }
8989 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8990 {
8991 error ("constant argument out of range for `%s'", insn_data[icode].name);
8992 return FALSE;
8993 }
8994 return TRUE;
8995 }
8996
8997 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8998 if it's not null, has the right mode, and satisfies operand 0's
8999 predicate. */
9000
9001 static rtx
frv_legitimize_target(enum insn_code icode,rtx target)9002 frv_legitimize_target (enum insn_code icode, rtx target)
9003 {
9004 enum machine_mode mode = insn_data[icode].operand[0].mode;
9005
9006 if (! target
9007 || GET_MODE (target) != mode
9008 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
9009 return gen_reg_rtx (mode);
9010 else
9011 return target;
9012 }
9013
9014 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9015 check whether ARG satisfies the operand's constraints. If it doesn't,
9016 copy ARG to a temporary register and return that. Otherwise return ARG
9017 itself. */
9018
9019 static rtx
frv_legitimize_argument(enum insn_code icode,int opnum,rtx arg)9020 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
9021 {
9022 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
9023
9024 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
9025 return arg;
9026 else
9027 return copy_to_mode_reg (mode, arg);
9028 }
9029
9030 /* Expand builtins that take a single, constant argument. At the moment,
9031 only MHDSETS falls into this category. */
9032
9033 static rtx
frv_expand_set_builtin(enum insn_code icode,tree arglist,rtx target)9034 frv_expand_set_builtin (enum insn_code icode, tree arglist, rtx target)
9035 {
9036 rtx pat;
9037 rtx op0 = frv_read_argument (&arglist);
9038
9039 if (! frv_check_constant_argument (icode, 1, op0))
9040 return NULL_RTX;
9041
9042 target = frv_legitimize_target (icode, target);
9043 pat = GEN_FCN (icode) (target, op0);
9044 if (! pat)
9045 return NULL_RTX;
9046
9047 emit_insn (pat);
9048 return target;
9049 }
9050
9051 /* Expand builtins that take one operand. */
9052
9053 static rtx
frv_expand_unop_builtin(enum insn_code icode,tree arglist,rtx target)9054 frv_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
9055 {
9056 rtx pat;
9057 rtx op0 = frv_read_argument (&arglist);
9058
9059 target = frv_legitimize_target (icode, target);
9060 op0 = frv_legitimize_argument (icode, 1, op0);
9061 pat = GEN_FCN (icode) (target, op0);
9062 if (! pat)
9063 return NULL_RTX;
9064
9065 emit_insn (pat);
9066 return target;
9067 }
9068
9069 /* Expand builtins that take two operands. */
9070
9071 static rtx
frv_expand_binop_builtin(enum insn_code icode,tree arglist,rtx target)9072 frv_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
9073 {
9074 rtx pat;
9075 rtx op0 = frv_read_argument (&arglist);
9076 rtx op1 = frv_read_argument (&arglist);
9077
9078 target = frv_legitimize_target (icode, target);
9079 op0 = frv_legitimize_argument (icode, 1, op0);
9080 op1 = frv_legitimize_argument (icode, 2, op1);
9081 pat = GEN_FCN (icode) (target, op0, op1);
9082 if (! pat)
9083 return NULL_RTX;
9084
9085 emit_insn (pat);
9086 return target;
9087 }
9088
9089 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9090 one. */
9091
9092 static rtx
frv_expand_cut_builtin(enum insn_code icode,tree arglist,rtx target)9093 frv_expand_cut_builtin (enum insn_code icode, tree arglist, rtx target)
9094 {
9095 rtx pat;
9096 rtx op0 = frv_read_argument (&arglist);
9097 rtx op1 = frv_read_argument (&arglist);
9098 rtx op2;
9099
9100 target = frv_legitimize_target (icode, target);
9101 op0 = frv_int_to_acc (icode, 1, op0);
9102 if (! op0)
9103 return NULL_RTX;
9104
9105 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
9106 {
9107 if (! frv_check_constant_argument (icode, 2, op1))
9108 return NULL_RTX;
9109 }
9110 else
9111 op1 = frv_legitimize_argument (icode, 2, op1);
9112
9113 op2 = frv_matching_accg_for_acc (op0);
9114 pat = GEN_FCN (icode) (target, op0, op1, op2);
9115 if (! pat)
9116 return NULL_RTX;
9117
9118 emit_insn (pat);
9119 return target;
9120 }
9121
9122 /* Expand builtins that take two operands and the second is immediate. */
9123
9124 static rtx
frv_expand_binopimm_builtin(enum insn_code icode,tree arglist,rtx target)9125 frv_expand_binopimm_builtin (enum insn_code icode, tree arglist, rtx target)
9126 {
9127 rtx pat;
9128 rtx op0 = frv_read_argument (&arglist);
9129 rtx op1 = frv_read_argument (&arglist);
9130
9131 if (! frv_check_constant_argument (icode, 2, op1))
9132 return NULL_RTX;
9133
9134 target = frv_legitimize_target (icode, target);
9135 op0 = frv_legitimize_argument (icode, 1, op0);
9136 pat = GEN_FCN (icode) (target, op0, op1);
9137 if (! pat)
9138 return NULL_RTX;
9139
9140 emit_insn (pat);
9141 return target;
9142 }
9143
9144 /* Expand builtins that take two operands, the first operand being a pointer to
9145 ints and return void. */
9146
9147 static rtx
frv_expand_voidbinop_builtin(enum insn_code icode,tree arglist)9148 frv_expand_voidbinop_builtin (enum insn_code icode, tree arglist)
9149 {
9150 rtx pat;
9151 rtx op0 = frv_read_argument (&arglist);
9152 rtx op1 = frv_read_argument (&arglist);
9153 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9154 rtx addr;
9155
9156 if (GET_CODE (op0) != MEM)
9157 {
9158 rtx reg = op0;
9159
9160 if (! offsettable_address_p (0, mode0, op0))
9161 {
9162 reg = gen_reg_rtx (Pmode);
9163 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9164 }
9165
9166 op0 = gen_rtx_MEM (SImode, reg);
9167 }
9168
9169 addr = XEXP (op0, 0);
9170 if (! offsettable_address_p (0, mode0, addr))
9171 addr = copy_to_mode_reg (Pmode, op0);
9172
9173 op0 = change_address (op0, V4SImode, addr);
9174 op1 = frv_legitimize_argument (icode, 1, op1);
9175 pat = GEN_FCN (icode) (op0, op1);
9176 if (! pat)
9177 return 0;
9178
9179 emit_insn (pat);
9180 return 0;
9181 }
9182
9183 /* Expand builtins that take three operands and return void. The first
9184 argument must be a constant that describes a pair or quad accumulators. A
9185 fourth argument is created that is the accumulator guard register that
9186 corresponds to the accumulator. */
9187
9188 static rtx
frv_expand_voidtriop_builtin(enum insn_code icode,tree arglist)9189 frv_expand_voidtriop_builtin (enum insn_code icode, tree arglist)
9190 {
9191 rtx pat;
9192 rtx op0 = frv_read_argument (&arglist);
9193 rtx op1 = frv_read_argument (&arglist);
9194 rtx op2 = frv_read_argument (&arglist);
9195 rtx op3;
9196
9197 op0 = frv_int_to_acc (icode, 0, op0);
9198 if (! op0)
9199 return NULL_RTX;
9200
9201 op1 = frv_legitimize_argument (icode, 1, op1);
9202 op2 = frv_legitimize_argument (icode, 2, op2);
9203 op3 = frv_matching_accg_for_acc (op0);
9204 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9205 if (! pat)
9206 return NULL_RTX;
9207
9208 emit_insn (pat);
9209 return NULL_RTX;
9210 }
9211
9212 /* Expand builtins that perform accumulator-to-accumulator operations.
9213 These builtins take two accumulator numbers as argument and return
9214 void. */
9215
9216 static rtx
frv_expand_voidaccop_builtin(enum insn_code icode,tree arglist)9217 frv_expand_voidaccop_builtin (enum insn_code icode, tree arglist)
9218 {
9219 rtx pat;
9220 rtx op0 = frv_read_argument (&arglist);
9221 rtx op1 = frv_read_argument (&arglist);
9222 rtx op2;
9223 rtx op3;
9224
9225 op0 = frv_int_to_acc (icode, 0, op0);
9226 if (! op0)
9227 return NULL_RTX;
9228
9229 op1 = frv_int_to_acc (icode, 1, op1);
9230 if (! op1)
9231 return NULL_RTX;
9232
9233 op2 = frv_matching_accg_for_acc (op0);
9234 op3 = frv_matching_accg_for_acc (op1);
9235 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9236 if (! pat)
9237 return NULL_RTX;
9238
9239 emit_insn (pat);
9240 return NULL_RTX;
9241 }
9242
9243 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9244 number as argument. */
9245
9246 static rtx
frv_expand_mclracc_builtin(tree arglist)9247 frv_expand_mclracc_builtin (tree arglist)
9248 {
9249 enum insn_code icode = CODE_FOR_mclracc;
9250 rtx pat;
9251 rtx op0 = frv_read_argument (&arglist);
9252
9253 op0 = frv_int_to_acc (icode, 0, op0);
9254 if (! op0)
9255 return NULL_RTX;
9256
9257 pat = GEN_FCN (icode) (op0);
9258 if (pat)
9259 emit_insn (pat);
9260
9261 return NULL_RTX;
9262 }
9263
9264 /* Expand builtins that take no arguments. */
9265
9266 static rtx
frv_expand_noargs_builtin(enum insn_code icode)9267 frv_expand_noargs_builtin (enum insn_code icode)
9268 {
9269 rtx pat = GEN_FCN (icode) (GEN_INT (0));
9270 if (pat)
9271 emit_insn (pat);
9272
9273 return NULL_RTX;
9274 }
9275
9276 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9277 number or accumulator guard number as argument and return an SI integer. */
9278
9279 static rtx
frv_expand_mrdacc_builtin(enum insn_code icode,tree arglist)9280 frv_expand_mrdacc_builtin (enum insn_code icode, tree arglist)
9281 {
9282 rtx pat;
9283 rtx target = gen_reg_rtx (SImode);
9284 rtx op0 = frv_read_argument (&arglist);
9285
9286 op0 = frv_int_to_acc (icode, 1, op0);
9287 if (! op0)
9288 return NULL_RTX;
9289
9290 pat = GEN_FCN (icode) (target, op0);
9291 if (! pat)
9292 return NULL_RTX;
9293
9294 emit_insn (pat);
9295 return target;
9296 }
9297
9298 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9299 accumulator guard as their first argument and an SImode value as their
9300 second. */
9301
9302 static rtx
frv_expand_mwtacc_builtin(enum insn_code icode,tree arglist)9303 frv_expand_mwtacc_builtin (enum insn_code icode, tree arglist)
9304 {
9305 rtx pat;
9306 rtx op0 = frv_read_argument (&arglist);
9307 rtx op1 = frv_read_argument (&arglist);
9308
9309 op0 = frv_int_to_acc (icode, 0, op0);
9310 if (! op0)
9311 return NULL_RTX;
9312
9313 op1 = frv_legitimize_argument (icode, 1, op1);
9314 pat = GEN_FCN (icode) (op0, op1);
9315 if (pat)
9316 emit_insn (pat);
9317
9318 return NULL_RTX;
9319 }
9320
9321 /* Expand builtins. */
9322
9323 static rtx
frv_expand_builtin(tree exp,rtx target,rtx subtarget ATTRIBUTE_UNUSED,enum machine_mode mode ATTRIBUTE_UNUSED,int ignore ATTRIBUTE_UNUSED)9324 frv_expand_builtin (tree exp,
9325 rtx target,
9326 rtx subtarget ATTRIBUTE_UNUSED,
9327 enum machine_mode mode ATTRIBUTE_UNUSED,
9328 int ignore ATTRIBUTE_UNUSED)
9329 {
9330 tree arglist = TREE_OPERAND (exp, 1);
9331 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9332 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9333 unsigned i;
9334 struct builtin_description *d;
9335
9336 if (! TARGET_MEDIA)
9337 {
9338 error ("media functions are not available unless -mmedia is used");
9339 return NULL_RTX;
9340 }
9341
9342 switch (fcode)
9343 {
9344 case FRV_BUILTIN_MCOP1:
9345 case FRV_BUILTIN_MCOP2:
9346 case FRV_BUILTIN_MDUNPACKH:
9347 case FRV_BUILTIN_MBTOHE:
9348 if (! TARGET_MEDIA_REV1)
9349 {
9350 error ("this media function is only available on the fr500");
9351 return NULL_RTX;
9352 }
9353 break;
9354
9355 case FRV_BUILTIN_MQXMACHS:
9356 case FRV_BUILTIN_MQXMACXHS:
9357 case FRV_BUILTIN_MQMACXHS:
9358 case FRV_BUILTIN_MADDACCS:
9359 case FRV_BUILTIN_MSUBACCS:
9360 case FRV_BUILTIN_MASACCS:
9361 case FRV_BUILTIN_MDADDACCS:
9362 case FRV_BUILTIN_MDSUBACCS:
9363 case FRV_BUILTIN_MDASACCS:
9364 case FRV_BUILTIN_MABSHS:
9365 case FRV_BUILTIN_MDROTLI:
9366 case FRV_BUILTIN_MCPLHI:
9367 case FRV_BUILTIN_MCPLI:
9368 case FRV_BUILTIN_MDCUTSSI:
9369 case FRV_BUILTIN_MQSATHS:
9370 case FRV_BUILTIN_MHSETLOS:
9371 case FRV_BUILTIN_MHSETLOH:
9372 case FRV_BUILTIN_MHSETHIS:
9373 case FRV_BUILTIN_MHSETHIH:
9374 case FRV_BUILTIN_MHDSETS:
9375 case FRV_BUILTIN_MHDSETH:
9376 if (! TARGET_MEDIA_REV2)
9377 {
9378 error ("this media function is only available on the fr400");
9379 return NULL_RTX;
9380 }
9381 break;
9382
9383 default:
9384 break;
9385 }
9386
9387 /* Expand unique builtins. */
9388
9389 switch (fcode)
9390 {
9391 case FRV_BUILTIN_MTRAP:
9392 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9393
9394 case FRV_BUILTIN_MCLRACC:
9395 return frv_expand_mclracc_builtin (arglist);
9396
9397 case FRV_BUILTIN_MCLRACCA:
9398 if (TARGET_ACC_8)
9399 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9400 else
9401 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9402
9403 case FRV_BUILTIN_MRDACC:
9404 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist);
9405
9406 case FRV_BUILTIN_MRDACCG:
9407 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist);
9408
9409 case FRV_BUILTIN_MWTACC:
9410 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist);
9411
9412 case FRV_BUILTIN_MWTACCG:
9413 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist);
9414
9415 default:
9416 break;
9417 }
9418
9419 /* Expand groups of builtins. */
9420
9421 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9422 if (d->code == fcode)
9423 return frv_expand_set_builtin (d->icode, arglist, target);
9424
9425 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9426 if (d->code == fcode)
9427 return frv_expand_unop_builtin (d->icode, arglist, target);
9428
9429 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9430 if (d->code == fcode)
9431 return frv_expand_binop_builtin (d->icode, arglist, target);
9432
9433 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9434 if (d->code == fcode)
9435 return frv_expand_cut_builtin (d->icode, arglist, target);
9436
9437 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9438 if (d->code == fcode)
9439 return frv_expand_binopimm_builtin (d->icode, arglist, target);
9440
9441 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9442 if (d->code == fcode)
9443 return frv_expand_voidbinop_builtin (d->icode, arglist);
9444
9445 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9446 if (d->code == fcode)
9447 return frv_expand_voidtriop_builtin (d->icode, arglist);
9448
9449 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9450 if (d->code == fcode)
9451 return frv_expand_voidaccop_builtin (d->icode, arglist);
9452
9453 return 0;
9454 }
9455
9456 static bool
frv_in_small_data_p(tree decl)9457 frv_in_small_data_p (tree decl)
9458 {
9459 HOST_WIDE_INT size;
9460 tree section_name;
9461
9462 /* Don't apply the -G flag to internal compiler structures. We
9463 should leave such structures in the main data section, partly
9464 for efficiency and partly because the size of some of them
9465 (such as C++ typeinfos) is not known until later. */
9466 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9467 return false;
9468
9469 /* If we already know which section the decl should be in, see if
9470 it's a small data section. */
9471 section_name = DECL_SECTION_NAME (decl);
9472 if (section_name)
9473 {
9474 if (TREE_CODE (section_name) != STRING_CST)
9475 abort ();
9476 if (frv_string_begins_with (section_name, ".sdata"))
9477 return true;
9478 if (frv_string_begins_with (section_name, ".sbss"))
9479 return true;
9480 return false;
9481 }
9482
9483 size = int_size_in_bytes (TREE_TYPE (decl));
9484 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9485 return true;
9486
9487 return false;
9488 }
9489
9490 static bool
frv_rtx_costs(rtx x,int code ATTRIBUTE_UNUSED,int outer_code ATTRIBUTE_UNUSED,int * total)9491 frv_rtx_costs (rtx x,
9492 int code ATTRIBUTE_UNUSED,
9493 int outer_code ATTRIBUTE_UNUSED,
9494 int *total)
9495 {
9496 switch (code)
9497 {
9498 case CONST_INT:
9499 /* Make 12 bit integers really cheap. */
9500 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9501 {
9502 *total = 0;
9503 return true;
9504 }
9505 /* Fall through. */
9506
9507 case CONST:
9508 case LABEL_REF:
9509 case SYMBOL_REF:
9510 case CONST_DOUBLE:
9511 *total = COSTS_N_INSNS (2);
9512 return true;
9513
9514 case PLUS:
9515 case MINUS:
9516 case AND:
9517 case IOR:
9518 case XOR:
9519 case ASHIFT:
9520 case ASHIFTRT:
9521 case LSHIFTRT:
9522 case NOT:
9523 case NEG:
9524 case COMPARE:
9525 if (GET_MODE (x) == SImode)
9526 *total = COSTS_N_INSNS (1);
9527 else if (GET_MODE (x) == DImode)
9528 *total = COSTS_N_INSNS (2);
9529 else
9530 *total = COSTS_N_INSNS (3);
9531 return true;
9532
9533 case MULT:
9534 if (GET_MODE (x) == SImode)
9535 *total = COSTS_N_INSNS (2);
9536 else
9537 *total = COSTS_N_INSNS (6); /* guess */
9538 return true;
9539
9540 case DIV:
9541 case UDIV:
9542 case MOD:
9543 case UMOD:
9544 *total = COSTS_N_INSNS (18);
9545 return true;
9546
9547 default:
9548 return false;
9549 }
9550 }
9551
9552 static void
frv_asm_out_constructor(rtx symbol,int priority ATTRIBUTE_UNUSED)9553 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9554 {
9555 ctors_section ();
9556 assemble_align (POINTER_SIZE);
9557 assemble_integer_with_op ("\t.picptr\t", symbol);
9558 }
9559
9560 static void
frv_asm_out_destructor(rtx symbol,int priority ATTRIBUTE_UNUSED)9561 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9562 {
9563 dtors_section ();
9564 assemble_align (POINTER_SIZE);
9565 assemble_integer_with_op ("\t.picptr\t", symbol);
9566 }
9567