1 /*
2  * Copyright 2008-2012 Freescale Semiconductor Inc.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *     * Redistributions of source code must retain the above copyright
7  *       notice, this list of conditions and the following disclaimer.
8  *     * Redistributions in binary form must reproduce the above copyright
9  *       notice, this list of conditions and the following disclaimer in the
10  *       documentation and/or other materials provided with the distribution.
11  *     * Neither the name of Freescale Semiconductor nor the
12  *       names of its contributors may be used to endorse or promote products
13  *       derived from this software without specific prior written permission.
14  *
15  *
16  * ALTERNATIVELY, this software may be distributed under the terms of the
17  * GNU General Public License ("GPL") as published by the Free Software
18  * Foundation, either version 2 of that License or (at your option) any
19  * later version.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
22  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 
34 /******************************************************************************
35  @File          fm_port.h
36 
37  @Description   FM Port internal structures and definitions.
38 *//***************************************************************************/
39 #ifndef __FM_PORT_H
40 #define __FM_PORT_H
41 
42 #include "error_ext.h"
43 #include "std_ext.h"
44 #include "fm_port_ext.h"
45 
46 #include "fm_common.h"
47 #include "fm_sp_common.h"
48 #include "fsl_fman_sp.h"
49 #include "fm_port_ext.h"
50 #include "fsl_fman_port.h"
51 
52 #define __ERR_MODULE__  MODULE_FM_PORT
53 
54 
55 #define MIN_EXT_BUF_SIZE                                64
56 #define DATA_ALIGNMENT                                  64
57 #define MAX_LIODN_OFFSET                                64
58 #define MAX_PORT_FIFO_SIZE                              MIN(BMI_MAX_FIFO_SIZE, 1024*BMI_FIFO_UNITS)
59 
60 /**************************************************************************//**
61  @Description       Memory Map defines
62 *//***************************************************************************/
63 #define BMI_PORT_REGS_OFFSET                            0
64 #define QMI_PORT_REGS_OFFSET                            0x400
65 #define PRS_PORT_REGS_OFFSET                            0x800
66 
67 /**************************************************************************//**
68  @Description       defaults
69 *//***************************************************************************/
70 #define DEFAULT_PORT_deqHighPriority_1G                 FALSE
71 #define DEFAULT_PORT_deqHighPriority_10G                TRUE
72 #define DEFAULT_PORT_deqType                            e_FM_PORT_DEQ_TYPE1
73 #define DEFAULT_PORT_deqPrefetchOption                  e_FM_PORT_DEQ_FULL_PREFETCH
74 #define DEFAULT_PORT_deqPrefetchOption_HC               e_FM_PORT_DEQ_NO_PREFETCH
75 #define DEFAULT_PORT_deqByteCnt_10G                     0x1400
76 #define DEFAULT_PORT_deqByteCnt_1G                      0x400
77 #define DEFAULT_PORT_bufferPrefixContent_privDataSize   DEFAULT_FM_SP_bufferPrefixContent_privDataSize
78 #define DEFAULT_PORT_bufferPrefixContent_passPrsResult  DEFAULT_FM_SP_bufferPrefixContent_passPrsResult
79 #define DEFAULT_PORT_bufferPrefixContent_passTimeStamp  DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp
80 #define DEFAULT_PORT_bufferPrefixContent_allOtherPCDInfo DEFAULT_FM_SP_bufferPrefixContent_allOtherPCDInfo
81 #define DEFAULT_PORT_bufferPrefixContent_dataAlign      DEFAULT_FM_SP_bufferPrefixContent_dataAlign
82 #define DEFAULT_PORT_cheksumLastBytesIgnore             0
83 #define DEFAULT_PORT_cutBytesFromEnd                    4
84 #define DEFAULT_PORT_fifoDeqPipelineDepth_IM            2
85 
86 #define DEFAULT_PORT_frmDiscardOverride                 FALSE
87 
88 #define DEFAULT_PORT_dmaSwapData                        (e_FmDmaSwapOption)DEFAULT_FMAN_SP_DMA_SWAP_DATA
89 #define DEFAULT_PORT_dmaIntContextCacheAttr             (e_FmDmaCacheOption)DEFAULT_FMAN_SP_DMA_INT_CONTEXT_CACHE_ATTR
90 #define DEFAULT_PORT_dmaHeaderCacheAttr                 (e_FmDmaCacheOption)DEFAULT_FMAN_SP_DMA_HEADER_CACHE_ATTR
91 #define DEFAULT_PORT_dmaScatterGatherCacheAttr          (e_FmDmaCacheOption)DEFAULT_FMAN_SP_DMA_SCATTER_GATHER_CACHE_ATTR
92 #define DEFAULT_PORT_dmaWriteOptimize                   DEFAULT_FMAN_SP_DMA_WRITE_OPTIMIZE
93 
94 #define DEFAULT_PORT_noScatherGather                    DEFAULT_FMAN_SP_NO_SCATTER_GATHER
95 #define DEFAULT_PORT_forwardIntContextReuse             FALSE
96 #define DEFAULT_PORT_BufMargins_startMargins            32
97 #define DEFAULT_PORT_BufMargins_endMargins              0
98 #define DEFAULT_PORT_syncReq                            TRUE
99 #define DEFAULT_PORT_syncReqForHc                       FALSE
100 #define DEFAULT_PORT_color                              e_FM_PORT_COLOR_GREEN
101 #define DEFAULT_PORT_errorsToDiscard                    FM_PORT_FRM_ERR_CLS_DISCARD
102 /* #define DEFAULT_PORT_dualRateLimitScaleDown             e_FM_PORT_DUAL_RATE_LIMITER_NONE */
103 /* #define DEFAULT_PORT_rateLimitBurstSizeHighGranularity  FALSE */
104 #define DEFAULT_PORT_exception                          IM_EV_BSY
105 #define DEFAULT_PORT_maxFrameLength                     9600
106 
107 #define DEFAULT_notSupported                            0xff
108 
109 #if (DPAA_VERSION < 11)
110 #define DEFAULT_PORT_rxFifoPriElevationLevel            MAX_PORT_FIFO_SIZE
111 #define DEFAULT_PORT_rxFifoThreshold                    (MAX_PORT_FIFO_SIZE*3/4)
112 
113 #define DEFAULT_PORT_txFifoMinFillLevel                 0
114 #define DEFAULT_PORT_txFifoLowComfLevel                 (5*KILOBYTE)
115 #define DEFAULT_PORT_fifoDeqPipelineDepth_1G            1
116 #define DEFAULT_PORT_fifoDeqPipelineDepth_10G           4
117 
118 #define DEFAULT_PORT_fifoDeqPipelineDepth_OH            2
119 
120 /* Host command port MUST NOT be changed to more than 1 !!! */
121 #define DEFAULT_PORT_numOfTasks(type)                       \
122     (uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) ||        \
123                 ((type) == e_FM_PORT_TYPE_TX_10G)) ? 16 :   \
124                ((((type) == e_FM_PORT_TYPE_RX) ||           \
125                  ((type) == e_FM_PORT_TYPE_TX) ||           \
126                  ((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) ? 3 : 1))
127 
128 #define DEFAULT_PORT_extraNumOfTasks(type)                  \
129     (uint32_t)(((type) == e_FM_PORT_TYPE_RX_10G)  ? 8 :    \
130                (((type) == e_FM_PORT_TYPE_RX) ? 2 : 0))
131 
132 #define DEFAULT_PORT_numOfOpenDmas(type)                    \
133     (uint32_t)((((type) == e_FM_PORT_TYPE_TX_10G) ||        \
134                 ((type) == e_FM_PORT_TYPE_RX_10G)) ? 8 : 1 )
135 
136 #define DEFAULT_PORT_extraNumOfOpenDmas(type)               \
137     (uint32_t)(((type) == e_FM_PORT_TYPE_RX_10G) ? 8 :    \
138                (((type) == e_FM_PORT_TYPE_RX) ? 1 : 0))
139 
140 #define DEFAULT_PORT_numOfFifoBufs(type)                    \
141     (uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) ||        \
142                 ((type) == e_FM_PORT_TYPE_TX_10G)) ? 48 :   \
143                 ((type) == e_FM_PORT_TYPE_RX) ? 45 :        \
144                 ((type) == e_FM_PORT_TYPE_TX) ? 44 : 8)
145 
146 #define DEFAULT_PORT_extraNumOfFifoBufs             0
147 
148 #else  /* (DPAA_VERSION < 11) */
149 /* Defaults are registers' reset values */
150 #define DEFAULT_PORT_rxFifoPriElevationLevel            MAX_PORT_FIFO_SIZE
151 #define DEFAULT_PORT_rxFifoThreshold                    MAX_PORT_FIFO_SIZE
152 
153 #define DEFAULT_PORT_txFifoMinFillLevel                 0
154 #define DEFAULT_PORT_txFifoLowComfLevel                 (5 * KILOBYTE)
155 #define DEFAULT_PORT_fifoDeqPipelineDepth_1G            2
156 #define DEFAULT_PORT_fifoDeqPipelineDepth_10G           4
157 
158 #define DEFAULT_PORT_fifoDeqPipelineDepth_OH            2
159 
160 #define DEFAULT_PORT_numOfTasks(type)                       \
161     (uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) ||        \
162                 ((type) == e_FM_PORT_TYPE_TX_10G)) ? 14 :   \
163                (((type) == e_FM_PORT_TYPE_RX) ||            \
164                  ((type) == e_FM_PORT_TYPE_TX)) ? 4 :       \
165                  ((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) ? 6 : 1)
166 
167 #define DEFAULT_PORT_extraNumOfTasks(type)          0
168 
169 #define DEFAULT_PORT_numOfOpenDmas(type)                    \
170     (uint32_t)(((type) == e_FM_PORT_TYPE_RX_10G) ? 8 :      \
171                ((type) == e_FM_PORT_TYPE_TX_10G) ? 12 :     \
172                ((type) == e_FM_PORT_TYPE_RX)     ? 2 :      \
173                ((type) == e_FM_PORT_TYPE_TX)     ? 3 :      \
174                ((type) == e_FM_PORT_TYPE_OH_HOST_COMMAND) ? 2 : 4)
175 
176 #define DEFAULT_PORT_extraNumOfOpenDmas(type)       0
177 
178 #define DEFAULT_PORT_numOfFifoBufs(type)                   \
179     (uint32_t) (((type) == e_FM_PORT_TYPE_RX_10G) ? 96 : \
180                 ((type) == e_FM_PORT_TYPE_TX_10G) ? 64 : \
181                 ((type) == e_FM_PORT_TYPE_OH_HOST_COMMAND) ? 10 : 50)
182 
183 #define DEFAULT_PORT_extraNumOfFifoBufs             0
184 
185 #endif /* (DPAA_VERSION < 11) */
186 
187 #define DEFAULT_PORT_txBdRingLength                 16
188 #define DEFAULT_PORT_rxBdRingLength                 128
189 #define DEFAULT_PORT_ImfwExtStructsMemId            0
190 #define DEFAULT_PORT_ImfwExtStructsMemAttr          MEMORY_ATTR_CACHEABLE
191 
192 #define FM_PORT_CG_REG_NUM(_cgId) (((FM_PORT_NUM_OF_CONGESTION_GRPS/32)-1)-_cgId/32)
193 
194 /**************************************************************************//**
195  @Collection    PCD Engines
196 *//***************************************************************************/
197 typedef uint32_t fmPcdEngines_t; /**< options as defined below: */
198 
199 #define FM_PCD_NONE                                 0                   /**< No PCD Engine indicated */
200 #define FM_PCD_PRS                                  0x80000000          /**< Parser indicated */
201 #define FM_PCD_KG                                   0x40000000          /**< Keygen indicated */
202 #define FM_PCD_CC                                   0x20000000          /**< Coarse classification indicated */
203 #define FM_PCD_PLCR                                 0x10000000          /**< Policer indicated */
204 #define FM_PCD_MANIP                                0x08000000          /**< Manipulation indicated */
205 /* @} */
206 
207 #define FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS       8
208 #define FM_PORT_MAX_NUM_OF_CONGESTION_GRPS_ALL_INTEGRATIONS 256
209 #define FM_PORT_CG_REG_NUM(_cgId) (((FM_PORT_NUM_OF_CONGESTION_GRPS/32)-1)-_cgId/32)
210 
211 #define FM_OH_PORT_ID                               0
212 
213 /***********************************************************************/
214 /*          SW parser OFFLOAD labels (offsets)                         */
215 /***********************************************************************/
216 #if (DPAA_VERSION == 10)
217 #define OFFLOAD_SW_PATCH_IPv4_IPR_LABEL         0x300
218 #define OFFLOAD_SW_PATCH_IPv6_IPR_LABEL         0x325
219 #define OFFLOAD_SW_PATCH_IPv6_IPF_LABEL         0x325
220 #else
221 #define OFFLOAD_SW_PATCH_IPv4_IPR_LABEL         0x100
222 /* Will be used for:
223  * 1. identify fragments
224  * 2. udp-lite
225  */
226 #define OFFLOAD_SW_PATCH_IPv6_IPR_LABEL         0x146
227 /* Will be used for:
228  * 1. will identify the fragmentable area
229  * 2. udp-lite
230  */
231 #define OFFLOAD_SW_PATCH_IPv6_IPF_LABEL         0x261
232 #define OFFLOAD_SW_PATCH_CAPWAP_LABEL           0x38d
233 #endif /* (DPAA_VERSION == 10) */
234 
235 #if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT))
236 #define UDP_LITE_SW_PATCH_LABEL                 0x2E0
237 #endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */
238 
239 
240 /**************************************************************************//**
241  @Description       Memory Mapped Registers
242 *//***************************************************************************/
243 
244 #if defined(__MWERKS__) && !defined(__GNUC__)
245 #pragma pack(push,1)
246 #endif /* defined(__MWERKS__) && ... */
247 
248 typedef struct
249 {
250     volatile uint32_t   fmbm_rcfg;      /**< Rx Configuration */
251     volatile uint32_t   fmbm_rst;       /**< Rx Status */
252     volatile uint32_t   fmbm_rda;       /**< Rx DMA attributes*/
253     volatile uint32_t   fmbm_rfp;       /**< Rx FIFO Parameters*/
254     volatile uint32_t   fmbm_rfed;      /**< Rx Frame End Data*/
255     volatile uint32_t   fmbm_ricp;      /**< Rx Internal Context Parameters*/
256     volatile uint32_t   fmbm_rim;       /**< Rx Internal Buffer Margins*/
257     volatile uint32_t   fmbm_rebm;      /**< Rx External Buffer Margins*/
258     volatile uint32_t   fmbm_rfne;      /**< Rx Frame Next Engine*/
259     volatile uint32_t   fmbm_rfca;      /**< Rx Frame Command Attributes.*/
260     volatile uint32_t   fmbm_rfpne;     /**< Rx Frame Parser Next Engine*/
261     volatile uint32_t   fmbm_rpso;      /**< Rx Parse Start Offset*/
262     volatile uint32_t   fmbm_rpp;       /**< Rx Policer Profile  */
263     volatile uint32_t   fmbm_rccb;      /**< Rx Coarse Classification Base */
264     volatile uint32_t   fmbm_reth;      /**< Rx Excessive Threshold */
265     volatile uint32_t   reserved1[0x01];/**< (0x03C) */
266     volatile uint32_t   fmbm_rprai[FM_PORT_PRS_RESULT_NUM_OF_WORDS];
267                                         /**< Rx Parse Results Array Initialization*/
268     volatile uint32_t   fmbm_rfqid;     /**< Rx Frame Queue ID*/
269     volatile uint32_t   fmbm_refqid;    /**< Rx Error Frame Queue ID*/
270     volatile uint32_t   fmbm_rfsdm;     /**< Rx Frame Status Discard Mask*/
271     volatile uint32_t   fmbm_rfsem;     /**< Rx Frame Status Error Mask*/
272     volatile uint32_t   fmbm_rfene;     /**< Rx Frame Enqueue Next Engine */
273     volatile uint32_t   reserved2[0x02];/**< (0x074-0x078) */
274     volatile uint32_t   fmbm_rcmne;     /**< Rx Frame Continuous Mode Next Engine */
275     volatile uint32_t   reserved3[0x20];/**< (0x080 0x0FF)  */
276     volatile uint32_t   fmbm_ebmpi[FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS];
277                                         /**< Buffer Manager pool Information-*/
278     volatile uint32_t   fmbm_acnt[FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS];
279                                         /**< Allocate Counter-*/
280     volatile uint32_t   reserved4[0x08];
281                                         /**< 0x130/0x140 - 0x15F reserved -*/
282     volatile uint32_t   fmbm_rcgm[FM_PORT_MAX_NUM_OF_CONGESTION_GRPS_ALL_INTEGRATIONS/32];
283                                         /**< Congestion Group Map*/
284     volatile uint32_t   fmbm_rmpd;      /**< BM Pool Depletion  */
285     volatile uint32_t   reserved5[0x1F];/**< (0x184 0x1FF) */
286     volatile uint32_t   fmbm_rstc;      /**< Rx Statistics Counters*/
287     volatile uint32_t   fmbm_rfrc;      /**< Rx Frame Counter*/
288     volatile uint32_t   fmbm_rfbc;      /**< Rx Bad Frames Counter*/
289     volatile uint32_t   fmbm_rlfc;      /**< Rx Large Frames Counter*/
290     volatile uint32_t   fmbm_rffc;      /**< Rx Filter Frames Counter*/
291     volatile uint32_t   fmbm_rfcd;      /**< Rx Frame Discard Counter*/
292     volatile uint32_t   fmbm_rfldec;    /**< Rx Frames List DMA Error Counter*/
293     volatile uint32_t   fmbm_rodc;      /**< Rx Out of Buffers Discard Counter-*/
294     volatile uint32_t   fmbm_rbdc;      /**< Rx Buffers Deallocate Counter-*/
295     volatile uint32_t   fmbm_rpec;      /**< Rx RX Prepare to enqueue Counter-*/
296     volatile uint32_t   reserved6[0x16];/**< (0x228 0x27F) */
297     volatile uint32_t   fmbm_rpc;       /**< Rx Performance Counters*/
298     volatile uint32_t   fmbm_rpcp;      /**< Rx Performance Count Parameters*/
299     volatile uint32_t   fmbm_rccn;      /**< Rx Cycle Counter*/
300     volatile uint32_t   fmbm_rtuc;      /**< Rx Tasks Utilization Counter*/
301     volatile uint32_t   fmbm_rrquc;     /**< Rx Receive Queue Utilization Counter*/
302     volatile uint32_t   fmbm_rduc;      /**< Rx DMA Utilization Counter*/
303     volatile uint32_t   fmbm_rfuc;      /**< Rx FIFO Utilization Counter*/
304     volatile uint32_t   fmbm_rpac;      /**< Rx Pause Activation Counter*/
305     volatile uint32_t   reserved7[0x18];/**< (0x2A0-0x2FF) */
306     volatile uint32_t   fmbm_rdcfg[0x3];/**< Rx Debug-*/
307     volatile uint32_t   fmbm_rgpr;      /**< Rx General Purpose Register. */
308     volatile uint32_t   reserved8[0x3a];/**< (0x310-0x3FF) */
309 } t_FmPortRxBmiRegs;
310 
311 typedef struct
312 {
313     volatile uint32_t   fmbm_tcfg;      /**< Tx Configuration */
314     volatile uint32_t   fmbm_tst;       /**< Tx Status */
315     volatile uint32_t   fmbm_tda;       /**< Tx DMA attributes */
316     volatile uint32_t   fmbm_tfp;       /**< Tx FIFO Parameters */
317     volatile uint32_t   fmbm_tfed;      /**< Tx Frame End Data */
318     volatile uint32_t   fmbm_ticp;      /**< Tx Internal Context Parameters */
319     volatile uint32_t   fmbm_tfdne;     /**< Tx Frame Dequeue Next Engine. */
320     volatile uint32_t   fmbm_tfca;      /**< Tx Frame Command attribute. */
321     volatile uint32_t   fmbm_tcfqid;    /**< Tx Confirmation Frame Queue ID. */
322     volatile uint32_t   fmbm_tfeqid;    /**< Tx Frame Error Queue ID */
323     volatile uint32_t   fmbm_tfene;     /**< Tx Frame Enqueue Next Engine */
324     volatile uint32_t   fmbm_trlmts;    /**< Tx Rate Limiter Scale */
325     volatile uint32_t   fmbm_trlmt;     /**< Tx Rate Limiter */
326     volatile uint32_t   fmbm_tccb;      /**< Tx Coarse Classification Base */
327     volatile uint32_t   reserved0[0x0e];/**< (0x038-0x070) */
328     volatile uint32_t   fmbm_tfne;      /**< Tx Frame Next Engine */
329     volatile uint32_t   fmbm_tpfcm[0x02];/**< Tx Priority based Flow Control (PFC) Mapping */
330     volatile uint32_t   fmbm_tcmne;     /**< Tx Frame Continuous Mode Next Engine */
331     volatile uint32_t   reserved2[0x60];/**< (0x080-0x200) */
332     volatile uint32_t   fmbm_tstc;      /**< Tx Statistics Counters */
333     volatile uint32_t   fmbm_tfrc;      /**< Tx Frame Counter */
334     volatile uint32_t   fmbm_tfdc;      /**< Tx Frames Discard Counter */
335     volatile uint32_t   fmbm_tfledc;    /**< Tx Frame Length error discard counter */
336     volatile uint32_t   fmbm_tfufdc;    /**< Tx Frame unsupported format discard Counter */
337     volatile uint32_t   fmbm_tbdc;      /**< Tx Buffers Deallocate Counter */
338     volatile uint32_t   reserved3[0x1A];/**< (0x218-0x280) */
339     volatile uint32_t   fmbm_tpc;       /**< Tx Performance Counters*/
340     volatile uint32_t   fmbm_tpcp;      /**< Tx Performance Count Parameters*/
341     volatile uint32_t   fmbm_tccn;      /**< Tx Cycle Counter*/
342     volatile uint32_t   fmbm_ttuc;      /**< Tx Tasks Utilization Counter*/
343     volatile uint32_t   fmbm_ttcquc;    /**< Tx Transmit Confirm Queue Utilization Counter*/
344     volatile uint32_t   fmbm_tduc;      /**< Tx DMA Utilization Counter*/
345     volatile uint32_t   fmbm_tfuc;      /**< Tx FIFO Utilization Counter*/
346     volatile uint32_t   reserved4[16];  /**< (0x29C-0x2FF) */
347     volatile uint32_t   fmbm_tdcfg[0x3];/**< Tx Debug-*/
348     volatile uint32_t   fmbm_tgpr;      /**< O/H General Purpose Register */
349     volatile uint32_t   reserved5[0x3a];/**< (0x310-0x3FF) */
350 } t_FmPortTxBmiRegs;
351 
352 typedef struct
353 {
354     volatile uint32_t   fmbm_ocfg;      /**< O/H Configuration  */
355     volatile uint32_t   fmbm_ost;       /**< O/H Status */
356     volatile uint32_t   fmbm_oda;       /**< O/H DMA attributes  */
357     volatile uint32_t   fmbm_oicp;      /**< O/H Internal Context Parameters  */
358     volatile uint32_t   fmbm_ofdne;     /**< O/H Frame Dequeue Next Engine  */
359     volatile uint32_t   fmbm_ofne;      /**< O/H Frame Next Engine  */
360     volatile uint32_t   fmbm_ofca;      /**< O/H Frame Command Attributes.  */
361     volatile uint32_t   fmbm_ofpne;     /**< O/H Frame Parser Next Engine  */
362     volatile uint32_t   fmbm_opso;      /**< O/H Parse Start Offset  */
363     volatile uint32_t   fmbm_opp;       /**< O/H Policer Profile */
364     volatile uint32_t   fmbm_occb;      /**< O/H Coarse Classification base */
365     volatile uint32_t   fmbm_oim;       /**< O/H Internal margins*/
366     volatile uint32_t   fmbm_ofp;       /**< O/H Fifo Parameters*/
367     volatile uint32_t   fmbm_ofed;      /**< O/H Frame End Data*/
368     volatile uint32_t   reserved0[2];   /**< (0x038 - 0x03F) */
369     volatile uint32_t   fmbm_oprai[FM_PORT_PRS_RESULT_NUM_OF_WORDS];
370                                         /**< O/H Parse Results Array Initialization  */
371     volatile uint32_t   fmbm_ofqid;     /**< O/H Frame Queue ID  */
372     volatile uint32_t   fmbm_oefqid;    /**< O/H Error Frame Queue ID  */
373     volatile uint32_t   fmbm_ofsdm;     /**< O/H Frame Status Discard Mask  */
374     volatile uint32_t   fmbm_ofsem;     /**< O/H Frame Status Error Mask  */
375     volatile uint32_t   fmbm_ofene;     /**< O/H Frame Enqueue Next Engine  */
376     volatile uint32_t   fmbm_orlmts;    /**< O/H Rate Limiter Scale  */
377     volatile uint32_t   fmbm_orlmt;     /**< O/H Rate Limiter  */
378     volatile uint32_t   fmbm_ocmne;     /**< O/H Continuous Mode Next Engine  */
379     volatile uint32_t   reserved1[0x20];/**< (0x080 - 0x0FF) */
380     volatile uint32_t   fmbm_oebmpi[2]; /**< Buffer Manager Observed Pool Information */
381     volatile uint32_t   reserved2[0x16];/**< (0x108 - 0x15F) */
382     volatile uint32_t   fmbm_ocgm;      /**< Observed Congestion Group Map */
383     volatile uint32_t   reserved3[0x7]; /**< (0x164 - 0x17F) */
384     volatile uint32_t   fmbm_ompd;      /**< Observed BMan Pool Depletion */
385     volatile uint32_t   reserved4[0x1F];/**< (0x184 - 0x1FF) */
386     volatile uint32_t   fmbm_ostc;      /**< O/H Statistics Counters  */
387     volatile uint32_t   fmbm_ofrc;      /**< O/H Frame Counter  */
388     volatile uint32_t   fmbm_ofdc;      /**< O/H Frames Discard Counter  */
389     volatile uint32_t   fmbm_ofledc;    /**< O/H Frames Length Error Discard Counter  */
390     volatile uint32_t   fmbm_ofufdc;    /**< O/H Frames Unsupported Format Discard Counter  */
391     volatile uint32_t   fmbm_offc;      /**< O/H Filter Frames Counter  */
392     volatile uint32_t   fmbm_ofwdc;     /**< - Rx Frames WRED Discard Counter  */
393     volatile uint32_t   fmbm_ofldec;    /**< O/H Frames List DMA Error Counter */
394     volatile uint32_t   fmbm_obdc;      /**< O/H Buffers Deallocate Counter */
395     volatile uint32_t   fmbm_oodc;      /**< O/H Out of Buffers Discard Counter */
396     volatile uint32_t   fmbm_opec;      /**< O/H Prepare to enqueue Counter */
397     volatile uint32_t   reserved5[0x15];/**< ( - 0x27F) */
398     volatile uint32_t   fmbm_opc;       /**< O/H Performance Counters  */
399     volatile uint32_t   fmbm_opcp;      /**< O/H Performance Count Parameters  */
400     volatile uint32_t   fmbm_occn;      /**< O/H Cycle Counter  */
401     volatile uint32_t   fmbm_otuc;      /**< O/H Tasks Utilization Counter  */
402     volatile uint32_t   fmbm_oduc;      /**< O/H DMA Utilization Counter */
403     volatile uint32_t   fmbm_ofuc;      /**< O/H FIFO Utilization Counter */
404     volatile uint32_t   reserved6[26];  /**< (0x298-0x2FF) */
405     volatile uint32_t   fmbm_odcfg[0x3];/**< O/H Debug (only 1 in P1023) */
406     volatile uint32_t   fmbm_ogpr;      /**< O/H General Purpose Register. */
407     volatile uint32_t   reserved7[0x3a];/**< (0x310 0x3FF) */
408 } t_FmPortOhBmiRegs;
409 
410 typedef union
411 {
412     t_FmPortRxBmiRegs rxPortBmiRegs;
413     t_FmPortTxBmiRegs txPortBmiRegs;
414     t_FmPortOhBmiRegs ohPortBmiRegs;
415 } u_FmPortBmiRegs;
416 
417 typedef struct
418 {
419     volatile uint32_t   reserved1[2];   /**<   0xn024 - 0x02B */
420     volatile uint32_t   fmqm_pndn;      /**<   PortID n Dequeue NIA Register */
421     volatile uint32_t   fmqm_pndc;      /**<   PortID n Dequeue Config Register */
422     volatile uint32_t   fmqm_pndtfc;    /**<   PortID n Dequeue Total Frame Counter */
423     volatile uint32_t   fmqm_pndfdc;    /**<   PortID n Dequeue FQID from Default Counter */
424     volatile uint32_t   fmqm_pndcc;     /**<   PortID n Dequeue Confirm Counter */
425 } t_FmPortNonRxQmiRegs;
426 
427 typedef struct
428 {
429     volatile uint32_t   fmqm_pnc;       /**<   PortID n Configuration Register */
430     volatile uint32_t   fmqm_pns;       /**<   PortID n Status Register */
431     volatile uint32_t   fmqm_pnts;      /**<   PortID n Task Status Register */
432     volatile uint32_t   reserved0[4];   /**<   0xn00C - 0xn01B */
433     volatile uint32_t   fmqm_pnen;      /**<   PortID n Enqueue NIA Register */
434     volatile uint32_t   fmqm_pnetfc;    /**<   PortID n Enqueue Total Frame Counter */
435     t_FmPortNonRxQmiRegs nonRxQmiRegs;  /**<   Registers for Tx Hc & Op ports */
436 } t_FmPortQmiRegs;
437 
438 typedef struct
439 {
440      struct
441     {
442         volatile uint32_t   softSeqAttach;  /**<   Soft Sequence Attachment */
443         volatile uint32_t   lcv;            /**<   Line-up Enable Confirmation Mask */
444     } hdrs[FM_PCD_PRS_NUM_OF_HDRS];
445     volatile uint32_t   reserved0[0xde];
446     volatile uint32_t   pcac;               /**<   Parse Internal Memory Configuration Access Control Register */
447     volatile uint32_t   pctpid;             /**<   Parse Internal Memory Configured TPID Register */
448 } t_FmPortPrsRegs;
449 
450 /**************************************************************************//*
451  @Description   Basic buffer descriptor (BD) structure
452 *//***************************************************************************/
453 typedef _Packed struct
454 {
455     volatile uint16_t       status;
456     volatile uint16_t       length;
457     volatile uint8_t        reserved0[0x6];
458     volatile uint8_t        reserved1[0x1];
459     volatile t_FmPhysAddr   buff;
460 } _PackedType t_FmImBd;
461 
462 typedef _Packed struct
463 {
464     volatile uint16_t       gen;                /**< tbd */
465     volatile uint8_t        reserved0[0x1];
466     volatile t_FmPhysAddr   bdRingBase;         /**< tbd */
467     volatile uint16_t       bdRingSize;         /**< tbd */
468     volatile uint16_t       offsetIn;           /**< tbd */
469     volatile uint16_t       offsetOut;          /**< tbd */
470     volatile uint8_t        reserved1[0x12];    /**< 0x0e - 0x1f */
471 } _PackedType t_FmPortImQd;
472 
473 typedef _Packed struct
474 {
475     volatile uint32_t   mode;               /**< Mode register */
476     volatile uint32_t   rxQdPtr;            /**< tbd */
477     volatile uint32_t   txQdPtr;            /**< tbd */
478     volatile uint16_t   mrblr;              /**< tbd */
479     volatile uint16_t   rxQdBsyCnt;         /**< tbd */
480     volatile uint8_t    reserved0[0x10];    /**< 0x10 - 0x1f */
481     t_FmPortImQd        rxQd;
482     t_FmPortImQd        txQd;
483     volatile uint8_t    reserved1[0xa0];    /**< 0x60 - 0xff */
484 } _PackedType t_FmPortImPram;
485 
486 #if defined(__MWERKS__) && !defined(__GNUC__)
487 #pragma pack(pop)
488 #endif /* defined(__MWERKS__) && ... */
489 
490 
491 /**************************************************************************//**
492  @Description       Registers bit fields
493 *//***************************************************************************/
494 
495 /**************************************************************************//**
496  @Description       BMI defines
497 *//***************************************************************************/
498 #if (DPAA_VERSION >= 11)
499 #define BMI_SP_ID_MASK                          0xff000000
500 #define BMI_SP_ID_SHIFT                         24
501 #define BMI_SP_EN                               0x01000000
502 #endif /* (DPAA_VERSION >= 11) */
503 
504 #define BMI_PORT_CFG_EN                         0x80000000
505 #define BMI_PORT_CFG_EN_MACSEC                  0x00800000
506 #define BMI_PORT_CFG_FDOVR                      0x02000000
507 #define BMI_PORT_CFG_IM                         0x01000000
508 #define BMI_PORT_CFG_AM                         0x00000040
509 #define BMI_PORT_STATUS_BSY                     0x80000000
510 #define BMI_COUNTERS_EN                         0x80000000
511 
512 #define BMI_PORT_RFNE_FRWD_DCL4C                0x10000000
513 #define BMI_PORT_RFNE_FRWD_RPD                  0x40000000
514 #define BMI_RFNE_FDCS_MASK                      0xFF000000
515 #define BMI_RFNE_HXS_MASK                       0x000000FF
516 
517 #define BMI_CMD_MR_LEAC                         0x00200000
518 #define BMI_CMD_MR_SLEAC                        0x00100000
519 #define BMI_CMD_MR_MA                           0x00080000
520 #define BMI_CMD_MR_DEAS                         0x00040000
521 #define BMI_CMD_RX_MR_DEF                       (BMI_CMD_MR_LEAC | \
522                                                  BMI_CMD_MR_SLEAC | \
523                                                  BMI_CMD_MR_MA | \
524                                                  BMI_CMD_MR_DEAS)
525 #define BMI_CMD_ATTR_ORDER                      0x80000000
526 #define BMI_CMD_ATTR_SYNC                       0x02000000
527 #define BMI_CMD_ATTR_MODE_MISS_ALLIGN_ADDR_EN   0x00080000
528 #define BMI_CMD_ATTR_MACCMD_MASK                0x0000ff00
529 #define BMI_CMD_ATTR_MACCMD_OVERRIDE            0x00008000
530 #define BMI_CMD_ATTR_MACCMD_SECURED             0x00001000
531 #define BMI_CMD_ATTR_MACCMD_SC_MASK             0x00000f00
532 
533 #define BMI_EXT_BUF_POOL_ID_MASK                0x003F0000
534 #define BMI_STATUS_RX_MASK_UNUSED               (uint32_t)(~(FM_PORT_FRM_ERR_DMA                    | \
535                                                              FM_PORT_FRM_ERR_PHYSICAL               | \
536                                                              FM_PORT_FRM_ERR_SIZE                   | \
537                                                              FM_PORT_FRM_ERR_CLS_DISCARD            | \
538                                                              FM_PORT_FRM_ERR_EXTRACTION             | \
539                                                              FM_PORT_FRM_ERR_NO_SCHEME              | \
540                                                              FM_PORT_FRM_ERR_COLOR_RED              | \
541                                                              FM_PORT_FRM_ERR_COLOR_YELLOW           | \
542                                                              FM_PORT_FRM_ERR_ILL_PLCR               | \
543                                                              FM_PORT_FRM_ERR_PLCR_FRAME_LEN         | \
544                                                              FM_PORT_FRM_ERR_PRS_TIMEOUT            | \
545                                                              FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT       | \
546                                                              FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED   | \
547                                                              FM_PORT_FRM_ERR_PRS_HDR_ERR            | \
548                                                              FM_PORT_FRM_ERR_IPRE                   | \
549                                                              FM_PORT_FRM_ERR_IPR_NCSP               | \
550                                                              FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW))
551 
552 #define BMI_STATUS_OP_MASK_UNUSED               (uint32_t)(BMI_STATUS_RX_MASK_UNUSED &                \
553                                                            ~(FM_PORT_FRM_ERR_LENGTH                 | \
554                                                              FM_PORT_FRM_ERR_NON_FM                 | \
555                                                              FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT))
556 
557 #define BMI_RATE_LIMIT_EN                       0x80000000
558 #define BMI_RATE_LIMIT_BURST_SIZE_GRAN          0x80000000
559 #define BMI_RATE_LIMIT_SCALE_BY_2               0x00000001
560 #define BMI_RATE_LIMIT_SCALE_BY_4               0x00000002
561 #define BMI_RATE_LIMIT_SCALE_BY_8               0x00000003
562 
563 #define BMI_RX_FIFO_THRESHOLD_BC                0x80000000
564 
565 #define BMI_PRS_RESULT_HIGH                     0x00000000
566 #define BMI_PRS_RESULT_LOW                      0xFFFFFFFF
567 
568 
569 #define RX_ERRS_TO_ENQ                          (FM_PORT_FRM_ERR_DMA                    | \
570                                                  FM_PORT_FRM_ERR_PHYSICAL               | \
571                                                  FM_PORT_FRM_ERR_SIZE                   | \
572                                                  FM_PORT_FRM_ERR_EXTRACTION             | \
573                                                  FM_PORT_FRM_ERR_NO_SCHEME              | \
574                                                  FM_PORT_FRM_ERR_ILL_PLCR               | \
575                                                  FM_PORT_FRM_ERR_PLCR_FRAME_LEN         | \
576                                                  FM_PORT_FRM_ERR_PRS_TIMEOUT            | \
577                                                  FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT       | \
578                                                  FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED   | \
579                                                  FM_PORT_FRM_ERR_PRS_HDR_ERR            | \
580                                                  FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW       | \
581                                                  FM_PORT_FRM_ERR_IPRE)
582 
583 #define OP_ERRS_TO_ENQ                          (RX_ERRS_TO_ENQ                         | \
584                                                  FM_PORT_FRM_ERR_LENGTH                 | \
585                                                  FM_PORT_FRM_ERR_NON_FM                 | \
586                                                  FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT)
587 
588 
589 #define BMI_RX_FIFO_PRI_ELEVATION_MASK          0x03FF0000
590 #define BMI_RX_FIFO_THRESHOLD_MASK              0x000003FF
591 #define BMI_TX_FIFO_MIN_FILL_MASK               0x03FF0000
592 #define BMI_FIFO_PIPELINE_DEPTH_MASK            0x0000F000
593 #define BMI_TX_LOW_COMF_MASK                    0x000003FF
594 
595 /* shifts */
596 #define BMI_PORT_CFG_MS_SEL_SHIFT               16
597 #define BMI_DMA_ATTR_IC_CACHE_SHIFT             FMAN_SP_DMA_ATTR_IC_CACHE_SHIFT
598 #define BMI_DMA_ATTR_HDR_CACHE_SHIFT            FMAN_SP_DMA_ATTR_HDR_CACHE_SHIFT
599 #define BMI_DMA_ATTR_SG_CACHE_SHIFT             FMAN_SP_DMA_ATTR_SG_CACHE_SHIFT
600 
601 #define BMI_IM_FOF_SHIFT                        28
602 #define BMI_PR_PORTID_SHIFT                     24
603 
604 #define BMI_RX_FIFO_PRI_ELEVATION_SHIFT         16
605 #define BMI_RX_FIFO_THRESHOLD_SHIFT             0
606 
607 #define BMI_RX_FRAME_END_CS_IGNORE_SHIFT        24
608 #define BMI_RX_FRAME_END_CUT_SHIFT              16
609 
610 #define BMI_IC_SIZE_SHIFT                       FMAN_SP_IC_SIZE_SHIFT
611 
612 #define BMI_INT_BUF_MARG_SHIFT                  28
613 
614 #define BMI_EXT_BUF_MARG_END_SHIFT              FMAN_SP_EXT_BUF_MARG_END_SHIFT
615 
616 #define BMI_CMD_ATTR_COLOR_SHIFT                26
617 #define BMI_CMD_ATTR_COM_MODE_SHIFT             16
618 #define BMI_CMD_ATTR_MACCMD_SHIFT               8
619 #define BMI_CMD_ATTR_MACCMD_OVERRIDE_SHIFT      15
620 #define BMI_CMD_ATTR_MACCMD_SECURED_SHIFT       12
621 #define BMI_CMD_ATTR_MACCMD_SC_SHIFT            8
622 
623 #define BMI_POOL_DEP_NUM_OF_POOLS_VECTOR_SHIFT  24
624 
625 #define BMI_TX_FIFO_MIN_FILL_SHIFT              16
626 #define BMI_TX_LOW_COMF_SHIFT                   0
627 
628 #define BMI_PERFORMANCE_TASK_COMP_SHIFT         24
629 #define BMI_PERFORMANCE_PORT_COMP_SHIFT         16
630 #define BMI_PERFORMANCE_DMA_COMP_SHIFT          12
631 #define BMI_PERFORMANCE_FIFO_COMP_SHIFT         0
632 
633 #define BMI_MAX_BURST_SHIFT                     16
634 #define BMI_COUNT_RATE_UNIT_SHIFT               16
635 
636 /* sizes */
637 #define FRAME_END_DATA_SIZE                     16
638 #define FRAME_OFFSET_UNITS                      16
639 #define MIN_TX_INT_OFFSET                       16
640 #define MAX_FRAME_OFFSET                        64
641 #define MAX_FIFO_PIPELINE_DEPTH                 8
642 #define MAX_PERFORMANCE_TASK_COMP               64
643 #define MAX_PERFORMANCE_TX_QUEUE_COMP           8
644 #define MAX_PERFORMANCE_RX_QUEUE_COMP           64
645 #define MAX_PERFORMANCE_DMA_COMP                16
646 #define MAX_NUM_OF_TASKS                        64
647 #define MAX_NUM_OF_EXTRA_TASKS                  8
648 #define MAX_NUM_OF_DMAS                         16
649 #define MAX_NUM_OF_EXTRA_DMAS                   8
650 #define MAX_BURST_SIZE                          1024
651 #define MIN_NUM_OF_OP_DMAS                      2
652 
653 
654 /**************************************************************************//**
655  @Description       QMI defines
656 *//***************************************************************************/
657 /* masks */
658 #define QMI_PORT_CFG_EN                         0x80000000
659 #define QMI_PORT_CFG_EN_COUNTERS                0x10000000
660 #define QMI_PORT_STATUS_DEQ_TNUM_BSY            0x80000000
661 #define QMI_PORT_STATUS_DEQ_FD_BSY              0x20000000
662 
663 #define QMI_DEQ_CFG_PREFETCH_NO_TNUM            0x02000000
664 #define QMI_DEQ_CFG_PREFETCH_WAITING_TNUM       0
665 #define QMI_DEQ_CFG_PREFETCH_1_FRAME            0
666 #define QMI_DEQ_CFG_PREFETCH_3_FRAMES           0x01000000
667 
668 #define QMI_DEQ_CFG_PRI                         0x80000000
669 #define QMI_DEQ_CFG_TYPE1                       0x10000000
670 #define QMI_DEQ_CFG_TYPE2                       0x20000000
671 #define QMI_DEQ_CFG_TYPE3                       0x30000000
672 
673 #define QMI_DEQ_CFG_SUBPORTAL_MASK              0x1f
674 #define QMI_DEQ_CFG_SUBPORTAL_SHIFT             20
675 
676 /**************************************************************************//**
677  @Description       PARSER defines
678 *//***************************************************************************/
679 /* masks */
680 #define PRS_HDR_ERROR_DIS                       0x00000800
681 #define PRS_HDR_SW_PRS_EN                       0x00000400
682 #define PRS_CP_OFFSET_MASK                      0x0000000F
683 #define PRS_TPID1_MASK                          0xFFFF0000
684 #define PRS_TPID2_MASK                          0x0000FFFF
685 #define PRS_TPID_DFLT                           0x91009100
686 
687 #define PRS_HDR_MPLS_LBL_INTER_EN               0x00200000
688 #define PRS_HDR_IPV6_ROUTE_HDR_EN               0x00008000
689 #define PRS_HDR_PPPOE_MTU_CHECK_EN              0x80000000
690 #define PRS_HDR_UDP_PAD_REMOVAL                 0x80000000
691 #define PRS_HDR_TCP_PAD_REMOVAL                 0x80000000
692 #define PRS_CAC_STOP                            0x00000001
693 #define PRS_CAC_ACTIVE                          0x00000100
694 
695 /* shifts */
696 #define PRS_PCTPID_SHIFT                        16
697 #define PRS_HDR_MPLS_NEXT_HDR_SHIFT             22
698 #define PRS_HDR_ETH_BC_SHIFT                    28
699 #define PRS_HDR_ETH_MC_SHIFT                    24
700 #define PRS_HDR_VLAN_STACKED_SHIFT              16
701 #define PRS_HDR_MPLS_STACKED_SHIFT              16
702 #define PRS_HDR_IPV4_1_BC_SHIFT                 28
703 #define PRS_HDR_IPV4_1_MC_SHIFT                 24
704 #define PRS_HDR_IPV4_2_UC_SHIFT                 20
705 #define PRS_HDR_IPV4_2_MC_BC_SHIFT              16
706 #define PRS_HDR_IPV6_1_MC_SHIFT                 24
707 #define PRS_HDR_IPV6_2_UC_SHIFT                 20
708 #define PRS_HDR_IPV6_2_MC_SHIFT                 16
709 
710 #define PRS_HDR_ETH_BC_MASK                     0x0fffffff
711 #define PRS_HDR_ETH_MC_MASK                     0xf0ffffff
712 #define PRS_HDR_VLAN_STACKED_MASK               0xfff0ffff
713 #define PRS_HDR_MPLS_STACKED_MASK               0xfff0ffff
714 #define PRS_HDR_IPV4_1_BC_MASK                  0x0fffffff
715 #define PRS_HDR_IPV4_1_MC_MASK                  0xf0ffffff
716 #define PRS_HDR_IPV4_2_UC_MASK                  0xff0fffff
717 #define PRS_HDR_IPV4_2_MC_BC_MASK               0xfff0ffff
718 #define PRS_HDR_IPV6_1_MC_MASK                  0xf0ffffff
719 #define PRS_HDR_IPV6_2_UC_MASK                  0xff0fffff
720 #define PRS_HDR_IPV6_2_MC_MASK                  0xfff0ffff
721 
722 /* others */
723 #define PRS_HDR_ENTRY_SIZE                      8
724 #define DEFAULT_CLS_PLAN_VECTOR                 0xFFFFFFFF
725 
726 #define IPSEC_SW_PATCH_START                    0x20
727 #define SCTP_SW_PATCH_START                     0x4D
728 #define DCCP_SW_PATCH_START                     0x41
729 
730 /**************************************************************************//**
731  @Description       IM defines
732 *//***************************************************************************/
733 #define BD_R_E                                  0x80000000
734 #define BD_L                                    0x08000000
735 
736 #define BD_RX_CRE                               0x00080000
737 #define BD_RX_FTL                               0x00040000
738 #define BD_RX_FTS                               0x00020000
739 #define BD_RX_OV                                0x00010000
740 
741 #define BD_RX_ERRORS                            (BD_RX_CRE | BD_RX_FTL | BD_RX_FTS | BD_RX_OV)
742 
743 #define FM_IM_SIZEOF_BD                         sizeof(t_FmImBd)
744 
745 #define BD_STATUS_MASK                          0xffff0000
746 #define BD_LENGTH_MASK                          0x0000ffff
747 
748 #define BD_STATUS_AND_LENGTH_SET(bd, val)       WRITE_UINT32(*(volatile uint32_t*)(bd), (val))
749 
750 #define BD_STATUS_AND_LENGTH(bd)                GET_UINT32(*(volatile uint32_t*)(bd))
751 
752 #define BD_GET(id)                              &p_FmPort->im.p_BdRing[id]
753 
754 #define IM_ILEGAL_BD_ID                         0xffff
755 
756 /* others */
757 #define IM_PRAM_ALIGN                           0x100
758 
759 /* masks */
760 #define IM_MODE_GBL                             0x20000000
761 #define IM_MODE_BO_MASK                         0x18000000
762 #define IM_MODE_BO_SHIFT                        3
763 #define IM_MODE_GRC_STP                         0x00800000
764 
765 #define IM_MODE_SET_BO(val)                     (uint32_t)((val << (31-IM_MODE_BO_SHIFT)) & IM_MODE_BO_MASK)
766 
767 #define IM_RXQD_BSYINTM                         0x0008
768 #define IM_RXQD_RXFINTM                         0x0010
769 #define IM_RXQD_FPMEVT_SEL_MASK                 0x0003
770 
771 #define IM_EV_BSY                               0x40000000
772 #define IM_EV_RX                                0x80000000
773 
774 
775 /**************************************************************************//**
776  @Description       Additional defines
777 *//***************************************************************************/
778 
779 typedef struct {
780     t_Handle                    h_FmMuram;
781     t_FmPortImPram              *p_FmPortImPram;
782     uint8_t                     fwExtStructsMemId;
783     uint32_t                    fwExtStructsMemAttr;
784     uint16_t                    bdRingSize;
785     t_FmImBd                    *p_BdRing;
786     t_Handle                    *p_BdShadow;
787     uint16_t                    currBdId;
788     uint16_t                    firstBdOfFrameId;
789 
790     /* Rx port parameters */
791     uint8_t                     dataMemId;          /**< Memory partition ID for data buffers */
792     uint32_t                    dataMemAttributes;  /**< Memory attributes for data buffers */
793     t_BufferPoolInfo            rxPool;
794     uint16_t                    mrblr;
795     uint16_t                    rxFrameAccumLength;
796     t_FmPortImRxStoreCallback   *f_RxStore;
797 
798     /* Tx port parameters */
799     uint32_t                    txFirstBdStatus;
800     t_FmPortImTxConfCallback    *f_TxConf;
801 } t_FmMacIm;
802 
803 
804 typedef struct {
805     struct fman_port_cfg                dfltCfg;
806     uint32_t                            dfltFqid;
807     uint32_t                            confFqid;
808     uint32_t                            errFqid;
809     uintptr_t                           baseAddr;
810     uint8_t                             deqSubPortal;
811     bool                                deqHighPriority;
812     e_FmPortDeqType                     deqType;
813     e_FmPortDeqPrefetchOption           deqPrefetchOption;
814     uint16_t                            deqByteCnt;
815     uint8_t                             cheksumLastBytesIgnore;
816     uint8_t                             cutBytesFromEnd;
817     t_FmBufPoolDepletion                bufPoolDepletion;
818     uint8_t                             pipelineDepth;
819     uint16_t                            fifoLowComfLevel;
820     bool                                frmDiscardOverride;
821     bool                                enRateLimit;
822     t_FmPortRateLimit                   rateLimit;
823     e_FmPortDualRateLimiterScaleDown    rateLimitDivider;
824     bool                                enBufPoolDepletion;
825     uint16_t                            liodnOffset;
826     uint16_t                            liodnBase;
827     t_FmExtPools                        extBufPools;
828     e_FmDmaSwapOption                   dmaSwapData;
829     e_FmDmaCacheOption                  dmaIntContextCacheAttr;
830     e_FmDmaCacheOption                  dmaHeaderCacheAttr;
831     e_FmDmaCacheOption                  dmaScatterGatherCacheAttr;
832     bool                                dmaReadOptimize;
833     bool                                dmaWriteOptimize;
834     uint32_t                            txFifoMinFillLevel;
835     uint32_t                            txFifoLowComfLevel;
836     uint32_t                            rxFifoPriElevationLevel;
837     uint32_t                            rxFifoThreshold;
838     t_FmSpBufMargins                    bufMargins;
839     t_FmSpIntContextDataCopy            intContext;
840     bool                                syncReq;
841     e_FmPortColor                       color;
842     fmPortFrameErrSelect_t              errorsToDiscard;
843     fmPortFrameErrSelect_t              errorsToEnq;
844     bool                                forwardReuseIntContext;
845     t_FmBufferPrefixContent             bufferPrefixContent;
846      t_FmBackupBmPools                   *p_BackupBmPools;
847     bool                                dontReleaseBuf;
848     bool                                setNumOfTasks;
849     bool                                setNumOfOpenDmas;
850     bool                                setSizeOfFifo;
851 #if (DPAA_VERSION >= 11)
852     bool                                noScatherGather;
853 #endif /* (DPAA_VERSION >= 11) */
854 
855 #ifdef FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669
856     bool                                bcbWorkaround;
857 #endif /* FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669 */
858 } t_FmPortDriverParam;
859 
860 
861 typedef struct t_FmPortRxPoolsParams
862 {
863     uint8_t     numOfPools;
864     uint16_t    secondLargestBufSize;
865     uint16_t    largestBufSize;
866 } t_FmPortRxPoolsParams;
867 
868 typedef struct t_FmPortDsarVars {
869     t_Handle                    *autoResOffsets;
870     t_FmPortDsarTablesSizes     *autoResMaxSizes;
871     uint32_t                    fmbm_tcfg;
872     uint32_t                    fmbm_tcmne;
873     uint32_t                    fmbm_rfne;
874     uint32_t                    fmbm_rfpne;
875     uint32_t                    fmbm_rcfg;
876     bool                        dsarEnabledParser;
877 } t_FmPortDsarVars;
878 typedef struct {
879     struct fman_port            port;
880     t_Handle                    h_Fm;
881     t_Handle                    h_FmPcd;
882     t_Handle                    h_FmMuram;
883     t_FmRevisionInfo            fmRevInfo;
884     uint8_t                     portId;
885     e_FmPortType                portType;
886     int                         enabled;
887     char                        name[MODULE_NAME_SIZE];
888     uint8_t                     hardwarePortId;
889     uint16_t                    fmClkFreq;
890     t_FmPortQmiRegs             *p_FmPortQmiRegs;
891     u_FmPortBmiRegs             *p_FmPortBmiRegs;
892     t_FmPortPrsRegs             *p_FmPortPrsRegs;
893     fmPcdEngines_t              pcdEngines;
894     uint32_t                    savedBmiNia;
895     uint8_t                     netEnvId;
896     uint32_t                    optArray[FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)];
897     uint32_t                    lcvs[FM_PCD_PRS_NUM_OF_HDRS];
898     uint8_t                     privateInfo;
899     uint32_t                    schemesPerPortVector;
900     bool                        useClsPlan;
901     uint8_t                     clsPlanGrpId;
902     t_Handle                    ccTreeId;
903     t_Handle                    completeArg;
904     void                        (*f_Complete)(t_Handle arg);
905     t_FmSpBufferOffsets         bufferOffsets;
906     /* Independent-Mode parameters support */
907     bool                        imEn;
908     t_FmMacIm                   im;
909     volatile bool               lock;
910     t_Handle                    h_Spinlock;
911     t_FmPortExceptionCallback   *f_Exception;
912     t_Handle                    h_App;
913     uint8_t                     internalBufferOffset;
914     uint8_t                     fmanCtrlEventId;
915     uint32_t                    exceptions;
916     bool                        polling;
917     t_FmExtPools                extBufPools;
918     uint32_t                    requiredAction;
919     uint32_t                    savedQmiPnen;
920     uint32_t                    savedBmiFene;
921     uint32_t                    savedBmiFpne;
922     uint32_t                    savedBmiCmne;
923     uint32_t                    savedBmiOfp;
924     uint32_t                    savedNonRxQmiRegsPndn;
925     uint32_t                    origNonRxQmiRegsPndn;
926     int                         savedPrsStartOffset;
927     bool                        includeInPrsStatistics;
928     uint16_t                    maxFrameLength;
929     t_FmFmanCtrl                orFmanCtrl;
930     t_FmPortRsrc                openDmas;
931     t_FmPortRsrc                tasks;
932     t_FmPortRsrc                fifoBufs;
933     t_FmPortRxPoolsParams       rxPoolsParams;
934 //    bool                        explicitUserSizeOfFifo;
935     t_Handle                    h_IpReassemblyManip;
936     t_Handle                    h_CapwapReassemblyManip;
937     t_Handle                    h_ReassemblyTree;
938     uint64_t                    fmMuramPhysBaseAddr;
939 #if (DPAA_VERSION >= 11)
940     bool                        vspe;
941     uint8_t                     dfltRelativeId;
942     e_FmPortGprFuncType         gprFunc;
943     t_FmPcdCtrlParamsPage       *p_ParamsPage;
944 #endif /* (DPAA_VERSION >= 11) */
945     t_FmPortDsarVars            deepSleepVars;
946     t_FmPortDriverParam         *p_FmPortDriverParam;
947 } t_FmPort;
948 
949 
950 void FmPortConfigIM (t_FmPort *p_FmPort, t_FmPortParams *p_FmPortParams);
951 t_Error FmPortImCheckInitParameters(t_FmPort *p_FmPort);
952 
953 t_Error FmPortImInit(t_FmPort *p_FmPort);
954 void    FmPortImFree(t_FmPort *p_FmPort);
955 
956 t_Error FmPortImEnable  (t_FmPort *p_FmPort);
957 t_Error FmPortImDisable (t_FmPort *p_FmPort);
958 t_Error FmPortImRx      (t_FmPort *p_FmPort);
959 
960 void    FmPortSetMacsecLcv(t_Handle h_FmPort);
961 void    FmPortSetMacsecCmd(t_Handle h_FmPort, uint8_t dfltSci);
962 
963 
964 t_Error FM_PORT_SetNumOfOpenDmas(t_Handle h_FmPort, t_FmPortRsrc *p_NumOfOpenDmas);
965 t_Error FM_PORT_SetNumOfTasks(t_Handle h_FmPort, t_FmPortRsrc *p_NumOfTasks);
966 t_Error FM_PORT_SetSizeOfFifo(t_Handle h_FmPort, t_FmPortRsrc *p_SizeOfFifo);
967 
BdBufferGet(t_PhysToVirt * f_PhysToVirt,t_FmImBd * p_Bd)968 static __inline__ uint8_t * BdBufferGet (t_PhysToVirt *f_PhysToVirt, t_FmImBd *p_Bd)
969 {
970     uint64_t    physAddr = (uint64_t)((uint64_t)GET_UINT8(p_Bd->buff.high) << 32);
971     physAddr |= GET_UINT32(p_Bd->buff.low);
972 
973     return (uint8_t *)f_PhysToVirt((physAddress_t)(physAddr));
974 }
975 
SET_ADDR(volatile t_FmPhysAddr * fmPhysAddr,uint64_t value)976 static __inline__ void SET_ADDR(volatile t_FmPhysAddr *fmPhysAddr, uint64_t value)
977 {
978     WRITE_UINT8(fmPhysAddr->high,(uint8_t)((value & 0x000000ff00000000LL) >> 32));
979     WRITE_UINT32(fmPhysAddr->low,(uint32_t)value);
980 }
981 
BdBufferSet(t_VirtToPhys * f_VirtToPhys,t_FmImBd * p_Bd,uint8_t * p_Buffer)982 static __inline__ void BdBufferSet(t_VirtToPhys *f_VirtToPhys, t_FmImBd *p_Bd, uint8_t *p_Buffer)
983 {
984     uint64_t    physAddr = (uint64_t)(f_VirtToPhys(p_Buffer));
985     SET_ADDR(&p_Bd->buff, physAddr);
986 }
987 
GetNextBdId(t_FmPort * p_FmPort,uint16_t id)988 static __inline__ uint16_t GetNextBdId(t_FmPort *p_FmPort, uint16_t id)
989 {
990     if (id < p_FmPort->im.bdRingSize-1)
991         return (uint16_t)(id+1);
992     else
993         return 0;
994 }
995 
996 void FM_PORT_Dsar_DumpRegs(void);
997 
998 
999 #endif /* __FM_PORT_H */
1000