1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #ifndef __AMDGPU_TTM_H__
25 #define __AMDGPU_TTM_H__
26
27 #include <linux/dma-direction.h>
28 #include <drm/gpu_scheduler.h>
29 #include "amdgpu_vram_mgr.h"
30 #include "amdgpu.h"
31
32 #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
33 #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
34 #define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
35 #define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3)
36 #define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4)
37
38 #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
39 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
40
41 #define AMDGPU_POISON 0xd0bed0be
42
43 extern const struct attribute_group amdgpu_vram_mgr_attr_group;
44 extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
45
46 struct hmm_range;
47
48 struct amdgpu_gtt_mgr {
49 struct ttm_resource_manager manager;
50 struct drm_mm mm;
51 spinlock_t lock;
52 };
53
54 struct amdgpu_mman {
55 struct ttm_device bdev;
56 struct ttm_pool *ttm_pools;
57 bool initialized;
58 void __iomem *aper_base_kaddr;
59 bus_space_handle_t aper_bsh;
60
61 /* buffer handling */
62 const struct amdgpu_buffer_funcs *buffer_funcs;
63 struct amdgpu_ring *buffer_funcs_ring;
64 bool buffer_funcs_enabled;
65
66 struct rwlock gtt_window_lock;
67 /* High priority scheduler entity for buffer moves */
68 struct drm_sched_entity high_pr;
69 /* Low priority scheduler entity for VRAM clearing */
70 struct drm_sched_entity low_pr;
71
72 struct amdgpu_vram_mgr vram_mgr;
73 struct amdgpu_gtt_mgr gtt_mgr;
74 struct ttm_resource_manager preempt_mgr;
75
76 uint64_t stolen_vga_size;
77 struct amdgpu_bo *stolen_vga_memory;
78 uint64_t stolen_extended_size;
79 struct amdgpu_bo *stolen_extended_memory;
80 bool keep_stolen_vga_memory;
81
82 struct amdgpu_bo *stolen_reserved_memory;
83 uint64_t stolen_reserved_offset;
84 uint64_t stolen_reserved_size;
85
86 /* discovery */
87 uint8_t *discovery_bin;
88 uint32_t discovery_tmr_size;
89 /* fw reserved memory */
90 struct amdgpu_bo *fw_reserved_memory;
91
92 /* firmware VRAM reservation */
93 u64 fw_vram_usage_start_offset;
94 u64 fw_vram_usage_size;
95 struct amdgpu_bo *fw_vram_usage_reserved_bo;
96 void *fw_vram_usage_va;
97
98 /* driver VRAM reservation */
99 u64 drv_vram_usage_start_offset;
100 u64 drv_vram_usage_size;
101 struct amdgpu_bo *drv_vram_usage_reserved_bo;
102 void *drv_vram_usage_va;
103
104 /* PAGE_SIZE'd BO for process memory r/w over SDMA. */
105 struct amdgpu_bo *sdma_access_bo;
106 void *sdma_access_ptr;
107 };
108
109 struct amdgpu_copy_mem {
110 struct ttm_buffer_object *bo;
111 struct ttm_resource *mem;
112 unsigned long offset;
113 };
114
115 int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
116 void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);
117 int amdgpu_preempt_mgr_init(struct amdgpu_device *adev);
118 void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev);
119 int amdgpu_vram_mgr_init(struct amdgpu_device *adev);
120 void amdgpu_vram_mgr_fini(struct amdgpu_device *adev);
121
122 bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
123 void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr);
124
125 uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man);
126
127 u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
128 int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
129 struct ttm_resource *mem,
130 u64 offset, u64 size,
131 struct device *dev,
132 enum dma_data_direction dir,
133 struct sg_table **sgt);
134 void amdgpu_vram_mgr_free_sgt(struct device *dev,
135 enum dma_data_direction dir,
136 struct sg_table *sgt);
137 uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr);
138 int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr,
139 uint64_t start, uint64_t size);
140 int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr,
141 uint64_t start);
142
143 bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
144 struct ttm_resource *res);
145
146 int amdgpu_ttm_init(struct amdgpu_device *adev);
147 void amdgpu_ttm_fini(struct amdgpu_device *adev);
148 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
149 bool enable);
150
151 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
152 uint64_t dst_offset, uint32_t byte_count,
153 struct dma_resv *resv,
154 struct dma_fence **fence, bool direct_submit,
155 bool vm_needs_flush, bool tmz);
156 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
157 const struct amdgpu_copy_mem *src,
158 const struct amdgpu_copy_mem *dst,
159 uint64_t size, bool tmz,
160 struct dma_resv *resv,
161 struct dma_fence **f);
162 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
163 uint32_t src_data,
164 struct dma_resv *resv,
165 struct dma_fence **fence,
166 bool delayed);
167
168 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
169 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
170 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
171
172 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
173 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,
174 struct hmm_range **range);
175 void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
176 struct hmm_range *range);
177 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
178 struct hmm_range *range);
179 #else
amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo * bo,struct vm_page ** pages,struct hmm_range ** range)180 static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
181 struct vm_page **pages,
182 struct hmm_range **range)
183 {
184 return -EPERM;
185 }
amdgpu_ttm_tt_discard_user_pages(struct ttm_tt * ttm,struct hmm_range * range)186 static inline void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
187 struct hmm_range *range)
188 {
189 }
amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt * ttm,struct hmm_range * range)190 static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
191 struct hmm_range *range)
192 {
193 return false;
194 }
195 #endif
196
197 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct vm_page **pages);
198 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
199 uint64_t *user_addr);
200 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
201 uint64_t addr, uint32_t flags);
202 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
203 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
204 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
205 unsigned long end, unsigned long *userptr);
206 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
207 int *last_invalidated);
208 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
209 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
210 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem);
211 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
212 struct ttm_resource *mem);
213 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type);
214
215 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
216
217 #endif
218