1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the TargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/IR/LLVMContext.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetLoweringObjectFile.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
35 #include <cctype>
36 using namespace llvm;
37
38 /// NOTE: The TargetMachine owns TLOF.
TargetLowering(const TargetMachine & tm)39 TargetLowering::TargetLowering(const TargetMachine &tm)
40 : TargetLoweringBase(tm) {}
41
getTargetNodeName(unsigned Opcode) const42 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
43 return nullptr;
44 }
45
46 /// Check whether a given call node is in tail position within its function. If
47 /// so, it sets Chain to the input chain of the tail call.
isInTailCallPosition(SelectionDAG & DAG,SDNode * Node,SDValue & Chain) const48 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
49 SDValue &Chain) const {
50 const Function *F = DAG.getMachineFunction().getFunction();
51
52 // Conservatively require the attributes of the call to match those of
53 // the return. Ignore noalias because it doesn't affect the call sequence.
54 AttributeSet CallerAttrs = F->getAttributes();
55 if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
56 .removeAttribute(Attribute::NoAlias).hasAttributes())
57 return false;
58
59 // It's not safe to eliminate the sign / zero extension of the return value.
60 if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) ||
61 CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
62 return false;
63
64 // Check if the only use is a function return node.
65 return isUsedByReturnOnly(Node, Chain);
66 }
67
68 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
69 /// and called function attributes.
setAttributes(ImmutableCallSite * CS,unsigned AttrIdx)70 void TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS,
71 unsigned AttrIdx) {
72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
73 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
74 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
75 isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
76 isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
77 isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
78 isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
79 isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
80 Alignment = CS->getParamAlignment(AttrIdx);
81 }
82
83 /// Generate a libcall taking the given operands as arguments and returning a
84 /// result of type RetVT.
85 std::pair<SDValue, SDValue>
makeLibCall(SelectionDAG & DAG,RTLIB::Libcall LC,EVT RetVT,const SDValue * Ops,unsigned NumOps,bool isSigned,SDLoc dl,bool doesNotReturn,bool isReturnValueUsed) const86 TargetLowering::makeLibCall(SelectionDAG &DAG,
87 RTLIB::Libcall LC, EVT RetVT,
88 const SDValue *Ops, unsigned NumOps,
89 bool isSigned, SDLoc dl,
90 bool doesNotReturn,
91 bool isReturnValueUsed) const {
92 TargetLowering::ArgListTy Args;
93 Args.reserve(NumOps);
94
95 TargetLowering::ArgListEntry Entry;
96 for (unsigned i = 0; i != NumOps; ++i) {
97 Entry.Node = Ops[i];
98 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
99 Entry.isSExt = shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned);
100 Entry.isZExt = !shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned);
101 Args.push_back(Entry);
102 }
103 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
104
105 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
106 TargetLowering::CallLoweringInfo CLI(DAG);
107 bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned);
108 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
109 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
110 .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
111 .setSExtResult(signExtend).setZExtResult(!signExtend);
112 return LowerCallTo(CLI);
113 }
114
115
116 /// SoftenSetCCOperands - Soften the operands of a comparison. This code is
117 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
softenSetCCOperands(SelectionDAG & DAG,EVT VT,SDValue & NewLHS,SDValue & NewRHS,ISD::CondCode & CCCode,SDLoc dl) const118 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
119 SDValue &NewLHS, SDValue &NewRHS,
120 ISD::CondCode &CCCode,
121 SDLoc dl) const {
122 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
123 && "Unsupported setcc type!");
124
125 // Expand into one or more soft-fp libcall(s).
126 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
127 switch (CCCode) {
128 case ISD::SETEQ:
129 case ISD::SETOEQ:
130 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
131 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
132 break;
133 case ISD::SETNE:
134 case ISD::SETUNE:
135 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
136 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
137 break;
138 case ISD::SETGE:
139 case ISD::SETOGE:
140 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
141 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
142 break;
143 case ISD::SETLT:
144 case ISD::SETOLT:
145 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
146 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
147 break;
148 case ISD::SETLE:
149 case ISD::SETOLE:
150 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
151 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
152 break;
153 case ISD::SETGT:
154 case ISD::SETOGT:
155 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
156 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
157 break;
158 case ISD::SETUO:
159 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
160 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
161 break;
162 case ISD::SETO:
163 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
164 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
165 break;
166 default:
167 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
168 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
169 switch (CCCode) {
170 case ISD::SETONE:
171 // SETONE = SETOLT | SETOGT
172 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
173 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
174 // Fallthrough
175 case ISD::SETUGT:
176 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
177 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
178 break;
179 case ISD::SETUGE:
180 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
181 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
182 break;
183 case ISD::SETULT:
184 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
185 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
186 break;
187 case ISD::SETULE:
188 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
189 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
190 break;
191 case ISD::SETUEQ:
192 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
193 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
194 break;
195 default: llvm_unreachable("Do not know how to soften this setcc!");
196 }
197 }
198
199 // Use the target specific return value for comparions lib calls.
200 EVT RetVT = getCmpLibcallReturnType();
201 SDValue Ops[2] = { NewLHS, NewRHS };
202 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
203 dl).first;
204 NewRHS = DAG.getConstant(0, RetVT);
205 CCCode = getCmpLibcallCC(LC1);
206 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
207 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
208 getSetCCResultType(*DAG.getContext(), RetVT),
209 NewLHS, NewRHS, DAG.getCondCode(CCCode));
210 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
211 dl).first;
212 NewLHS = DAG.getNode(ISD::SETCC, dl,
213 getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
214 NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
215 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
216 NewRHS = SDValue();
217 }
218 }
219
220 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
221 /// current function. The returned value is a member of the
222 /// MachineJumpTableInfo::JTEntryKind enum.
getJumpTableEncoding() const223 unsigned TargetLowering::getJumpTableEncoding() const {
224 // In non-pic modes, just use the address of a block.
225 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
226 return MachineJumpTableInfo::EK_BlockAddress;
227
228 // In PIC mode, if the target supports a GPRel32 directive, use it.
229 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
230 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
231
232 // Otherwise, use a label difference.
233 return MachineJumpTableInfo::EK_LabelDifference32;
234 }
235
getPICJumpTableRelocBase(SDValue Table,SelectionDAG & DAG) const236 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
237 SelectionDAG &DAG) const {
238 // If our PIC model is GP relative, use the global offset table as the base.
239 unsigned JTEncoding = getJumpTableEncoding();
240
241 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
242 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
243 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
244
245 return Table;
246 }
247
248 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
249 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
250 /// MCExpr.
251 const MCExpr *
getPICJumpTableRelocBaseExpr(const MachineFunction * MF,unsigned JTI,MCContext & Ctx) const252 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
253 unsigned JTI,MCContext &Ctx) const{
254 // The normal PIC reloc base is the label at the start of the jump table.
255 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
256 }
257
258 bool
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const259 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
260 // Assume that everything is safe in static mode.
261 if (getTargetMachine().getRelocationModel() == Reloc::Static)
262 return true;
263
264 // In dynamic-no-pic mode, assume that known defined values are safe.
265 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
266 GA &&
267 !GA->getGlobal()->isDeclaration() &&
268 !GA->getGlobal()->isWeakForLinker())
269 return true;
270
271 // Otherwise assume nothing is safe.
272 return false;
273 }
274
275 //===----------------------------------------------------------------------===//
276 // Optimization Methods
277 //===----------------------------------------------------------------------===//
278
279 /// ShrinkDemandedConstant - Check to see if the specified operand of the
280 /// specified instruction is a constant integer. If so, check to see if there
281 /// are any bits set in the constant that are not demanded. If so, shrink the
282 /// constant and return true.
ShrinkDemandedConstant(SDValue Op,const APInt & Demanded)283 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
284 const APInt &Demanded) {
285 SDLoc dl(Op);
286
287 // FIXME: ISD::SELECT, ISD::SELECT_CC
288 switch (Op.getOpcode()) {
289 default: break;
290 case ISD::XOR:
291 case ISD::AND:
292 case ISD::OR: {
293 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
294 if (!C) return false;
295
296 if (Op.getOpcode() == ISD::XOR &&
297 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
298 return false;
299
300 // if we can expand it to have all bits set, do it
301 if (C->getAPIntValue().intersects(~Demanded)) {
302 EVT VT = Op.getValueType();
303 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
304 DAG.getConstant(Demanded &
305 C->getAPIntValue(),
306 VT));
307 return CombineTo(Op, New);
308 }
309
310 break;
311 }
312 }
313
314 return false;
315 }
316
317 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
318 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
319 /// cast, but it could be generalized for targets with other types of
320 /// implicit widening casts.
321 bool
ShrinkDemandedOp(SDValue Op,unsigned BitWidth,const APInt & Demanded,SDLoc dl)322 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
323 unsigned BitWidth,
324 const APInt &Demanded,
325 SDLoc dl) {
326 assert(Op.getNumOperands() == 2 &&
327 "ShrinkDemandedOp only supports binary operators!");
328 assert(Op.getNode()->getNumValues() == 1 &&
329 "ShrinkDemandedOp only supports nodes with one result!");
330
331 // Early return, as this function cannot handle vector types.
332 if (Op.getValueType().isVector())
333 return false;
334
335 // Don't do this if the node has another user, which may require the
336 // full value.
337 if (!Op.getNode()->hasOneUse())
338 return false;
339
340 // Search for the smallest integer type with free casts to and from
341 // Op's type. For expedience, just check power-of-2 integer types.
342 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
343 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
344 unsigned SmallVTBits = DemandedSize;
345 if (!isPowerOf2_32(SmallVTBits))
346 SmallVTBits = NextPowerOf2(SmallVTBits);
347 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
348 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
349 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
350 TLI.isZExtFree(SmallVT, Op.getValueType())) {
351 // We found a type with free casts.
352 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
353 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
354 Op.getNode()->getOperand(0)),
355 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
356 Op.getNode()->getOperand(1)));
357 bool NeedZext = DemandedSize > SmallVTBits;
358 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
359 dl, Op.getValueType(), X);
360 return CombineTo(Op, Z);
361 }
362 }
363 return false;
364 }
365
366 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
367 /// DemandedMask bits of the result of Op are ever used downstream. If we can
368 /// use this information to simplify Op, create a new simplified DAG node and
369 /// return true, returning the original and new nodes in Old and New. Otherwise,
370 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
371 /// the expression (used to simplify the caller). The KnownZero/One bits may
372 /// only be accurate for those bits in the DemandedMask.
SimplifyDemandedBits(SDValue Op,const APInt & DemandedMask,APInt & KnownZero,APInt & KnownOne,TargetLoweringOpt & TLO,unsigned Depth) const373 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
374 const APInt &DemandedMask,
375 APInt &KnownZero,
376 APInt &KnownOne,
377 TargetLoweringOpt &TLO,
378 unsigned Depth) const {
379 unsigned BitWidth = DemandedMask.getBitWidth();
380 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
381 "Mask size mismatches value type size!");
382 APInt NewMask = DemandedMask;
383 SDLoc dl(Op);
384
385 // Don't know anything.
386 KnownZero = KnownOne = APInt(BitWidth, 0);
387
388 // Other users may use these bits.
389 if (!Op.getNode()->hasOneUse()) {
390 if (Depth != 0) {
391 // If not at the root, Just compute the KnownZero/KnownOne bits to
392 // simplify things downstream.
393 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
394 return false;
395 }
396 // If this is the root being simplified, allow it to have multiple uses,
397 // just set the NewMask to all bits.
398 NewMask = APInt::getAllOnesValue(BitWidth);
399 } else if (DemandedMask == 0) {
400 // Not demanding any bits from Op.
401 if (Op.getOpcode() != ISD::UNDEF)
402 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
403 return false;
404 } else if (Depth == 6) { // Limit search depth.
405 return false;
406 }
407
408 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
409 switch (Op.getOpcode()) {
410 case ISD::Constant:
411 // We know all of the bits for a constant!
412 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
413 KnownZero = ~KnownOne;
414 return false; // Don't fall through, will infinitely loop.
415 case ISD::AND:
416 // If the RHS is a constant, check to see if the LHS would be zero without
417 // using the bits from the RHS. Below, we use knowledge about the RHS to
418 // simplify the LHS, here we're using information from the LHS to simplify
419 // the RHS.
420 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
421 APInt LHSZero, LHSOne;
422 // Do not increment Depth here; that can cause an infinite loop.
423 TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
424 // If the LHS already has zeros where RHSC does, this and is dead.
425 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
426 return TLO.CombineTo(Op, Op.getOperand(0));
427 // If any of the set bits in the RHS are known zero on the LHS, shrink
428 // the constant.
429 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
430 return true;
431 }
432
433 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
434 KnownOne, TLO, Depth+1))
435 return true;
436 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
437 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
438 KnownZero2, KnownOne2, TLO, Depth+1))
439 return true;
440 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
441
442 // If all of the demanded bits are known one on one side, return the other.
443 // These bits cannot contribute to the result of the 'and'.
444 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
445 return TLO.CombineTo(Op, Op.getOperand(0));
446 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
447 return TLO.CombineTo(Op, Op.getOperand(1));
448 // If all of the demanded bits in the inputs are known zeros, return zero.
449 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
450 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
451 // If the RHS is a constant, see if we can simplify it.
452 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
453 return true;
454 // If the operation can be done in a smaller type, do so.
455 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
456 return true;
457
458 // Output known-1 bits are only known if set in both the LHS & RHS.
459 KnownOne &= KnownOne2;
460 // Output known-0 are known to be clear if zero in either the LHS | RHS.
461 KnownZero |= KnownZero2;
462 break;
463 case ISD::OR:
464 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
465 KnownOne, TLO, Depth+1))
466 return true;
467 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
468 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
469 KnownZero2, KnownOne2, TLO, Depth+1))
470 return true;
471 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
472
473 // If all of the demanded bits are known zero on one side, return the other.
474 // These bits cannot contribute to the result of the 'or'.
475 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
476 return TLO.CombineTo(Op, Op.getOperand(0));
477 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
478 return TLO.CombineTo(Op, Op.getOperand(1));
479 // If all of the potentially set bits on one side are known to be set on
480 // the other side, just use the 'other' side.
481 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
482 return TLO.CombineTo(Op, Op.getOperand(0));
483 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
484 return TLO.CombineTo(Op, Op.getOperand(1));
485 // If the RHS is a constant, see if we can simplify it.
486 if (TLO.ShrinkDemandedConstant(Op, NewMask))
487 return true;
488 // If the operation can be done in a smaller type, do so.
489 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
490 return true;
491
492 // Output known-0 bits are only known if clear in both the LHS & RHS.
493 KnownZero &= KnownZero2;
494 // Output known-1 are known to be set if set in either the LHS | RHS.
495 KnownOne |= KnownOne2;
496 break;
497 case ISD::XOR:
498 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
499 KnownOne, TLO, Depth+1))
500 return true;
501 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
502 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
503 KnownOne2, TLO, Depth+1))
504 return true;
505 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
506
507 // If all of the demanded bits are known zero on one side, return the other.
508 // These bits cannot contribute to the result of the 'xor'.
509 if ((KnownZero & NewMask) == NewMask)
510 return TLO.CombineTo(Op, Op.getOperand(0));
511 if ((KnownZero2 & NewMask) == NewMask)
512 return TLO.CombineTo(Op, Op.getOperand(1));
513 // If the operation can be done in a smaller type, do so.
514 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
515 return true;
516
517 // If all of the unknown bits are known to be zero on one side or the other
518 // (but not both) turn this into an *inclusive* or.
519 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
520 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
521 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
522 Op.getOperand(0),
523 Op.getOperand(1)));
524
525 // Output known-0 bits are known if clear or set in both the LHS & RHS.
526 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
527 // Output known-1 are known to be set if set in only one of the LHS, RHS.
528 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
529
530 // If all of the demanded bits on one side are known, and all of the set
531 // bits on that side are also known to be set on the other side, turn this
532 // into an AND, as we know the bits will be cleared.
533 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
534 // NB: it is okay if more bits are known than are requested
535 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
536 if (KnownOne == KnownOne2) { // set bits are the same on both sides
537 EVT VT = Op.getValueType();
538 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
539 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
540 Op.getOperand(0), ANDC));
541 }
542 }
543
544 // If the RHS is a constant, see if we can simplify it.
545 // for XOR, we prefer to force bits to 1 if they will make a -1.
546 // if we can't force bits, try to shrink constant
547 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
548 APInt Expanded = C->getAPIntValue() | (~NewMask);
549 // if we can expand it to have all bits set, do it
550 if (Expanded.isAllOnesValue()) {
551 if (Expanded != C->getAPIntValue()) {
552 EVT VT = Op.getValueType();
553 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
554 TLO.DAG.getConstant(Expanded, VT));
555 return TLO.CombineTo(Op, New);
556 }
557 // if it already has all the bits set, nothing to change
558 // but don't shrink either!
559 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
560 return true;
561 }
562 }
563
564 KnownZero = KnownZeroOut;
565 KnownOne = KnownOneOut;
566 break;
567 case ISD::SELECT:
568 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
569 KnownOne, TLO, Depth+1))
570 return true;
571 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
572 KnownOne2, TLO, Depth+1))
573 return true;
574 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
575 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
576
577 // If the operands are constants, see if we can simplify them.
578 if (TLO.ShrinkDemandedConstant(Op, NewMask))
579 return true;
580
581 // Only known if known in both the LHS and RHS.
582 KnownOne &= KnownOne2;
583 KnownZero &= KnownZero2;
584 break;
585 case ISD::SELECT_CC:
586 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
587 KnownOne, TLO, Depth+1))
588 return true;
589 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
590 KnownOne2, TLO, Depth+1))
591 return true;
592 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
593 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
594
595 // If the operands are constants, see if we can simplify them.
596 if (TLO.ShrinkDemandedConstant(Op, NewMask))
597 return true;
598
599 // Only known if known in both the LHS and RHS.
600 KnownOne &= KnownOne2;
601 KnownZero &= KnownZero2;
602 break;
603 case ISD::SHL:
604 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
605 unsigned ShAmt = SA->getZExtValue();
606 SDValue InOp = Op.getOperand(0);
607
608 // If the shift count is an invalid immediate, don't do anything.
609 if (ShAmt >= BitWidth)
610 break;
611
612 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
613 // single shift. We can do this if the bottom bits (which are shifted
614 // out) are never demanded.
615 if (InOp.getOpcode() == ISD::SRL &&
616 isa<ConstantSDNode>(InOp.getOperand(1))) {
617 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
618 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
619 unsigned Opc = ISD::SHL;
620 int Diff = ShAmt-C1;
621 if (Diff < 0) {
622 Diff = -Diff;
623 Opc = ISD::SRL;
624 }
625
626 SDValue NewSA =
627 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
628 EVT VT = Op.getValueType();
629 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
630 InOp.getOperand(0), NewSA));
631 }
632 }
633
634 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
635 KnownZero, KnownOne, TLO, Depth+1))
636 return true;
637
638 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
639 // are not demanded. This will likely allow the anyext to be folded away.
640 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
641 SDValue InnerOp = InOp.getNode()->getOperand(0);
642 EVT InnerVT = InnerOp.getValueType();
643 unsigned InnerBits = InnerVT.getSizeInBits();
644 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
645 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
646 EVT ShTy = getShiftAmountTy(InnerVT);
647 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
648 ShTy = InnerVT;
649 SDValue NarrowShl =
650 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
651 TLO.DAG.getConstant(ShAmt, ShTy));
652 return
653 TLO.CombineTo(Op,
654 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
655 NarrowShl));
656 }
657 // Repeat the SHL optimization above in cases where an extension
658 // intervenes: (shl (anyext (shr x, c1)), c2) to
659 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
660 // aren't demanded (as above) and that the shifted upper c1 bits of
661 // x aren't demanded.
662 if (InOp.hasOneUse() &&
663 InnerOp.getOpcode() == ISD::SRL &&
664 InnerOp.hasOneUse() &&
665 isa<ConstantSDNode>(InnerOp.getOperand(1))) {
666 uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
667 ->getZExtValue();
668 if (InnerShAmt < ShAmt &&
669 InnerShAmt < InnerBits &&
670 NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
671 NewMask.trunc(ShAmt) == 0) {
672 SDValue NewSA =
673 TLO.DAG.getConstant(ShAmt - InnerShAmt,
674 Op.getOperand(1).getValueType());
675 EVT VT = Op.getValueType();
676 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
677 InnerOp.getOperand(0));
678 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
679 NewExt, NewSA));
680 }
681 }
682 }
683
684 KnownZero <<= SA->getZExtValue();
685 KnownOne <<= SA->getZExtValue();
686 // low bits known zero.
687 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
688 }
689 break;
690 case ISD::SRL:
691 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
692 EVT VT = Op.getValueType();
693 unsigned ShAmt = SA->getZExtValue();
694 unsigned VTSize = VT.getSizeInBits();
695 SDValue InOp = Op.getOperand(0);
696
697 // If the shift count is an invalid immediate, don't do anything.
698 if (ShAmt >= BitWidth)
699 break;
700
701 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
702 // single shift. We can do this if the top bits (which are shifted out)
703 // are never demanded.
704 if (InOp.getOpcode() == ISD::SHL &&
705 isa<ConstantSDNode>(InOp.getOperand(1))) {
706 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
707 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
708 unsigned Opc = ISD::SRL;
709 int Diff = ShAmt-C1;
710 if (Diff < 0) {
711 Diff = -Diff;
712 Opc = ISD::SHL;
713 }
714
715 SDValue NewSA =
716 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
717 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
718 InOp.getOperand(0), NewSA));
719 }
720 }
721
722 // Compute the new bits that are at the top now.
723 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
724 KnownZero, KnownOne, TLO, Depth+1))
725 return true;
726 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
727 KnownZero = KnownZero.lshr(ShAmt);
728 KnownOne = KnownOne.lshr(ShAmt);
729
730 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
731 KnownZero |= HighBits; // High bits known zero.
732 }
733 break;
734 case ISD::SRA:
735 // If this is an arithmetic shift right and only the low-bit is set, we can
736 // always convert this into a logical shr, even if the shift amount is
737 // variable. The low bit of the shift cannot be an input sign bit unless
738 // the shift amount is >= the size of the datatype, which is undefined.
739 if (NewMask == 1)
740 return TLO.CombineTo(Op,
741 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
742 Op.getOperand(0), Op.getOperand(1)));
743
744 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
745 EVT VT = Op.getValueType();
746 unsigned ShAmt = SA->getZExtValue();
747
748 // If the shift count is an invalid immediate, don't do anything.
749 if (ShAmt >= BitWidth)
750 break;
751
752 APInt InDemandedMask = (NewMask << ShAmt);
753
754 // If any of the demanded bits are produced by the sign extension, we also
755 // demand the input sign bit.
756 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
757 if (HighBits.intersects(NewMask))
758 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
759
760 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
761 KnownZero, KnownOne, TLO, Depth+1))
762 return true;
763 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
764 KnownZero = KnownZero.lshr(ShAmt);
765 KnownOne = KnownOne.lshr(ShAmt);
766
767 // Handle the sign bit, adjusted to where it is now in the mask.
768 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
769
770 // If the input sign bit is known to be zero, or if none of the top bits
771 // are demanded, turn this into an unsigned shift right.
772 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits)
773 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
774 Op.getOperand(0),
775 Op.getOperand(1)));
776
777 int Log2 = NewMask.exactLogBase2();
778 if (Log2 >= 0) {
779 // The bit must come from the sign.
780 SDValue NewSA =
781 TLO.DAG.getConstant(BitWidth - 1 - Log2,
782 Op.getOperand(1).getValueType());
783 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
784 Op.getOperand(0), NewSA));
785 }
786
787 if (KnownOne.intersects(SignBit))
788 // New bits are known one.
789 KnownOne |= HighBits;
790 }
791 break;
792 case ISD::SIGN_EXTEND_INREG: {
793 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
794
795 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
796 // If we only care about the highest bit, don't bother shifting right.
797 if (MsbMask == DemandedMask) {
798 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
799 SDValue InOp = Op.getOperand(0);
800
801 // Compute the correct shift amount type, which must be getShiftAmountTy
802 // for scalar types after legalization.
803 EVT ShiftAmtTy = Op.getValueType();
804 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
805 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
806
807 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
808 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
809 Op.getValueType(), InOp, ShiftAmt));
810 }
811
812 // Sign extension. Compute the demanded bits in the result that are not
813 // present in the input.
814 APInt NewBits =
815 APInt::getHighBitsSet(BitWidth,
816 BitWidth - ExVT.getScalarType().getSizeInBits());
817
818 // If none of the extended bits are demanded, eliminate the sextinreg.
819 if ((NewBits & NewMask) == 0)
820 return TLO.CombineTo(Op, Op.getOperand(0));
821
822 APInt InSignBit =
823 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
824 APInt InputDemandedBits =
825 APInt::getLowBitsSet(BitWidth,
826 ExVT.getScalarType().getSizeInBits()) &
827 NewMask;
828
829 // Since the sign extended bits are demanded, we know that the sign
830 // bit is demanded.
831 InputDemandedBits |= InSignBit;
832
833 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
834 KnownZero, KnownOne, TLO, Depth+1))
835 return true;
836 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
837
838 // If the sign bit of the input is known set or clear, then we know the
839 // top bits of the result.
840
841 // If the input sign bit is known zero, convert this into a zero extension.
842 if (KnownZero.intersects(InSignBit))
843 return TLO.CombineTo(Op,
844 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
845
846 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
847 KnownOne |= NewBits;
848 KnownZero &= ~NewBits;
849 } else { // Input sign bit unknown
850 KnownZero &= ~NewBits;
851 KnownOne &= ~NewBits;
852 }
853 break;
854 }
855 case ISD::BUILD_PAIR: {
856 EVT HalfVT = Op.getOperand(0).getValueType();
857 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
858
859 APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
860 APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
861
862 APInt KnownZeroLo, KnownOneLo;
863 APInt KnownZeroHi, KnownOneHi;
864
865 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
866 KnownOneLo, TLO, Depth + 1))
867 return true;
868
869 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
870 KnownOneHi, TLO, Depth + 1))
871 return true;
872
873 KnownZero = KnownZeroLo.zext(BitWidth) |
874 KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
875
876 KnownOne = KnownOneLo.zext(BitWidth) |
877 KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
878 break;
879 }
880 case ISD::ZERO_EXTEND: {
881 unsigned OperandBitWidth =
882 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
883 APInt InMask = NewMask.trunc(OperandBitWidth);
884
885 // If none of the top bits are demanded, convert this into an any_extend.
886 APInt NewBits =
887 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
888 if (!NewBits.intersects(NewMask))
889 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
890 Op.getValueType(),
891 Op.getOperand(0)));
892
893 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
894 KnownZero, KnownOne, TLO, Depth+1))
895 return true;
896 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
897 KnownZero = KnownZero.zext(BitWidth);
898 KnownOne = KnownOne.zext(BitWidth);
899 KnownZero |= NewBits;
900 break;
901 }
902 case ISD::SIGN_EXTEND: {
903 EVT InVT = Op.getOperand(0).getValueType();
904 unsigned InBits = InVT.getScalarType().getSizeInBits();
905 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
906 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
907 APInt NewBits = ~InMask & NewMask;
908
909 // If none of the top bits are demanded, convert this into an any_extend.
910 if (NewBits == 0)
911 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
912 Op.getValueType(),
913 Op.getOperand(0)));
914
915 // Since some of the sign extended bits are demanded, we know that the sign
916 // bit is demanded.
917 APInt InDemandedBits = InMask & NewMask;
918 InDemandedBits |= InSignBit;
919 InDemandedBits = InDemandedBits.trunc(InBits);
920
921 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
922 KnownOne, TLO, Depth+1))
923 return true;
924 KnownZero = KnownZero.zext(BitWidth);
925 KnownOne = KnownOne.zext(BitWidth);
926
927 // If the sign bit is known zero, convert this to a zero extend.
928 if (KnownZero.intersects(InSignBit))
929 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
930 Op.getValueType(),
931 Op.getOperand(0)));
932
933 // If the sign bit is known one, the top bits match.
934 if (KnownOne.intersects(InSignBit)) {
935 KnownOne |= NewBits;
936 assert((KnownZero & NewBits) == 0);
937 } else { // Otherwise, top bits aren't known.
938 assert((KnownOne & NewBits) == 0);
939 assert((KnownZero & NewBits) == 0);
940 }
941 break;
942 }
943 case ISD::ANY_EXTEND: {
944 unsigned OperandBitWidth =
945 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
946 APInt InMask = NewMask.trunc(OperandBitWidth);
947 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
948 KnownZero, KnownOne, TLO, Depth+1))
949 return true;
950 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
951 KnownZero = KnownZero.zext(BitWidth);
952 KnownOne = KnownOne.zext(BitWidth);
953 break;
954 }
955 case ISD::TRUNCATE: {
956 // Simplify the input, using demanded bit information, and compute the known
957 // zero/one bits live out.
958 unsigned OperandBitWidth =
959 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
960 APInt TruncMask = NewMask.zext(OperandBitWidth);
961 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
962 KnownZero, KnownOne, TLO, Depth+1))
963 return true;
964 KnownZero = KnownZero.trunc(BitWidth);
965 KnownOne = KnownOne.trunc(BitWidth);
966
967 // If the input is only used by this truncate, see if we can shrink it based
968 // on the known demanded bits.
969 if (Op.getOperand(0).getNode()->hasOneUse()) {
970 SDValue In = Op.getOperand(0);
971 switch (In.getOpcode()) {
972 default: break;
973 case ISD::SRL:
974 // Shrink SRL by a constant if none of the high bits shifted in are
975 // demanded.
976 if (TLO.LegalTypes() &&
977 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
978 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
979 // undesirable.
980 break;
981 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
982 if (!ShAmt)
983 break;
984 SDValue Shift = In.getOperand(1);
985 if (TLO.LegalTypes()) {
986 uint64_t ShVal = ShAmt->getZExtValue();
987 Shift =
988 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
989 }
990
991 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
992 OperandBitWidth - BitWidth);
993 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
994
995 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
996 // None of the shifted in bits are needed. Add a truncate of the
997 // shift input, then shift it.
998 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
999 Op.getValueType(),
1000 In.getOperand(0));
1001 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1002 Op.getValueType(),
1003 NewTrunc,
1004 Shift));
1005 }
1006 break;
1007 }
1008 }
1009
1010 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1011 break;
1012 }
1013 case ISD::AssertZext: {
1014 // AssertZext demands all of the high bits, plus any of the low bits
1015 // demanded by its users.
1016 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1017 APInt InMask = APInt::getLowBitsSet(BitWidth,
1018 VT.getSizeInBits());
1019 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1020 KnownZero, KnownOne, TLO, Depth+1))
1021 return true;
1022 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1023
1024 KnownZero |= ~InMask & NewMask;
1025 break;
1026 }
1027 case ISD::BITCAST:
1028 // If this is an FP->Int bitcast and if the sign bit is the only
1029 // thing demanded, turn this into a FGETSIGN.
1030 if (!TLO.LegalOperations() &&
1031 !Op.getValueType().isVector() &&
1032 !Op.getOperand(0).getValueType().isVector() &&
1033 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1034 Op.getOperand(0).getValueType().isFloatingPoint()) {
1035 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1036 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1037 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1038 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1039 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1040 // place. We expect the SHL to be eliminated by other optimizations.
1041 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1042 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1043 if (!OpVTLegal && OpVTSizeInBits > 32)
1044 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1045 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1046 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1047 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1048 Op.getValueType(),
1049 Sign, ShAmt));
1050 }
1051 }
1052 break;
1053 case ISD::ADD:
1054 case ISD::MUL:
1055 case ISD::SUB: {
1056 // Add, Sub, and Mul don't demand any bits in positions beyond that
1057 // of the highest bit demanded of them.
1058 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1059 BitWidth - NewMask.countLeadingZeros());
1060 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1061 KnownOne2, TLO, Depth+1))
1062 return true;
1063 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1064 KnownOne2, TLO, Depth+1))
1065 return true;
1066 // See if the operation should be performed at a smaller bit width.
1067 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1068 return true;
1069 }
1070 // FALL THROUGH
1071 default:
1072 // Just use computeKnownBits to compute output bits.
1073 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1074 break;
1075 }
1076
1077 // If we know the value of all of the demanded bits, return this as a
1078 // constant.
1079 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1080 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1081
1082 return false;
1083 }
1084
1085 /// computeKnownBitsForTargetNode - Determine which of the bits specified
1086 /// in Mask are known to be either zero or one and return them in the
1087 /// KnownZero/KnownOne bitsets.
computeKnownBitsForTargetNode(const SDValue Op,APInt & KnownZero,APInt & KnownOne,const SelectionDAG & DAG,unsigned Depth) const1088 void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1089 APInt &KnownZero,
1090 APInt &KnownOne,
1091 const SelectionDAG &DAG,
1092 unsigned Depth) const {
1093 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1094 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1095 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1096 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1097 "Should use MaskedValueIsZero if you don't know whether Op"
1098 " is a target node!");
1099 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1100 }
1101
1102 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1103 /// targets that want to expose additional information about sign bits to the
1104 /// DAG Combiner.
ComputeNumSignBitsForTargetNode(SDValue Op,const SelectionDAG &,unsigned Depth) const1105 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1106 const SelectionDAG &,
1107 unsigned Depth) const {
1108 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1109 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1110 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1111 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1112 "Should use ComputeNumSignBits if you don't know whether Op"
1113 " is a target node!");
1114 return 1;
1115 }
1116
1117 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1118 /// one bit set. This differs from computeKnownBits in that it doesn't need to
1119 /// determine which bit is set.
1120 ///
ValueHasExactlyOneBitSet(SDValue Val,const SelectionDAG & DAG)1121 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1122 // A left-shift of a constant one will have exactly one bit set, because
1123 // shifting the bit off the end is undefined.
1124 if (Val.getOpcode() == ISD::SHL)
1125 if (ConstantSDNode *C =
1126 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1127 if (C->getAPIntValue() == 1)
1128 return true;
1129
1130 // Similarly, a right-shift of a constant sign-bit will have exactly
1131 // one bit set.
1132 if (Val.getOpcode() == ISD::SRL)
1133 if (ConstantSDNode *C =
1134 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1135 if (C->getAPIntValue().isSignBit())
1136 return true;
1137
1138 // More could be done here, though the above checks are enough
1139 // to handle some common cases.
1140
1141 // Fall back to computeKnownBits to catch other known cases.
1142 EVT OpVT = Val.getValueType();
1143 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1144 APInt KnownZero, KnownOne;
1145 DAG.computeKnownBits(Val, KnownZero, KnownOne);
1146 return (KnownZero.countPopulation() == BitWidth - 1) &&
1147 (KnownOne.countPopulation() == 1);
1148 }
1149
isConstTrueVal(const SDNode * N) const1150 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
1151 if (!N)
1152 return false;
1153
1154 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1155 if (!CN) {
1156 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1157 if (!BV)
1158 return false;
1159
1160 BitVector UndefElements;
1161 CN = BV->getConstantSplatNode(&UndefElements);
1162 // Only interested in constant splats, and we don't try to handle undef
1163 // elements in identifying boolean constants.
1164 if (!CN || UndefElements.none())
1165 return false;
1166 }
1167
1168 switch (getBooleanContents(N->getValueType(0))) {
1169 case UndefinedBooleanContent:
1170 return CN->getAPIntValue()[0];
1171 case ZeroOrOneBooleanContent:
1172 return CN->isOne();
1173 case ZeroOrNegativeOneBooleanContent:
1174 return CN->isAllOnesValue();
1175 }
1176
1177 llvm_unreachable("Invalid boolean contents");
1178 }
1179
isConstFalseVal(const SDNode * N) const1180 bool TargetLowering::isConstFalseVal(const SDNode *N) const {
1181 if (!N)
1182 return false;
1183
1184 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1185 if (!CN) {
1186 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1187 if (!BV)
1188 return false;
1189
1190 BitVector UndefElements;
1191 CN = BV->getConstantSplatNode(&UndefElements);
1192 // Only interested in constant splats, and we don't try to handle undef
1193 // elements in identifying boolean constants.
1194 if (!CN || UndefElements.none())
1195 return false;
1196 }
1197
1198 if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
1199 return !CN->getAPIntValue()[0];
1200
1201 return CN->isNullValue();
1202 }
1203
1204 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1205 /// and cc. If it is unable to simplify it, return a null SDValue.
1206 SDValue
SimplifySetCC(EVT VT,SDValue N0,SDValue N1,ISD::CondCode Cond,bool foldBooleans,DAGCombinerInfo & DCI,SDLoc dl) const1207 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1208 ISD::CondCode Cond, bool foldBooleans,
1209 DAGCombinerInfo &DCI, SDLoc dl) const {
1210 SelectionDAG &DAG = DCI.DAG;
1211
1212 // These setcc operations always fold.
1213 switch (Cond) {
1214 default: break;
1215 case ISD::SETFALSE:
1216 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1217 case ISD::SETTRUE:
1218 case ISD::SETTRUE2: {
1219 TargetLowering::BooleanContent Cnt =
1220 getBooleanContents(N0->getValueType(0));
1221 return DAG.getConstant(
1222 Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
1223 }
1224 }
1225
1226 // Ensure that the constant occurs on the RHS, and fold constant
1227 // comparisons.
1228 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1229 if (isa<ConstantSDNode>(N0.getNode()) &&
1230 (DCI.isBeforeLegalizeOps() ||
1231 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1232 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1233
1234 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1235 const APInt &C1 = N1C->getAPIntValue();
1236
1237 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1238 // equality comparison, then we're just comparing whether X itself is
1239 // zero.
1240 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1241 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1242 N0.getOperand(1).getOpcode() == ISD::Constant) {
1243 const APInt &ShAmt
1244 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1245 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1246 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1247 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1248 // (srl (ctlz x), 5) == 0 -> X != 0
1249 // (srl (ctlz x), 5) != 1 -> X != 0
1250 Cond = ISD::SETNE;
1251 } else {
1252 // (srl (ctlz x), 5) != 0 -> X == 0
1253 // (srl (ctlz x), 5) == 1 -> X == 0
1254 Cond = ISD::SETEQ;
1255 }
1256 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1257 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1258 Zero, Cond);
1259 }
1260 }
1261
1262 SDValue CTPOP = N0;
1263 // Look through truncs that don't change the value of a ctpop.
1264 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1265 CTPOP = N0.getOperand(0);
1266
1267 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1268 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1269 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1270 EVT CTVT = CTPOP.getValueType();
1271 SDValue CTOp = CTPOP.getOperand(0);
1272
1273 // (ctpop x) u< 2 -> (x & x-1) == 0
1274 // (ctpop x) u> 1 -> (x & x-1) != 0
1275 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1276 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1277 DAG.getConstant(1, CTVT));
1278 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1279 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1280 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1281 }
1282
1283 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1284 }
1285
1286 // (zext x) == C --> x == (trunc C)
1287 // (sext x) == C --> x == (trunc C)
1288 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1289 DCI.isBeforeLegalize() && N0->hasOneUse()) {
1290 unsigned MinBits = N0.getValueSizeInBits();
1291 SDValue PreExt;
1292 bool Signed = false;
1293 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1294 // ZExt
1295 MinBits = N0->getOperand(0).getValueSizeInBits();
1296 PreExt = N0->getOperand(0);
1297 } else if (N0->getOpcode() == ISD::AND) {
1298 // DAGCombine turns costly ZExts into ANDs
1299 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1300 if ((C->getAPIntValue()+1).isPowerOf2()) {
1301 MinBits = C->getAPIntValue().countTrailingOnes();
1302 PreExt = N0->getOperand(0);
1303 }
1304 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
1305 // SExt
1306 MinBits = N0->getOperand(0).getValueSizeInBits();
1307 PreExt = N0->getOperand(0);
1308 Signed = true;
1309 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1310 // ZEXTLOAD / SEXTLOAD
1311 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1312 MinBits = LN0->getMemoryVT().getSizeInBits();
1313 PreExt = N0;
1314 } else if (LN0->getExtensionType() == ISD::SEXTLOAD) {
1315 Signed = true;
1316 MinBits = LN0->getMemoryVT().getSizeInBits();
1317 PreExt = N0;
1318 }
1319 }
1320
1321 // Figure out how many bits we need to preserve this constant.
1322 unsigned ReqdBits = Signed ?
1323 C1.getBitWidth() - C1.getNumSignBits() + 1 :
1324 C1.getActiveBits();
1325
1326 // Make sure we're not losing bits from the constant.
1327 if (MinBits > 0 &&
1328 MinBits < C1.getBitWidth() &&
1329 MinBits >= ReqdBits) {
1330 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1331 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1332 // Will get folded away.
1333 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
1334 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
1335 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1336 }
1337 }
1338 }
1339
1340 // If the LHS is '(and load, const)', the RHS is 0,
1341 // the test is for equality or unsigned, and all 1 bits of the const are
1342 // in the same partial word, see if we can shorten the load.
1343 if (DCI.isBeforeLegalize() &&
1344 !ISD::isSignedIntSetCC(Cond) &&
1345 N0.getOpcode() == ISD::AND && C1 == 0 &&
1346 N0.getNode()->hasOneUse() &&
1347 isa<LoadSDNode>(N0.getOperand(0)) &&
1348 N0.getOperand(0).getNode()->hasOneUse() &&
1349 isa<ConstantSDNode>(N0.getOperand(1))) {
1350 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1351 APInt bestMask;
1352 unsigned bestWidth = 0, bestOffset = 0;
1353 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1354 unsigned origWidth = N0.getValueType().getSizeInBits();
1355 unsigned maskWidth = origWidth;
1356 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1357 // 8 bits, but have to be careful...
1358 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1359 origWidth = Lod->getMemoryVT().getSizeInBits();
1360 const APInt &Mask =
1361 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1362 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1363 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1364 for (unsigned offset=0; offset<origWidth/width; offset++) {
1365 if ((newMask & Mask) == Mask) {
1366 if (!getDataLayout()->isLittleEndian())
1367 bestOffset = (origWidth/width - offset - 1) * (width/8);
1368 else
1369 bestOffset = (uint64_t)offset * (width/8);
1370 bestMask = Mask.lshr(offset * (width/8) * 8);
1371 bestWidth = width;
1372 break;
1373 }
1374 newMask = newMask << width;
1375 }
1376 }
1377 }
1378 if (bestWidth) {
1379 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1380 if (newVT.isRound()) {
1381 EVT PtrType = Lod->getOperand(1).getValueType();
1382 SDValue Ptr = Lod->getBasePtr();
1383 if (bestOffset != 0)
1384 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1385 DAG.getConstant(bestOffset, PtrType));
1386 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1387 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1388 Lod->getPointerInfo().getWithOffset(bestOffset),
1389 false, false, false, NewAlign);
1390 return DAG.getSetCC(dl, VT,
1391 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1392 DAG.getConstant(bestMask.trunc(bestWidth),
1393 newVT)),
1394 DAG.getConstant(0LL, newVT), Cond);
1395 }
1396 }
1397 }
1398
1399 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1400 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1401 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1402
1403 // If the comparison constant has bits in the upper part, the
1404 // zero-extended value could never match.
1405 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1406 C1.getBitWidth() - InSize))) {
1407 switch (Cond) {
1408 case ISD::SETUGT:
1409 case ISD::SETUGE:
1410 case ISD::SETEQ: return DAG.getConstant(0, VT);
1411 case ISD::SETULT:
1412 case ISD::SETULE:
1413 case ISD::SETNE: return DAG.getConstant(1, VT);
1414 case ISD::SETGT:
1415 case ISD::SETGE:
1416 // True if the sign bit of C1 is set.
1417 return DAG.getConstant(C1.isNegative(), VT);
1418 case ISD::SETLT:
1419 case ISD::SETLE:
1420 // True if the sign bit of C1 isn't set.
1421 return DAG.getConstant(C1.isNonNegative(), VT);
1422 default:
1423 break;
1424 }
1425 }
1426
1427 // Otherwise, we can perform the comparison with the low bits.
1428 switch (Cond) {
1429 case ISD::SETEQ:
1430 case ISD::SETNE:
1431 case ISD::SETUGT:
1432 case ISD::SETUGE:
1433 case ISD::SETULT:
1434 case ISD::SETULE: {
1435 EVT newVT = N0.getOperand(0).getValueType();
1436 if (DCI.isBeforeLegalizeOps() ||
1437 (isOperationLegal(ISD::SETCC, newVT) &&
1438 getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1439 EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
1440 SDValue NewConst = DAG.getConstant(C1.trunc(InSize), newVT);
1441
1442 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1443 NewConst, Cond);
1444 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1445 }
1446 break;
1447 }
1448 default:
1449 break; // todo, be more careful with signed comparisons
1450 }
1451 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1452 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1453 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1454 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1455 EVT ExtDstTy = N0.getValueType();
1456 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1457
1458 // If the constant doesn't fit into the number of bits for the source of
1459 // the sign extension, it is impossible for both sides to be equal.
1460 if (C1.getMinSignedBits() > ExtSrcTyBits)
1461 return DAG.getConstant(Cond == ISD::SETNE, VT);
1462
1463 SDValue ZextOp;
1464 EVT Op0Ty = N0.getOperand(0).getValueType();
1465 if (Op0Ty == ExtSrcTy) {
1466 ZextOp = N0.getOperand(0);
1467 } else {
1468 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1469 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1470 DAG.getConstant(Imm, Op0Ty));
1471 }
1472 if (!DCI.isCalledByLegalizer())
1473 DCI.AddToWorklist(ZextOp.getNode());
1474 // Otherwise, make this a use of a zext.
1475 return DAG.getSetCC(dl, VT, ZextOp,
1476 DAG.getConstant(C1 & APInt::getLowBitsSet(
1477 ExtDstTyBits,
1478 ExtSrcTyBits),
1479 ExtDstTy),
1480 Cond);
1481 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1482 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1483 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1484 if (N0.getOpcode() == ISD::SETCC &&
1485 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1486 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1487 if (TrueWhenTrue)
1488 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1489 // Invert the condition.
1490 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1491 CC = ISD::getSetCCInverse(CC,
1492 N0.getOperand(0).getValueType().isInteger());
1493 if (DCI.isBeforeLegalizeOps() ||
1494 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1495 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1496 }
1497
1498 if ((N0.getOpcode() == ISD::XOR ||
1499 (N0.getOpcode() == ISD::AND &&
1500 N0.getOperand(0).getOpcode() == ISD::XOR &&
1501 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1502 isa<ConstantSDNode>(N0.getOperand(1)) &&
1503 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1504 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1505 // can only do this if the top bits are known zero.
1506 unsigned BitWidth = N0.getValueSizeInBits();
1507 if (DAG.MaskedValueIsZero(N0,
1508 APInt::getHighBitsSet(BitWidth,
1509 BitWidth-1))) {
1510 // Okay, get the un-inverted input value.
1511 SDValue Val;
1512 if (N0.getOpcode() == ISD::XOR)
1513 Val = N0.getOperand(0);
1514 else {
1515 assert(N0.getOpcode() == ISD::AND &&
1516 N0.getOperand(0).getOpcode() == ISD::XOR);
1517 // ((X^1)&1)^1 -> X & 1
1518 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1519 N0.getOperand(0).getOperand(0),
1520 N0.getOperand(1));
1521 }
1522
1523 return DAG.getSetCC(dl, VT, Val, N1,
1524 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1525 }
1526 } else if (N1C->getAPIntValue() == 1 &&
1527 (VT == MVT::i1 ||
1528 getBooleanContents(N0->getValueType(0)) ==
1529 ZeroOrOneBooleanContent)) {
1530 SDValue Op0 = N0;
1531 if (Op0.getOpcode() == ISD::TRUNCATE)
1532 Op0 = Op0.getOperand(0);
1533
1534 if ((Op0.getOpcode() == ISD::XOR) &&
1535 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1536 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1537 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1538 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1539 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1540 Cond);
1541 }
1542 if (Op0.getOpcode() == ISD::AND &&
1543 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1544 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1545 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1546 if (Op0.getValueType().bitsGT(VT))
1547 Op0 = DAG.getNode(ISD::AND, dl, VT,
1548 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1549 DAG.getConstant(1, VT));
1550 else if (Op0.getValueType().bitsLT(VT))
1551 Op0 = DAG.getNode(ISD::AND, dl, VT,
1552 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1553 DAG.getConstant(1, VT));
1554
1555 return DAG.getSetCC(dl, VT, Op0,
1556 DAG.getConstant(0, Op0.getValueType()),
1557 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1558 }
1559 if (Op0.getOpcode() == ISD::AssertZext &&
1560 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1561 return DAG.getSetCC(dl, VT, Op0,
1562 DAG.getConstant(0, Op0.getValueType()),
1563 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1564 }
1565 }
1566
1567 APInt MinVal, MaxVal;
1568 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1569 if (ISD::isSignedIntSetCC(Cond)) {
1570 MinVal = APInt::getSignedMinValue(OperandBitSize);
1571 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1572 } else {
1573 MinVal = APInt::getMinValue(OperandBitSize);
1574 MaxVal = APInt::getMaxValue(OperandBitSize);
1575 }
1576
1577 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1578 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1579 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1580 // X >= C0 --> X > (C0 - 1)
1581 APInt C = C1 - 1;
1582 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1583 if ((DCI.isBeforeLegalizeOps() ||
1584 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1585 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1586 isLegalICmpImmediate(C.getSExtValue())))) {
1587 return DAG.getSetCC(dl, VT, N0,
1588 DAG.getConstant(C, N1.getValueType()),
1589 NewCC);
1590 }
1591 }
1592
1593 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1594 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1595 // X <= C0 --> X < (C0 + 1)
1596 APInt C = C1 + 1;
1597 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1598 if ((DCI.isBeforeLegalizeOps() ||
1599 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1600 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1601 isLegalICmpImmediate(C.getSExtValue())))) {
1602 return DAG.getSetCC(dl, VT, N0,
1603 DAG.getConstant(C, N1.getValueType()),
1604 NewCC);
1605 }
1606 }
1607
1608 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1609 return DAG.getConstant(0, VT); // X < MIN --> false
1610 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1611 return DAG.getConstant(1, VT); // X >= MIN --> true
1612 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1613 return DAG.getConstant(0, VT); // X > MAX --> false
1614 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1615 return DAG.getConstant(1, VT); // X <= MAX --> true
1616
1617 // Canonicalize setgt X, Min --> setne X, Min
1618 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1619 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1620 // Canonicalize setlt X, Max --> setne X, Max
1621 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1622 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1623
1624 // If we have setult X, 1, turn it into seteq X, 0
1625 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1626 return DAG.getSetCC(dl, VT, N0,
1627 DAG.getConstant(MinVal, N0.getValueType()),
1628 ISD::SETEQ);
1629 // If we have setugt X, Max-1, turn it into seteq X, Max
1630 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1631 return DAG.getSetCC(dl, VT, N0,
1632 DAG.getConstant(MaxVal, N0.getValueType()),
1633 ISD::SETEQ);
1634
1635 // If we have "setcc X, C0", check to see if we can shrink the immediate
1636 // by changing cc.
1637
1638 // SETUGT X, SINTMAX -> SETLT X, 0
1639 if (Cond == ISD::SETUGT &&
1640 C1 == APInt::getSignedMaxValue(OperandBitSize))
1641 return DAG.getSetCC(dl, VT, N0,
1642 DAG.getConstant(0, N1.getValueType()),
1643 ISD::SETLT);
1644
1645 // SETULT X, SINTMIN -> SETGT X, -1
1646 if (Cond == ISD::SETULT &&
1647 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1648 SDValue ConstMinusOne =
1649 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1650 N1.getValueType());
1651 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1652 }
1653
1654 // Fold bit comparisons when we can.
1655 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1656 (VT == N0.getValueType() ||
1657 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1658 N0.getOpcode() == ISD::AND)
1659 if (ConstantSDNode *AndRHS =
1660 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1661 EVT ShiftTy = DCI.isBeforeLegalize() ?
1662 getPointerTy() : getShiftAmountTy(N0.getValueType());
1663 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1664 // Perform the xform if the AND RHS is a single bit.
1665 if (AndRHS->getAPIntValue().isPowerOf2()) {
1666 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1667 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1668 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1669 }
1670 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1671 // (X & 8) == 8 --> (X & 8) >> 3
1672 // Perform the xform if C1 is a single bit.
1673 if (C1.isPowerOf2()) {
1674 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1675 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1676 DAG.getConstant(C1.logBase2(), ShiftTy)));
1677 }
1678 }
1679 }
1680
1681 if (C1.getMinSignedBits() <= 64 &&
1682 !isLegalICmpImmediate(C1.getSExtValue())) {
1683 // (X & -256) == 256 -> (X >> 8) == 1
1684 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1685 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1686 if (ConstantSDNode *AndRHS =
1687 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1688 const APInt &AndRHSC = AndRHS->getAPIntValue();
1689 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1690 unsigned ShiftBits = AndRHSC.countTrailingZeros();
1691 EVT ShiftTy = DCI.isBeforeLegalize() ?
1692 getPointerTy() : getShiftAmountTy(N0.getValueType());
1693 EVT CmpTy = N0.getValueType();
1694 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1695 DAG.getConstant(ShiftBits, ShiftTy));
1696 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
1697 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1698 }
1699 }
1700 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1701 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1702 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1703 // X < 0x100000000 -> (X >> 32) < 1
1704 // X >= 0x100000000 -> (X >> 32) >= 1
1705 // X <= 0x0ffffffff -> (X >> 32) < 1
1706 // X > 0x0ffffffff -> (X >> 32) >= 1
1707 unsigned ShiftBits;
1708 APInt NewC = C1;
1709 ISD::CondCode NewCond = Cond;
1710 if (AdjOne) {
1711 ShiftBits = C1.countTrailingOnes();
1712 NewC = NewC + 1;
1713 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1714 } else {
1715 ShiftBits = C1.countTrailingZeros();
1716 }
1717 NewC = NewC.lshr(ShiftBits);
1718 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
1719 EVT ShiftTy = DCI.isBeforeLegalize() ?
1720 getPointerTy() : getShiftAmountTy(N0.getValueType());
1721 EVT CmpTy = N0.getValueType();
1722 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1723 DAG.getConstant(ShiftBits, ShiftTy));
1724 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
1725 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1726 }
1727 }
1728 }
1729 }
1730
1731 if (isa<ConstantFPSDNode>(N0.getNode())) {
1732 // Constant fold or commute setcc.
1733 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1734 if (O.getNode()) return O;
1735 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1736 // If the RHS of an FP comparison is a constant, simplify it away in
1737 // some cases.
1738 if (CFP->getValueAPF().isNaN()) {
1739 // If an operand is known to be a nan, we can fold it.
1740 switch (ISD::getUnorderedFlavor(Cond)) {
1741 default: llvm_unreachable("Unknown flavor!");
1742 case 0: // Known false.
1743 return DAG.getConstant(0, VT);
1744 case 1: // Known true.
1745 return DAG.getConstant(1, VT);
1746 case 2: // Undefined.
1747 return DAG.getUNDEF(VT);
1748 }
1749 }
1750
1751 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1752 // constant if knowing that the operand is non-nan is enough. We prefer to
1753 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1754 // materialize 0.0.
1755 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1756 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1757
1758 // If the condition is not legal, see if we can find an equivalent one
1759 // which is legal.
1760 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1761 // If the comparison was an awkward floating-point == or != and one of
1762 // the comparison operands is infinity or negative infinity, convert the
1763 // condition to a less-awkward <= or >=.
1764 if (CFP->getValueAPF().isInfinity()) {
1765 if (CFP->getValueAPF().isNegative()) {
1766 if (Cond == ISD::SETOEQ &&
1767 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1768 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1769 if (Cond == ISD::SETUEQ &&
1770 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1771 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1772 if (Cond == ISD::SETUNE &&
1773 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1774 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1775 if (Cond == ISD::SETONE &&
1776 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1777 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1778 } else {
1779 if (Cond == ISD::SETOEQ &&
1780 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1781 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1782 if (Cond == ISD::SETUEQ &&
1783 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1784 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1785 if (Cond == ISD::SETUNE &&
1786 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1787 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1788 if (Cond == ISD::SETONE &&
1789 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1790 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1791 }
1792 }
1793 }
1794 }
1795
1796 if (N0 == N1) {
1797 // The sext(setcc()) => setcc() optimization relies on the appropriate
1798 // constant being emitted.
1799 uint64_t EqVal = 0;
1800 switch (getBooleanContents(N0.getValueType())) {
1801 case UndefinedBooleanContent:
1802 case ZeroOrOneBooleanContent:
1803 EqVal = ISD::isTrueWhenEqual(Cond);
1804 break;
1805 case ZeroOrNegativeOneBooleanContent:
1806 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1807 break;
1808 }
1809
1810 // We can always fold X == X for integer setcc's.
1811 if (N0.getValueType().isInteger()) {
1812 return DAG.getConstant(EqVal, VT);
1813 }
1814 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1815 if (UOF == 2) // FP operators that are undefined on NaNs.
1816 return DAG.getConstant(EqVal, VT);
1817 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1818 return DAG.getConstant(EqVal, VT);
1819 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1820 // if it is not already.
1821 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1822 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1823 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1824 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1825 }
1826
1827 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1828 N0.getValueType().isInteger()) {
1829 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1830 N0.getOpcode() == ISD::XOR) {
1831 // Simplify (X+Y) == (X+Z) --> Y == Z
1832 if (N0.getOpcode() == N1.getOpcode()) {
1833 if (N0.getOperand(0) == N1.getOperand(0))
1834 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1835 if (N0.getOperand(1) == N1.getOperand(1))
1836 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1837 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1838 // If X op Y == Y op X, try other combinations.
1839 if (N0.getOperand(0) == N1.getOperand(1))
1840 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1841 Cond);
1842 if (N0.getOperand(1) == N1.getOperand(0))
1843 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1844 Cond);
1845 }
1846 }
1847
1848 // If RHS is a legal immediate value for a compare instruction, we need
1849 // to be careful about increasing register pressure needlessly.
1850 bool LegalRHSImm = false;
1851
1852 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1853 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1854 // Turn (X+C1) == C2 --> X == C2-C1
1855 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1856 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1857 DAG.getConstant(RHSC->getAPIntValue()-
1858 LHSR->getAPIntValue(),
1859 N0.getValueType()), Cond);
1860 }
1861
1862 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1863 if (N0.getOpcode() == ISD::XOR)
1864 // If we know that all of the inverted bits are zero, don't bother
1865 // performing the inversion.
1866 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1867 return
1868 DAG.getSetCC(dl, VT, N0.getOperand(0),
1869 DAG.getConstant(LHSR->getAPIntValue() ^
1870 RHSC->getAPIntValue(),
1871 N0.getValueType()),
1872 Cond);
1873 }
1874
1875 // Turn (C1-X) == C2 --> X == C1-C2
1876 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1877 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1878 return
1879 DAG.getSetCC(dl, VT, N0.getOperand(1),
1880 DAG.getConstant(SUBC->getAPIntValue() -
1881 RHSC->getAPIntValue(),
1882 N0.getValueType()),
1883 Cond);
1884 }
1885 }
1886
1887 // Could RHSC fold directly into a compare?
1888 if (RHSC->getValueType(0).getSizeInBits() <= 64)
1889 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1890 }
1891
1892 // Simplify (X+Z) == X --> Z == 0
1893 // Don't do this if X is an immediate that can fold into a cmp
1894 // instruction and X+Z has other uses. It could be an induction variable
1895 // chain, and the transform would increase register pressure.
1896 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1897 if (N0.getOperand(0) == N1)
1898 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1899 DAG.getConstant(0, N0.getValueType()), Cond);
1900 if (N0.getOperand(1) == N1) {
1901 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1902 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1903 DAG.getConstant(0, N0.getValueType()), Cond);
1904 if (N0.getNode()->hasOneUse()) {
1905 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1906 // (Z-X) == X --> Z == X<<1
1907 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1908 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
1909 if (!DCI.isCalledByLegalizer())
1910 DCI.AddToWorklist(SH.getNode());
1911 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1912 }
1913 }
1914 }
1915 }
1916
1917 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1918 N1.getOpcode() == ISD::XOR) {
1919 // Simplify X == (X+Z) --> Z == 0
1920 if (N1.getOperand(0) == N0)
1921 return DAG.getSetCC(dl, VT, N1.getOperand(1),
1922 DAG.getConstant(0, N1.getValueType()), Cond);
1923 if (N1.getOperand(1) == N0) {
1924 if (DAG.isCommutativeBinOp(N1.getOpcode()))
1925 return DAG.getSetCC(dl, VT, N1.getOperand(0),
1926 DAG.getConstant(0, N1.getValueType()), Cond);
1927 if (N1.getNode()->hasOneUse()) {
1928 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1929 // X == (Z-X) --> X<<1 == Z
1930 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1931 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
1932 if (!DCI.isCalledByLegalizer())
1933 DCI.AddToWorklist(SH.getNode());
1934 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1935 }
1936 }
1937 }
1938
1939 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1940 // Note that where y is variable and is known to have at most
1941 // one bit set (for example, if it is z&1) we cannot do this;
1942 // the expressions are not equivalent when y==0.
1943 if (N0.getOpcode() == ISD::AND)
1944 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1945 if (ValueHasExactlyOneBitSet(N1, DAG)) {
1946 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1947 if (DCI.isBeforeLegalizeOps() ||
1948 isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1949 SDValue Zero = DAG.getConstant(0, N1.getValueType());
1950 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1951 }
1952 }
1953 }
1954 if (N1.getOpcode() == ISD::AND)
1955 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1956 if (ValueHasExactlyOneBitSet(N0, DAG)) {
1957 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1958 if (DCI.isBeforeLegalizeOps() ||
1959 isCondCodeLegal(Cond, N1.getSimpleValueType())) {
1960 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1961 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1962 }
1963 }
1964 }
1965 }
1966
1967 // Fold away ALL boolean setcc's.
1968 SDValue Temp;
1969 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1970 switch (Cond) {
1971 default: llvm_unreachable("Unknown integer setcc!");
1972 case ISD::SETEQ: // X == Y -> ~(X^Y)
1973 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1974 N0 = DAG.getNOT(dl, Temp, MVT::i1);
1975 if (!DCI.isCalledByLegalizer())
1976 DCI.AddToWorklist(Temp.getNode());
1977 break;
1978 case ISD::SETNE: // X != Y --> (X^Y)
1979 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1980 break;
1981 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1982 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1983 Temp = DAG.getNOT(dl, N0, MVT::i1);
1984 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1985 if (!DCI.isCalledByLegalizer())
1986 DCI.AddToWorklist(Temp.getNode());
1987 break;
1988 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
1989 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1990 Temp = DAG.getNOT(dl, N1, MVT::i1);
1991 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1992 if (!DCI.isCalledByLegalizer())
1993 DCI.AddToWorklist(Temp.getNode());
1994 break;
1995 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
1996 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
1997 Temp = DAG.getNOT(dl, N0, MVT::i1);
1998 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1999 if (!DCI.isCalledByLegalizer())
2000 DCI.AddToWorklist(Temp.getNode());
2001 break;
2002 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2003 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2004 Temp = DAG.getNOT(dl, N1, MVT::i1);
2005 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2006 break;
2007 }
2008 if (VT != MVT::i1) {
2009 if (!DCI.isCalledByLegalizer())
2010 DCI.AddToWorklist(N0.getNode());
2011 // FIXME: If running after legalize, we probably can't do this.
2012 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2013 }
2014 return N0;
2015 }
2016
2017 // Could not fold it.
2018 return SDValue();
2019 }
2020
2021 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2022 /// node is a GlobalAddress + offset.
isGAPlusOffset(SDNode * N,const GlobalValue * & GA,int64_t & Offset) const2023 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2024 int64_t &Offset) const {
2025 if (isa<GlobalAddressSDNode>(N)) {
2026 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2027 GA = GASD->getGlobal();
2028 Offset += GASD->getOffset();
2029 return true;
2030 }
2031
2032 if (N->getOpcode() == ISD::ADD) {
2033 SDValue N1 = N->getOperand(0);
2034 SDValue N2 = N->getOperand(1);
2035 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2036 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2037 if (V) {
2038 Offset += V->getSExtValue();
2039 return true;
2040 }
2041 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2042 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2043 if (V) {
2044 Offset += V->getSExtValue();
2045 return true;
2046 }
2047 }
2048 }
2049
2050 return false;
2051 }
2052
2053
2054 SDValue TargetLowering::
PerformDAGCombine(SDNode * N,DAGCombinerInfo & DCI) const2055 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2056 // Default implementation: no optimization.
2057 return SDValue();
2058 }
2059
2060 //===----------------------------------------------------------------------===//
2061 // Inline Assembler Implementation Methods
2062 //===----------------------------------------------------------------------===//
2063
2064
2065 TargetLowering::ConstraintType
getConstraintType(const std::string & Constraint) const2066 TargetLowering::getConstraintType(const std::string &Constraint) const {
2067 unsigned S = Constraint.size();
2068
2069 if (S == 1) {
2070 switch (Constraint[0]) {
2071 default: break;
2072 case 'r': return C_RegisterClass;
2073 case 'm': // memory
2074 case 'o': // offsetable
2075 case 'V': // not offsetable
2076 return C_Memory;
2077 case 'i': // Simple Integer or Relocatable Constant
2078 case 'n': // Simple Integer
2079 case 'E': // Floating Point Constant
2080 case 'F': // Floating Point Constant
2081 case 's': // Relocatable Constant
2082 case 'p': // Address.
2083 case 'X': // Allow ANY value.
2084 case 'I': // Target registers.
2085 case 'J':
2086 case 'K':
2087 case 'L':
2088 case 'M':
2089 case 'N':
2090 case 'O':
2091 case 'P':
2092 case '<':
2093 case '>':
2094 return C_Other;
2095 }
2096 }
2097
2098 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
2099 if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}"
2100 return C_Memory;
2101 return C_Register;
2102 }
2103 return C_Unknown;
2104 }
2105
2106 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2107 /// with another that has more specific requirements based on the type of the
2108 /// corresponding operand.
LowerXConstraint(EVT ConstraintVT) const2109 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2110 if (ConstraintVT.isInteger())
2111 return "r";
2112 if (ConstraintVT.isFloatingPoint())
2113 return "f"; // works for many targets
2114 return nullptr;
2115 }
2116
2117 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2118 /// vector. If it is invalid, don't add anything to Ops.
LowerAsmOperandForConstraint(SDValue Op,std::string & Constraint,std::vector<SDValue> & Ops,SelectionDAG & DAG) const2119 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2120 std::string &Constraint,
2121 std::vector<SDValue> &Ops,
2122 SelectionDAG &DAG) const {
2123
2124 if (Constraint.length() > 1) return;
2125
2126 char ConstraintLetter = Constraint[0];
2127 switch (ConstraintLetter) {
2128 default: break;
2129 case 'X': // Allows any operand; labels (basic block) use this.
2130 if (Op.getOpcode() == ISD::BasicBlock) {
2131 Ops.push_back(Op);
2132 return;
2133 }
2134 // fall through
2135 case 'i': // Simple Integer or Relocatable Constant
2136 case 'n': // Simple Integer
2137 case 's': { // Relocatable Constant
2138 // These operands are interested in values of the form (GV+C), where C may
2139 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2140 // is possible and fine if either GV or C are missing.
2141 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2142 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2143
2144 // If we have "(add GV, C)", pull out GV/C
2145 if (Op.getOpcode() == ISD::ADD) {
2146 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2147 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2148 if (!C || !GA) {
2149 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2150 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2151 }
2152 if (!C || !GA)
2153 C = nullptr, GA = nullptr;
2154 }
2155
2156 // If we find a valid operand, map to the TargetXXX version so that the
2157 // value itself doesn't get selected.
2158 if (GA) { // Either &GV or &GV+C
2159 if (ConstraintLetter != 'n') {
2160 int64_t Offs = GA->getOffset();
2161 if (C) Offs += C->getZExtValue();
2162 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2163 C ? SDLoc(C) : SDLoc(),
2164 Op.getValueType(), Offs));
2165 return;
2166 }
2167 }
2168 if (C) { // just C, no GV.
2169 // Simple constants are not allowed for 's'.
2170 if (ConstraintLetter != 's') {
2171 // gcc prints these as sign extended. Sign extend value to 64 bits
2172 // now; without this it would get ZExt'd later in
2173 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2174 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2175 MVT::i64));
2176 return;
2177 }
2178 }
2179 break;
2180 }
2181 }
2182 }
2183
2184 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
getRegForInlineAsmConstraint(const std::string & Constraint,MVT VT) const2185 getRegForInlineAsmConstraint(const std::string &Constraint,
2186 MVT VT) const {
2187 if (Constraint.empty() || Constraint[0] != '{')
2188 return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
2189 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2190
2191 // Remove the braces from around the name.
2192 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2193
2194 std::pair<unsigned, const TargetRegisterClass*> R =
2195 std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
2196
2197 // Figure out which register class contains this reg.
2198 const TargetRegisterInfo *RI =
2199 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2200 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2201 E = RI->regclass_end(); RCI != E; ++RCI) {
2202 const TargetRegisterClass *RC = *RCI;
2203
2204 // If none of the value types for this register class are valid, we
2205 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2206 if (!isLegalRC(RC))
2207 continue;
2208
2209 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2210 I != E; ++I) {
2211 if (RegName.equals_lower(RI->getName(*I))) {
2212 std::pair<unsigned, const TargetRegisterClass*> S =
2213 std::make_pair(*I, RC);
2214
2215 // If this register class has the requested value type, return it,
2216 // otherwise keep searching and return the first class found
2217 // if no other is found which explicitly has the requested type.
2218 if (RC->hasType(VT))
2219 return S;
2220 else if (!R.second)
2221 R = S;
2222 }
2223 }
2224 }
2225
2226 return R;
2227 }
2228
2229 //===----------------------------------------------------------------------===//
2230 // Constraint Selection.
2231
2232 /// isMatchingInputConstraint - Return true of this is an input operand that is
2233 /// a matching constraint like "4".
isMatchingInputConstraint() const2234 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2235 assert(!ConstraintCode.empty() && "No known constraint!");
2236 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2237 }
2238
2239 /// getMatchedOperand - If this is an input matching constraint, this method
2240 /// returns the output operand it matches.
getMatchedOperand() const2241 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2242 assert(!ConstraintCode.empty() && "No known constraint!");
2243 return atoi(ConstraintCode.c_str());
2244 }
2245
2246
2247 /// ParseConstraints - Split up the constraint string from the inline
2248 /// assembly value into the specific constraints and their prefixes,
2249 /// and also tie in the associated operand values.
2250 /// If this returns an empty vector, and if the constraint string itself
2251 /// isn't empty, there was an error parsing.
ParseConstraints(ImmutableCallSite CS) const2252 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2253 ImmutableCallSite CS) const {
2254 /// ConstraintOperands - Information about all of the constraints.
2255 AsmOperandInfoVector ConstraintOperands;
2256 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2257 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2258
2259 // Do a prepass over the constraints, canonicalizing them, and building up the
2260 // ConstraintOperands list.
2261 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2262 unsigned ResNo = 0; // ResNo - The result number of the next output.
2263
2264 for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) {
2265 ConstraintOperands.emplace_back(std::move(CI));
2266 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2267
2268 // Update multiple alternative constraint count.
2269 if (OpInfo.multipleAlternatives.size() > maCount)
2270 maCount = OpInfo.multipleAlternatives.size();
2271
2272 OpInfo.ConstraintVT = MVT::Other;
2273
2274 // Compute the value type for each operand.
2275 switch (OpInfo.Type) {
2276 case InlineAsm::isOutput:
2277 // Indirect outputs just consume an argument.
2278 if (OpInfo.isIndirect) {
2279 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2280 break;
2281 }
2282
2283 // The return value of the call is this value. As such, there is no
2284 // corresponding argument.
2285 assert(!CS.getType()->isVoidTy() &&
2286 "Bad inline asm!");
2287 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2288 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2289 } else {
2290 assert(ResNo == 0 && "Asm only has one result!");
2291 OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2292 }
2293 ++ResNo;
2294 break;
2295 case InlineAsm::isInput:
2296 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2297 break;
2298 case InlineAsm::isClobber:
2299 // Nothing to do.
2300 break;
2301 }
2302
2303 if (OpInfo.CallOperandVal) {
2304 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2305 if (OpInfo.isIndirect) {
2306 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2307 if (!PtrTy)
2308 report_fatal_error("Indirect operand for inline asm not a pointer!");
2309 OpTy = PtrTy->getElementType();
2310 }
2311
2312 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2313 if (StructType *STy = dyn_cast<StructType>(OpTy))
2314 if (STy->getNumElements() == 1)
2315 OpTy = STy->getElementType(0);
2316
2317 // If OpTy is not a single value, it may be a struct/union that we
2318 // can tile with integers.
2319 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2320 unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
2321 switch (BitSize) {
2322 default: break;
2323 case 1:
2324 case 8:
2325 case 16:
2326 case 32:
2327 case 64:
2328 case 128:
2329 OpInfo.ConstraintVT =
2330 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2331 break;
2332 }
2333 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2334 unsigned PtrSize
2335 = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace());
2336 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2337 } else {
2338 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2339 }
2340 }
2341 }
2342
2343 // If we have multiple alternative constraints, select the best alternative.
2344 if (ConstraintOperands.size()) {
2345 if (maCount) {
2346 unsigned bestMAIndex = 0;
2347 int bestWeight = -1;
2348 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2349 int weight = -1;
2350 unsigned maIndex;
2351 // Compute the sums of the weights for each alternative, keeping track
2352 // of the best (highest weight) one so far.
2353 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2354 int weightSum = 0;
2355 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2356 cIndex != eIndex; ++cIndex) {
2357 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2358 if (OpInfo.Type == InlineAsm::isClobber)
2359 continue;
2360
2361 // If this is an output operand with a matching input operand,
2362 // look up the matching input. If their types mismatch, e.g. one
2363 // is an integer, the other is floating point, or their sizes are
2364 // different, flag it as an maCantMatch.
2365 if (OpInfo.hasMatchingInput()) {
2366 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2367 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2368 if ((OpInfo.ConstraintVT.isInteger() !=
2369 Input.ConstraintVT.isInteger()) ||
2370 (OpInfo.ConstraintVT.getSizeInBits() !=
2371 Input.ConstraintVT.getSizeInBits())) {
2372 weightSum = -1; // Can't match.
2373 break;
2374 }
2375 }
2376 }
2377 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2378 if (weight == -1) {
2379 weightSum = -1;
2380 break;
2381 }
2382 weightSum += weight;
2383 }
2384 // Update best.
2385 if (weightSum > bestWeight) {
2386 bestWeight = weightSum;
2387 bestMAIndex = maIndex;
2388 }
2389 }
2390
2391 // Now select chosen alternative in each constraint.
2392 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2393 cIndex != eIndex; ++cIndex) {
2394 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2395 if (cInfo.Type == InlineAsm::isClobber)
2396 continue;
2397 cInfo.selectAlternative(bestMAIndex);
2398 }
2399 }
2400 }
2401
2402 // Check and hook up tied operands, choose constraint code to use.
2403 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2404 cIndex != eIndex; ++cIndex) {
2405 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2406
2407 // If this is an output operand with a matching input operand, look up the
2408 // matching input. If their types mismatch, e.g. one is an integer, the
2409 // other is floating point, or their sizes are different, flag it as an
2410 // error.
2411 if (OpInfo.hasMatchingInput()) {
2412 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2413
2414 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2415 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2416 getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
2417 OpInfo.ConstraintVT);
2418 std::pair<unsigned, const TargetRegisterClass*> InputRC =
2419 getRegForInlineAsmConstraint(Input.ConstraintCode,
2420 Input.ConstraintVT);
2421 if ((OpInfo.ConstraintVT.isInteger() !=
2422 Input.ConstraintVT.isInteger()) ||
2423 (MatchRC.second != InputRC.second)) {
2424 report_fatal_error("Unsupported asm: input constraint"
2425 " with a matching output constraint of"
2426 " incompatible type!");
2427 }
2428 }
2429
2430 }
2431 }
2432
2433 return ConstraintOperands;
2434 }
2435
2436
2437 /// getConstraintGenerality - Return an integer indicating how general CT
2438 /// is.
getConstraintGenerality(TargetLowering::ConstraintType CT)2439 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2440 switch (CT) {
2441 case TargetLowering::C_Other:
2442 case TargetLowering::C_Unknown:
2443 return 0;
2444 case TargetLowering::C_Register:
2445 return 1;
2446 case TargetLowering::C_RegisterClass:
2447 return 2;
2448 case TargetLowering::C_Memory:
2449 return 3;
2450 }
2451 llvm_unreachable("Invalid constraint type");
2452 }
2453
2454 /// Examine constraint type and operand type and determine a weight value.
2455 /// This object must already have been set up with the operand type
2456 /// and the current alternative constraint selected.
2457 TargetLowering::ConstraintWeight
getMultipleConstraintMatchWeight(AsmOperandInfo & info,int maIndex) const2458 TargetLowering::getMultipleConstraintMatchWeight(
2459 AsmOperandInfo &info, int maIndex) const {
2460 InlineAsm::ConstraintCodeVector *rCodes;
2461 if (maIndex >= (int)info.multipleAlternatives.size())
2462 rCodes = &info.Codes;
2463 else
2464 rCodes = &info.multipleAlternatives[maIndex].Codes;
2465 ConstraintWeight BestWeight = CW_Invalid;
2466
2467 // Loop over the options, keeping track of the most general one.
2468 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2469 ConstraintWeight weight =
2470 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2471 if (weight > BestWeight)
2472 BestWeight = weight;
2473 }
2474
2475 return BestWeight;
2476 }
2477
2478 /// Examine constraint type and operand type and determine a weight value.
2479 /// This object must already have been set up with the operand type
2480 /// and the current alternative constraint selected.
2481 TargetLowering::ConstraintWeight
getSingleConstraintMatchWeight(AsmOperandInfo & info,const char * constraint) const2482 TargetLowering::getSingleConstraintMatchWeight(
2483 AsmOperandInfo &info, const char *constraint) const {
2484 ConstraintWeight weight = CW_Invalid;
2485 Value *CallOperandVal = info.CallOperandVal;
2486 // If we don't have a value, we can't do a match,
2487 // but allow it at the lowest weight.
2488 if (!CallOperandVal)
2489 return CW_Default;
2490 // Look at the constraint type.
2491 switch (*constraint) {
2492 case 'i': // immediate integer.
2493 case 'n': // immediate integer with a known value.
2494 if (isa<ConstantInt>(CallOperandVal))
2495 weight = CW_Constant;
2496 break;
2497 case 's': // non-explicit intregal immediate.
2498 if (isa<GlobalValue>(CallOperandVal))
2499 weight = CW_Constant;
2500 break;
2501 case 'E': // immediate float if host format.
2502 case 'F': // immediate float.
2503 if (isa<ConstantFP>(CallOperandVal))
2504 weight = CW_Constant;
2505 break;
2506 case '<': // memory operand with autodecrement.
2507 case '>': // memory operand with autoincrement.
2508 case 'm': // memory operand.
2509 case 'o': // offsettable memory operand
2510 case 'V': // non-offsettable memory operand
2511 weight = CW_Memory;
2512 break;
2513 case 'r': // general register.
2514 case 'g': // general register, memory operand or immediate integer.
2515 // note: Clang converts "g" to "imr".
2516 if (CallOperandVal->getType()->isIntegerTy())
2517 weight = CW_Register;
2518 break;
2519 case 'X': // any operand.
2520 default:
2521 weight = CW_Default;
2522 break;
2523 }
2524 return weight;
2525 }
2526
2527 /// ChooseConstraint - If there are multiple different constraints that we
2528 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2529 /// This is somewhat tricky: constraints fall into four classes:
2530 /// Other -> immediates and magic values
2531 /// Register -> one specific register
2532 /// RegisterClass -> a group of regs
2533 /// Memory -> memory
2534 /// Ideally, we would pick the most specific constraint possible: if we have
2535 /// something that fits into a register, we would pick it. The problem here
2536 /// is that if we have something that could either be in a register or in
2537 /// memory that use of the register could cause selection of *other*
2538 /// operands to fail: they might only succeed if we pick memory. Because of
2539 /// this the heuristic we use is:
2540 ///
2541 /// 1) If there is an 'other' constraint, and if the operand is valid for
2542 /// that constraint, use it. This makes us take advantage of 'i'
2543 /// constraints when available.
2544 /// 2) Otherwise, pick the most general constraint present. This prefers
2545 /// 'm' over 'r', for example.
2546 ///
ChooseConstraint(TargetLowering::AsmOperandInfo & OpInfo,const TargetLowering & TLI,SDValue Op,SelectionDAG * DAG)2547 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2548 const TargetLowering &TLI,
2549 SDValue Op, SelectionDAG *DAG) {
2550 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2551 unsigned BestIdx = 0;
2552 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2553 int BestGenerality = -1;
2554
2555 // Loop over the options, keeping track of the most general one.
2556 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2557 TargetLowering::ConstraintType CType =
2558 TLI.getConstraintType(OpInfo.Codes[i]);
2559
2560 // If this is an 'other' constraint, see if the operand is valid for it.
2561 // For example, on X86 we might have an 'rI' constraint. If the operand
2562 // is an integer in the range [0..31] we want to use I (saving a load
2563 // of a register), otherwise we must use 'r'.
2564 if (CType == TargetLowering::C_Other && Op.getNode()) {
2565 assert(OpInfo.Codes[i].size() == 1 &&
2566 "Unhandled multi-letter 'other' constraint");
2567 std::vector<SDValue> ResultOps;
2568 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
2569 ResultOps, *DAG);
2570 if (!ResultOps.empty()) {
2571 BestType = CType;
2572 BestIdx = i;
2573 break;
2574 }
2575 }
2576
2577 // Things with matching constraints can only be registers, per gcc
2578 // documentation. This mainly affects "g" constraints.
2579 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2580 continue;
2581
2582 // This constraint letter is more general than the previous one, use it.
2583 int Generality = getConstraintGenerality(CType);
2584 if (Generality > BestGenerality) {
2585 BestType = CType;
2586 BestIdx = i;
2587 BestGenerality = Generality;
2588 }
2589 }
2590
2591 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2592 OpInfo.ConstraintType = BestType;
2593 }
2594
2595 /// ComputeConstraintToUse - Determines the constraint code and constraint
2596 /// type to use for the specific AsmOperandInfo, setting
2597 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
ComputeConstraintToUse(AsmOperandInfo & OpInfo,SDValue Op,SelectionDAG * DAG) const2598 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2599 SDValue Op,
2600 SelectionDAG *DAG) const {
2601 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2602
2603 // Single-letter constraints ('r') are very common.
2604 if (OpInfo.Codes.size() == 1) {
2605 OpInfo.ConstraintCode = OpInfo.Codes[0];
2606 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2607 } else {
2608 ChooseConstraint(OpInfo, *this, Op, DAG);
2609 }
2610
2611 // 'X' matches anything.
2612 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2613 // Labels and constants are handled elsewhere ('X' is the only thing
2614 // that matches labels). For Functions, the type here is the type of
2615 // the result, which is not what we want to look at; leave them alone.
2616 Value *v = OpInfo.CallOperandVal;
2617 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2618 OpInfo.CallOperandVal = v;
2619 return;
2620 }
2621
2622 // Otherwise, try to resolve it to something we know about by looking at
2623 // the actual operand type.
2624 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2625 OpInfo.ConstraintCode = Repl;
2626 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2627 }
2628 }
2629 }
2630
2631 /// \brief Given an exact SDIV by a constant, create a multiplication
2632 /// with the multiplicative inverse of the constant.
BuildExactSDIV(SDValue Op1,SDValue Op2,SDLoc dl,SelectionDAG & DAG) const2633 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2634 SelectionDAG &DAG) const {
2635 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
2636 APInt d = C->getAPIntValue();
2637 assert(d != 0 && "Division by zero!");
2638
2639 // Shift the value upfront if it is even, so the LSB is one.
2640 unsigned ShAmt = d.countTrailingZeros();
2641 if (ShAmt) {
2642 // TODO: For UDIV use SRL instead of SRA.
2643 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
2644 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
2645 true);
2646 d = d.ashr(ShAmt);
2647 }
2648
2649 // Calculate the multiplicative inverse, using Newton's method.
2650 APInt t, xn = d;
2651 while ((t = d*xn) != 1)
2652 xn *= APInt(d.getBitWidth(), 2) - t;
2653
2654 Op2 = DAG.getConstant(xn, Op1.getValueType());
2655 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2656 }
2657
2658 /// \brief Given an ISD::SDIV node expressing a divide by constant,
2659 /// return a DAG expression to select that will generate the same value by
2660 /// multiplying by a magic number.
2661 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
BuildSDIV(SDNode * N,const APInt & Divisor,SelectionDAG & DAG,bool IsAfterLegalization,std::vector<SDNode * > * Created) const2662 SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor,
2663 SelectionDAG &DAG, bool IsAfterLegalization,
2664 std::vector<SDNode *> *Created) const {
2665 assert(Created && "No vector to hold sdiv ops.");
2666
2667 EVT VT = N->getValueType(0);
2668 SDLoc dl(N);
2669
2670 // Check to see if we can do this.
2671 // FIXME: We should be more aggressive here.
2672 if (!isTypeLegal(VT))
2673 return SDValue();
2674
2675 APInt::ms magics = Divisor.magic();
2676
2677 // Multiply the numerator (operand 0) by the magic value
2678 // FIXME: We should support doing a MUL in a wider type
2679 SDValue Q;
2680 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2681 isOperationLegalOrCustom(ISD::MULHS, VT))
2682 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2683 DAG.getConstant(magics.m, VT));
2684 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2685 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2686 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2687 N->getOperand(0),
2688 DAG.getConstant(magics.m, VT)).getNode(), 1);
2689 else
2690 return SDValue(); // No mulhs or equvialent
2691 // If d > 0 and m < 0, add the numerator
2692 if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2693 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2694 Created->push_back(Q.getNode());
2695 }
2696 // If d < 0 and m > 0, subtract the numerator.
2697 if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2698 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2699 Created->push_back(Q.getNode());
2700 }
2701 // Shift right algebraic if shift value is nonzero
2702 if (magics.s > 0) {
2703 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2704 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2705 Created->push_back(Q.getNode());
2706 }
2707 // Extract the sign bit and add it to the quotient
2708 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
2709 DAG.getConstant(VT.getScalarSizeInBits() - 1,
2710 getShiftAmountTy(Q.getValueType())));
2711 Created->push_back(T.getNode());
2712 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2713 }
2714
2715 /// \brief Given an ISD::UDIV node expressing a divide by constant,
2716 /// return a DAG expression to select that will generate the same value by
2717 /// multiplying by a magic number.
2718 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
BuildUDIV(SDNode * N,const APInt & Divisor,SelectionDAG & DAG,bool IsAfterLegalization,std::vector<SDNode * > * Created) const2719 SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
2720 SelectionDAG &DAG, bool IsAfterLegalization,
2721 std::vector<SDNode *> *Created) const {
2722 assert(Created && "No vector to hold udiv ops.");
2723
2724 EVT VT = N->getValueType(0);
2725 SDLoc dl(N);
2726
2727 // Check to see if we can do this.
2728 // FIXME: We should be more aggressive here.
2729 if (!isTypeLegal(VT))
2730 return SDValue();
2731
2732 // FIXME: We should use a narrower constant when the upper
2733 // bits are known to be zero.
2734 APInt::mu magics = Divisor.magicu();
2735
2736 SDValue Q = N->getOperand(0);
2737
2738 // If the divisor is even, we can avoid using the expensive fixup by shifting
2739 // the divided value upfront.
2740 if (magics.a != 0 && !Divisor[0]) {
2741 unsigned Shift = Divisor.countTrailingZeros();
2742 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2743 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
2744 Created->push_back(Q.getNode());
2745
2746 // Get magic number for the shifted divisor.
2747 magics = Divisor.lshr(Shift).magicu(Shift);
2748 assert(magics.a == 0 && "Should use cheap fixup now");
2749 }
2750
2751 // Multiply the numerator (operand 0) by the magic value
2752 // FIXME: We should support doing a MUL in a wider type
2753 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2754 isOperationLegalOrCustom(ISD::MULHU, VT))
2755 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2756 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2757 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2758 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2759 DAG.getConstant(magics.m, VT)).getNode(), 1);
2760 else
2761 return SDValue(); // No mulhu or equvialent
2762
2763 Created->push_back(Q.getNode());
2764
2765 if (magics.a == 0) {
2766 assert(magics.s < Divisor.getBitWidth() &&
2767 "We shouldn't generate an undefined shift!");
2768 return DAG.getNode(ISD::SRL, dl, VT, Q,
2769 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2770 } else {
2771 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2772 Created->push_back(NPQ.getNode());
2773 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2774 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
2775 Created->push_back(NPQ.getNode());
2776 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2777 Created->push_back(NPQ.getNode());
2778 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2779 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
2780 }
2781 }
2782
2783 bool TargetLowering::
verifyReturnAddressArgumentIsConstant(SDValue Op,SelectionDAG & DAG) const2784 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
2785 if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2786 DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2787 "be a constant integer");
2788 return true;
2789 }
2790
2791 return false;
2792 }
2793
2794 //===----------------------------------------------------------------------===//
2795 // Legalization Utilities
2796 //===----------------------------------------------------------------------===//
2797
expandMUL(SDNode * N,SDValue & Lo,SDValue & Hi,EVT HiLoVT,SelectionDAG & DAG,SDValue LL,SDValue LH,SDValue RL,SDValue RH) const2798 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2799 SelectionDAG &DAG, SDValue LL, SDValue LH,
2800 SDValue RL, SDValue RH) const {
2801 EVT VT = N->getValueType(0);
2802 SDLoc dl(N);
2803
2804 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2805 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2806 bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2807 bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2808 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2809 unsigned OuterBitSize = VT.getSizeInBits();
2810 unsigned InnerBitSize = HiLoVT.getSizeInBits();
2811 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2812 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2813
2814 // LL, LH, RL, and RH must be either all NULL or all set to a value.
2815 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2816 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2817
2818 if (!LL.getNode() && !RL.getNode() &&
2819 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2820 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2821 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2822 }
2823
2824 if (!LL.getNode())
2825 return false;
2826
2827 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2828 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2829 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2830 // The inputs are both zero-extended.
2831 if (HasUMUL_LOHI) {
2832 // We can emit a umul_lohi.
2833 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2834 RL);
2835 Hi = SDValue(Lo.getNode(), 1);
2836 return true;
2837 }
2838 if (HasMULHU) {
2839 // We can emit a mulhu+mul.
2840 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2841 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2842 return true;
2843 }
2844 }
2845 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2846 // The input values are both sign-extended.
2847 if (HasSMUL_LOHI) {
2848 // We can emit a smul_lohi.
2849 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2850 RL);
2851 Hi = SDValue(Lo.getNode(), 1);
2852 return true;
2853 }
2854 if (HasMULHS) {
2855 // We can emit a mulhs+mul.
2856 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2857 Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2858 return true;
2859 }
2860 }
2861
2862 if (!LH.getNode() && !RH.getNode() &&
2863 isOperationLegalOrCustom(ISD::SRL, VT) &&
2864 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2865 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2866 SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT));
2867 LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2868 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2869 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2870 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2871 }
2872
2873 if (!LH.getNode())
2874 return false;
2875
2876 if (HasUMUL_LOHI) {
2877 // Lo,Hi = umul LHS, RHS.
2878 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2879 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2880 Lo = UMulLOHI;
2881 Hi = UMulLOHI.getValue(1);
2882 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2883 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2884 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2885 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2886 return true;
2887 }
2888 if (HasMULHU) {
2889 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2890 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2891 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2892 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2893 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2894 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2895 return true;
2896 }
2897 }
2898 return false;
2899 }
2900
expandFP_TO_SINT(SDNode * Node,SDValue & Result,SelectionDAG & DAG) const2901 bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
2902 SelectionDAG &DAG) const {
2903 EVT VT = Node->getOperand(0).getValueType();
2904 EVT NVT = Node->getValueType(0);
2905 SDLoc dl(SDValue(Node, 0));
2906
2907 // FIXME: Only f32 to i64 conversions are supported.
2908 if (VT != MVT::f32 || NVT != MVT::i64)
2909 return false;
2910
2911 // Expand f32 -> i64 conversion
2912 // This algorithm comes from compiler-rt's implementation of fixsfdi:
2913 // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
2914 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
2915 VT.getSizeInBits());
2916 SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT);
2917 SDValue ExponentLoBit = DAG.getConstant(23, IntVT);
2918 SDValue Bias = DAG.getConstant(127, IntVT);
2919 SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()),
2920 IntVT);
2921 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT);
2922 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT);
2923
2924 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
2925
2926 SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
2927 DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
2928 DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT)));
2929 SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
2930
2931 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
2932 DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
2933 DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT)));
2934 Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
2935
2936 SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
2937 DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
2938 DAG.getConstant(0x00800000, IntVT));
2939
2940 R = DAG.getZExtOrTrunc(R, dl, NVT);
2941
2942
2943 R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
2944 DAG.getNode(ISD::SHL, dl, NVT, R,
2945 DAG.getZExtOrTrunc(
2946 DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
2947 dl, getShiftAmountTy(IntVT))),
2948 DAG.getNode(ISD::SRL, dl, NVT, R,
2949 DAG.getZExtOrTrunc(
2950 DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
2951 dl, getShiftAmountTy(IntVT))),
2952 ISD::SETGT);
2953
2954 SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
2955 DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
2956 Sign);
2957
2958 Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, IntVT),
2959 DAG.getConstant(0, NVT), Ret, ISD::SETLT);
2960 return true;
2961 }
2962